[PATCH 2/2] spi: davinci: enable DMA when channels are defined in DT
When booting with DT the SPI driver is always using
the SPI_IO_TYPE_INTR mode to transfer data even if DMA channels are
defined in the DT.
This commit changes the behaviour to select the SPI_IO_TYPE_DMA mode
if DMA channels are defined in the DT and will keep SPI_IO_TYPE_INTR
if the channels are not defined in it.
Signed-off-by: Fabien Parent <fpar...@baylibre.com>
---
drivers/spi/spi-davinci.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/spi/spi-davinci.c b/drivers/spi/spi-davinci.c
index cb80c1d3f86a..b73072ae8adb 100644
--- a/drivers/spi/spi-davinci.c
+++ b/drivers/spi/spi-davinci.c
@@ -389,6 +389,7 @@ static int davinci_spi_of_setup(struct spi_device *spi)
{
struct davinci_spi_config *spicfg = spi->controller_data;
struct device_node *np = spi->dev.of_node;
+ struct davinci_spi *dspi = spi_master_get_devdata(spi->master);
u32 prop;
if (spicfg == NULL && np) {
@@ -400,6 +401,9 @@ static int davinci_spi_of_setup(struct spi_device *spi)
if (!of_property_read_u32(np, "ti,spi-wdelay", ))
spicfg->wdelay = (u8)prop;
spi->controller_data = spicfg;
+
+ if (dspi->dma_rx && dspi->dma_tx)
+ spicfg->io_type = SPI_IO_TYPE_DMA;
}
return 0;
--
2.11.0
[PATCH 1/2] spi: davinci: Use SPI framework to handle DMA mapping
Uppers layers like MTD can pass vmalloc'd buffers to the SPI driver,
and the current implementation will fail to map these kind of buffers.
The SPI framework is able to detect the best way to handle and map
buffers.
This commit updates the davinci SPI driver in order to use the SPI
framework to handle the DMA mapping of buffers coming from an upper
layer.
Signed-off-by: Fabien Parent <fpar...@baylibre.com>
---
drivers/spi/spi-davinci.c | 78 ---
1 file changed, 46 insertions(+), 32 deletions(-)
diff --git a/drivers/spi/spi-davinci.c b/drivers/spi/spi-davinci.c
index 02fb96797ac8..cb80c1d3f86a 100644
--- a/drivers/spi/spi-davinci.c
+++ b/drivers/spi/spi-davinci.c
@@ -630,7 +630,6 @@ static int davinci_spi_bufs(struct spi_device *spi, struct
spi_transfer *t)
};
struct dma_async_tx_descriptor *rxdesc;
struct dma_async_tx_descriptor *txdesc;
- void *buf;
dummy_buf = kzalloc(t->len, GFP_KERNEL);
if (!dummy_buf)
@@ -639,42 +638,40 @@ static int davinci_spi_bufs(struct spi_device *spi,
struct spi_transfer *t)
dmaengine_slave_config(dspi->dma_rx, _rx_conf);
dmaengine_slave_config(dspi->dma_tx, _tx_conf);
- sg_init_table(_rx, 1);
- if (!t->rx_buf)
- buf = dummy_buf;
- else
- buf = t->rx_buf;
- t->rx_dma = dma_map_single(>dev, buf,
- t->len, DMA_FROM_DEVICE);
- if (dma_mapping_error(>dev, !t->rx_dma)) {
- ret = -EFAULT;
- goto err_rx_map;
+ if (!t->rx_buf) {
+ sg_init_table(_rx, 1);
+ t->rx_dma = dma_map_single(>dev, dummy_buf,
+ t->len, DMA_FROM_DEVICE);
+ if (dma_mapping_error(>dev, !t->rx_dma)) {
+ ret = -EFAULT;
+ goto err_rx_map;
+ }
+ sg_dma_address(_rx) = t->rx_dma;
+ sg_dma_len(_rx) = t->len;
}
- sg_dma_address(_rx) = t->rx_dma;
- sg_dma_len(_rx) = t->len;
sg_init_table(_tx, 1);
- if (!t->tx_buf)
- buf = dummy_buf;
- else
- buf = (void *)t->tx_buf;
- t->tx_dma = dma_map_single(>dev, buf,
- t->len, DMA_TO_DEVICE);
- if (dma_mapping_error(>dev, t->tx_dma)) {
- ret = -EFAULT;
- goto err_tx_map;
+ if (!t->tx_buf) {
+ t->tx_dma = dma_map_single(>dev, (void *)t->tx_buf,
+ t->len, DMA_TO_DEVICE);
+ if (dma_mapping_error(>dev, t->tx_dma)) {
+ ret = -EFAULT;
+ goto err_tx_map;
+ }
+ sg_dma_address(_tx) = t->tx_dma;
+ sg_dma_len(_tx) = t->len;
}
- sg_dma_address(_tx) = t->tx_dma;
- sg_dma_len(_tx) = t->len;
rxdesc = dmaengine_prep_slave_sg(dspi->dma_rx,
- _rx, 1, DMA_DEV_TO_MEM,
+ t->rx_sg.sgl ?: _rx, t->rx_sg.nents ?: 1,
+ DMA_DEV_TO_MEM,
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
if (!rxdesc)
goto err_desc;
txdesc = dmaengine_prep_slave_sg(dspi->dma_tx,
- _tx, 1, DMA_MEM_TO_DEV,
+ t->tx_sg.sgl ?: _tx, t->tx_sg.nents ?: 1,
+ DMA_MEM_TO_DEV,
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
if (!txdesc)
goto err_desc;
@@ -713,10 +710,12 @@ static int davinci_spi_bufs(struct spi_device *spi,
struct spi_transfer *t)
if (spicfg->io_type == SPI_IO_TYPE_DMA) {
clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
- dma_unmap_single(>dev, t->rx_dma,
- t->len, DMA_FROM_DEVICE);
- dma_unmap_single(>dev, t->tx_dma,
- t->len, DMA_TO_DEVICE);
+ if (!t->rx_buf)
+ dma_unmap_single(>dev, t->rx_dma,
+ t->len, DMA_FROM_DEVICE);
+ if (!t->tx_buf)
+ dma_unmap_single(>dev, t->tx_dma,
+
[PATCH] ARM: davinci: da850-evm: fix read access to SPI flash
Read access to the SPI flash are broken on da850-evm, i.e. the data
read is not what is actually programmed on the flash.
According to the datasheet for the M25P64 part present on the da850-evm,
if the SPI frequency is higher than 20MHz then the READ command is not
usable anymore and only the FAST_READ command can be used to read data.
This commit specifies in the DTS that we should use FAST_READ command
instead of the READ command.
Signed-off-by: Fabien Parent <fpar...@baylibre.com>
---
arch/arm/boot/dts/da850-evm.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts
index 41de15fe15a2..78492a0bbbab 100644
--- a/arch/arm/boot/dts/da850-evm.dts
+++ b/arch/arm/boot/dts/da850-evm.dts
@@ -99,6 +99,7 @@
#size-cells = <1>;
compatible = "m25p64";
spi-max-frequency = <3000>;
+ m25p,fast-read;
reg = <0>;
partition@0 {
label = "U-Boot-SPL";
--
2.11.0
[PATCH] ARM: dts: da850-lcdk: Add ethernet0 alias to DT
In order to avoid Linux generating a random mac address on every boot,
add an ethernet0 alias that will allow u-boot to patch the dtb with
the MAC address programmed into the EEPROM.
Signed-off-by: Fabien Parent <fpar...@baylibre.com>
---
arch/arm/boot/dts/da850-lcdk.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/da850-lcdk.dts b/arch/arm/boot/dts/da850-lcdk.dts
index 7b8ab21..18dfec93 100644
--- a/arch/arm/boot/dts/da850-lcdk.dts
+++ b/arch/arm/boot/dts/da850-lcdk.dts
@@ -13,6 +13,7 @@
aliases {
serial2 =
+ ethernet0 =
};
chosen {
--
2.10.2
Re: [PATCH 2/3] power: supply: cros: add support for dedicated port
Hi,
Making sure this patch and the next one [1] are not being forgotten.
[1] https://patchwork.kernel.org/patch/10437565/
On Wed, May 30, 2018 at 5:17 AM, Fabien Parent wrote:
> ChromeOS devices can have one optional dedicated port.
> The Dedicated port is unique and similar to the USB PD ports
> except that it doesn't support as many properties.
>
> The presence of a dedicated port is determined from whether the
> EC's charger port count is equal to 'number of USB PD port' + 1.
> The dedicated port ID is always the last valid port ID.
>
> This commit keeps compatibility with Embedded Controllers that do not
> support the new EC_CMD_CHARGE_PORT_COUNT command by setting
> the number of charger port to be equal to the number of USB PD port
> when this command fails.
>
> Signed-off-by: Fabien Parent
> ---
> drivers/power/supply/cros_usbpd-charger.c | 115 +++---
> 1 file changed, 101 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/power/supply/cros_usbpd-charger.c
> b/drivers/power/supply/cros_usbpd-charger.c
> index 3a0c96fd1bc1..808688a6586c 100644
> --- a/drivers/power/supply/cros_usbpd-charger.c
> +++ b/drivers/power/supply/cros_usbpd-charger.c
> @@ -12,8 +12,12 @@
> #include
> #include
>
> -#define CHARGER_DIR_NAME "CROS_USBPD_CHARGER%d"
> -#define CHARGER_DIR_NAME_LENGTH
> sizeof(CHARGER_DIR_NAME)
> +#define CHARGER_USBPD_DIR_NAME "CROS_USBPD_CHARGER%d"
> +#define CHARGER_DEDICATED_DIR_NAME "CROS_DEDICATED_CHARGER"
> +#define CHARGER_DIR_NAME_LENGTH
> (sizeof(CHARGER_USBPD_DIR_NAME) >= \
> +sizeof(CHARGER_DEDICATED_DIR_NAME) ?
> \
> +sizeof(CHARGER_USBPD_DIR_NAME) : \
> +sizeof(CHARGER_DEDICATED_DIR_NAME))
> #define CHARGER_CACHE_UPDATE_DELAY msecs_to_jiffies(500)
> #define CHARGER_MANUFACTURER_MODEL_LENGTH 32
>
> @@ -42,6 +46,7 @@ struct charger_data {
> struct cros_ec_dev *ec_dev;
> struct cros_ec_device *ec_device;
> int num_charger_ports;
> + int num_usbpd_ports;
> int num_registered_psy;
> struct port_data *ports[EC_USB_PD_MAX_PORTS];
> struct notifier_block notifier;
> @@ -58,6 +63,12 @@ static enum power_supply_property
> cros_usbpd_charger_props[] = {
> POWER_SUPPLY_PROP_USB_TYPE
> };
>
> +static enum power_supply_property cros_usbpd_dedicated_charger_props[] = {
> + POWER_SUPPLY_PROP_ONLINE,
> + POWER_SUPPLY_PROP_STATUS,
> + POWER_SUPPLY_PROP_VOLTAGE_NOW,
> +};
> +
> static enum power_supply_usb_type cros_usbpd_charger_usb_types[] = {
> POWER_SUPPLY_USB_TYPE_UNKNOWN,
> POWER_SUPPLY_USB_TYPE_SDP,
> @@ -69,6 +80,11 @@ static enum power_supply_usb_type
> cros_usbpd_charger_usb_types[] = {
> POWER_SUPPLY_USB_TYPE_APPLE_BRICK_ID
> };
>
> +static bool cros_usbpd_charger_port_is_dedicated(struct port_data *port)
> +{
> + return port->port_number >= port->charger->num_usbpd_ports;
> +}
> +
> static int cros_usbpd_charger_ec_command(struct charger_data *charger,
> unsigned int version,
> unsigned int command,
> @@ -102,6 +118,23 @@ static int cros_usbpd_charger_ec_command(struct
> charger_data *charger,
> }
>
> static int cros_usbpd_charger_get_num_ports(struct charger_data *charger)
> +{
> + struct ec_response_charge_port_count resp;
> + int ret;
> +
> + ret = cros_usbpd_charger_ec_command(charger, 0,
> + EC_CMD_CHARGE_PORT_COUNT,
> + NULL, 0, , sizeof(resp));
> + if (ret < 0) {
> + dev_err(charger->dev,
> + "Unable to get the number of ports (err:0x%x)\n",
> ret);
> + return ret;
> + }
> +
> + return resp.port_count;
> +}
> +
> +static int cros_usbpd_charger_get_usbpd_num_ports(struct charger_data
> *charger)
> {
> struct ec_response_usb_pd_ports resp;
> int ret;
> @@ -246,7 +279,10 @@ static int cros_usbpd_charger_get_power_info(struct
> port_data *port)
> port->psy_usb_type = POWER_SUPPLY_USB_TYPE_SDP;
> }
>
> - port->psy_desc.type = POWER_SUPPLY_TYPE_USB;
> + if (cros_usbpd_charger_port_is_dedicated(port))
> + port->psy_desc.type = POWER_SUPPLY_TYPE_MAINS;
> + else
> + port->
[PATCH 0/3] power: supply: cros: add support for dedicated port and expose connected ports
Dear all, This patch series adds support for an optional dedicated port to the ChromeOS power supply driver and adds a new property that expose when a power supply is connected. The series was tested on ChromeOS "Fizz" hardware. This patch series depends on the following patch serie which adds the ChromeOS power supply driver: * https://lkml.org/lkml/2018/5/2/585 [PATCH v4 0/3] mfd/power: cros_ec: add support for USBPD charger driver The ChromeOS power supply driver also depends on the following patches to be applied: * https://lkml.org/lkml/2018/4/23/602 ([PATCH v8 0/6] typec: tcpm: Add sink side support for PPS) * https://lkml.org/lkml/2018/4/18/229 ([RESEND PATCH v5 4/7] mfd: cros_ec_dev: Register cros-ec-rtc driver as a subdevice.) Best Regards, Fabien Fabien Parent (3): mfd: cros: add charger port count command definition power: supply: cros: add support for dedicated port power: supply: cros: add property to detect connected ports drivers/power/supply/cros_usbpd-charger.c | 129 +++--- include/linux/mfd/cros_ec_commands.h | 10 ++ 2 files changed, 124 insertions(+), 15 deletions(-) -- 2.17.0
[PATCH 3/3] power: supply: cros: add property to detect connected ports
When a port is connected but acting as a source, its 'online' and
'status' properties are identical to a port that is not connected. This
makes it tedious for userspace to know for sure whether a port is
connected or not.
This commit adds a new property 'present' to reflect whether a port
is connected or not.
Signed-off-by: Fabien Parent
---
drivers/power/supply/cros_usbpd-charger.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/power/supply/cros_usbpd-charger.c
b/drivers/power/supply/cros_usbpd-charger.c
index 808688a6586c..d44ab35670ab 100644
--- a/drivers/power/supply/cros_usbpd-charger.c
+++ b/drivers/power/supply/cros_usbpd-charger.c
@@ -32,6 +32,7 @@ struct port_data {
struct power_supply_desc psy_desc;
int psy_usb_type;
int psy_online;
+ int psy_present;
int psy_status;
int psy_current_max;
int psy_voltage_max_design;
@@ -54,6 +55,7 @@ struct charger_data {
static enum power_supply_property cros_usbpd_charger_props[] = {
POWER_SUPPLY_PROP_ONLINE,
+ POWER_SUPPLY_PROP_PRESENT,
POWER_SUPPLY_PROP_STATUS,
POWER_SUPPLY_PROP_CURRENT_MAX,
POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN,
@@ -65,6 +67,7 @@ static enum power_supply_property cros_usbpd_charger_props[]
= {
static enum power_supply_property cros_usbpd_dedicated_charger_props[] = {
POWER_SUPPLY_PROP_ONLINE,
+ POWER_SUPPLY_PROP_PRESENT,
POWER_SUPPLY_PROP_STATUS,
POWER_SUPPLY_PROP_VOLTAGE_NOW,
};
@@ -205,18 +208,22 @@ static int cros_usbpd_charger_get_power_info(struct
port_data *port)
case USB_PD_PORT_POWER_DISCONNECTED:
port->psy_status = POWER_SUPPLY_STATUS_NOT_CHARGING;
port->psy_online = 0;
+ port->psy_present = 0;
break;
case USB_PD_PORT_POWER_SOURCE:
port->psy_status = POWER_SUPPLY_STATUS_NOT_CHARGING;
port->psy_online = 0;
+ port->psy_present = 1;
break;
case USB_PD_PORT_POWER_SINK:
port->psy_status = POWER_SUPPLY_STATUS_CHARGING;
port->psy_online = 1;
+ port->psy_present = 1;
break;
case USB_PD_PORT_POWER_SINK_NOT_CHARGING:
port->psy_status = POWER_SUPPLY_STATUS_NOT_CHARGING;
port->psy_online = 1;
+ port->psy_present = 1;
break;
default:
dev_err(dev, "Unknown role %d\n", resp.role);
@@ -362,6 +369,7 @@ static int cros_usbpd_charger_get_prop(struct power_supply
*psy,
*/
if (ec_device->mkbp_event_supported || port->psy_online)
break;
+ case POWER_SUPPLY_PROP_PRESENT:
case POWER_SUPPLY_PROP_CURRENT_MAX:
case POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN:
case POWER_SUPPLY_PROP_VOLTAGE_NOW:
@@ -380,6 +388,9 @@ static int cros_usbpd_charger_get_prop(struct power_supply
*psy,
case POWER_SUPPLY_PROP_ONLINE:
val->intval = port->psy_online;
break;
+ case POWER_SUPPLY_PROP_PRESENT:
+ val->intval = port->psy_present;
+ break;
case POWER_SUPPLY_PROP_STATUS:
val->intval = port->psy_status;
break;
--
2.17.0
[PATCH 1/3] mfd: cros: add charger port count command definition
A new more command has been added to the ChromeOS embedded controller
that allows to get the number of charger port count. Unlike
EC_CMD_USB_PD_PORTS, this new command also includes the dedicated
port if present.
This command will be used to expose the dedicated charger port
in the ChromeOS charger driver.
Signed-off-by: Fabien Parent
---
include/linux/mfd/cros_ec_commands.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/include/linux/mfd/cros_ec_commands.h
b/include/linux/mfd/cros_ec_commands.h
index 0d926492ac3a..e3187f8bdb7e 100644
--- a/include/linux/mfd/cros_ec_commands.h
+++ b/include/linux/mfd/cros_ec_commands.h
@@ -3005,6 +3005,16 @@ struct ec_params_usb_pd_info_request {
uint8_t port;
} __packed;
+/*
+ * This command will return the number of USB PD charge port + the number
+ * of dedicated port present.
+ * EC_CMD_USB_PD_PORTS does NOT include the dedicated ports
+ */
+#define EC_CMD_CHARGE_PORT_COUNT 0x0105
+struct ec_response_charge_port_count {
+ uint8_t port_count;
+} __packed;
+
/* Read USB-PD Device discovery info */
#define EC_CMD_USB_PD_DISCOVERY 0x0113
struct ec_params_usb_pd_discovery_entry {
--
2.17.0
[PATCH 2/3] power: supply: cros: add support for dedicated port
ChromeOS devices can have one optional dedicated port.
The Dedicated port is unique and similar to the USB PD ports
except that it doesn't support as many properties.
The presence of a dedicated port is determined from whether the
EC's charger port count is equal to 'number of USB PD port' + 1.
The dedicated port ID is always the last valid port ID.
This commit keeps compatibility with Embedded Controllers that do not
support the new EC_CMD_CHARGE_PORT_COUNT command by setting
the number of charger port to be equal to the number of USB PD port
when this command fails.
Signed-off-by: Fabien Parent
---
drivers/power/supply/cros_usbpd-charger.c | 115 +++---
1 file changed, 101 insertions(+), 14 deletions(-)
diff --git a/drivers/power/supply/cros_usbpd-charger.c
b/drivers/power/supply/cros_usbpd-charger.c
index 3a0c96fd1bc1..808688a6586c 100644
--- a/drivers/power/supply/cros_usbpd-charger.c
+++ b/drivers/power/supply/cros_usbpd-charger.c
@@ -12,8 +12,12 @@
#include
#include
-#define CHARGER_DIR_NAME "CROS_USBPD_CHARGER%d"
-#define CHARGER_DIR_NAME_LENGTHsizeof(CHARGER_DIR_NAME)
+#define CHARGER_USBPD_DIR_NAME "CROS_USBPD_CHARGER%d"
+#define CHARGER_DEDICATED_DIR_NAME "CROS_DEDICATED_CHARGER"
+#define CHARGER_DIR_NAME_LENGTH(sizeof(CHARGER_USBPD_DIR_NAME)
>= \
+sizeof(CHARGER_DEDICATED_DIR_NAME) ? \
+sizeof(CHARGER_USBPD_DIR_NAME) : \
+sizeof(CHARGER_DEDICATED_DIR_NAME))
#define CHARGER_CACHE_UPDATE_DELAY msecs_to_jiffies(500)
#define CHARGER_MANUFACTURER_MODEL_LENGTH 32
@@ -42,6 +46,7 @@ struct charger_data {
struct cros_ec_dev *ec_dev;
struct cros_ec_device *ec_device;
int num_charger_ports;
+ int num_usbpd_ports;
int num_registered_psy;
struct port_data *ports[EC_USB_PD_MAX_PORTS];
struct notifier_block notifier;
@@ -58,6 +63,12 @@ static enum power_supply_property cros_usbpd_charger_props[]
= {
POWER_SUPPLY_PROP_USB_TYPE
};
+static enum power_supply_property cros_usbpd_dedicated_charger_props[] = {
+ POWER_SUPPLY_PROP_ONLINE,
+ POWER_SUPPLY_PROP_STATUS,
+ POWER_SUPPLY_PROP_VOLTAGE_NOW,
+};
+
static enum power_supply_usb_type cros_usbpd_charger_usb_types[] = {
POWER_SUPPLY_USB_TYPE_UNKNOWN,
POWER_SUPPLY_USB_TYPE_SDP,
@@ -69,6 +80,11 @@ static enum power_supply_usb_type
cros_usbpd_charger_usb_types[] = {
POWER_SUPPLY_USB_TYPE_APPLE_BRICK_ID
};
+static bool cros_usbpd_charger_port_is_dedicated(struct port_data *port)
+{
+ return port->port_number >= port->charger->num_usbpd_ports;
+}
+
static int cros_usbpd_charger_ec_command(struct charger_data *charger,
unsigned int version,
unsigned int command,
@@ -102,6 +118,23 @@ static int cros_usbpd_charger_ec_command(struct
charger_data *charger,
}
static int cros_usbpd_charger_get_num_ports(struct charger_data *charger)
+{
+ struct ec_response_charge_port_count resp;
+ int ret;
+
+ ret = cros_usbpd_charger_ec_command(charger, 0,
+ EC_CMD_CHARGE_PORT_COUNT,
+ NULL, 0, , sizeof(resp));
+ if (ret < 0) {
+ dev_err(charger->dev,
+ "Unable to get the number of ports (err:0x%x)\n", ret);
+ return ret;
+ }
+
+ return resp.port_count;
+}
+
+static int cros_usbpd_charger_get_usbpd_num_ports(struct charger_data *charger)
{
struct ec_response_usb_pd_ports resp;
int ret;
@@ -246,7 +279,10 @@ static int cros_usbpd_charger_get_power_info(struct
port_data *port)
port->psy_usb_type = POWER_SUPPLY_USB_TYPE_SDP;
}
- port->psy_desc.type = POWER_SUPPLY_TYPE_USB;
+ if (cros_usbpd_charger_port_is_dedicated(port))
+ port->psy_desc.type = POWER_SUPPLY_TYPE_MAINS;
+ else
+ port->psy_desc.type = POWER_SUPPLY_TYPE_USB;
dev_dbg(dev,
"Port %d: type=%d vmax=%d vnow=%d cmax=%d clim=%d pmax=%d\n",
@@ -281,7 +317,8 @@ static int cros_usbpd_charger_get_port_status(struct
port_data *port,
if (ret < 0)
return ret;
- ret = cros_usbpd_charger_get_discovery_info(port);
+ if (!cros_usbpd_charger_port_is_dedicated(port))
+ ret = cros_usbpd_charger_get_discovery_info(port);
port->last_update = jiffies;
return ret;
@@ -425,17 +462,56 @@ static int cros_usbpd_charger_probe(struct
platform_device *pd)
platform_set_drvdata(pd, charger);
+ /*
+* We need to know the number of USB P
Re: [PATCH 1/3] mfd: cros: add charger port count command definition
On Mon, Jun 4, 2018 at 1:59 AM, Lee Jones wrote: > On Tue, 29 May 2018, Fabien Parent wrote: > >> A new more command has been added to the ChromeOS embedded controller >> that allows to get the number of charger port count. Unlike >> EC_CMD_USB_PD_PORTS, this new command also includes the dedicated >> port if present. >> >> This command will be used to expose the dedicated charger port >> in the ChromeOS charger driver. >> >> Signed-off-by: Fabien Parent >> --- >> include/linux/mfd/cros_ec_commands.h | 10 ++ >> 1 file changed, 10 insertions(+) > > Does not want to apply. I didn't investigate why. > > Please rebase and resend? Sorry, I forgot to add you as "to:" to the patch series. This patch applies on top of https://lkml.org/lkml/2018/5/2/590 ([PATCH v4 1/3] mfd: cros_ec: Add USBPD charger commands and struct definitions) > -- > Lee Jones [李琼斯] > Linaro Services Technical Lead > Linaro.org │ Open source software for ARM SoCs > Follow Linaro: Facebook | Twitter | Blog
Re: [PATCH 0/3] power: supply: cros: add support for dedicated port and expose connected ports
+ Lee Jones for the mfd patch. On Tue, May 29, 2018 at 8:17 PM, Fabien Parent wrote: > Dear all, > > This patch series adds support for an optional dedicated port > to the ChromeOS power supply driver and adds a new property that expose > when a power supply is connected. The series was tested on ChromeOS "Fizz" > hardware. > > This patch series depends on the following patch serie which adds > the ChromeOS power supply driver: > * https://lkml.org/lkml/2018/5/2/585 [PATCH v4 0/3] mfd/power: cros_ec: add >support for USBPD charger driver > > The ChromeOS power supply driver also depends on the following patches to be > applied: > * https://lkml.org/lkml/2018/4/23/602 ([PATCH v8 0/6] typec: tcpm: Add >sink side support for PPS) > * https://lkml.org/lkml/2018/4/18/229 ([RESEND PATCH v5 4/7] mfd: >cros_ec_dev: Register cros-ec-rtc driver as a subdevice.) > > Best Regards, > Fabien > > Fabien Parent (3): > mfd: cros: add charger port count command definition > power: supply: cros: add support for dedicated port > power: supply: cros: add property to detect connected ports > > drivers/power/supply/cros_usbpd-charger.c | 129 +++--- > include/linux/mfd/cros_ec_commands.h | 10 ++ > 2 files changed, 124 insertions(+), 15 deletions(-) > > -- > 2.17.0 >
[PATCH v2 2/3] power: supply: cros: add support for dedicated port
ChromeOS devices can have one optional dedicated port.
The Dedicated port is unique and similar to the USB PD ports
except that it doesn't support as many properties.
The presence of a dedicated port is determined from whether the
EC's charger port count is equal to 'number of USB PD port' + 1.
The dedicated port ID is always the last valid port ID.
This commit keeps compatibility with Embedded Controllers that do not
support the new EC_CMD_CHARGE_PORT_COUNT command by setting
the number of charger port to be equal to the number of USB PD port
when this command fails.
Signed-off-by: Fabien Parent
---
V1 -> V2:
* Rebased
---
drivers/power/supply/cros_usbpd-charger.c | 115 +++---
1 file changed, 101 insertions(+), 14 deletions(-)
diff --git a/drivers/power/supply/cros_usbpd-charger.c
b/drivers/power/supply/cros_usbpd-charger.c
index 688a16bacfbb..fe1502715e46 100644
--- a/drivers/power/supply/cros_usbpd-charger.c
+++ b/drivers/power/supply/cros_usbpd-charger.c
@@ -12,8 +12,12 @@
#include
#include
-#define CHARGER_DIR_NAME "CROS_USBPD_CHARGER%d"
-#define CHARGER_DIR_NAME_LENGTHsizeof(CHARGER_DIR_NAME)
+#define CHARGER_USBPD_DIR_NAME "CROS_USBPD_CHARGER%d"
+#define CHARGER_DEDICATED_DIR_NAME "CROS_DEDICATED_CHARGER"
+#define CHARGER_DIR_NAME_LENGTH(sizeof(CHARGER_USBPD_DIR_NAME)
>= \
+sizeof(CHARGER_DEDICATED_DIR_NAME) ? \
+sizeof(CHARGER_USBPD_DIR_NAME) : \
+sizeof(CHARGER_DEDICATED_DIR_NAME))
#define CHARGER_CACHE_UPDATE_DELAY msecs_to_jiffies(500)
#define CHARGER_MANUFACTURER_MODEL_LENGTH 32
@@ -42,6 +46,7 @@ struct charger_data {
struct cros_ec_dev *ec_dev;
struct cros_ec_device *ec_device;
int num_charger_ports;
+ int num_usbpd_ports;
int num_registered_psy;
struct port_data *ports[EC_USB_PD_MAX_PORTS];
struct notifier_block notifier;
@@ -58,6 +63,12 @@ static enum power_supply_property cros_usbpd_charger_props[]
= {
POWER_SUPPLY_PROP_USB_TYPE
};
+static enum power_supply_property cros_usbpd_dedicated_charger_props[] = {
+ POWER_SUPPLY_PROP_ONLINE,
+ POWER_SUPPLY_PROP_STATUS,
+ POWER_SUPPLY_PROP_VOLTAGE_NOW,
+};
+
static enum power_supply_usb_type cros_usbpd_charger_usb_types[] = {
POWER_SUPPLY_USB_TYPE_UNKNOWN,
POWER_SUPPLY_USB_TYPE_SDP,
@@ -69,6 +80,11 @@ static enum power_supply_usb_type
cros_usbpd_charger_usb_types[] = {
POWER_SUPPLY_USB_TYPE_APPLE_BRICK_ID
};
+static bool cros_usbpd_charger_port_is_dedicated(struct port_data *port)
+{
+ return port->port_number >= port->charger->num_usbpd_ports;
+}
+
static int cros_usbpd_charger_ec_command(struct charger_data *charger,
unsigned int version,
unsigned int command,
@@ -102,6 +118,23 @@ static int cros_usbpd_charger_ec_command(struct
charger_data *charger,
}
static int cros_usbpd_charger_get_num_ports(struct charger_data *charger)
+{
+ struct ec_response_charge_port_count resp;
+ int ret;
+
+ ret = cros_usbpd_charger_ec_command(charger, 0,
+ EC_CMD_CHARGE_PORT_COUNT,
+ NULL, 0, , sizeof(resp));
+ if (ret < 0) {
+ dev_err(charger->dev,
+ "Unable to get the number of ports (err:0x%x)\n", ret);
+ return ret;
+ }
+
+ return resp.port_count;
+}
+
+static int cros_usbpd_charger_get_usbpd_num_ports(struct charger_data *charger)
{
struct ec_response_usb_pd_ports resp;
int ret;
@@ -246,7 +279,10 @@ static int cros_usbpd_charger_get_power_info(struct
port_data *port)
port->psy_usb_type = POWER_SUPPLY_USB_TYPE_SDP;
}
- port->psy_desc.type = POWER_SUPPLY_TYPE_USB;
+ if (cros_usbpd_charger_port_is_dedicated(port))
+ port->psy_desc.type = POWER_SUPPLY_TYPE_MAINS;
+ else
+ port->psy_desc.type = POWER_SUPPLY_TYPE_USB;
dev_dbg(dev,
"Port %d: type=%d vmax=%d vnow=%d cmax=%d clim=%d pmax=%d\n",
@@ -281,7 +317,8 @@ static int cros_usbpd_charger_get_port_status(struct
port_data *port,
if (ret < 0)
return ret;
- ret = cros_usbpd_charger_get_discovery_info(port);
+ if (!cros_usbpd_charger_port_is_dedicated(port))
+ ret = cros_usbpd_charger_get_discovery_info(port);
port->last_update = jiffies;
return ret;
@@ -426,17 +463,56 @@ static int cros_usbpd_charger_probe(struct
platform_device *pd)
platform_set_drvdata(pd, charger);
+ /*
+* We need to k
[PATCH v2 3/3] power: supply: cros: add property to detect connected ports
When a port is connected but acting as a source, its 'online' and
'status' properties are identical to a port that is not connected. This
makes it tedious for userspace to know for sure whether a port is
connected or not.
This commit adds a new property 'present' to reflect whether a port
is connected or not.
Signed-off-by: Fabien Parent
---
V1 -> V2:
* No change
---
drivers/power/supply/cros_usbpd-charger.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/power/supply/cros_usbpd-charger.c
b/drivers/power/supply/cros_usbpd-charger.c
index fe1502715e46..6307424f36ec 100644
--- a/drivers/power/supply/cros_usbpd-charger.c
+++ b/drivers/power/supply/cros_usbpd-charger.c
@@ -32,6 +32,7 @@ struct port_data {
struct power_supply_desc psy_desc;
int psy_usb_type;
int psy_online;
+ int psy_present;
int psy_status;
int psy_current_max;
int psy_voltage_max_design;
@@ -54,6 +55,7 @@ struct charger_data {
static enum power_supply_property cros_usbpd_charger_props[] = {
POWER_SUPPLY_PROP_ONLINE,
+ POWER_SUPPLY_PROP_PRESENT,
POWER_SUPPLY_PROP_STATUS,
POWER_SUPPLY_PROP_CURRENT_MAX,
POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN,
@@ -65,6 +67,7 @@ static enum power_supply_property cros_usbpd_charger_props[]
= {
static enum power_supply_property cros_usbpd_dedicated_charger_props[] = {
POWER_SUPPLY_PROP_ONLINE,
+ POWER_SUPPLY_PROP_PRESENT,
POWER_SUPPLY_PROP_STATUS,
POWER_SUPPLY_PROP_VOLTAGE_NOW,
};
@@ -205,18 +208,22 @@ static int cros_usbpd_charger_get_power_info(struct
port_data *port)
case USB_PD_PORT_POWER_DISCONNECTED:
port->psy_status = POWER_SUPPLY_STATUS_NOT_CHARGING;
port->psy_online = 0;
+ port->psy_present = 0;
break;
case USB_PD_PORT_POWER_SOURCE:
port->psy_status = POWER_SUPPLY_STATUS_NOT_CHARGING;
port->psy_online = 0;
+ port->psy_present = 1;
break;
case USB_PD_PORT_POWER_SINK:
port->psy_status = POWER_SUPPLY_STATUS_CHARGING;
port->psy_online = 1;
+ port->psy_present = 1;
break;
case USB_PD_PORT_POWER_SINK_NOT_CHARGING:
port->psy_status = POWER_SUPPLY_STATUS_NOT_CHARGING;
port->psy_online = 1;
+ port->psy_present = 1;
break;
default:
dev_err(dev, "Unknown role %d\n", resp.role);
@@ -363,6 +370,7 @@ static int cros_usbpd_charger_get_prop(struct power_supply
*psy,
if (ec_device->mkbp_event_supported || port->psy_online)
break;
/* fall through */
+ case POWER_SUPPLY_PROP_PRESENT:
case POWER_SUPPLY_PROP_CURRENT_MAX:
case POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN:
case POWER_SUPPLY_PROP_VOLTAGE_NOW:
@@ -381,6 +389,9 @@ static int cros_usbpd_charger_get_prop(struct power_supply
*psy,
case POWER_SUPPLY_PROP_ONLINE:
val->intval = port->psy_online;
break;
+ case POWER_SUPPLY_PROP_PRESENT:
+ val->intval = port->psy_present;
+ break;
case POWER_SUPPLY_PROP_STATUS:
val->intval = port->psy_status;
break;
--
2.18.0
[PATCH v2 1/3] mfd: cros: add charger port count command definition
A new more command has been added to the ChromeOS embedded controller
that allows to get the number of charger port count. Unlike
EC_CMD_USB_PD_PORTS, this new command also includes the dedicated
port if present.
This command will be used to expose the dedicated charger port
in the ChromeOS charger driver.
Signed-off-by: Fabien Parent
Acked-for-MFD-by: Lee Jones
---
V1 -> V2:
* No change
---
include/linux/mfd/cros_ec_commands.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/include/linux/mfd/cros_ec_commands.h
b/include/linux/mfd/cros_ec_commands.h
index 0d926492ac3a..e3187f8bdb7e 100644
--- a/include/linux/mfd/cros_ec_commands.h
+++ b/include/linux/mfd/cros_ec_commands.h
@@ -3005,6 +3005,16 @@ struct ec_params_usb_pd_info_request {
uint8_t port;
} __packed;
+/*
+ * This command will return the number of USB PD charge port + the number
+ * of dedicated port present.
+ * EC_CMD_USB_PD_PORTS does NOT include the dedicated ports
+ */
+#define EC_CMD_CHARGE_PORT_COUNT 0x0105
+struct ec_response_charge_port_count {
+ uint8_t port_count;
+} __packed;
+
/* Read USB-PD Device discovery info */
#define EC_CMD_USB_PD_DISCOVERY 0x0113
struct ec_params_usb_pd_discovery_entry {
--
2.18.0
[PATCH v2 0/3] power: supply: cros: add support for dedicated port and expose connected ports
Dear all, This patch series adds support for an optional dedicated port to the ChromeOS power supply driver and adds a new property that expose when a power supply is connected. The series was tested on ChromeOS "Fizz" hardware. This patch series depends on the following patch serie which adds the ChromeOS power supply driver: * https://lkml.org/lkml/2018/5/2/585 [PATCH v4 0/3] mfd/power: cros_ec: add support for USBPD charger driver The ChromeOS power supply driver also depends on the following patches to be applied: * https://lkml.org/lkml/2018/4/23/602 ([PATCH v8 0/6] typec: tcpm: Add sink side support for PPS) * https://lkml.org/lkml/2018/4/18/229 ([RESEND PATCH v5 4/7] mfd: cros_ec_dev: Register cros-ec-rtc driver as a subdevice.) Best Regards, Fabien V2: * Rebased to fixed apply issue with patch #2 Fabien Parent (3): mfd: cros: add charger port count command definition power: supply: cros: add support for dedicated port power: supply: cros: add property to detect connected ports drivers/power/supply/cros_usbpd-charger.c | 126 +++--- include/linux/mfd/cros_ec_commands.h | 10 ++ 2 files changed, 122 insertions(+), 14 deletions(-) -- 2.18.0
[PATCH 2/2] arm64: dts: mediatek: mt8516: add usb1 node
The MT8516 has 2 USB instances. Add support for the second USB instance.
usb1 can only work in host mode.
Signed-off-by: Fabien Parent
---
arch/arm64/boot/dts/mediatek/mt8516.dtsi | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8516.dtsi
b/arch/arm64/boot/dts/mediatek/mt8516.dtsi
index 50049b6c1ba7..eca7969e15ab 100644
--- a/arch/arm64/boot/dts/mediatek/mt8516.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8516.dtsi
@@ -455,6 +455,20 @@ usb0: usb@1110 {
status = "disabled";
};
+ usb1: usb@1119 {
+ compatible = "mediatek,mtk-musb";
+ reg = <0 0x1119 0 0x1000>;
+ interrupts = ;
+ interrupt-names = "mc";
+ phys = <_port PHY_TYPE_USB2>;
+ clocks = < CLK_TOP_USB>,
+< CLK_TOP_USBIF>,
+< CLK_TOP_USB_1P>;
+ clock-names = "main","mcu","univpll";
+ dr_mode = "host";
+ status = "disabled";
+ };
+
usb_phy: usb@ {
compatible = "mediatek,generic-tphy-v1";
reg = <0 0x 0 0x800>;
@@ -469,6 +483,13 @@ usb0_port: usb-phy@0800 {
clock-names = "ref";
#phy-cells = <1>;
};
+
+ usb1_port: usb-phy@0900 {
+ reg = <0 0x0900 0 0x100>;
+ clocks = < CLK_TOP_USB_PHY48M>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ };
};
auxadc: adc@11003000 {
--
2.28.0
[PATCH 1/2] arm64: dts: mediatek: mt8516: rename usb phy
The USB phy node is named usb0_phy but there is only one phy with
2 ports on MT8516. Rename the phy to make it more obvious it can
also support the usb1 node.
The usb1 node will be added in a follow-up commit.
Signed-off-by: Fabien Parent
---
arch/arm64/boot/dts/mediatek/mt8516.dtsi | 2 +-
arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8516.dtsi
b/arch/arm64/boot/dts/mediatek/mt8516.dtsi
index 943c426e9aaf..50049b6c1ba7 100644
--- a/arch/arm64/boot/dts/mediatek/mt8516.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8516.dtsi
@@ -455,7 +455,7 @@ usb0: usb@1110 {
status = "disabled";
};
- usb0_phy: usb@ {
+ usb_phy: usb@ {
compatible = "mediatek,generic-tphy-v1";
reg = <0 0x 0 0x800>;
#address-cells = <2>;
diff --git a/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi
b/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi
index dfceffe6950a..8bad8faf35d2 100644
--- a/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi
+++ b/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi
@@ -195,7 +195,7 @@ usb_con: connector {
};
};
-_phy {
+_phy {
status = "okay";
};
--
2.28.0
Re: [PATCH v2 2/2] drm/mediatek: mtk_hdmi: add MT8167 support for HDMI
Hi Chun-Kuang,
On Wed, Oct 14, 2020 at 3:00 PM Chun-Kuang Hu wrote:
>
> Hi, Fabien:
>
> Fabien Parent 於 2020年10月14日 週三 上午2:19寫道：
> >
> > Add support for HDMI on MT8167. HDMI on MT8167 is similar to
> > MT8173/MT2701 execpt for the two registers: SYS_CFG1C and SYS_CFG20
>
> I think you should drop this series. According to Mediatek HDMI
> binding document [1], the second parameter of mediatek,syscon-hdmi is
> the register offset. I think you could set register offset to 0x800
> for mt8167.
Ok, thank you. I will try it.
>
> [1]
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt?h=v5.9
>
> Regards,
> Chun-Kuang.
>
> >
> > Signed-off-by: Fabien Parent
> > ---
> >
> > Changelog:
> > v2: fix name of pdata structure
> >
> > drivers/gpu/drm/mediatek/mtk_hdmi.c | 7 +++
> > drivers/gpu/drm/mediatek/mtk_hdmi_regs.h | 2 ++
> > 2 files changed, 9 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c
> > b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> > index 57370c036497..484ea9cd654a 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> > @@ -1835,9 +1835,16 @@ static struct mtk_hdmi_data mt8173_hdmi_driver_data
> > = {
> > .sys_cfg20 = HDMI_SYS_CFG20,
> > };
> >
> > +static struct mtk_hdmi_data mt8167_hdmi_driver_data = {
> > + .sys_cfg1c = MT8167_HDMI_SYS_CFG1C,
> > + .sys_cfg20 = MT8167_HDMI_SYS_CFG20,
> > +};
> > +
> > static const struct of_device_id mtk_drm_hdmi_of_ids[] = {
> > { .compatible = "mediatek,mt8173-hdmi",
> > .data = _hdmi_driver_data },
> > + { .compatible = "mediatek,mt8167-hdmi",
> > + .data = _hdmi_driver_data },
> > {}
> > };
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_regs.h
> > b/drivers/gpu/drm/mediatek/mtk_hdmi_regs.h
> > index 2050ba45b23a..a0f9c367d7aa 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_hdmi_regs.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_regs.h
> > @@ -195,6 +195,7 @@
> > #define GEN_RGB(0 << 7)
> >
> > #define HDMI_SYS_CFG1C 0x000
> > +#define MT8167_HDMI_SYS_CFG1C 0x800
> > #define HDMI_ONBIT(0)
> > #define HDMI_RST BIT(1)
> > #define ANLG_ONBIT(2)
> > @@ -211,6 +212,7 @@
> > #define HTPLG_PIN_SEL_OFF BIT(30)
> > #define AES_EFUSE_ENABLE BIT(31)
> > #define HDMI_SYS_CFG20 0x004
> > +#define MT8167_HDMI_SYS_CFG20 0x804
> > #define DEEP_COLOR_MODE_MASK (3 << 1)
> > #define COLOR_8BIT_MODE(0 << 1)
> > #define COLOR_10BIT_MODE (1 << 1)
> > --
> > 2.28.0
> >
Re: [PATCH v2 2/2] drm/mediatek: mtk_hdmi: add MT8167 support for HDMI
Hi Chun-Kuang,
On Wed, Oct 14, 2020 at 6:25 PM Fabien Parent wrote:
>
> Hi Chun-Kuang,
>
> On Wed, Oct 14, 2020 at 3:00 PM Chun-Kuang Hu wrote:
> >
> > Hi, Fabien:
> >
> > Fabien Parent 於 2020年10月14日 週三 上午2:19寫道：
> > >
> > > Add support for HDMI on MT8167. HDMI on MT8167 is similar to
> > > MT8173/MT2701 execpt for the two registers: SYS_CFG1C and SYS_CFG20
> >
> > I think you should drop this series. According to Mediatek HDMI
> > binding document [1], the second parameter of mediatek,syscon-hdmi is
> > the register offset. I think you could set register offset to 0x800
> > for mt8167.
> Ok, thank you. I will try it.
Thanks, it works. Dropping this series.
>
> >
> > [1]
> > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt?h=v5.9
> >
> > Regards,
> > Chun-Kuang.
> >
> > >
> > > Signed-off-by: Fabien Parent
> > > ---
> > >
> > > Changelog:
> > > v2: fix name of pdata structure
> > >
> > > drivers/gpu/drm/mediatek/mtk_hdmi.c | 7 +++
> > > drivers/gpu/drm/mediatek/mtk_hdmi_regs.h | 2 ++
> > > 2 files changed, 9 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c
> > > b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> > > index 57370c036497..484ea9cd654a 100644
> > > --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
> > > +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> > > @@ -1835,9 +1835,16 @@ static struct mtk_hdmi_data
> > > mt8173_hdmi_driver_data = {
> > > .sys_cfg20 = HDMI_SYS_CFG20,
> > > };
> > >
> > > +static struct mtk_hdmi_data mt8167_hdmi_driver_data = {
> > > + .sys_cfg1c = MT8167_HDMI_SYS_CFG1C,
> > > + .sys_cfg20 = MT8167_HDMI_SYS_CFG20,
> > > +};
> > > +
> > > static const struct of_device_id mtk_drm_hdmi_of_ids[] = {
> > > { .compatible = "mediatek,mt8173-hdmi",
> > > .data = _hdmi_driver_data },
> > > + { .compatible = "mediatek,mt8167-hdmi",
> > > + .data = _hdmi_driver_data },
> > > {}
> > > };
> > >
> > > diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_regs.h
> > > b/drivers/gpu/drm/mediatek/mtk_hdmi_regs.h
> > > index 2050ba45b23a..a0f9c367d7aa 100644
> > > --- a/drivers/gpu/drm/mediatek/mtk_hdmi_regs.h
> > > +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_regs.h
> > > @@ -195,6 +195,7 @@
> > > #define GEN_RGB(0 << 7)
> > >
> > > #define HDMI_SYS_CFG1C 0x000
> > > +#define MT8167_HDMI_SYS_CFG1C 0x800
> > > #define HDMI_ONBIT(0)
> > > #define HDMI_RST BIT(1)
> > > #define ANLG_ONBIT(2)
> > > @@ -211,6 +212,7 @@
> > > #define HTPLG_PIN_SEL_OFF BIT(30)
> > > #define AES_EFUSE_ENABLE BIT(31)
> > > #define HDMI_SYS_CFG20 0x004
> > > +#define MT8167_HDMI_SYS_CFG20 0x804
> > > #define DEEP_COLOR_MODE_MASK (3 << 1)
> > > #define COLOR_8BIT_MODE(0 << 1)
> > > #define COLOR_10BIT_MODE (1 << 1)
> > > --
> > > 2.28.0
> > >
[PATCH 1/2] dt-bindings: dma: mtk-apdma: add bindings for MT8516 SOC
Add bindings to APDMA for MT8516 SoC. MT8516 is compatible with MT6577. Signed-off-by: Fabien Parent --- Documentation/devicetree/bindings/dma/mtk-uart-apdma.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/dma/mtk-uart-apdma.txt b/Documentation/devicetree/bindings/dma/mtk-uart-apdma.txt index 2117db0ce4f2..fef9c1eeb264 100644 --- a/Documentation/devicetree/bindings/dma/mtk-uart-apdma.txt +++ b/Documentation/devicetree/bindings/dma/mtk-uart-apdma.txt @@ -4,6 +4,7 @@ Required properties: - compatible should contain: * "mediatek,mt2712-uart-dma" for MT2712 compatible APDMA * "mediatek,mt6577-uart-dma" for MT6577 and all of the above + * "mediatek,mt8516-uart-dma", "mediatek,mt6577" for MT8516 SoC - reg: The base address of the APDMA register bank. -- 2.28.0
[PATCH 2/2] arm64: dts: mediatek: mt8516: add support for APDMA
Add support the APDMA IP on MT8516. APDMA is a DMA controller
for UARTs.
Signed-off-by: Fabien Parent
---
arch/arm64/boot/dts/mediatek/mt8516.dtsi | 27
1 file changed, 27 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8516.dtsi
b/arch/arm64/boot/dts/mediatek/mt8516.dtsi
index eca7969e15ab..a017664f8eed 100644
--- a/arch/arm64/boot/dts/mediatek/mt8516.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8516.dtsi
@@ -269,6 +269,27 @@ gic: interrupt-controller@1031 {
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
+ apdma: dma-controller@11000480 {
+ compatible = "mediatek,mt8516-uart-dma",
+"mediatek,mt6577-uart-dma";
+ reg = <0 0x11000480 0 0x80>,
+ <0 0x11000500 0 0x80>,
+ <0 0x11000580 0 0x80>,
+ <0 0x11000600 0 0x80>,
+ <0 0x11000980 0 0x80>,
+ <0 0x11000a00 0 0x80>;
+ interrupts = ,
+,
+,
+,
+,
+;
+ dma-requests = <6>;
+ clocks = < CLK_TOP_APDMA>;
+ clock-names = "apdma";
+ #dma-cells = <1>;
+ };
+
uart0: serial@11005000 {
compatible = "mediatek,mt8516-uart",
"mediatek,mt6577-uart";
@@ -277,6 +298,8 @@ uart0: serial@11005000 {
clocks = < CLK_TOP_UART0_SEL>,
< CLK_TOP_UART0>;
clock-names = "baud", "bus";
+ dmas = < 0
+1>;
status = "disabled";
};
@@ -288,6 +311,8 @@ uart1: serial@11006000 {
clocks = < CLK_TOP_UART1_SEL>,
< CLK_TOP_UART1>;
clock-names = "baud", "bus";
+ dmas = < 2
+3>;
status = "disabled";
};
@@ -299,6 +324,8 @@ uart2: serial@11007000 {
clocks = < CLK_TOP_UART2_SEL>,
< CLK_TOP_UART2>;
clock-names = "baud", "bus";
+ dmas = < 4
+5>;
status = "disabled";
};
--
2.28.0
[PATCH 2/2] arm64: dts: mediatek: mt8516: add efuse node
Add node to support e-fuses on MT8516
Signed-off-by: Fabien Parent
---
arch/arm64/boot/dts/mediatek/mt8516.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8516.dtsi
b/arch/arm64/boot/dts/mediatek/mt8516.dtsi
index 89af661e7f63..18ddea519be2 100644
--- a/arch/arm64/boot/dts/mediatek/mt8516.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8516.dtsi
@@ -237,6 +237,13 @@ pio: pinctrl@1000b000 {
interrupts = ;
};
+ efuse: efuse@10009000 {
+ compatible = "mediatek,mt8516-efuse", "mediatek,efuse";
+ reg = <0 0x10009000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
pwrap: pwrap@1000f000 {
compatible = "mediatek,mt8516-pwrap";
reg = <0 0x1000f000 0 0x1000>;
--
2.28.0
[PATCH 1/2] dt-bindings: nvmem: mtk-efuse: add documentation for MT8516 SoC
Add binding documentation for MT8516 SoCs. Signed-off-by: Fabien Parent --- Documentation/devicetree/bindings/nvmem/mtk-efuse.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/nvmem/mtk-efuse.txt b/Documentation/devicetree/bindings/nvmem/mtk-efuse.txt index 0668c45a156d..ef93c3b95424 100644 --- a/Documentation/devicetree/bindings/nvmem/mtk-efuse.txt +++ b/Documentation/devicetree/bindings/nvmem/mtk-efuse.txt @@ -7,6 +7,7 @@ Required properties: "mediatek,mt7622-efuse", "mediatek,efuse": for MT7622 "mediatek,mt7623-efuse", "mediatek,efuse": for MT7623 "mediatek,mt8173-efuse" or "mediatek,efuse": for MT8173 + "mediatek,mt8516-efuse", "mediatek,efuse": for MT8516 - reg: Should contain registers location and length = Data cells = -- 2.28.0
[PATCH] dt-bindings: pwm: mtk-disp: add MT8167 SoC binding
Add binding for MT8167 SoC. The IP is compatible with MT8173. Signed-off-by: Fabien Parent --- Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt b/Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt index 0521957c253f..902b271891ae 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt @@ -4,6 +4,7 @@ Required properties: - compatible: should be "mediatek,-disp-pwm": - "mediatek,mt2701-disp-pwm": found on mt2701 SoC. - "mediatek,mt6595-disp-pwm": found on mt6595 SoC. + - "mediatek,mt8167-disp-pwm", "mediatek,mt8173-disp-pwm": found on mt8167 SoC. - "mediatek,mt8173-disp-pwm": found on mt8173 SoC. - reg: physical base address and length of the controller's registers. - #pwm-cells: must be 2. See pwm.yaml in this directory for a description of -- 2.28.0
[PATCH v2 RESEND 1/2] dt-bindings: clock: mediatek: add bindings for MT8167 clocks
Add binding documentation for topckgen, apmixedsys, infracfg, audsys, imgsys, mfgcfg, vdecsys on MT8167 SoC. Signed-off-by: Fabien Parent Reviewed-by: Rob Herring --- ChangeLog: V2: no changes .../arm/mediatek/mediatek,apmixedsys.txt | 1 + .../bindings/arm/mediatek/mediatek,audsys.txt | 1 + .../bindings/arm/mediatek/mediatek,imgsys.txt | 1 + .../arm/mediatek/mediatek,infracfg.txt| 1 + .../bindings/arm/mediatek/mediatek,mfgcfg.txt | 1 + .../arm/mediatek/mediatek,topckgen.txt| 1 + .../arm/mediatek/mediatek,vdecsys.txt | 1 + include/dt-bindings/clock/mt8167-clk.h| 131 ++ 8 files changed, 138 insertions(+) create mode 100644 include/dt-bindings/clock/mt8167-clk.h diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt index bd7a0fa5801b..ea827e8763de 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt @@ -15,6 +15,7 @@ Required Properties: - "mediatek,mt7623-apmixedsys", "mediatek,mt2701-apmixedsys" - "mediatek,mt7629-apmixedsys" - "mediatek,mt8135-apmixedsys" + - "mediatek,mt8167-apmixedsys", "syscon" - "mediatek,mt8173-apmixedsys" - "mediatek,mt8183-apmixedsys", "syscon" - "mediatek,mt8516-apmixedsys" diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt index 38309db115f5..b32d374193c7 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt @@ -11,6 +11,7 @@ Required Properties: - "mediatek,mt6779-audio", "syscon" - "mediatek,mt7622-audsys", "syscon" - "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon" + - "mediatek,mt8167-audiosys", "syscon" - "mediatek,mt8183-audiosys", "syscon" - "mediatek,mt8516-audsys", "syscon" - #clock-cells: Must be 1 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt index 1e1f00718a7d..dce4c9241932 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt @@ -12,6 +12,7 @@ Required Properties: - "mediatek,mt6779-imgsys", "syscon" - "mediatek,mt6797-imgsys", "syscon" - "mediatek,mt7623-imgsys", "mediatek,mt2701-imgsys", "syscon" + - "mediatek,mt8167-imgsys", "syscon" - "mediatek,mt8173-imgsys", "syscon" - "mediatek,mt8183-imgsys", "syscon" - #clock-cells: Must be 1 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt index 49a968be1a80..eb3523c7a7be 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt @@ -16,6 +16,7 @@ Required Properties: - "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon" - "mediatek,mt7629-infracfg", "syscon" - "mediatek,mt8135-infracfg", "syscon" + - "mediatek,mt8167-infracfg", "syscon" - "mediatek,mt8173-infracfg", "syscon" - "mediatek,mt8183-infracfg", "syscon" - "mediatek,mt8516-infracfg", "syscon" diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt index ad5f9d2f6818..054424fb64b4 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt @@ -8,6 +8,7 @@ Required Properties: - compatible: Should be one of: - "mediatek,mt2712-mfgcfg", "syscon" - "mediatek,mt6779-mfgcfg", "syscon" + - "mediatek,mt8167-mfgcfg", "syscon" - "mediatek,mt8183-mfgcfg", "syscon" - #clock-cells: Must be 1 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt index 9b0394cbb
[PATCH v2 RESEND 2/2] clk: mediatek: Add MT8167 clock support
Add the following clock support for MT8167 SoC: topckgen, apmixedsys,
infracfg, audsys, imgsys, mfgcfg, vdecsys.
Signed-off-by: Fabien Parent
---
ChangeLog:
V2: removed unused variable reported by kernel test robot
drivers/clk/mediatek/Kconfig | 48 +
drivers/clk/mediatek/Makefile|6 +
drivers/clk/mediatek/clk-mt8167-aud.c| 66 ++
drivers/clk/mediatek/clk-mt8167-img.c| 60 ++
drivers/clk/mediatek/clk-mt8167-mfgcfg.c | 58 ++
drivers/clk/mediatek/clk-mt8167-mm.c | 132 +++
drivers/clk/mediatek/clk-mt8167-vdec.c | 73 ++
drivers/clk/mediatek/clk-mt8167.c| 1062 ++
8 files changed, 1505 insertions(+)
create mode 100644 drivers/clk/mediatek/clk-mt8167-aud.c
create mode 100644 drivers/clk/mediatek/clk-mt8167-img.c
create mode 100644 drivers/clk/mediatek/clk-mt8167-mfgcfg.c
create mode 100644 drivers/clk/mediatek/clk-mt8167-mm.c
create mode 100644 drivers/clk/mediatek/clk-mt8167-vdec.c
create mode 100644 drivers/clk/mediatek/clk-mt8167.c
diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 89ceb2fbc7c4..ce8475098b31 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -352,6 +352,54 @@ config COMMON_CLK_MT8135
help
This driver supports MediaTek MT8135 clocks.
+config COMMON_CLK_MT8167
+ bool "Clock driver for MediaTek MT8167"
+ depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
+ select COMMON_CLK_MEDIATEK
+ default ARCH_MEDIATEK
+ help
+ This driver supports MediaTek MT8167 basic clocks.
+
+config COMMON_CLK_MT8167_AUDSYS
+ bool "Clock driver for MediaTek MT8167 audsys"
+ depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
+ select COMMON_CLK_MEDIATEK
+ default ARCH_MEDIATEK
+ help
+ This driver supports MediaTek MT8167 audsys clocks.
+
+config COMMON_CLK_MT8167_IMGSYS
+ bool "Clock driver for MediaTek MT8167 imgsys"
+ depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
+ select COMMON_CLK_MEDIATEK
+ default ARCH_MEDIATEK
+ help
+ This driver supports MediaTek MT8167 imgsys clocks.
+
+config COMMON_CLK_MT8167_MFGCFG
+ bool "Clock driver for MediaTek MT8167 mfgcfg"
+ depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
+ select COMMON_CLK_MEDIATEK
+ default ARCH_MEDIATEK
+ help
+ This driver supports MediaTek MT8167 mfgcfg clocks.
+
+config COMMON_CLK_MT8167_MMSYS
+ bool "Clock driver for MediaTek MT8167 mmsys"
+ depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
+ select COMMON_CLK_MEDIATEK
+ default ARCH_MEDIATEK
+ help
+ This driver supports MediaTek MT8167 mmsys clocks.
+
+config COMMON_CLK_MT8167_VDECSYS
+ bool "Clock driver for MediaTek MT8167 vdecsys"
+ depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
+ select COMMON_CLK_MEDIATEK
+ default ARCH_MEDIATEK
+ help
+ This driver supports MediaTek MT8167 vdecsys clocks.
+
config COMMON_CLK_MT8173
bool "Clock driver for MediaTek MT8173"
depends on ARCH_MEDIATEK || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 959b556d32ea..3b0c2be73824 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -47,6 +47,12 @@ obj-$(CONFIG_COMMON_CLK_MT7629) += clk-mt7629.o
obj-$(CONFIG_COMMON_CLK_MT7629_ETHSYS) += clk-mt7629-eth.o
obj-$(CONFIG_COMMON_CLK_MT7629_HIFSYS) += clk-mt7629-hif.o
obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
+obj-$(CONFIG_COMMON_CLK_MT8167) += clk-mt8167.o
+obj-$(CONFIG_COMMON_CLK_MT8167_AUDSYS) += clk-mt8167-aud.o
+obj-$(CONFIG_COMMON_CLK_MT8167_IMGSYS) += clk-mt8167-img.o
+obj-$(CONFIG_COMMON_CLK_MT8167_MFGCFG) += clk-mt8167-mfgcfg.o
+obj-$(CONFIG_COMMON_CLK_MT8167_MMSYS) += clk-mt8167-mm.o
+obj-$(CONFIG_COMMON_CLK_MT8167_VDECSYS) += clk-mt8167-vdec.o
obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173.o
obj-$(CONFIG_COMMON_CLK_MT8173_MMSYS) += clk-mt8173-mm.o
obj-$(CONFIG_COMMON_CLK_MT8183) += clk-mt8183.o
diff --git a/drivers/clk/mediatek/clk-mt8167-aud.c
b/drivers/clk/mediatek/clk-mt8167-aud.c
new file mode 100644
index ..3f7bf6485792
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8167-aud.c
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2020 MediaTek Inc.
+ * Copyright (c) 2020 BayLibre, SAS
+ * Author: James Liao
+ * Fabien Parent
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include
+
+static const struct mtk_gate_regs aud_cg_regs = {
+ .set_ofs = 0x0,
+ .clr_ofs = 0x0,
+ .sta_ofs = 0x0,
+};
+
+#define GATE_AUD(_id, _name, _parent, _shift) {\
+ .id = _id,
Re: [PATCH v5 3/3] mfd: mt6397: Add support for MT6392 pmic
On Tue, Sep 8, 2020 at 3:53 PM Lee Jones wrote:
>
> On Mon, 07 Sep 2020, Fabien Parent wrote:
>
> > Update the MT6397 MFD driver to support the MT6392 PMIC.
> >
> > Signed-off-by: Fabien Parent
> > ---
> >
> > V5:
> > * Rebased
> > * removed mt6392-regulator compatible. This will be send in another
> > series to make this series easier to merge.
> >
> > V4:
> > * Use DEFINE_RES_* macro to define RTC ressources.
> > * Use PLATFORM_DEVID_NONE instead of -1 value when registering
> > devices.
> >
> > V3:
> > * No change
> >
> > V2:
> > * Pass IRQ comain to fix invalid MFD devices IRQs.
> > * Remove resources and mfd cells for device we don't support.
> > * Rename IRQ names to follow what's done for MT6397.
> >
> > ---
>
> You shouldn't need to add your own '---' marker.
>
> Just place the changelog under the existing one.
>
> > drivers/mfd/mt6397-core.c| 40 +++
> > drivers/mfd/mt6397-irq.c | 9 +
> > include/linux/mfd/mt6392/core.h | 42 +++
> > include/linux/mfd/mt6392/registers.h | 487 +++
> > include/linux/mfd/mt6397/core.h | 1 +
> > 5 files changed, 579 insertions(+)
> > create mode 100644 include/linux/mfd/mt6392/core.h
> > create mode 100644 include/linux/mfd/mt6392/registers.h
> >
> > diff --git a/drivers/mfd/mt6397-core.c b/drivers/mfd/mt6397-core.c
> > index f6cd8a660602..6ba3585b1b36 100644
> > --- a/drivers/mfd/mt6397-core.c
> > +++ b/drivers/mfd/mt6397-core.c
> > @@ -13,9 +13,11 @@
> > #include
> > #include
> > #include
> > +#include
> > #include
> > #include
> > #include
> > +#include
> > #include
> >
> > #define MT6323_RTC_BASE 0x8000
> > @@ -27,6 +29,9 @@
> > #define MT6397_RTC_BASE 0xe000
> > #define MT6397_RTC_SIZE 0x3e
> >
> > +#define MT6392_RTC_BASE 0x8000
> > +#define MT6392_RTC_SIZE 0x3e
> > +
>
> Nit: Why aren't these (all) in the header files above?
Not sure, I just followed what people did previously here.
>
> > #define MT6323_PWRC_BASE 0x8000
> > #define MT6323_PWRC_SIZE 0x40
> >
> > @@ -40,6 +45,11 @@ static const struct resource mt6358_rtc_resources[] = {
> > DEFINE_RES_IRQ(MT6358_IRQ_RTC),
> > };
> >
> > +static const struct resource mt6392_rtc_resources[] = {
> > + DEFINE_RES_MEM(MT6392_RTC_BASE, MT6392_RTC_SIZE),
> > + DEFINE_RES_IRQ(MT6392_IRQ_RTC),
> > +};
> > +
> > static const struct resource mt6397_rtc_resources[] = {
> > DEFINE_RES_MEM(MT6397_RTC_BASE, MT6397_RTC_SIZE),
> > DEFINE_RES_IRQ(MT6397_IRQ_RTC),
> > @@ -50,6 +60,11 @@ static const struct resource mt6323_keys_resources[] = {
> > DEFINE_RES_IRQ(MT6323_IRQ_STATUS_FCHRKEY),
> > };
> >
> > +static const struct resource mt6392_keys_resources[] = {
> > + DEFINE_RES_IRQ(MT6392_IRQ_PWRKEY),
> > + DEFINE_RES_IRQ(MT6392_IRQ_FCHRKEY),
> > +};
> > +
> > static const struct resource mt6397_keys_resources[] = {
> > DEFINE_RES_IRQ(MT6397_IRQ_PWRKEY),
> > DEFINE_RES_IRQ(MT6397_IRQ_HOMEKEY),
> > @@ -99,6 +114,20 @@ static const struct mfd_cell mt6358_devs[] = {
> > },
> > };
> >
> > +static const struct mfd_cell mt6392_devs[] = {
> > + {
> > + .name = "mt6397-rtc",
> > + .num_resources = ARRAY_SIZE(mt6392_rtc_resources),
> > + .resources = mt6392_rtc_resources,
> > + .of_compatible = "mediatek,mt6392-rtc",
> > + }, {
> > + .name = "mtk-pmic-keys",
> > + .num_resources = ARRAY_SIZE(mt6392_keys_resources),
> > + .resources = mt6392_keys_resources,
> > + .of_compatible = "mediatek,mt6392-keys"
> > + },
> > +};
> > +
> > static const struct mfd_cell mt6397_devs[] = {
> > {
> > .name = "mt6397-rtc",
> > @@ -149,6 +178,14 @@ static const struct chip_data mt6358_core = {
> > .irq_init = mt6358_irq_init,
> > };
> >
> > +static const struct chip_data mt6392_core = {
> > + .cid_addr = MT6392_CID,
> > + .cid_shift = 0,
> > + .cells = mt6392_devs,
> > + .cell_size = ARRAY_SIZE(mt6392_devs),
> > + .irq_init = mt6397_irq_init,
> > +};
> > +
&
[PATCH v6 1/3] dt-bindings: mfd: mt6397: Add bindings for MT6392 PMIC
Add the currently supported bindings for the MT6392 PMIC. Signed-off-by: Fabien Parent Reviewed-by: Rob Herring Acked-for-MFD-by: Lee Jones --- V6: * No changes V5: * Rebased, removed regulator documentation because it will be send later on in another patch series V4: * No change V3: * No change V2: * New patch Documentation/devicetree/bindings/mfd/mt6397.txt | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mfd/mt6397.txt b/Documentation/devicetree/bindings/mfd/mt6397.txt index 2661775a3825..f051a951ba72 100644 --- a/Documentation/devicetree/bindings/mfd/mt6397.txt +++ b/Documentation/devicetree/bindings/mfd/mt6397.txt @@ -21,6 +21,7 @@ Required properties: compatible: "mediatek,mt6323" for PMIC MT6323 "mediatek,mt6358" for PMIC MT6358 + "mediatek,mt6392" for PMIC MT6392 "mediatek,mt6397" for PMIC MT6397 Optional subnodes: @@ -52,7 +53,10 @@ Optional subnodes: - keys Required properties: - - compatible: "mediatek,mt6397-keys" or "mediatek,mt6323-keys" + - compatible: + - "mediatek,mt6323-keys" + - "mediatek,mt6392-keys", "mediatek,mt6397-keys" + - "mediatek,mt6397-keys" see ../input/mtk-pmic-keys.txt - power-controller -- 2.28.0
[PATCH v6 2/3] dt-bindings: input: mtk-pmic-keys: add MT6392 binding definition
Add the binding documentation of the mtk-pmic-keys for the MT6392 PMICs. Signed-off-by: Fabien Parent Reviewed-by: Rob Herring --- v6: * No changes v5: * rebased * Rename MT6397/MT6392/MT6323 into MT63XX to make it more readable when the list of support PMIC increase * Removed Reviewed-by from Rob Herring because of the new extra changes made to this patch * change the compatible for MT6392 to also contains MT6397 since MT6392 PMIC key driver is compatible with mt6397. v4: * Patch was previously sent separately but merge to this patch series since there is a hard dependency on the MFD patch. .../devicetree/bindings/input/mtk-pmic-keys.txt | 13 - 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/input/mtk-pmic-keys.txt b/Documentation/devicetree/bindings/input/mtk-pmic-keys.txt index 535d92885372..71c82687ab92 100644 --- a/Documentation/devicetree/bindings/input/mtk-pmic-keys.txt +++ b/Documentation/devicetree/bindings/input/mtk-pmic-keys.txt @@ -1,15 +1,18 @@ -MediaTek MT6397/MT6323 PMIC Keys Device Driver +MediaTek MT63xx PMIC Keys Device Driver -There are two key functions provided by MT6397/MT6323 PMIC, pwrkey +There are two key functions provided by MT63xx PMIC, pwrkey and homekey. The key functions are defined as the subnode of the function -node provided by MT6397/MT6323 PMIC that is being defined as one kind +node provided by MT63xx PMIC that is being defined as one kind of Muti-Function Device (MFD) -For MT6397/MT6323 MFD bindings see: +For MT63xx MFD bindings see: Documentation/devicetree/bindings/mfd/mt6397.txt Required properties: -- compatible: "mediatek,mt6397-keys" or "mediatek,mt6323-keys" +- compatible: Should be one of: + - "mediatek,mt6323-keys" for MT6323 PMIC + - "mediatek,mt6392-keys", "mediatek,mt6397-keys" for MT6392 PMIC + - "mediatek,mt6397-keys" for MT6397 PMIC - linux,keycodes: See Documentation/devicetree/bindings/input/input.yaml Optional Properties: -- 2.28.0
[PATCH v6 3/3] mfd: mt6397: Add support for MT6392 pmic
Update the MT6397 MFD driver to support the MT6392 PMIC.
Signed-off-by: Fabien Parent
---
V6:
* Update copyrights
V5:
* Rebased
* removed mt6392-regulator compatible. This will be send in another
series to make this series easier to merge.
V4:
* Use DEFINE_RES_* macro to define RTC ressources.
* Use PLATFORM_DEVID_NONE instead of -1 value when registering devices.
V3:
* No change
V2:
* Pass IRQ comain to fix invalid MFD devices IRQs.
* Remove resources and mfd cells for device we don't support.
* Rename IRQ names to follow what's done for MT6397.
drivers/mfd/mt6397-core.c| 40 +++
drivers/mfd/mt6397-irq.c | 9 +
include/linux/mfd/mt6392/core.h | 42 +++
include/linux/mfd/mt6392/registers.h | 487 +++
include/linux/mfd/mt6397/core.h | 1 +
5 files changed, 579 insertions(+)
create mode 100644 include/linux/mfd/mt6392/core.h
create mode 100644 include/linux/mfd/mt6392/registers.h
diff --git a/drivers/mfd/mt6397-core.c b/drivers/mfd/mt6397-core.c
index f6cd8a660602..6ba3585b1b36 100644
--- a/drivers/mfd/mt6397-core.c
+++ b/drivers/mfd/mt6397-core.c
@@ -13,9 +13,11 @@
#include
#include
#include
+#include
#include
#include
#include
+#include
#include
#define MT6323_RTC_BASE0x8000
@@ -27,6 +29,9 @@
#define MT6397_RTC_BASE0xe000
#define MT6397_RTC_SIZE0x3e
+#define MT6392_RTC_BASE0x8000
+#define MT6392_RTC_SIZE0x3e
+
#define MT6323_PWRC_BASE 0x8000
#define MT6323_PWRC_SIZE 0x40
@@ -40,6 +45,11 @@ static const struct resource mt6358_rtc_resources[] = {
DEFINE_RES_IRQ(MT6358_IRQ_RTC),
};
+static const struct resource mt6392_rtc_resources[] = {
+ DEFINE_RES_MEM(MT6392_RTC_BASE, MT6392_RTC_SIZE),
+ DEFINE_RES_IRQ(MT6392_IRQ_RTC),
+};
+
static const struct resource mt6397_rtc_resources[] = {
DEFINE_RES_MEM(MT6397_RTC_BASE, MT6397_RTC_SIZE),
DEFINE_RES_IRQ(MT6397_IRQ_RTC),
@@ -50,6 +60,11 @@ static const struct resource mt6323_keys_resources[] = {
DEFINE_RES_IRQ(MT6323_IRQ_STATUS_FCHRKEY),
};
+static const struct resource mt6392_keys_resources[] = {
+ DEFINE_RES_IRQ(MT6392_IRQ_PWRKEY),
+ DEFINE_RES_IRQ(MT6392_IRQ_FCHRKEY),
+};
+
static const struct resource mt6397_keys_resources[] = {
DEFINE_RES_IRQ(MT6397_IRQ_PWRKEY),
DEFINE_RES_IRQ(MT6397_IRQ_HOMEKEY),
@@ -99,6 +114,20 @@ static const struct mfd_cell mt6358_devs[] = {
},
};
+static const struct mfd_cell mt6392_devs[] = {
+ {
+ .name = "mt6397-rtc",
+ .num_resources = ARRAY_SIZE(mt6392_rtc_resources),
+ .resources = mt6392_rtc_resources,
+ .of_compatible = "mediatek,mt6392-rtc",
+ }, {
+ .name = "mtk-pmic-keys",
+ .num_resources = ARRAY_SIZE(mt6392_keys_resources),
+ .resources = mt6392_keys_resources,
+ .of_compatible = "mediatek,mt6392-keys"
+ },
+};
+
static const struct mfd_cell mt6397_devs[] = {
{
.name = "mt6397-rtc",
@@ -149,6 +178,14 @@ static const struct chip_data mt6358_core = {
.irq_init = mt6358_irq_init,
};
+static const struct chip_data mt6392_core = {
+ .cid_addr = MT6392_CID,
+ .cid_shift = 0,
+ .cells = mt6392_devs,
+ .cell_size = ARRAY_SIZE(mt6392_devs),
+ .irq_init = mt6397_irq_init,
+};
+
static const struct chip_data mt6397_core = {
.cid_addr = MT6397_CID,
.cid_shift = 0,
@@ -218,6 +255,9 @@ static const struct of_device_id mt6397_of_match[] = {
}, {
.compatible = "mediatek,mt6358",
.data = _core,
+ }, {
+ .compatible = "mediatek,mt6392",
+ .data = _core,
}, {
.compatible = "mediatek,mt6397",
.data = _core,
diff --git a/drivers/mfd/mt6397-irq.c b/drivers/mfd/mt6397-irq.c
index 2924919da991..9bf95e2ddf02 100644
--- a/drivers/mfd/mt6397-irq.c
+++ b/drivers/mfd/mt6397-irq.c
@@ -12,6 +12,8 @@
#include
#include
#include
+#include
+#include
#include
#include
@@ -181,6 +183,13 @@ int mt6397_irq_init(struct mt6397_chip *chip)
chip->int_status[1] = MT6397_INT_STATUS1;
break;
+ case MT6392_CHIP_ID:
+ chip->int_con[0] = MT6392_INT_CON0;
+ chip->int_con[1] = MT6392_INT_CON1;
+ chip->int_status[0] = MT6392_INT_STATUS0;
+ chip->int_status[1] = MT6392_INT_STATUS1;
+ break;
+
default:
dev_err(chip->dev, "unsupported chip: 0x%x\n", chip->chip_id);
return -ENODEV;
diff --git a/include/linux/mfd/mt6392/core.h b/in
[PATCH 2/2] soc: mediatek: mmsys: Add support for MT8167 SoC
Add routing table for DSI on MT8167 SoC. The registers are mostly
incompatible with the current defines, so new one for MT8167 are added.
Signed-off-by: Fabien Parent
---
This patch depends on the patch series
"soc: mediatek: Prepare MMSYS for DDP routing using tables"
[0] https://lore.kernel.org/patchwork/cover/1317813/
drivers/soc/mediatek/mtk-mmsys.c | 50
1 file changed, 50 insertions(+)
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index f00d6d08c9c5..9890990a74a9 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -85,6 +85,22 @@
#define DSI_SEL_IN_RDMA0x1
#define DSI_SEL_IN_MASK0x1
+/* MT8167 */
+#define MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x030
+#define MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN 0x038
+#define MT8167_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x058
+#define MT8167_DISP_REG_CONFIG_DISP_DSI0_SEL_IN0x064
+#define MT8167_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN 0x06c
+
+#define MT8167_DITHER_MOUT_EN_RDMA0BIT(0)
+#define MT8167_DITHER_MOUT_EN_MASK 0x7
+
+#define MT8167_RDMA0_SOUT_DSI0 0x2
+#define MT8167_RDMA0_SOUT_MASK 0x3
+
+#define MT8167_DSI0_SEL_IN_RDMA0 0x1
+#define MT8167_DSI0_SEL_IN_MASK0x3
+
struct mtk_mmsys_routes {
u32 from_comp;
u32 to_comp;
@@ -124,6 +140,30 @@ struct mtk_mmsys {
const struct mtk_mmsys_driver_data *data;
};
+static const struct mtk_mmsys_routes mt8167_mmsys_routing_table[] = {
+ {
+ DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
+ MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN,
+ OVL0_MOUT_EN_COLOR0, OVL0_MOUT_EN_COLOR0
+ }, {
+ DDP_COMPONENT_DITHER, DDP_COMPONENT_RDMA0,
+ MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN,
+ MT8167_DITHER_MOUT_EN_MASK, MT8167_DITHER_MOUT_EN_RDMA0
+ }, {
+ DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
+ MT8167_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN,
+ COLOR0_SEL_IN_OVL0, COLOR0_SEL_IN_OVL0
+ }, {
+ DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI0,
+ MT8167_DISP_REG_CONFIG_DISP_DSI0_SEL_IN,
+ MT8167_DSI0_SEL_IN_MASK, MT8167_DSI0_SEL_IN_RDMA0
+ }, {
+ DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI0,
+ MT8167_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN,
+ MT8167_RDMA0_SOUT_MASK, MT8167_RDMA0_SOUT_DSI0
+ },
+};
+
static const struct mtk_mmsys_routes mt8173_mmsys_routing_table[] = {
{
DDP_COMPONENT_BLS, DDP_COMPONENT_DSI0,
@@ -288,6 +328,12 @@ static const struct mtk_mmsys_routes
mt8173_mmsys_routing_table[] = {
}
};
+static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
+ .clk_driver = "clk-mt8167-mm",
+ .routes = mt8167_mmsys_routing_table,
+ .num_routes = ARRAY_SIZE(mt8167_mmsys_routing_table),
+};
+
static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
.clk_driver = "clk-mt8173-mm",
.routes = mt8173_mmsys_routing_table,
@@ -385,6 +431,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
.compatible = "mediatek,mt6797-mmsys",
.data = _mmsys_driver_data,
},
+ {
+ .compatible = "mediatek,mt8167-mmsys",
+ .data = _mmsys_driver_data,
+ },
{
.compatible = "mediatek,mt8173-mmsys",
.data = _mmsys_driver_data,
--
2.28.0
[PATCH 1/2] dt-bindings: mediatek: mmsys: add mt1867 binding
Add binding documentation for MT8167 SoC. Signed-off-by: Fabien Parent --- .../devicetree/bindings/arm/mediatek/mediatek,mmsys.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt index d8c9108c3b4a..78c50733985c 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt @@ -13,6 +13,7 @@ Required Properties: - "mediatek,mt6779-mmsys", "syscon" - "mediatek,mt6797-mmsys", "syscon" - "mediatek,mt7623-mmsys", "mediatek,mt2701-mmsys", "syscon" + - "mediatek,mt8167-mmsys", "syscon" - "mediatek,mt8173-mmsys", "syscon" - "mediatek,mt8183-mmsys", "syscon" - #clock-cells: Must be 1 -- 2.28.0
Re: [PATCH v2 5/5] drm/mediatek: Add support for main DDP path on MT8167
Hi Chun-Kuang,
On Fri, Oct 23, 2020 at 5:52 PM Chun-Kuang Hu wrote:
>
> Hi, Fabien:
>
> Fabien Parent 於 2020年10月23日 週五 下午9:31寫道：
> >
> > Add the main (DSI) drm display path for MT8167.
> >
> > Signed-off-by: Fabien Parent
> > ---
> >
> > Changelog:
> >
> > V2: No change
> >
> > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 38 ++
> > 1 file changed, 38 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > index 59c85c63b7cc..3952435093fe 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > @@ -112,6 +112,17 @@ static const enum mtk_ddp_comp_id
> > mt2712_mtk_ddp_third[] = {
> > DDP_COMPONENT_PWM2,
> > };
> >
> > +static enum mtk_ddp_comp_id mt8167_mtk_ddp_main[] = {
> > + DDP_COMPONENT_OVL0,
> > + DDP_COMPONENT_COLOR0,
> > + DDP_COMPONENT_CCORR,
> > + DDP_COMPONENT_AAL0,
> > + DDP_COMPONENT_GAMMA,
> > + DDP_COMPONENT_DITHER,
> > + DDP_COMPONENT_RDMA0,
> > + DDP_COMPONENT_DSI0,
> > +};
> > +
> > static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = {
> > DDP_COMPONENT_OVL0,
> > DDP_COMPONENT_COLOR0,
> > @@ -163,6 +174,11 @@ static const struct mtk_mmsys_driver_data
> > mt8173_mmsys_driver_data = {
> > .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
> > };
> >
> > +static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
> > + .main_path = mt8167_mtk_ddp_main,
> > + .main_len = ARRAY_SIZE(mt8167_mtk_ddp_main),
> > +};
> > +
> > static int mtk_drm_kms_init(struct drm_device *drm)
> > {
> > struct mtk_drm_private *private = drm->dev_private;
> > @@ -401,26 +417,42 @@ static const struct component_master_ops mtk_drm_ops
> > = {
> > static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
> > { .compatible = "mediatek,mt2701-disp-ovl",
> > .data = (void *)MTK_DISP_OVL },
> > + { .compatible = "mediatek,mt8167-disp-ovl",
> > + .data = (void *)MTK_DISP_OVL },
> > { .compatible = "mediatek,mt8173-disp-ovl",
> > .data = (void *)MTK_DISP_OVL },
> > { .compatible = "mediatek,mt2701-disp-rdma",
> > .data = (void *)MTK_DISP_RDMA },
> > + { .compatible = "mediatek,mt8167-disp-rdma",
> > + .data = (void *)MTK_DISP_RDMA },
> > { .compatible = "mediatek,mt8173-disp-rdma",
> > .data = (void *)MTK_DISP_RDMA },
> > { .compatible = "mediatek,mt8173-disp-wdma",
> > .data = (void *)MTK_DISP_WDMA },
> > + { .compatible = "mediatek,mt8167-disp-ccorr",
> > + .data = (void *)MTK_DISP_CCORR },
> > { .compatible = "mediatek,mt2701-disp-color",
> > .data = (void *)MTK_DISP_COLOR },
> > + { .compatible = "mediatek,mt8167-disp-color",
> > + .data = (void *)MTK_DISP_COLOR },
> > { .compatible = "mediatek,mt8173-disp-color",
> > .data = (void *)MTK_DISP_COLOR },
> > + { .compatible = "mediatek,mt8167-disp-aal",
> > + .data = (void *)MTK_DISP_AAL},
> > { .compatible = "mediatek,mt8173-disp-aal",
> > .data = (void *)MTK_DISP_AAL},
> > + { .compatible = "mediatek,mt8167-disp-gamma",
> > + .data = (void *)MTK_DISP_GAMMA, },
> > { .compatible = "mediatek,mt8173-disp-gamma",
> > .data = (void *)MTK_DISP_GAMMA, },
> > + { .compatible = "mediatek,mt8167-disp-dither",
> > + .data = (void *)MTK_DISP_DITHER },
> > { .compatible = "mediatek,mt8173-disp-ufoe",
> > .data = (void *)MTK_DISP_UFOE },
> > { .compatible = "mediatek,mt2701-dsi",
> > .data = (void *)MTK_DSI },
> > + { .compatible = "mediatek,mt8167-dsi",
> > + .data = (void *)MTK_DSI },
> > { .compatible = "mediatek,mt8173-dsi",
> > .data = (void *)MTK_DSI },
> > { .compatible = "mediatek,mt2701-dpi",
> > @@ -431,10 +463,14 @@ static const struct of_device_id
> > mtk_ddp_comp_dt_ids[] = {
> > .data = (void *)MTK_DISP_MUTEX },
> > { .compatible = "mediatek,mt2712-disp-mute
[PATCH v6 RESEND 2/3] dt-bindings: input: mtk-pmic-keys: add MT6392 binding definition
Add the binding documentation of the mtk-pmic-keys for the MT6392 PMICs. Signed-off-by: Fabien Parent Reviewed-by: Rob Herring --- v6: * No changes v5: * rebased * Rename MT6397/MT6392/MT6323 into MT63XX to make it more readable when the list of support PMIC increase * Removed Reviewed-by from Rob Herring because of the new extra changes made to this patch * change the compatible for MT6392 to also contains MT6397 since MT6392 PMIC key driver is compatible with mt6397. v4: * Patch was previously sent separately but merge to this patch series since there is a hard dependency on the MFD patch. .../devicetree/bindings/input/mtk-pmic-keys.txt | 13 - 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/input/mtk-pmic-keys.txt b/Documentation/devicetree/bindings/input/mtk-pmic-keys.txt index 535d92885372..71c82687ab92 100644 --- a/Documentation/devicetree/bindings/input/mtk-pmic-keys.txt +++ b/Documentation/devicetree/bindings/input/mtk-pmic-keys.txt @@ -1,15 +1,18 @@ -MediaTek MT6397/MT6323 PMIC Keys Device Driver +MediaTek MT63xx PMIC Keys Device Driver -There are two key functions provided by MT6397/MT6323 PMIC, pwrkey +There are two key functions provided by MT63xx PMIC, pwrkey and homekey. The key functions are defined as the subnode of the function -node provided by MT6397/MT6323 PMIC that is being defined as one kind +node provided by MT63xx PMIC that is being defined as one kind of Muti-Function Device (MFD) -For MT6397/MT6323 MFD bindings see: +For MT63xx MFD bindings see: Documentation/devicetree/bindings/mfd/mt6397.txt Required properties: -- compatible: "mediatek,mt6397-keys" or "mediatek,mt6323-keys" +- compatible: Should be one of: + - "mediatek,mt6323-keys" for MT6323 PMIC + - "mediatek,mt6392-keys", "mediatek,mt6397-keys" for MT6392 PMIC + - "mediatek,mt6397-keys" for MT6397 PMIC - linux,keycodes: See Documentation/devicetree/bindings/input/input.yaml Optional Properties: -- 2.28.0
[PATCH v6 RESEND 1/3] dt-bindings: mfd: mt6397: Add bindings for MT6392 PMIC
Add the currently supported bindings for the MT6392 PMIC. Signed-off-by: Fabien Parent Reviewed-by: Rob Herring Acked-for-MFD-by: Lee Jones --- V6: * No changes V5: * Rebased, removed regulator documentation because it will be send later on in another patch series V4: * No change V3: * No change V2: * New patch Documentation/devicetree/bindings/mfd/mt6397.txt | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mfd/mt6397.txt b/Documentation/devicetree/bindings/mfd/mt6397.txt index 2661775a3825..f051a951ba72 100644 --- a/Documentation/devicetree/bindings/mfd/mt6397.txt +++ b/Documentation/devicetree/bindings/mfd/mt6397.txt @@ -21,6 +21,7 @@ Required properties: compatible: "mediatek,mt6323" for PMIC MT6323 "mediatek,mt6358" for PMIC MT6358 + "mediatek,mt6392" for PMIC MT6392 "mediatek,mt6397" for PMIC MT6397 Optional subnodes: @@ -52,7 +53,10 @@ Optional subnodes: - keys Required properties: - - compatible: "mediatek,mt6397-keys" or "mediatek,mt6323-keys" + - compatible: + - "mediatek,mt6323-keys" + - "mediatek,mt6392-keys", "mediatek,mt6397-keys" + - "mediatek,mt6397-keys" see ../input/mtk-pmic-keys.txt - power-controller -- 2.28.0
[PATCH v6 RESEND 3/3] mfd: mt6397: Add support for MT6392 pmic
Update the MT6397 MFD driver to support the MT6392 PMIC.
Signed-off-by: Fabien Parent
---
V6:
* Update copyrights
V5:
* Rebased
* removed mt6392-regulator compatible. This will be send in another
series to make this series easier to merge.
V4:
* Use DEFINE_RES_* macro to define RTC ressources.
* Use PLATFORM_DEVID_NONE instead of -1 value when registering devices.
V3:
* No change
V2:
* Pass IRQ comain to fix invalid MFD devices IRQs.
* Remove resources and mfd cells for device we don't support.
* Rename IRQ names to follow what's done for MT6397.
drivers/mfd/mt6397-core.c| 40 +++
drivers/mfd/mt6397-irq.c | 9 +
include/linux/mfd/mt6392/core.h | 42 +++
include/linux/mfd/mt6392/registers.h | 487 +++
include/linux/mfd/mt6397/core.h | 1 +
5 files changed, 579 insertions(+)
create mode 100644 include/linux/mfd/mt6392/core.h
create mode 100644 include/linux/mfd/mt6392/registers.h
diff --git a/drivers/mfd/mt6397-core.c b/drivers/mfd/mt6397-core.c
index f6cd8a660602..6ba3585b1b36 100644
--- a/drivers/mfd/mt6397-core.c
+++ b/drivers/mfd/mt6397-core.c
@@ -13,9 +13,11 @@
#include
#include
#include
+#include
#include
#include
#include
+#include
#include
#define MT6323_RTC_BASE0x8000
@@ -27,6 +29,9 @@
#define MT6397_RTC_BASE0xe000
#define MT6397_RTC_SIZE0x3e
+#define MT6392_RTC_BASE0x8000
+#define MT6392_RTC_SIZE0x3e
+
#define MT6323_PWRC_BASE 0x8000
#define MT6323_PWRC_SIZE 0x40
@@ -40,6 +45,11 @@ static const struct resource mt6358_rtc_resources[] = {
DEFINE_RES_IRQ(MT6358_IRQ_RTC),
};
+static const struct resource mt6392_rtc_resources[] = {
+ DEFINE_RES_MEM(MT6392_RTC_BASE, MT6392_RTC_SIZE),
+ DEFINE_RES_IRQ(MT6392_IRQ_RTC),
+};
+
static const struct resource mt6397_rtc_resources[] = {
DEFINE_RES_MEM(MT6397_RTC_BASE, MT6397_RTC_SIZE),
DEFINE_RES_IRQ(MT6397_IRQ_RTC),
@@ -50,6 +60,11 @@ static const struct resource mt6323_keys_resources[] = {
DEFINE_RES_IRQ(MT6323_IRQ_STATUS_FCHRKEY),
};
+static const struct resource mt6392_keys_resources[] = {
+ DEFINE_RES_IRQ(MT6392_IRQ_PWRKEY),
+ DEFINE_RES_IRQ(MT6392_IRQ_FCHRKEY),
+};
+
static const struct resource mt6397_keys_resources[] = {
DEFINE_RES_IRQ(MT6397_IRQ_PWRKEY),
DEFINE_RES_IRQ(MT6397_IRQ_HOMEKEY),
@@ -99,6 +114,20 @@ static const struct mfd_cell mt6358_devs[] = {
},
};
+static const struct mfd_cell mt6392_devs[] = {
+ {
+ .name = "mt6397-rtc",
+ .num_resources = ARRAY_SIZE(mt6392_rtc_resources),
+ .resources = mt6392_rtc_resources,
+ .of_compatible = "mediatek,mt6392-rtc",
+ }, {
+ .name = "mtk-pmic-keys",
+ .num_resources = ARRAY_SIZE(mt6392_keys_resources),
+ .resources = mt6392_keys_resources,
+ .of_compatible = "mediatek,mt6392-keys"
+ },
+};
+
static const struct mfd_cell mt6397_devs[] = {
{
.name = "mt6397-rtc",
@@ -149,6 +178,14 @@ static const struct chip_data mt6358_core = {
.irq_init = mt6358_irq_init,
};
+static const struct chip_data mt6392_core = {
+ .cid_addr = MT6392_CID,
+ .cid_shift = 0,
+ .cells = mt6392_devs,
+ .cell_size = ARRAY_SIZE(mt6392_devs),
+ .irq_init = mt6397_irq_init,
+};
+
static const struct chip_data mt6397_core = {
.cid_addr = MT6397_CID,
.cid_shift = 0,
@@ -218,6 +255,9 @@ static const struct of_device_id mt6397_of_match[] = {
}, {
.compatible = "mediatek,mt6358",
.data = _core,
+ }, {
+ .compatible = "mediatek,mt6392",
+ .data = _core,
}, {
.compatible = "mediatek,mt6397",
.data = _core,
diff --git a/drivers/mfd/mt6397-irq.c b/drivers/mfd/mt6397-irq.c
index 2924919da991..9bf95e2ddf02 100644
--- a/drivers/mfd/mt6397-irq.c
+++ b/drivers/mfd/mt6397-irq.c
@@ -12,6 +12,8 @@
#include
#include
#include
+#include
+#include
#include
#include
@@ -181,6 +183,13 @@ int mt6397_irq_init(struct mt6397_chip *chip)
chip->int_status[1] = MT6397_INT_STATUS1;
break;
+ case MT6392_CHIP_ID:
+ chip->int_con[0] = MT6392_INT_CON0;
+ chip->int_con[1] = MT6392_INT_CON1;
+ chip->int_status[0] = MT6392_INT_STATUS0;
+ chip->int_status[1] = MT6392_INT_STATUS1;
+ break;
+
default:
dev_err(chip->dev, "unsupported chip: 0x%x\n", chip->chip_id);
return -ENODEV;
diff --git a/include/linux/mfd/mt6392/core.h b/in
[PATCH 1/3] dt-bindings: arm64: dts: mediatek: Add mt8167-pumpkin board
Add binding documentation for the MT8167 Pumpkin board. Signed-off-by: Fabien Parent --- Documentation/devicetree/bindings/arm/mediatek.yaml | 4 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 30908963ae26..5c772b937efc 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -84,6 +84,10 @@ properties: - enum: - mediatek,mt8135-evbp1 - const: mediatek,mt8135 + - items: + - enum: + - mediatek,mt8167-pumpkin + - const: mediatek,mt8167 - description: Google Elm (Acer Chromebook R13) items: - const: google,elm-rev8 -- 2.28.0
[PATCH 2/3] arm64: dts: mediatek: add dtsi for MT8167
The MT8167 SoC provides the following peripherals: GPIO, UART, USB2, SPI, eMMC, SDIO, NAND, Flash, ADC, I2C, PWM, TImers, IR, Ethernet, Audio (I2S, SPDIF, TDM, HDMI), HDMI, DSI, CSI, MDP (Multimedia Data Path), Video encoding (H.264), Video Decoding (H.264, VP8). The MT8167 is compatible with MT8516 but provides multimedia IPs to it. This commit is just adding the basic dtsi file with the support of the following IOs: GPIO, Clocks. Signed-off-by: Fabien Parent --- arch/arm64/boot/dts/mediatek/mt8167-pinfunc.h | 744 ++ arch/arm64/boot/dts/mediatek/mt8167.dtsi | 61 ++ 2 files changed, 805 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8167-pinfunc.h create mode 100644 arch/arm64/boot/dts/mediatek/mt8167.dtsi diff --git a/arch/arm64/boot/dts/mediatek/mt8167-pinfunc.h b/arch/arm64/boot/dts/mediatek/mt8167-pinfunc.h new file mode 100644 index ..061c3255a973 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8167-pinfunc.h @@ -0,0 +1,744 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 MediaTek Inc. + */ +#ifndef __DTS_MT8167_PINFUNC_H +#define __DTS_MT8167_PINFUNC_H + +#include + +#define MT8167_PIN_0_EINT0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define MT8167_PIN_0_EINT0__FUNC_PWM_B (MTK_PIN_NO(0) | 1) +#define MT8167_PIN_0_EINT0__FUNC_DPI_CK (MTK_PIN_NO(0) | 2) +#define MT8167_PIN_0_EINT0__FUNC_I2S2_BCK (MTK_PIN_NO(0) | 3) +#define MT8167_PIN_0_EINT0__FUNC_EXT_TXD0 (MTK_PIN_NO(0) | 4) +#define MT8167_PIN_0_EINT0__FUNC_SQICS (MTK_PIN_NO(0) | 6) +#define MT8167_PIN_0_EINT0__FUNC_DBG_MON_A_6 (MTK_PIN_NO(0) | 7) + +#define MT8167_PIN_1_EINT1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define MT8167_PIN_1_EINT1__FUNC_PWM_C (MTK_PIN_NO(1) | 1) +#define MT8167_PIN_1_EINT1__FUNC_DPI_D12 (MTK_PIN_NO(1) | 2) +#define MT8167_PIN_1_EINT1__FUNC_I2S2_DI (MTK_PIN_NO(1) | 3) +#define MT8167_PIN_1_EINT1__FUNC_EXT_TXD1 (MTK_PIN_NO(1) | 4) +#define MT8167_PIN_1_EINT1__FUNC_CONN_MCU_TDO (MTK_PIN_NO(1) | 5) +#define MT8167_PIN_1_EINT1__FUNC_SQISO (MTK_PIN_NO(1) | 6) +#define MT8167_PIN_1_EINT1__FUNC_DBG_MON_A_7 (MTK_PIN_NO(1) | 7) + +#define MT8167_PIN_2_EINT2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define MT8167_PIN_2_EINT2__FUNC_CLKM0 (MTK_PIN_NO(2) | 1) +#define MT8167_PIN_2_EINT2__FUNC_DPI_D13 (MTK_PIN_NO(2) | 2) +#define MT8167_PIN_2_EINT2__FUNC_I2S2_LRCK (MTK_PIN_NO(2) | 3) +#define MT8167_PIN_2_EINT2__FUNC_EXT_TXD2 (MTK_PIN_NO(2) | 4) +#define MT8167_PIN_2_EINT2__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(2) | 5) +#define MT8167_PIN_2_EINT2__FUNC_SQISI (MTK_PIN_NO(2) | 6) +#define MT8167_PIN_2_EINT2__FUNC_DBG_MON_A_8 (MTK_PIN_NO(2) | 7) + +#define MT8167_PIN_3_EINT3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define MT8167_PIN_3_EINT3__FUNC_CLKM1 (MTK_PIN_NO(3) | 1) +#define MT8167_PIN_3_EINT3__FUNC_DPI_D14 (MTK_PIN_NO(3) | 2) +#define MT8167_PIN_3_EINT3__FUNC_SPI_MI (MTK_PIN_NO(3) | 3) +#define MT8167_PIN_3_EINT3__FUNC_EXT_TXD3 (MTK_PIN_NO(3) | 4) +#define MT8167_PIN_3_EINT3__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(3) | 5) +#define MT8167_PIN_3_EINT3__FUNC_SQIWP (MTK_PIN_NO(3) | 6) +#define MT8167_PIN_3_EINT3__FUNC_DBG_MON_A_9 (MTK_PIN_NO(3) | 7) + +#define MT8167_PIN_4_EINT4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define MT8167_PIN_4_EINT4__FUNC_CLKM2 (MTK_PIN_NO(4) | 1) +#define MT8167_PIN_4_EINT4__FUNC_DPI_D15 (MTK_PIN_NO(4) | 2) +#define MT8167_PIN_4_EINT4__FUNC_SPI_MO (MTK_PIN_NO(4) | 3) +#define MT8167_PIN_4_EINT4__FUNC_EXT_TXC (MTK_PIN_NO(4) | 4) +#define MT8167_PIN_4_EINT4__FUNC_CONN_MCU_TCK (MTK_PIN_NO(4) | 5) +#define MT8167_PIN_4_EINT4__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(4) | 6) +#define MT8167_PIN_4_EINT4__FUNC_DBG_MON_A_10 (MTK_PIN_NO(4) | 7) + +#define MT8167_PIN_5_EINT5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define MT8167_PIN_5_EINT5__FUNC_UCTS2 (MTK_PIN_NO(5) | 1) +#define MT8167_PIN_5_EINT5__FUNC_DPI_D16 (MTK_PIN_NO(5) | 2) +#define MT8167_PIN_5_EINT5__FUNC_SPI_CSB (MTK_PIN_NO(5) | 3) +#define MT8167_PIN_5_EINT5__FUNC_EXT_RXER (MTK_PIN_NO(5) | 4) +#define MT8167_PIN_5_EINT5__FUNC_CONN_MCU_TDI (MTK_PIN_NO(5) | 5) +#define MT8167_PIN_5_EINT5__FUNC_CONN_TEST_CK (MTK_PIN_NO(5) | 6) +#define MT8167_PIN_5_EINT5__FUNC_DBG_MON_A_11 (MTK_PIN_NO(5) | 7) + +#define MT8167_PIN_6_EINT6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define MT8167_PIN_6_EINT6__FUNC_URTS2 (MTK_PIN_NO(6) | 1) +#define MT8167_PIN_6_EINT6__FUNC_DPI_D17 (MTK_PIN_NO(6) | 2) +#define MT8167_PIN_6_EINT6__FUNC_SPI_CLK (MTK_PIN_NO(6) | 3) +#define MT8167_PIN_6_EINT6__FUNC_EXT_RXC (MTK_PIN_NO(6) | 4) +#define MT8167_PIN_6_EINT6__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(6) | 5) +#define MT8167_PIN_6_EINT6__FUNC_MM_TEST_CK (MTK_PIN_NO(6) | 6) +#define MT8167_PIN_6_EINT6__FUNC_DBG_MON_A_12 (MTK_PIN_NO(6) | 7) + +#define MT8167_PIN_7_EINT7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +#define MT8167_PIN_7_EINT7__FUNC_SQIRST (MTK_PIN_NO(7) | 1) +#define MT8167_PIN_7_EINT7__FUNC_DPI_D6 (MTK_PIN_NO(7) | 2) +#define MT8167_PIN_7_EINT7__FUNC_SDA1_0 (MTK_PIN_NO(7) | 3) +#define MT8167_PIN_7_EINT7__FUNC_EXT_RXDV (MTK_PIN_NO(7) | 4) +#define
[PATCH 3/3] arm64: dts: mediatek: add MT8167 pumpkin board dts
The pumpkin board is made by Gossamer Engineering and is using
a MediaTek SoC. The board currently comes in two available version:
MT8516 SoC and MT8167 SoC.
The board provides the following IOs: eMMC, NAND, SD card, USB type-A,
Ethernet, Wi-Fi, Bluetooth, Audio (jack out, 2 PDM port, 1 analog in),
serial over USB, HDMI, DSI, CSI, and an expansion header.
The board can be powered by battery and/or via a USB Type-C port and
is using a PMIC MT6392.
The eMMC and NAND are sharing pins and cannot be used together.
This commit is adding the basic boot support for the Pumpkin MT8167
board.
Signed-off-by: Fabien Parent
---
arch/arm64/boot/dts/mediatek/Makefile | 1 +
.../boot/dts/mediatek/mt8167-pumpkin.dts | 20 +++
2 files changed, 21 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts
diff --git a/arch/arm64/boot/dts/mediatek/Makefile
b/arch/arm64/boot/dts/mediatek/Makefile
index 3ee682c266cc..8012216987ef 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -6,6 +6,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana-rev7.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts
b/arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts
new file mode 100644
index ..774a2f3fb4b2
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2020 BayLibre, SAS.
+ * Author: Fabien Parent
+ */
+
+/dts-v1/;
+
+#include "mt8167.dtsi"
+#include "pumpkin-common.dtsi"
+
+/ {
+ model = "Pumpkin MT8167";
+ compatible = "mediatek,mt8167-pumpkin", "mediatek,mt8167";
+
+ memory@4000 {
+ device_type = "memory";
+ reg = <0 0x4000 0 0x8000>;
+ };
+};
--
2.28.0
Re: [PATCH v5 1/2] dt-bindings: regulator: add support for MT6392
Hi Mark, On Mon, Oct 26, 2020 at 9:36 PM Mark Brown wrote: > > On Mon, Oct 26, 2020 at 07:38:14PM +0100, Fabien Parent wrote: > > On Mon, Oct 26, 2020 at 6:24 PM Mark Brown wrote: > > > > > .name = "mt6392-regulator", > > > > .of_compatible = "mediatek,mt6392-regulator" > > > > This is still unneeded, it's just a reflection of Linux implementation > > > details and should be removed. The MFD can just register the child > > > without supplying a compatible and things will continue to work just as > > > well. > > > I'm not exactly sure how it is supposed to work. mfd_add_devices seems > > to register devices based on of_compatible or acpi_match from the > > mfd_cell. This platform does not have ACPI so I don't understand how > > It should also support unconditionally registering devices, if it no > longer does so that's a regression in the framework which should be > fixed. Looking at mfd_add_devices() I can't see an issue though, both > ACPI and DT information is optional - the entire DT section in > mfd_add_device() will be skipped if no of_compatible is specified in the > cell. Are you *sure* that the regulator driver isn't running? You are correct, the regulator driver is running and probes successfully. From my investigation it seems the failure when removing the compatible string from the MFD and the DTS is because the regulator driver does not have a of_node matched since the compatible is gone. Because of that all the regulators registered by the driver are not linked to the regulator definitions in the device tree. And all the drivers that tries to acquire a regulator get -EPROBE_DEFER because of it.
[PATCH v2 1/2] dt-bindings: dma: mtk-apdma: add bindings for MT8516 SOC
Add bindings to APDMA for MT8516 SoC. MT8516 is compatible with MT6577. Signed-off-by: Fabien Parent Reviewed-by: Matthias Brugger Acked-by: Rob Herring --- V2: no change Documentation/devicetree/bindings/dma/mtk-uart-apdma.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/dma/mtk-uart-apdma.txt b/Documentation/devicetree/bindings/dma/mtk-uart-apdma.txt index 2117db0ce4f2..fef9c1eeb264 100644 --- a/Documentation/devicetree/bindings/dma/mtk-uart-apdma.txt +++ b/Documentation/devicetree/bindings/dma/mtk-uart-apdma.txt @@ -4,6 +4,7 @@ Required properties: - compatible should contain: * "mediatek,mt2712-uart-dma" for MT2712 compatible APDMA * "mediatek,mt6577-uart-dma" for MT6577 and all of the above + * "mediatek,mt8516-uart-dma", "mediatek,mt6577" for MT8516 SoC - reg: The base address of the APDMA register bank. -- 2.29.2
[PATCH v2 2/2] arm64: dts: mediatek: mt8516: add support for APDMA
Add support the APDMA IP on MT8516. APDMA is a DMA controller
for UARTs.
Signed-off-by: Fabien Parent
---
V2: Add missing dma-names properties on uart nodes
arch/arm64/boot/dts/mediatek/mt8516.dtsi | 30
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8516.dtsi
b/arch/arm64/boot/dts/mediatek/mt8516.dtsi
index e6e4d9d60094..b80e95574bef 100644
--- a/arch/arm64/boot/dts/mediatek/mt8516.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8516.dtsi
@@ -276,6 +276,27 @@ gic: interrupt-controller@1031 {
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
+ apdma: dma-controller@11000480 {
+ compatible = "mediatek,mt8516-uart-dma",
+"mediatek,mt6577-uart-dma";
+ reg = <0 0x11000480 0 0x80>,
+ <0 0x11000500 0 0x80>,
+ <0 0x11000580 0 0x80>,
+ <0 0x11000600 0 0x80>,
+ <0 0x11000980 0 0x80>,
+ <0 0x11000a00 0 0x80>;
+ interrupts = ,
+,
+,
+,
+,
+;
+ dma-requests = <6>;
+ clocks = < CLK_TOP_APDMA>;
+ clock-names = "apdma";
+ #dma-cells = <1>;
+ };
+
uart0: serial@11005000 {
compatible = "mediatek,mt8516-uart",
"mediatek,mt6577-uart";
@@ -284,6 +305,9 @@ uart0: serial@11005000 {
clocks = < CLK_TOP_UART0_SEL>,
< CLK_TOP_UART0>;
clock-names = "baud", "bus";
+ dmas = < 0
+1>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -295,6 +319,9 @@ uart1: serial@11006000 {
clocks = < CLK_TOP_UART1_SEL>,
< CLK_TOP_UART1>;
clock-names = "baud", "bus";
+ dmas = < 2
+3>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -306,6 +333,9 @@ uart2: serial@11007000 {
clocks = < CLK_TOP_UART2_SEL>,
< CLK_TOP_UART2>;
clock-names = "baud", "bus";
+ dmas = < 4
+5>;
+ dma-names = "tx", "rx";
status = "disabled";
};
--
2.29.2
[PATCH v3 1/2] dt-bindings: dma: mtk-apdma: add bindings for MT8516 SOC
Add bindings to APDMA for MT8516 SoC. MT8516 is compatible with MT6577. Signed-off-by: Fabien Parent Reviewed-by: Matthias Brugger Acked-by: Rob Herring --- V3: remove unicode symbol that slips into patch summary V2: no change Documentation/devicetree/bindings/dma/mtk-uart-apdma.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/dma/mtk-uart-apdma.txt b/Documentation/devicetree/bindings/dma/mtk-uart-apdma.txt index 2117db0ce4f2..fef9c1eeb264 100644 --- a/Documentation/devicetree/bindings/dma/mtk-uart-apdma.txt +++ b/Documentation/devicetree/bindings/dma/mtk-uart-apdma.txt @@ -4,6 +4,7 @@ Required properties: - compatible should contain: * "mediatek,mt2712-uart-dma" for MT2712 compatible APDMA * "mediatek,mt6577-uart-dma" for MT6577 and all of the above + * "mediatek,mt8516-uart-dma", "mediatek,mt6577" for MT8516 SoC - reg: The base address of the APDMA register bank. -- 2.29.2
[PATCH v3 2/2] arm64: dts: mediatek: mt8516: add support for APDMA
Add support the APDMA IP on MT8516. APDMA is a DMA controller
for UARTs.
Signed-off-by: Fabien Parent
---
V3: remove unicode symbol that slips into patch summary
V2: Add missing dma-names properties on uart nodes
arch/arm64/boot/dts/mediatek/mt8516.dtsi | 30
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8516.dtsi
b/arch/arm64/boot/dts/mediatek/mt8516.dtsi
index e6e4d9d60094..b80e95574bef 100644
--- a/arch/arm64/boot/dts/mediatek/mt8516.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8516.dtsi
@@ -276,6 +276,27 @@ gic: interrupt-controller@1031 {
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
+ apdma: dma-controller@11000480 {
+ compatible = "mediatek,mt8516-uart-dma",
+"mediatek,mt6577-uart-dma";
+ reg = <0 0x11000480 0 0x80>,
+ <0 0x11000500 0 0x80>,
+ <0 0x11000580 0 0x80>,
+ <0 0x11000600 0 0x80>,
+ <0 0x11000980 0 0x80>,
+ <0 0x11000a00 0 0x80>;
+ interrupts = ,
+,
+,
+,
+,
+;
+ dma-requests = <6>;
+ clocks = < CLK_TOP_APDMA>;
+ clock-names = "apdma";
+ #dma-cells = <1>;
+ };
+
uart0: serial@11005000 {
compatible = "mediatek,mt8516-uart",
"mediatek,mt6577-uart";
@@ -284,6 +305,9 @@ uart0: serial@11005000 {
clocks = < CLK_TOP_UART0_SEL>,
< CLK_TOP_UART0>;
clock-names = "baud", "bus";
+ dmas = < 0
+1>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -295,6 +319,9 @@ uart1: serial@11006000 {
clocks = < CLK_TOP_UART1_SEL>,
< CLK_TOP_UART1>;
clock-names = "baud", "bus";
+ dmas = < 2
+3>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -306,6 +333,9 @@ uart2: serial@11007000 {
clocks = < CLK_TOP_UART2_SEL>,
< CLK_TOP_UART2>;
clock-names = "baud", "bus";
+ dmas = < 4
+5>;
+ dma-names = "tx", "rx";
status = "disabled";
};
--
2.29.2
Re: [PATCH v2 1/2] dt-bindings: dma: mtk-apdma: add bindings for MT8516 SOC
Sorry, resending without the unicode symbol in the title On Wed, Dec 9, 2020 at 12:44 PM Fabien Parent wrote: > > Add bindings to APDMA for MT8516 SoC. MT8516 is compatible with MT6577. > > Signed-off-by: Fabien Parent > Reviewed-by: Matthias Brugger > Acked-by: Rob Herring > --- > > V2: no change > > Documentation/devicetree/bindings/dma/mtk-uart-apdma.txt | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/dma/mtk-uart-apdma.txt > b/Documentation/devicetree/bindings/dma/mtk-uart-apdma.txt > index 2117db0ce4f2..fef9c1eeb264 100644 > --- a/Documentation/devicetree/bindings/dma/mtk-uart-apdma.txt > +++ b/Documentation/devicetree/bindings/dma/mtk-uart-apdma.txt > @@ -4,6 +4,7 @@ Required properties: > - compatible should contain: >* "mediatek,mt2712-uart-dma" for MT2712 compatible APDMA >* "mediatek,mt6577-uart-dma" for MT6577 and all of the above > + * "mediatek,mt8516-uart-dma", "mediatek,mt6577" for MT8516 SoC > > - reg: The base address of the APDMA register bank. > > -- > 2.29.2 >
Re: [PATCH v2 2/2] arm64: dts: mediatek: mt8516: add support for APDMA
Sorry, resending without the unicode symbol in the title
On Wed, Dec 9, 2020 at 12:44 PM Fabien Parent wrote:
>
> Add support the APDMA IP on MT8516. APDMA is a DMA controller
> for UARTs.
>
> Signed-off-by: Fabien Parent
> ---
>
> V2: Add missing dma-names properties on uart nodes
>
> arch/arm64/boot/dts/mediatek/mt8516.dtsi | 30
> 1 file changed, 30 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8516.dtsi
> b/arch/arm64/boot/dts/mediatek/mt8516.dtsi
> index e6e4d9d60094..b80e95574bef 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8516.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8516.dtsi
> @@ -276,6 +276,27 @@ gic: interrupt-controller@1031 {
> (GIC_CPU_MASK_SIMPLE(4) |
> IRQ_TYPE_LEVEL_HIGH)>;
> };
>
> + apdma: dma-controller@11000480 {
> + compatible = "mediatek,mt8516-uart-dma",
> +"mediatek,mt6577-uart-dma";
> + reg = <0 0x11000480 0 0x80>,
> + <0 0x11000500 0 0x80>,
> + <0 0x11000580 0 0x80>,
> + <0 0x11000600 0 0x80>,
> + <0 0x11000980 0 0x80>,
> + <0 0x11000a00 0 0x80>;
> + interrupts = ,
> +,
> +,
> +,
> +,
> +;
> + dma-requests = <6>;
> + clocks = < CLK_TOP_APDMA>;
> + clock-names = "apdma";
> + #dma-cells = <1>;
> + };
> +
> uart0: serial@11005000 {
> compatible = "mediatek,mt8516-uart",
> "mediatek,mt6577-uart";
> @@ -284,6 +305,9 @@ uart0: serial@11005000 {
> clocks = < CLK_TOP_UART0_SEL>,
> < CLK_TOP_UART0>;
> clock-names = "baud", "bus";
> + dmas = < 0
> +1>;
> + dma-names = "tx", "rx";
> status = "disabled";
> };
>
> @@ -295,6 +319,9 @@ uart1: serial@11006000 {
> clocks = < CLK_TOP_UART1_SEL>,
> < CLK_TOP_UART1>;
> clock-names = "baud", "bus";
> + dmas = < 2
> +3>;
> + dma-names = "tx", "rx";
> status = "disabled";
> };
>
> @@ -306,6 +333,9 @@ uart2: serial@11007000 {
> clocks = < CLK_TOP_UART2_SEL>,
> < CLK_TOP_UART2>;
> clock-names = "baud", "bus";
> + dmas = < 4
> +5>;
> + dma-names = "tx", "rx";
> status = "disabled";
> };
>
> --
> 2.29.2
>
[PATCH v2 1/2] arm64: dts: mediatek: mt8183: add pwm node
MT8183 SoC has 4 PWMs. Add the pwm node in order to support them.
Signed-off-by: Fabien Parent
---
V2: rename pwm0 to pwm1 since disp-pwm has been merged in v5.11 as pwm0
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 5b782a4769e7..a0004bd9f9c2 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -667,6 +667,20 @@ pwm0: pwm@1100e000 {
clock-names = "main", "mm";
};
+ pwm1: pwm@11006000 {
+ compatible = "mediatek,mt8183-pwm";
+ reg = <0 0x11006000 0 0x1000>;
+ #pwm-cells = <2>;
+ clocks = < CLK_INFRA_PWM>,
+< CLK_INFRA_PWM_HCLK>,
+< CLK_INFRA_PWM1>,
+< CLK_INFRA_PWM2>,
+< CLK_INFRA_PWM3>,
+< CLK_INFRA_PWM4>;
+ clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
+ "pwm4";
+ };
+
i2c3: i2c@1100f000 {
compatible = "mediatek,mt8183-i2c";
reg = <0 0x1100f000 0 0x1000>,
--
2.29.2
[PATCH v2 2/2] arm64: dts: mediatek: mt8183-evb: add PWM support
Enable the pwm driver and set the pinctrl for PWM A line.
Signed-off-by: Fabien Parent
---
V2:
* rename pwm0 to pwm1 since disp-pwm has been merged in v5.11 as pwm0
* rename the pio node and labels to match the coding standard of this
dts
arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
index cba2d8933e79..3249c959f76f 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
@@ -344,6 +344,12 @@ pins_spi{
bias-disable;
};
};
+
+ pwm_pins_1: pwm1 {
+ pins_pwm {
+ pinmux = ;
+ };
+ };
};
{
@@ -392,3 +398,9 @@ {
{
status = "okay";
};
+
+ {
+ status = "okay";
+ pinctrl-0 = <_pins_1>;
+ pinctrl-names = "default";
+};
--
2.29.2
[PATCH v3 2/2] soc: mediatek: pm-domains: Add support for mt8167
Add the needed board data to support mt8167 SoC.
Signed-off-by: Fabien Parent
Reviewed-by: Enric Balletbo i Serra
---
This patch was made on top of
https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/log/?h=v5.10-next/soc
v3:
* s/MT8167_POWER_DOMAIN_DISP/MT8167_POWER_DOMAIN_MM
* s/.domains/.domains_data
v2:
* Implement on top of new SCPSYS PM domains driver
drivers/soc/mediatek/mt8167-pm-domains.h | 86
drivers/soc/mediatek/mtk-pm-domains.c| 5 ++
drivers/soc/mediatek/mtk-pm-domains.h| 1 +
include/linux/soc/mediatek/infracfg.h| 8 +++
4 files changed, 100 insertions(+)
create mode 100644 drivers/soc/mediatek/mt8167-pm-domains.h
diff --git a/drivers/soc/mediatek/mt8167-pm-domains.h
b/drivers/soc/mediatek/mt8167-pm-domains.h
new file mode 100644
index ..ad0b8dfa0527
--- /dev/null
+++ b/drivers/soc/mediatek/mt8167-pm-domains.h
@@ -0,0 +1,86 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_MT8167_PM_DOMAINS_H
+#define __SOC_MEDIATEK_MT8167_PM_DOMAINS_H
+
+#include "mtk-pm-domains.h"
+#include
+
+#define MT8167_PWR_STATUS_MFG_2D BIT(24)
+#define MT8167_PWR_STATUS_MFG_ASYNCBIT(25)
+
+/*
+ * MT8167 power domain support
+ */
+
+static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = {
+ [MT8167_POWER_DOMAIN_MM] = {
+ .sta_mask = PWR_STATUS_DISP,
+ .ctl_offs = SPM_DIS_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .bp_infracfg = {
+ BUS_PROT_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_MM_EMI |
+ MT8167_TOP_AXI_PROT_EN_MCU_MM),
+ },
+ .caps = MTK_SCPD_ACTIVE_WAKEUP,
+ },
+ [MT8167_POWER_DOMAIN_VDEC] = {
+ .sta_mask = PWR_STATUS_VDEC,
+ .ctl_offs = SPM_VDE_PWR_CON,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .caps = MTK_SCPD_ACTIVE_WAKEUP,
+ },
+ [MT8167_POWER_DOMAIN_ISP] = {
+ .sta_mask = PWR_STATUS_ISP,
+ .ctl_offs = SPM_ISP_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(13, 12),
+ .caps = MTK_SCPD_ACTIVE_WAKEUP,
+ },
+ [MT8167_POWER_DOMAIN_MFG_ASYNC] = {
+ .sta_mask = MT8167_PWR_STATUS_MFG_ASYNC,
+ .ctl_offs = SPM_MFG_ASYNC_PWR_CON,
+ .sram_pdn_bits = 0,
+ .sram_pdn_ack_bits = 0,
+ .bp_infracfg = {
+ BUS_PROT_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_MCU_MFG |
+ MT8167_TOP_AXI_PROT_EN_MFG_EMI),
+ },
+ },
+ [MT8167_POWER_DOMAIN_MFG_2D] = {
+ .sta_mask = MT8167_PWR_STATUS_MFG_2D,
+ .ctl_offs = SPM_MFG_2D_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ },
+ [MT8167_POWER_DOMAIN_MFG] = {
+ .sta_mask = PWR_STATUS_MFG,
+ .ctl_offs = SPM_MFG_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ },
+ [MT8167_POWER_DOMAIN_CONN] = {
+ .sta_mask = PWR_STATUS_CONN,
+ .ctl_offs = SPM_CONN_PWR_CON,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = 0,
+ .caps = MTK_SCPD_ACTIVE_WAKEUP,
+ .bp_infracfg = {
+ BUS_PROT_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_CONN_EMI |
+ MT8167_TOP_AXI_PROT_EN_CONN_MCU |
+ MT8167_TOP_AXI_PROT_EN_MCU_CONN),
+ },
+ },
+};
+
+static const struct scpsys_soc_data mt8167_scpsys_data = {
+ .domains_data = scpsys_domain_data_mt8167,
+ .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8167),
+ .pwr_sta_offs = SPM_PWR_STATUS,
+ .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
+};
+
+#endif /* __SOC_MEDIATEK_MT8167_PM_DOMAINS_H */
+
diff --git a/drivers/soc/mediatek/mtk-pm-domains.c
b/drivers/soc/mediatek/mtk-pm-domains.c
index fb70cb3b07b3..2d0d50ff35f0 100644
--- a/drivers/soc/mediatek/mtk-pm-domains.c
+++ b/drivers/soc/mediatek/mtk-pm-domains.c
@@ -15,6 +15,7 @@
#include
#include
+#include "mt8167-pm-domains.h"
#include "mt8173-pm-domains.h"
#include "mt8183-pm-domains.h"
#include "mt8192-pm-domains.h"
@@ -514,6 +515,10 @@ static void scpsys_domain_cleanup(struct scpsys *scpsys)
}
static const struct of_device_id scpsys_of_match[] = {
+ {
+ .compatible = "mediatek,mt8167-power-controller",
+ .data = _scpsys_data,
+ },
[PATCH v3 1/2] dt-bindings: power: Add MT8167 power domains
Add power domains dt-bindings for MT8167. Signed-off-by: Fabien Parent Acked-by: Rob Herring --- This patch was made on top of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/log/?h=v5.10-next/soc v3: * Remove MT8167_POWER_DOMAIN_DISP since it was an alias for MT8167_POWER_DOMAIN_MM v2: * Implement on top of new SCPSYS PM domains driver .../power/mediatek,power-controller.yaml| 2 ++ include/dt-bindings/power/mt8167-power.h| 17 + 2 files changed, 19 insertions(+) create mode 100644 include/dt-bindings/power/mt8167-power.h diff --git a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml index fd12bafe3548..ad6db377f943 100644 --- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml +++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml @@ -23,6 +23,7 @@ properties: compatible: enum: + - mediatek,mt8167-power-controller - mediatek,mt8173-power-controller - mediatek,mt8183-power-controller - mediatek,mt8192-power-controller @@ -59,6 +60,7 @@ patternProperties: reg: description: | Power domain index. Valid values are defined in: + "include/dt-bindings/power/mt8167-power.h" - for MT8167 type power domain. "include/dt-bindings/power/mt8173-power.h" - for MT8173 type power domain. "include/dt-bindings/power/mt8183-power.h" - for MT8183 type power domain. "include/dt-bindings/power/mt8192-power.h" - for MT8192 type power domain. diff --git a/include/dt-bindings/power/mt8167-power.h b/include/dt-bindings/power/mt8167-power.h new file mode 100644 index ..c8ec9983a4bc --- /dev/null +++ b/include/dt-bindings/power/mt8167-power.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (c) 2020 MediaTek Inc. + */ + +#ifndef _DT_BINDINGS_POWER_MT8167_POWER_H +#define _DT_BINDINGS_POWER_MT8167_POWER_H + +#define MT8167_POWER_DOMAIN_MM 0 +#define MT8167_POWER_DOMAIN_VDEC 1 +#define MT8167_POWER_DOMAIN_ISP2 +#define MT8167_POWER_DOMAIN_CONN 3 +#define MT8167_POWER_DOMAIN_MFG_ASYNC 4 +#define MT8167_POWER_DOMAIN_MFG_2D 5 +#define MT8167_POWER_DOMAIN_MFG6 + +#endif /* _DT_BINDINGS_POWER_MT8167_POWER_H */ -- 2.29.2
[PATCH] mmc: host: mtk-sd: enable recheck_sdio_irq for MT8516 SoC
MT8516 SoC suffers from sometimes losing SDIO IRQs, this makes SDIO
devices sometimes unstable. Make use of the new property
recheck_sdio_irq to fix the SDIO stability issues on MT8516.
Signed-off-by: Fabien Parent
---
drivers/mmc/host/mtk-sd.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
index a704745e5882..3dc102eefe49 100644
--- a/drivers/mmc/host/mtk-sd.c
+++ b/drivers/mmc/host/mtk-sd.c
@@ -524,7 +524,7 @@ static const struct mtk_mmc_compatible mt7622_compat = {
static const struct mtk_mmc_compatible mt8516_compat = {
.clk_div_bits = 12,
- .recheck_sdio_irq = false,
+ .recheck_sdio_irq = true,
.hs400_tune = false,
.pad_tune_reg = MSDC_PAD_TUNE0,
.async_fifo = true,
--
2.28.0
[PATCH v2 0/5] Add DRM/DSI support for MT8167 SoC
This series adds support for DSI on the MT8167 SoC. HDMI is not yet supported as secondary display path. mmsys is not supported by this series and will be sent in a seperate series based on [0]. [0] https://patchwork.kernel.org/project/linux-mediatek/list/?series=360447 Changelog: V2: removed 3 patches Fabien Parent (5): dt-bindings: display: mediatek: disp: add documentation for MT8167 SoC dt-bindings: display: mediatek: dsi: add documentation for MT8167 SoC drm/mediatek: add disp-color MT8167 support drm/mediatek: add DDP support for MT8167 drm/mediatek: Add support for main DDP path on MT8167 .../display/mediatek/mediatek,disp.txt| 4 +- .../display/mediatek/mediatek,dsi.txt | 4 +- drivers/gpu/drm/mediatek/mtk_disp_color.c | 7 +++ drivers/gpu/drm/mediatek/mtk_drm_ddp.c| 47 +++ drivers/gpu/drm/mediatek/mtk_drm_drv.c| 38 +++ 5 files changed, 96 insertions(+), 4 deletions(-) -- 2.28.0
[PATCH v2 4/5] drm/mediatek: add DDP support for MT8167
Add DDP support for MT8167 SoC.
Signed-off-by: Fabien Parent
---
Changelog:
V2: don't set DDP_MUTEX_SOF_DSI{1,2,3} since they are not available on MT8167
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 47 ++
1 file changed, 47 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 014c1bbe1df2..1f99db6b1a42 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -25,6 +25,19 @@
#define INT_MUTEX BIT(1)
+#define MT8167_MUTEX_MOD_DISP_PWM 1
+#define MT8167_MUTEX_MOD_DISP_OVL0 6
+#define MT8167_MUTEX_MOD_DISP_OVL1 7
+#define MT8167_MUTEX_MOD_DISP_RDMA08
+#define MT8167_MUTEX_MOD_DISP_RDMA19
+#define MT8167_MUTEX_MOD_DISP_WDMA010
+#define MT8167_MUTEX_MOD_DISP_CCORR11
+#define MT8167_MUTEX_MOD_DISP_COLOR12
+#define MT8167_MUTEX_MOD_DISP_AAL 13
+#define MT8167_MUTEX_MOD_DISP_GAMMA14
+#define MT8167_MUTEX_MOD_DISP_DITHER 15
+#define MT8167_MUTEX_MOD_DISP_UFOE 16
+
#define MT8173_MUTEX_MOD_DISP_OVL0 11
#define MT8173_MUTEX_MOD_DISP_OVL1 12
#define MT8173_MUTEX_MOD_DISP_RDMA013
@@ -73,6 +86,8 @@
#define MUTEX_SOF_DPI1 4
#define MUTEX_SOF_DSI2 5
#define MUTEX_SOF_DSI3 6
+#define MT8167_MUTEX_SOF_DPI0 2
+#define MT8167_MUTEX_SOF_DPI1 3
struct mtk_disp_mutex {
@@ -135,6 +150,21 @@ static const unsigned int
mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1,
};
+static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+ [DDP_COMPONENT_AAL0] = MT8167_MUTEX_MOD_DISP_AAL,
+ [DDP_COMPONENT_CCORR] = MT8167_MUTEX_MOD_DISP_CCORR,
+ [DDP_COMPONENT_COLOR0] = MT8167_MUTEX_MOD_DISP_COLOR,
+ [DDP_COMPONENT_DITHER] = MT8167_MUTEX_MOD_DISP_DITHER,
+ [DDP_COMPONENT_GAMMA] = MT8167_MUTEX_MOD_DISP_GAMMA,
+ [DDP_COMPONENT_OVL0] = MT8167_MUTEX_MOD_DISP_OVL0,
+ [DDP_COMPONENT_OVL1] = MT8167_MUTEX_MOD_DISP_OVL1,
+ [DDP_COMPONENT_PWM0] = MT8167_MUTEX_MOD_DISP_PWM,
+ [DDP_COMPONENT_RDMA0] = MT8167_MUTEX_MOD_DISP_RDMA0,
+ [DDP_COMPONENT_RDMA1] = MT8167_MUTEX_MOD_DISP_RDMA1,
+ [DDP_COMPONENT_UFOE] = MT8167_MUTEX_MOD_DISP_UFOE,
+ [DDP_COMPONENT_WDMA0] = MT8167_MUTEX_MOD_DISP_WDMA0,
+};
+
static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL,
[DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0,
@@ -163,6 +193,13 @@ static const unsigned int
mt2712_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = {
[DDP_MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3,
};
+static const unsigned int mt8167_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = {
+ [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
+ [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
+ [DDP_MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0,
+ [DDP_MUTEX_SOF_DPI1] = MT8167_MUTEX_SOF_DPI1,
+};
+
static const struct mtk_ddp_data mt2701_ddp_driver_data = {
.mutex_mod = mt2701_mutex_mod,
.mutex_sof = mt2712_mutex_sof,
@@ -177,6 +214,14 @@ static const struct mtk_ddp_data mt2712_ddp_driver_data = {
.mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0,
};
+static const struct mtk_ddp_data mt8167_ddp_driver_data = {
+ .mutex_mod = mt8167_mutex_mod,
+ .mutex_sof = mt8167_mutex_sof,
+ .mutex_mod_reg = MT2701_DISP_MUTEX0_MOD0,
+ .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0,
+ .no_clk = true,
+};
+
static const struct mtk_ddp_data mt8173_ddp_driver_data = {
.mutex_mod = mt8173_mutex_mod,
.mutex_sof = mt2712_mutex_sof,
@@ -400,6 +445,8 @@ static const struct of_device_id ddp_driver_dt_match[] = {
.data = _ddp_driver_data},
{ .compatible = "mediatek,mt2712-disp-mutex",
.data = _ddp_driver_data},
+ { .compatible = "mediatek,mt8167-disp-mutex",
+ .data = _ddp_driver_data},
{ .compatible = "mediatek,mt8173-disp-mutex",
.data = _ddp_driver_data},
{},
--
2.28.0
[PATCH v2 3/5] drm/mediatek: add disp-color MT8167 support
Add support for disp-color on MT8167 SoC.
Signed-off-by: Fabien Parent
Reviewed-by: Chun-Kuang Hu
---
Changelog:
V2: No change
drivers/gpu/drm/mediatek/mtk_disp_color.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_color.c
b/drivers/gpu/drm/mediatek/mtk_disp_color.c
index 3ae9c810845b..a1227cefbf31 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_color.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_color.c
@@ -16,6 +16,7 @@
#define DISP_COLOR_CFG_MAIN0x0400
#define DISP_COLOR_START_MT27010x0f00
+#define DISP_COLOR_START_MT81670x0400
#define DISP_COLOR_START_MT81730x0c00
#define DISP_COLOR_START(comp) ((comp)->data->color_offset)
#define DISP_COLOR_WIDTH(comp) (DISP_COLOR_START(comp) + 0x50)
@@ -148,6 +149,10 @@ static const struct mtk_disp_color_data
mt2701_color_driver_data = {
.color_offset = DISP_COLOR_START_MT2701,
};
+static const struct mtk_disp_color_data mt8167_color_driver_data = {
+ .color_offset = DISP_COLOR_START_MT8167,
+};
+
static const struct mtk_disp_color_data mt8173_color_driver_data = {
.color_offset = DISP_COLOR_START_MT8173,
};
@@ -155,6 +160,8 @@ static const struct mtk_disp_color_data
mt8173_color_driver_data = {
static const struct of_device_id mtk_disp_color_driver_dt_match[] = {
{ .compatible = "mediatek,mt2701-disp-color",
.data = _color_driver_data},
+ { .compatible = "mediatek,mt8167-disp-color",
+ .data = _color_driver_data},
{ .compatible = "mediatek,mt8173-disp-color",
.data = _color_driver_data},
{},
--
2.28.0
[PATCH v2 2/5] dt-bindings: display: mediatek: dsi: add documentation for MT8167 SoC
Add binding documentation for the MT8167 SoC. Signed-off-by: Fabien Parent --- Changelog: V2: removed part that added a new clock .../devicetree/bindings/display/mediatek/mediatek,dsi.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt index f06f24d405a5..6a10de812158 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt @@ -7,7 +7,7 @@ channel output. Required properties: - compatible: "mediatek,-dsi" -- the supported chips are mt2701, mt7623, mt8173 and mt8183. +- the supported chips are mt2701, mt7623, mt8167, mt8173 and mt8183. - reg: Physical base address and length of the controller's registers - interrupts: The interrupt signal from the function block. - clocks: device clocks @@ -26,7 +26,7 @@ The MIPI TX configuration module controls the MIPI D-PHY. Required properties: - compatible: "mediatek,-mipi-tx" -- the supported chips are mt2701, 7623, mt8173 and mt8183. +- the supported chips are mt2701, 7623, mt8167, mt8173 and mt8183. - reg: Physical base address and length of the controller's registers - clocks: PLL reference clock - clock-output-names: name of the output clock line to the DSI encoder -- 2.28.0
[PATCH v2 5/5] drm/mediatek: Add support for main DDP path on MT8167
Add the main (DSI) drm display path for MT8167.
Signed-off-by: Fabien Parent
---
Changelog:
V2: No change
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 38 ++
1 file changed, 38 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 59c85c63b7cc..3952435093fe 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -112,6 +112,17 @@ static const enum mtk_ddp_comp_id mt2712_mtk_ddp_third[] =
{
DDP_COMPONENT_PWM2,
};
+static enum mtk_ddp_comp_id mt8167_mtk_ddp_main[] = {
+ DDP_COMPONENT_OVL0,
+ DDP_COMPONENT_COLOR0,
+ DDP_COMPONENT_CCORR,
+ DDP_COMPONENT_AAL0,
+ DDP_COMPONENT_GAMMA,
+ DDP_COMPONENT_DITHER,
+ DDP_COMPONENT_RDMA0,
+ DDP_COMPONENT_DSI0,
+};
+
static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = {
DDP_COMPONENT_OVL0,
DDP_COMPONENT_COLOR0,
@@ -163,6 +174,11 @@ static const struct mtk_mmsys_driver_data
mt8173_mmsys_driver_data = {
.ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
};
+static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
+ .main_path = mt8167_mtk_ddp_main,
+ .main_len = ARRAY_SIZE(mt8167_mtk_ddp_main),
+};
+
static int mtk_drm_kms_init(struct drm_device *drm)
{
struct mtk_drm_private *private = drm->dev_private;
@@ -401,26 +417,42 @@ static const struct component_master_ops mtk_drm_ops = {
static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
{ .compatible = "mediatek,mt2701-disp-ovl",
.data = (void *)MTK_DISP_OVL },
+ { .compatible = "mediatek,mt8167-disp-ovl",
+ .data = (void *)MTK_DISP_OVL },
{ .compatible = "mediatek,mt8173-disp-ovl",
.data = (void *)MTK_DISP_OVL },
{ .compatible = "mediatek,mt2701-disp-rdma",
.data = (void *)MTK_DISP_RDMA },
+ { .compatible = "mediatek,mt8167-disp-rdma",
+ .data = (void *)MTK_DISP_RDMA },
{ .compatible = "mediatek,mt8173-disp-rdma",
.data = (void *)MTK_DISP_RDMA },
{ .compatible = "mediatek,mt8173-disp-wdma",
.data = (void *)MTK_DISP_WDMA },
+ { .compatible = "mediatek,mt8167-disp-ccorr",
+ .data = (void *)MTK_DISP_CCORR },
{ .compatible = "mediatek,mt2701-disp-color",
.data = (void *)MTK_DISP_COLOR },
+ { .compatible = "mediatek,mt8167-disp-color",
+ .data = (void *)MTK_DISP_COLOR },
{ .compatible = "mediatek,mt8173-disp-color",
.data = (void *)MTK_DISP_COLOR },
+ { .compatible = "mediatek,mt8167-disp-aal",
+ .data = (void *)MTK_DISP_AAL},
{ .compatible = "mediatek,mt8173-disp-aal",
.data = (void *)MTK_DISP_AAL},
+ { .compatible = "mediatek,mt8167-disp-gamma",
+ .data = (void *)MTK_DISP_GAMMA, },
{ .compatible = "mediatek,mt8173-disp-gamma",
.data = (void *)MTK_DISP_GAMMA, },
+ { .compatible = "mediatek,mt8167-disp-dither",
+ .data = (void *)MTK_DISP_DITHER },
{ .compatible = "mediatek,mt8173-disp-ufoe",
.data = (void *)MTK_DISP_UFOE },
{ .compatible = "mediatek,mt2701-dsi",
.data = (void *)MTK_DSI },
+ { .compatible = "mediatek,mt8167-dsi",
+ .data = (void *)MTK_DSI },
{ .compatible = "mediatek,mt8173-dsi",
.data = (void *)MTK_DSI },
{ .compatible = "mediatek,mt2701-dpi",
@@ -431,10 +463,14 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt2712-disp-mutex",
.data = (void *)MTK_DISP_MUTEX },
+ { .compatible = "mediatek,mt8167-disp-mutex",
+ .data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt8173-disp-mutex",
.data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt2701-disp-pwm",
.data = (void *)MTK_DISP_BLS },
+ { .compatible = "mediatek,mt8167-disp-pwm",
+ .data = (void *)MTK_DISP_PWM },
{ .compatible = "mediatek,mt8173-disp-pwm",
.data = (void *)MTK_DISP_PWM },
{ .compatible = "mediatek,mt8173-disp-od",
@@ -449,6 +485,8 @@ static const struct of_device_id mtk_drm_of_ids[] = {
.data = _mmsys_driver_data},
{ .compatible = "mediatek,mt2712-mmsys",
.data = _mmsys_driver_data},
+ { .compatible = "mediatek,mt8167-mmsys",
+ .data = _mmsys_driver_data},
{ .compatible = "mediatek,mt8173-mmsys",
.data = _mmsys_driver_data},
{ }
--
2.28.0
[PATCH v2 1/5] dt-bindings: display: mediatek: disp: add documentation for MT8167 SoC
Add binding documentation for the MT8167 SoC Signed-off-by: Fabien Parent Reviewed-by: Chun-Kuang Hu --- Changelog: V2: No change .../devicetree/bindings/display/mediatek/mediatek,disp.txt| 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt index 121220745d46..33977e15bebd 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt @@ -43,7 +43,7 @@ Required properties (all function blocks): "mediatek,-dpi" - DPI controller, see mediatek,dpi.txt "mediatek,-disp-mutex"- display mutex "mediatek,-disp-od" - overdrive - the supported chips are mt2701, mt7623, mt2712 and mt8173. + the supported chips are mt2701, mt7623, mt2712, mt8167 and mt8173. - reg: Physical base address and length of the function block register space - interrupts: The interrupt signal from the function block (required, except for merge and split function blocks). @@ -59,7 +59,7 @@ Required properties (DMA function blocks): "mediatek,-disp-ovl" "mediatek,-disp-rdma" "mediatek,-disp-wdma" - the supported chips are mt2701 and mt8173. + the supported chips are mt2701, mt8167 and mt8173. - larb: Should contain a phandle pointing to the local arbiter device as defined in Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt - iommus: Should point to the respective IOMMU block with master port as -- 2.28.0
[PATCH v5 1/2] dt-bindings: regulator: add support for MT6392
Add binding documentation of the regulator for MT6392 SoCs.
Signed-off-by: Fabien Parent
Reviewed-by: Rob Herring
---
v5:
* No change
v4:
* No change
v3:
* No change
v2:
* Use 'pmic' as node name for the pmic.
* Use 'regulators' as node name for the regulators
* use dash instead of underscore for regulator's node names.
.../bindings/regulator/mt6392-regulator.txt | 220 ++
1 file changed, 220 insertions(+)
create mode 100644
Documentation/devicetree/bindings/regulator/mt6392-regulator.txt
diff --git a/Documentation/devicetree/bindings/regulator/mt6392-regulator.txt
b/Documentation/devicetree/bindings/regulator/mt6392-regulator.txt
new file mode 100644
index ..d03c0707fabc
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/mt6392-regulator.txt
@@ -0,0 +1,220 @@
+Mediatek MT6392 Regulator
+
+Required properties:
+- compatible: "mediatek,mt6392-regulator"
+- mt6392regulator: List of regulators provided by this controller. It is named
+ according to its regulator type, buck_ and ldo_.
+ The definition for each of these nodes is defined using the standard binding
+ for regulators at Documentation/devicetree/bindings/regulator/regulator.txt.
+
+The valid names for regulators are::
+BUCK:
+ buck_vproc, buck_vsys, buck_vcore
+LDO:
+ ldo_vxo22, ldo_vaud22, ldo_vcama, ldo_vaud28, ldo_vadc18, ldo_vcn35,
+ ldo_vio28. ldo_vusb, ldo_vmc, ldo_vmch, ldo_vemc3v3, ldo_vgp1, ldo_vgp2,
+ ldo_vcn18, ldo_vcamaf, ldo_vm, ldo_vio18, ldo_vcamd, ldo_vcamio, ldo_vm25,
+ ldo_vefuse
+
+Example:
+ pmic {
+ compatible = "mediatek,mt6392", "mediatek,mt6323";
+ mediatek,system-power-controller;
+
+ regulator {
+ compatible = "mediatek,mt6392-regulator";
+
+ mt6392_vproc_reg: buck-vproc {
+ regulator-name = "buck_vproc";
+ regulator-min-microvolt = < 70>;
+ regulator-max-microvolt = <135>;
+ regulator-ramp-delay = <12500>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ mt6392_vsys_reg: buck-vsys {
+ regulator-name = "buck_vsys";
+ regulator-min-microvolt = <140>;
+ regulator-max-microvolt = <2987500>;
+ regulator-ramp-delay = <25000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ mt6392_vcore_reg: buck-vcore {
+ regulator-name = "buck_vcore";
+ regulator-min-microvolt = < 70>;
+ regulator-max-microvolt = <135>;
+ regulator-ramp-delay = <12500>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ mt6392_vxo22_reg: ldo-vxo22 {
+ regulator-name = "ldo_vxo22";
+ regulator-min-microvolt = <220>;
+ regulator-max-microvolt = <220>;
+ regulator-enable-ramp-delay = <110>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ mt6392_vaud22_reg: ldo-vaud22 {
+ regulator-name = "ldo_vaud22";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <220>;
+ regulator-enable-ramp-delay = <264>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ mt6392_vcama_reg: ldo-vcama {
+ regulator-name = "ldo_vcama";
+ regulator-min-microvolt = <280>;
+ regulator-max-microvolt = <280>;
+ regulator-enable-ramp-delay = <264>;
+ };
+
+ mt6392_vaud28_reg: ldo-vaud28 {
+ regulator-name = "ldo_vaud28";
+ regulator-min-microvolt = <280>;
+ regulator-max-microvolt = <280>;
+
[PATCH v5 2/2] regulator: mt6392: Add support for MT6392 regulator
The MT6392 is a regulator found on boards based on the MediaTek
MT8167, MT8516, and probably other SoCs. It is a so called PMIC and
connectcts as a slave to a SoC using SPI, wrapped inside PWRAP.
Signed-off-by: Fabien Parent
---
V5:
* Removed unneeded code
* Fix indentation
* Rebased
* Switched some regulator to be linear
* Use C++ style header style
* Fix copyrights
V4:
* No change
V3:
* fix regulator's of_match following the renaming of the of nodes.
V2:
* no changes
drivers/regulator/Kconfig | 9 +
drivers/regulator/Makefile | 1 +
drivers/regulator/mt6392-regulator.c | 454 +
include/linux/regulator/mt6392-regulator.h | 40 ++
4 files changed, 504 insertions(+)
create mode 100644 drivers/regulator/mt6392-regulator.c
create mode 100644 include/linux/regulator/mt6392-regulator.h
diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index 020a00d6696b..e689c5a85197 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -739,6 +739,15 @@ config REGULATOR_MT6380
This driver supports the control of different power rails of device
through regulator interface.
+config REGULATOR_MT6392
+ tristate "MediaTek MT6392 PMIC"
+ depends on MFD_MT6397
+ help
+ Say y here to select this option to enable the power regulator of
+ MediaTek MT6392 PMIC.
+ This driver supports the control of different power rails of device
+ through regulator interface.
+
config REGULATOR_MT6397
tristate "MediaTek MT6397 PMIC"
depends on MFD_MT6397
diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
index 6ebae516258e..1bac57a5bfcf 100644
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -91,6 +91,7 @@ obj-$(CONFIG_REGULATOR_MT6323)+= mt6323-regulator.o
obj-$(CONFIG_REGULATOR_MT6358) += mt6358-regulator.o
obj-$(CONFIG_REGULATOR_MT6360) += mt6360-regulator.o
obj-$(CONFIG_REGULATOR_MT6380) += mt6380-regulator.o
+obj-$(CONFIG_REGULATOR_MT6392) += mt6392-regulator.o
obj-$(CONFIG_REGULATOR_MT6397) += mt6397-regulator.o
obj-$(CONFIG_REGULATOR_QCOM_LABIBB) += qcom-labibb-regulator.o
obj-$(CONFIG_REGULATOR_QCOM_RPM) += qcom_rpm-regulator.o
diff --git a/drivers/regulator/mt6392-regulator.c
b/drivers/regulator/mt6392-regulator.c
new file mode 100644
index ..25e620944b2a
--- /dev/null
+++ b/drivers/regulator/mt6392-regulator.c
@@ -0,0 +1,454 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (c) 2020 MediaTek Inc.
+// Copyright (c) 2020 BayLibre, SAS.
+// Author: Chen Zhong
+// Author: Fabien Parent
+//
+// Based on mt6397-regulator.c
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define MT6392_BUCK_MODE_AUTO 0
+#define MT6392_BUCK_MODE_FORCE_PWM 1
+#define MT6392_LDO_MODE_NORMAL 0
+#define MT6392_LDO_MODE_LP 1
+
+/*
+ * MT6392 regulators' information
+ *
+ * @desc: standard fields of regulator description.
+ * @qi: Mask for query enable signal status of regulators
+ * @vselon_reg: Register sections for hardware control mode of bucks
+ * @vselctrl_reg: Register for controlling the buck control mode.
+ * @vselctrl_mask: Mask for query buck's voltage control mode.
+ */
+struct mt6392_regulator_info {
+ struct regulator_desc desc;
+ u32 qi;
+ u32 vselon_reg;
+ u32 vselctrl_reg;
+ u32 vselctrl_mask;
+ u32 modeset_reg;
+ u32 modeset_mask;
+};
+
+#define MT6392_BUCK(match, vreg, min, max, step, volt_ranges, enreg, \
+ vosel, vosel_mask, voselon, vosel_ctrl, \
+ _modeset_reg, _modeset_mask)\
+[MT6392_ID_##vreg] = { \
+ .desc = { \
+ .name = #vreg, \
+ .of_match = of_match_ptr(match),\
+ .ops = _volt_range_ops, \
+ .type = REGULATOR_VOLTAGE, \
+ .id = MT6392_ID_##vreg, \
+ .owner = THIS_MODULE, \
+ .n_voltages = (max - min)/step + 1, \
+ .linear_ranges = volt_ranges, \
+ .n_linear_ranges = ARRAY_SIZE(volt_ranges), \
+ .vsel_reg = vosel, \
+ .vsel_mask = vosel_mask,\
+ .enable_reg = enreg,\
+
[PATCH 0/8] Add DRM/DSI support for MT8167 SoC.
This series adds support for DSI on the MT8167 SoC. HDMI is not yet supported as secondary display path. mmsys is not supported by this series and will be sent in a seperate series based on [0]. [0] https://patchwork.kernel.org/project/linux-mediatek/list/?series=360447 Fabien Parent (8): dt-bindings: display: mediatek: disp: add documentation for MT8167 SoC dt-bindings: display: mediatek: dsi: add documentation for MT8167 SoC drm/mediatek: add disp-color MT8167 support drm/mediatek: dsi: add pdata variable to start clk in HS mode drm/mediatek: dsi: add support for mipi26m clk drm/mediatek: dsi: add support for MT8167 SoC drm/mediatek: add DDP support for MT8167 drm/mediatek: Add support for main DDP path on MT8167 .../display/mediatek/mediatek,disp.txt| 4 +- .../display/mediatek/mediatek,dsi.txt | 7 +-- drivers/gpu/drm/mediatek/mtk_disp_color.c | 7 +++ drivers/gpu/drm/mediatek/mtk_drm_ddp.c| 50 +++ drivers/gpu/drm/mediatek/mtk_drm_drv.c| 38 ++ drivers/gpu/drm/mediatek/mtk_dsi.c| 20 +++- 6 files changed, 120 insertions(+), 6 deletions(-) -- 2.28.0
[PATCH 2/8] dt-bindings: display: mediatek: dsi: add documentation for MT8167 SoC
Add binding documentation for the MT8167 SoC. The SoC needs an additional clock compared to the already supported SoC: mipi26m. Signed-off-by: Fabien Parent --- .../devicetree/bindings/display/mediatek/mediatek,dsi.txt | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt index f06f24d405a5..10ae6be7225e 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt @@ -7,12 +7,13 @@ channel output. Required properties: - compatible: "mediatek,-dsi" -- the supported chips are mt2701, mt7623, mt8173 and mt8183. +- the supported chips are mt2701, mt7623, mt8167, mt8173 and mt8183. - reg: Physical base address and length of the controller's registers - interrupts: The interrupt signal from the function block. - clocks: device clocks See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. -- clock-names: must contain "engine", "digital", and "hs" +- clock-names: must contain "engine", "digital", "hs" + Can optionnally also contain "mipi26m" - phys: phandle link to the MIPI D-PHY controller. - phy-names: must contain "dphy" - port: Output port node with endpoint definitions as described in @@ -26,7 +27,7 @@ The MIPI TX configuration module controls the MIPI D-PHY. Required properties: - compatible: "mediatek,-mipi-tx" -- the supported chips are mt2701, 7623, mt8173 and mt8183. +- the supported chips are mt2701, 7623, mt8167, mt8173 and mt8183. - reg: Physical base address and length of the controller's registers - clocks: PLL reference clock - clock-output-names: name of the output clock line to the DSI encoder -- 2.28.0
[PATCH 4/8] drm/mediatek: dsi: add pdata variable to start clk in HS mode
On MT8167, DSI seems to work fine only if we start the clk in HS mode.
If we don't start the clk in HS but try to switch later to HS, the
display does not work.
This commit adds a platform data variable to be used to start the
DSI clk in HS mode at power on.
Signed-off-by: Fabien Parent
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 4a188a942c38..461643c05689 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -175,6 +175,7 @@ struct mtk_dsi_driver_data {
const u32 reg_cmdq_off;
bool has_shadow_ctl;
bool has_size_ctl;
+ bool use_hs_on_power_on;
};
struct mtk_dsi {
@@ -671,7 +672,7 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
mtk_dsi_clk_ulp_mode_leave(dsi);
mtk_dsi_lane0_ulp_mode_leave(dsi);
- mtk_dsi_clk_hs_mode(dsi, 0);
+ mtk_dsi_clk_hs_mode(dsi, !!dsi->driver_data->use_hs_on_power_on);
return 0;
err_disable_engine_clk:
--
2.28.0
[PATCH 5/8] drm/mediatek: dsi: add support for mipi26m clk
MT8167 SoC needs an additional clock to be enabled. Add support for
the mipi26m clk.
Signed-off-by: Fabien Parent
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 461643c05689..08786734df8e 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -193,6 +193,7 @@ struct mtk_dsi {
struct clk *engine_clk;
struct clk *digital_clk;
struct clk *hs_clk;
+ struct clk *mipi26m;
u32 data_rate;
@@ -653,6 +654,12 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
goto err_disable_engine_clk;
}
+ ret = clk_prepare_enable(dsi->mipi26m);
+ if (ret < 0) {
+ dev_err(dev, "Failed to enable mipi26m clock: %d\n", ret);
+ goto err_phy_power_off;
+ }
+
mtk_dsi_enable(dsi);
if (dsi->driver_data->has_shadow_ctl)
@@ -710,6 +717,7 @@ static void mtk_dsi_poweroff(struct mtk_dsi *dsi)
clk_disable_unprepare(dsi->engine_clk);
clk_disable_unprepare(dsi->digital_clk);
+ clk_disable_unprepare(dsi->mipi26m);
phy_power_off(dsi->phy);
}
@@ -1086,6 +1094,8 @@ static int mtk_dsi_probe(struct platform_device *pdev)
goto err_unregister_host;
}
+ dsi->mipi26m = devm_clk_get_optional(dev, "mipi26m");
+
dsi->hs_clk = devm_clk_get(dev, "hs");
if (IS_ERR(dsi->hs_clk)) {
ret = PTR_ERR(dsi->hs_clk);
--
2.28.0
[PATCH 8/8] drm/mediatek: Add support for main DDP path on MT8167
Add the main (DSI) drm display path for MT8167.
Signed-off-by: Fabien Parent
---
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 38 ++
1 file changed, 38 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 59c85c63b7cc..3952435093fe 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -112,6 +112,17 @@ static const enum mtk_ddp_comp_id mt2712_mtk_ddp_third[] =
{
DDP_COMPONENT_PWM2,
};
+static enum mtk_ddp_comp_id mt8167_mtk_ddp_main[] = {
+ DDP_COMPONENT_OVL0,
+ DDP_COMPONENT_COLOR0,
+ DDP_COMPONENT_CCORR,
+ DDP_COMPONENT_AAL0,
+ DDP_COMPONENT_GAMMA,
+ DDP_COMPONENT_DITHER,
+ DDP_COMPONENT_RDMA0,
+ DDP_COMPONENT_DSI0,
+};
+
static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = {
DDP_COMPONENT_OVL0,
DDP_COMPONENT_COLOR0,
@@ -163,6 +174,11 @@ static const struct mtk_mmsys_driver_data
mt8173_mmsys_driver_data = {
.ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
};
+static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
+ .main_path = mt8167_mtk_ddp_main,
+ .main_len = ARRAY_SIZE(mt8167_mtk_ddp_main),
+};
+
static int mtk_drm_kms_init(struct drm_device *drm)
{
struct mtk_drm_private *private = drm->dev_private;
@@ -401,26 +417,42 @@ static const struct component_master_ops mtk_drm_ops = {
static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
{ .compatible = "mediatek,mt2701-disp-ovl",
.data = (void *)MTK_DISP_OVL },
+ { .compatible = "mediatek,mt8167-disp-ovl",
+ .data = (void *)MTK_DISP_OVL },
{ .compatible = "mediatek,mt8173-disp-ovl",
.data = (void *)MTK_DISP_OVL },
{ .compatible = "mediatek,mt2701-disp-rdma",
.data = (void *)MTK_DISP_RDMA },
+ { .compatible = "mediatek,mt8167-disp-rdma",
+ .data = (void *)MTK_DISP_RDMA },
{ .compatible = "mediatek,mt8173-disp-rdma",
.data = (void *)MTK_DISP_RDMA },
{ .compatible = "mediatek,mt8173-disp-wdma",
.data = (void *)MTK_DISP_WDMA },
+ { .compatible = "mediatek,mt8167-disp-ccorr",
+ .data = (void *)MTK_DISP_CCORR },
{ .compatible = "mediatek,mt2701-disp-color",
.data = (void *)MTK_DISP_COLOR },
+ { .compatible = "mediatek,mt8167-disp-color",
+ .data = (void *)MTK_DISP_COLOR },
{ .compatible = "mediatek,mt8173-disp-color",
.data = (void *)MTK_DISP_COLOR },
+ { .compatible = "mediatek,mt8167-disp-aal",
+ .data = (void *)MTK_DISP_AAL},
{ .compatible = "mediatek,mt8173-disp-aal",
.data = (void *)MTK_DISP_AAL},
+ { .compatible = "mediatek,mt8167-disp-gamma",
+ .data = (void *)MTK_DISP_GAMMA, },
{ .compatible = "mediatek,mt8173-disp-gamma",
.data = (void *)MTK_DISP_GAMMA, },
+ { .compatible = "mediatek,mt8167-disp-dither",
+ .data = (void *)MTK_DISP_DITHER },
{ .compatible = "mediatek,mt8173-disp-ufoe",
.data = (void *)MTK_DISP_UFOE },
{ .compatible = "mediatek,mt2701-dsi",
.data = (void *)MTK_DSI },
+ { .compatible = "mediatek,mt8167-dsi",
+ .data = (void *)MTK_DSI },
{ .compatible = "mediatek,mt8173-dsi",
.data = (void *)MTK_DSI },
{ .compatible = "mediatek,mt2701-dpi",
@@ -431,10 +463,14 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt2712-disp-mutex",
.data = (void *)MTK_DISP_MUTEX },
+ { .compatible = "mediatek,mt8167-disp-mutex",
+ .data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt8173-disp-mutex",
.data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt2701-disp-pwm",
.data = (void *)MTK_DISP_BLS },
+ { .compatible = "mediatek,mt8167-disp-pwm",
+ .data = (void *)MTK_DISP_PWM },
{ .compatible = "mediatek,mt8173-disp-pwm",
.data = (void *)MTK_DISP_PWM },
{ .compatible = "mediatek,mt8173-disp-od",
@@ -449,6 +485,8 @@ static const struct of_device_id mtk_drm_of_ids[] = {
.data = _mmsys_driver_data},
{ .compatible = "mediatek,mt2712-mmsys",
.data = _mmsys_driver_data},
+ { .compatible = "mediatek,mt8167-mmsys",
+ .data = _mmsys_driver_data},
{ .compatible = "mediatek,mt8173-mmsys",
.data = _mmsys_driver_data},
{ }
--
2.28.0
[PATCH 6/8] drm/mediatek: dsi: add support for MT8167 SoC
Add platform data to support the MT8167 SoC.
Signed-off-by: Fabien Parent
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 08786734df8e..d90dd0f83292 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -1182,6 +1182,11 @@ static int mtk_dsi_remove(struct platform_device *pdev)
return 0;
}
+static const struct mtk_dsi_driver_data mt8167_dsi_driver_data = {
+ .reg_cmdq_off = 0x180,
+ .use_hs_on_power_on = true,
+};
+
static const struct mtk_dsi_driver_data mt8173_dsi_driver_data = {
.reg_cmdq_off = 0x200,
};
@@ -1199,6 +1204,8 @@ static const struct mtk_dsi_driver_data
mt8183_dsi_driver_data = {
static const struct of_device_id mtk_dsi_of_match[] = {
{ .compatible = "mediatek,mt2701-dsi",
.data = _dsi_driver_data },
+ { .compatible = "mediatek,mt8167-dsi",
+ .data = _dsi_driver_data },
{ .compatible = "mediatek,mt8173-dsi",
.data = _dsi_driver_data },
{ .compatible = "mediatek,mt8183-dsi",
--
2.28.0
[PATCH 1/8] dt-bindings: display: mediatek: disp: add documentation for MT8167 SoC
Add binding documentation for the MT8167 SoC Signed-off-by: Fabien Parent --- .../devicetree/bindings/display/mediatek/mediatek,disp.txt| 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt index 121220745d46..33977e15bebd 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt @@ -43,7 +43,7 @@ Required properties (all function blocks): "mediatek,-dpi" - DPI controller, see mediatek,dpi.txt "mediatek,-disp-mutex"- display mutex "mediatek,-disp-od" - overdrive - the supported chips are mt2701, mt7623, mt2712 and mt8173. + the supported chips are mt2701, mt7623, mt2712, mt8167 and mt8173. - reg: Physical base address and length of the function block register space - interrupts: The interrupt signal from the function block (required, except for merge and split function blocks). @@ -59,7 +59,7 @@ Required properties (DMA function blocks): "mediatek,-disp-ovl" "mediatek,-disp-rdma" "mediatek,-disp-wdma" - the supported chips are mt2701 and mt8173. + the supported chips are mt2701, mt8167 and mt8173. - larb: Should contain a phandle pointing to the local arbiter device as defined in Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt - iommus: Should point to the respective IOMMU block with master port as -- 2.28.0
[PATCH 7/8] drm/mediatek: add DDP support for MT8167
Add DDP support for MT8167 SoC.
Signed-off-by: Fabien Parent
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 50 ++
1 file changed, 50 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 014c1bbe1df2..bb62fdcf3d71 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -25,6 +25,19 @@
#define INT_MUTEX BIT(1)
+#define MT8167_MUTEX_MOD_DISP_PWM 1
+#define MT8167_MUTEX_MOD_DISP_OVL0 6
+#define MT8167_MUTEX_MOD_DISP_OVL1 7
+#define MT8167_MUTEX_MOD_DISP_RDMA08
+#define MT8167_MUTEX_MOD_DISP_RDMA19
+#define MT8167_MUTEX_MOD_DISP_WDMA010
+#define MT8167_MUTEX_MOD_DISP_CCORR11
+#define MT8167_MUTEX_MOD_DISP_COLOR12
+#define MT8167_MUTEX_MOD_DISP_AAL 13
+#define MT8167_MUTEX_MOD_DISP_GAMMA14
+#define MT8167_MUTEX_MOD_DISP_DITHER 15
+#define MT8167_MUTEX_MOD_DISP_UFOE 16
+
#define MT8173_MUTEX_MOD_DISP_OVL0 11
#define MT8173_MUTEX_MOD_DISP_OVL1 12
#define MT8173_MUTEX_MOD_DISP_RDMA013
@@ -73,6 +86,8 @@
#define MUTEX_SOF_DPI1 4
#define MUTEX_SOF_DSI2 5
#define MUTEX_SOF_DSI3 6
+#define MT8167_MUTEX_SOF_DPI0 2
+#define MT8167_MUTEX_SOF_DPI1 3
struct mtk_disp_mutex {
@@ -135,6 +150,21 @@ static const unsigned int
mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1,
};
+static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+ [DDP_COMPONENT_AAL0] = MT8167_MUTEX_MOD_DISP_AAL,
+ [DDP_COMPONENT_CCORR] = MT8167_MUTEX_MOD_DISP_CCORR,
+ [DDP_COMPONENT_COLOR0] = MT8167_MUTEX_MOD_DISP_COLOR,
+ [DDP_COMPONENT_DITHER] = MT8167_MUTEX_MOD_DISP_DITHER,
+ [DDP_COMPONENT_GAMMA] = MT8167_MUTEX_MOD_DISP_GAMMA,
+ [DDP_COMPONENT_OVL0] = MT8167_MUTEX_MOD_DISP_OVL0,
+ [DDP_COMPONENT_OVL1] = MT8167_MUTEX_MOD_DISP_OVL1,
+ [DDP_COMPONENT_PWM0] = MT8167_MUTEX_MOD_DISP_PWM,
+ [DDP_COMPONENT_RDMA0] = MT8167_MUTEX_MOD_DISP_RDMA0,
+ [DDP_COMPONENT_RDMA1] = MT8167_MUTEX_MOD_DISP_RDMA1,
+ [DDP_COMPONENT_UFOE] = MT8167_MUTEX_MOD_DISP_UFOE,
+ [DDP_COMPONENT_WDMA0] = MT8167_MUTEX_MOD_DISP_WDMA0,
+};
+
static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL,
[DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0,
@@ -163,6 +193,16 @@ static const unsigned int
mt2712_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = {
[DDP_MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3,
};
+static const unsigned int mt8167_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = {
+ [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
+ [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
+ [DDP_MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1,
+ [DDP_MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0,
+ [DDP_MUTEX_SOF_DPI1] = MT8167_MUTEX_SOF_DPI1,
+ [DDP_MUTEX_SOF_DSI2] = MUTEX_SOF_DSI2,
+ [DDP_MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3,
+};
+
static const struct mtk_ddp_data mt2701_ddp_driver_data = {
.mutex_mod = mt2701_mutex_mod,
.mutex_sof = mt2712_mutex_sof,
@@ -177,6 +217,14 @@ static const struct mtk_ddp_data mt2712_ddp_driver_data = {
.mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0,
};
+static const struct mtk_ddp_data mt8167_ddp_driver_data = {
+ .mutex_mod = mt8167_mutex_mod,
+ .mutex_sof = mt8167_mutex_sof,
+ .mutex_mod_reg = MT2701_DISP_MUTEX0_MOD0,
+ .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0,
+ .no_clk = true,
+};
+
static const struct mtk_ddp_data mt8173_ddp_driver_data = {
.mutex_mod = mt8173_mutex_mod,
.mutex_sof = mt2712_mutex_sof,
@@ -400,6 +448,8 @@ static const struct of_device_id ddp_driver_dt_match[] = {
.data = _ddp_driver_data},
{ .compatible = "mediatek,mt2712-disp-mutex",
.data = _ddp_driver_data},
+ { .compatible = "mediatek,mt8167-disp-mutex",
+ .data = _ddp_driver_data},
{ .compatible = "mediatek,mt8173-disp-mutex",
.data = _ddp_driver_data},
{},
--
2.28.0
[PATCH 3/8] drm/mediatek: add disp-color MT8167 support
Add support for disp-color on MT8167 SoC.
Signed-off-by: Fabien Parent
---
drivers/gpu/drm/mediatek/mtk_disp_color.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_color.c
b/drivers/gpu/drm/mediatek/mtk_disp_color.c
index 3ae9c810845b..a1227cefbf31 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_color.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_color.c
@@ -16,6 +16,7 @@
#define DISP_COLOR_CFG_MAIN0x0400
#define DISP_COLOR_START_MT27010x0f00
+#define DISP_COLOR_START_MT81670x0400
#define DISP_COLOR_START_MT81730x0c00
#define DISP_COLOR_START(comp) ((comp)->data->color_offset)
#define DISP_COLOR_WIDTH(comp) (DISP_COLOR_START(comp) + 0x50)
@@ -148,6 +149,10 @@ static const struct mtk_disp_color_data
mt2701_color_driver_data = {
.color_offset = DISP_COLOR_START_MT2701,
};
+static const struct mtk_disp_color_data mt8167_color_driver_data = {
+ .color_offset = DISP_COLOR_START_MT8167,
+};
+
static const struct mtk_disp_color_data mt8173_color_driver_data = {
.color_offset = DISP_COLOR_START_MT8173,
};
@@ -155,6 +160,8 @@ static const struct mtk_disp_color_data
mt8173_color_driver_data = {
static const struct of_device_id mtk_disp_color_driver_dt_match[] = {
{ .compatible = "mediatek,mt2701-disp-color",
.data = _color_driver_data},
+ { .compatible = "mediatek,mt8167-disp-color",
+ .data = _color_driver_data},
{ .compatible = "mediatek,mt8173-disp-color",
.data = _color_driver_data},
{},
--
2.28.0
[PATCH 2/3] dt-bindings: thermal: mediatek: add documentation for MT8516 SoC
Add binding documentation for the MediaTek MT8516 SoC. The SoC thermal IP is similar to MT2701. Signed-off-by: Fabien Parent --- Documentation/devicetree/bindings/thermal/mediatek-thermal.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt b/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt index 2d20f6b0dca0..5c7e7bdd029a 100644 --- a/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt +++ b/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt @@ -14,6 +14,7 @@ Required properties: - "mediatek,mt2712-thermal" : For MT2712 family of SoCs - "mediatek,mt7622-thermal" : For MT7622 SoC - "mediatek,mt8183-thermal" : For MT8183 family of SoCs + - "mediatek,mt8516-thermal", "mediatek,mt2701-thermal : For MT8516 family of SoCs - reg: Address range of the thermal controller - interrupts: IRQ for the thermal controller - clocks, clock-names: Clocks needed for the thermal controller. required -- 2.28.0
[PATCH 3/3] thermal: mtk_thermal: make device_reset optional
MT8516 does not support thermal reset. Use device_reset_optional instead of device_reset. Signed-off-by: Fabien Parent --- drivers/thermal/mtk_thermal.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c index 0bd7aa564bc2..149c6d7fd5a0 100644 --- a/drivers/thermal/mtk_thermal.c +++ b/drivers/thermal/mtk_thermal.c @@ -1052,7 +1052,7 @@ static int mtk_thermal_probe(struct platform_device *pdev) return -EINVAL; } - ret = device_reset(>dev); + ret = device_reset_optional(>dev); if (ret) return ret; -- 2.28.0
[PATCH 1/3] dt-bindings: thermal: mediatek: make resets property optional
MT8516 Thermal IP does not support reset. Make the resets property optional in order to be able to support MT8516 SoC. Signed-off-by: Fabien Parent --- Documentation/devicetree/bindings/thermal/mediatek-thermal.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt b/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt index 1e249c42fae0..2d20f6b0dca0 100644 --- a/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt +++ b/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt @@ -20,12 +20,12 @@ Required properties: clocks are: "therm": Main clock needed for register access "auxadc": The AUXADC clock -- resets: Reference to the reset controller controlling the thermal controller. - mediatek,auxadc: A phandle to the AUXADC which the thermal controller uses - mediatek,apmixedsys: A phandle to the APMIXEDSYS controller. - #thermal-sensor-cells : Should be 0. See Documentation/devicetree/bindings/thermal/thermal-sensor.yaml for a description. Optional properties: +- resets: Reference to the reset controller controlling the thermal controller. - nvmem-cells: A phandle to the calibration data provided by a nvmem device. If unspecified default values shall be used. - nvmem-cell-names: Should be "calibration-data" -- 2.28.0
Re: [PATCH 2/8] dt-bindings: display: mediatek: dsi: add documentation for MT8167 SoC
Hi Chun-Kuang,
On Wed, Oct 21, 2020 at 7:01 PM Chun-Kuang Hu wrote:
>
> Hi, Fabien:
>
> Fabien Parent 於 2020年10月21日 週三 上午1:43寫道：
> >
> > Add binding documentation for the MT8167 SoC. The SoC needs
> > an additional clock compared to the already supported SoC: mipi26m.
> >
> > Signed-off-by: Fabien Parent
> > ---
> > .../devicetree/bindings/display/mediatek/mediatek,dsi.txt | 7 ---
> > 1 file changed, 4 insertions(+), 3 deletions(-)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
> > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
> > index f06f24d405a5..10ae6be7225e 100644
> > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
> > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
> > @@ -7,12 +7,13 @@ channel output.
> >
> > Required properties:
> > - compatible: "mediatek,-dsi"
> > -- the supported chips are mt2701, mt7623, mt8173 and mt8183.
> > +- the supported chips are mt2701, mt7623, mt8167, mt8173 and mt8183.
> > - reg: Physical base address and length of the controller's registers
> > - interrupts: The interrupt signal from the function block.
> > - clocks: device clocks
> >See Documentation/devicetree/bindings/clock/clock-bindings.txt for
> > details.
> > -- clock-names: must contain "engine", "digital", and "hs"
> > +- clock-names: must contain "engine", "digital", "hs"
> > + Can optionnally also contain "mipi26m"
>
> It seems that mipi26m is the clock of mipi-tx. In mt8173.dtsi [1],
> mipi-tx's clock is 26m.
>
> mipi_tx0: mipi-dphy@10215000 {
> compatible = "mediatek,mt8173-mipi-tx";
> reg = <0 0x10215000 0 0x1000>;
> clocks = <>;
> clock-output-names = "mipi_tx0_pll";
> #clock-cells = <0>;
> #phy-cells = <0>;
> status = "disabled";
> };
>
> If this is the clock of mipi-tx, it should be controlled by mipi-tx driver.
Thanks, I will fix that in v2.
>
> [1]
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/mediatek/mt8173.dtsi?h=v5.9
>
> Regards,
> Chun-Kuang.
>
> > - phys: phandle link to the MIPI D-PHY controller.
> > - phy-names: must contain "dphy"
> > - port: Output port node with endpoint definitions as described in
> > @@ -26,7 +27,7 @@ The MIPI TX configuration module controls the MIPI D-PHY.
> >
> > Required properties:
> > - compatible: "mediatek,-mipi-tx"
> > -- the supported chips are mt2701, 7623, mt8173 and mt8183.
> > +- the supported chips are mt2701, 7623, mt8167, mt8173 and mt8183.
> > - reg: Physical base address and length of the controller's registers
> > - clocks: PLL reference clock
> > - clock-output-names: name of the output clock line to the DSI encoder
> > --
> > 2.28.0
> >
Re: [PATCH 4/8] drm/mediatek: dsi: add pdata variable to start clk in HS mode
Hi Chun-Kuang,
On Wed, Oct 21, 2020 at 7:07 PM Chun-Kuang Hu wrote:
>
> Hi, Fabien:
>
> Fabien Parent 於 2020年10月21日 週三 上午1:43寫道：
> >
> > On MT8167, DSI seems to work fine only if we start the clk in HS mode.
> > If we don't start the clk in HS but try to switch later to HS, the
> > display does not work.
> >
> > This commit adds a platform data variable to be used to start the
> > DSI clk in HS mode at power on.
>
> This patch looks like a hack patch. If you cowork with Mediatek,
> please find out the correct solution or give a reasonable explanation.
> If you could not get help from Mediatek, I would wait for comment on
> this patch.
It seems that this workaround is because of a specific display and not
because of a specific issue of the MT8167 DSI IP. I will drop this
patch in v2.
> Regards,
> Chun-Kuang.
>
> >
> > Signed-off-by: Fabien Parent
> > ---
> > drivers/gpu/drm/mediatek/mtk_dsi.c | 3 ++-
> > 1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
> > b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > index 4a188a942c38..461643c05689 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > @@ -175,6 +175,7 @@ struct mtk_dsi_driver_data {
> > const u32 reg_cmdq_off;
> > bool has_shadow_ctl;
> > bool has_size_ctl;
> > + bool use_hs_on_power_on;
> > };
> >
> > struct mtk_dsi {
> > @@ -671,7 +672,7 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
> >
> > mtk_dsi_clk_ulp_mode_leave(dsi);
> > mtk_dsi_lane0_ulp_mode_leave(dsi);
> > - mtk_dsi_clk_hs_mode(dsi, 0);
> > + mtk_dsi_clk_hs_mode(dsi, !!dsi->driver_data->use_hs_on_power_on);
> >
> > return 0;
> > err_disable_engine_clk:
> > --
> > 2.28.0
> >
Re: [PATCH v5 1/2] dt-bindings: regulator: add support for MT6392
Hi Mark,
On Mon, Oct 26, 2020 at 1:13 PM Mark Brown wrote:
>
> On Sat, Oct 24, 2020 at 10:03:03PM +0200, Fabien Parent wrote:
>
> > +Required properties:
> > +- compatible: "mediatek,mt6392-regulator"
>
> This is no longer used by the driver, should be unneeded and therefore
> should be removed.
It is not used by the driver but it will be used by the MFD driver [0]
like this:
static const struct mfd_cell mt6392_devs[] = {
{
[snip]
}, {
[snip]
}, {
.name = "mt6392-regulator",
.of_compatible = "mediatek,mt6392-regulator"
}, {
[snip]
},
};
[0] drivers/mfd/mt6397-core.c
>
> > +- mt6392regulator: List of regulators provided by this controller. It is
> > named
>
> This property doesn't seem to appear anywhere - there's regulators, the
> collection of subnodes for each individual regulator which I think is
> what is referenced here, but nothing called mt6392regulator.
Indeed, I will fix it in the next rev.
Re: [PATCH 2/2] clocksource: mediatek: add clk13m and bus clock support
Hi Rob,
On Mon, Oct 26, 2020 at 2:30 PM Rob Herring wrote:
>
> On Sat, Oct 17, 2020 at 05:38:57PM +0200, Fabien Parent wrote:
> > Some MediaTek SoC like MT8516 need to enable additional clocks
> > for the GPT timer. Enable them if present.
> >
> > Signed-off-by: Fabien Parent
> > ---
> > drivers/clocksource/timer-mediatek.c | 12
> > 1 file changed, 12 insertions(+)
> >
> > diff --git a/drivers/clocksource/timer-mediatek.c
> > b/drivers/clocksource/timer-mediatek.c
> > index 9318edcd8963..42e2d2090484 100644
> > --- a/drivers/clocksource/timer-mediatek.c
> > +++ b/drivers/clocksource/timer-mediatek.c
> > @@ -9,6 +9,7 @@
> >
> > #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
> >
> > +#include
> > #include
> > #include
> > #include
> > @@ -278,8 +279,19 @@ static int __init mtk_syst_init(struct device_node
> > *node)
> >
> > static int __init mtk_gpt_init(struct device_node *node)
> > {
> > + struct clk *clk_13m, *clk_bus;
> > int ret;
> >
> > + /* Optional clock*/
>
> Then use the optional api variant.
I looked for optional API variant but could only find these:
* struct clk *devm_clk_get_optional(struct device *dev, const char *id);
* struct clk *devm_clk_get_optional(struct device *dev, const char *id);
These two require a "struct device" parameter but in the function
mtk_gpt_init, we only have a "struct device_node" I didn't see any way
to get a "struct device" from a "struct device_node".
>
> > + clk_13m = of_clk_get_by_name(node, "clk13m");
> > + if (!IS_ERR(clk_13m))
>
> And then you can drop this check (or handle it for any error other than
> clock is not present).
>
> > + clk_prepare_enable(clk_13m);
> > +
> > + /* Optional clock*/
> > + clk_bus = of_clk_get_by_name(node, "bus");
> > + if (!IS_ERR(clk_bus))
> > + clk_prepare_enable(clk_bus);
> > +
> > to.clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
> > to.clkevt.set_state_shutdown = mtk_gpt_clkevt_shutdown;
> > to.clkevt.set_state_periodic = mtk_gpt_clkevt_set_periodic;
> > --
> > 2.28.0
> >
Re: [PATCH v5 1/2] dt-bindings: regulator: add support for MT6392
Hi Mark,
On Mon, Oct 26, 2020 at 6:24 PM Mark Brown wrote:
>
> On Mon, Oct 26, 2020 at 06:18:35PM +0100, Fabien Parent wrote:
> > On Mon, Oct 26, 2020 at 1:13 PM Mark Brown wrote:
>
> > > On Sat, Oct 24, 2020 at 10:03:03PM +0200, Fabien Parent wrote:
>
> > > > +Required properties:
> > > > +- compatible: "mediatek,mt6392-regulator"
>
> > > This is no longer used by the driver, should be unneeded and therefore
> > > should be removed.
>
> > It is not used by the driver but it will be used by the MFD driver [0]
> > like this:
> > static const struct mfd_cell mt6392_devs[] = {
> > {
> > [snip]
> > }, {
> > [snip]
> > }, {
> > .name = "mt6392-regulator",
> > .of_compatible = "mediatek,mt6392-regulator"
>
> This is still unneeded, it's just a reflection of Linux implementation
> details and should be removed. The MFD can just register the child
> without supplying a compatible and things will continue to work just as
> well.
I'm not exactly sure how it is supposed to work. mfd_add_devices seems
to register devices based on of_compatible or acpi_match from the
mfd_cell. This platform does not have ACPI so I don't understand how
the regulator driver would probe without this line. Anyway I tried to
remove the lines below in the MFD driver and the device tree and the
boot of the board failed because the regulator driver didn't probe.
Any help to get me understand how it should work without this line
would be helpful, thanks.
regulators {
- compatible = "mediatek,mt6392-regulator";
-
mt6392_vproc_reg: buck-vproc {
@@ -135,7 +135,6 @@ static const struct mfd_cell mt6392_devs[] = {
.of_compatible = "mediatek,mt6392-keys"
}, {
.name = "mt6392-regulator",
- .of_compatible = "mediatek,mt6392-regulator"
}, {
Re: [PATCH v3 05/16] soc: mediatek: pm_domains: Make bus protection generic
> - ret = mtk_infracfg_set_bus_protection(pd->infracfg, > - bpd[i].bus_prot_mask, > - > bpd[i].bus_prot_reg_update); [snip] > - ret = mtk_infracfg_clear_bus_protection(pd->infracfg, > - bpd[i].bus_prot_mask, > - > bpd[i].bus_prot_reg_update); Since you got rid of all the dependencies to mtk-infracfg.c, maybe you can also remove the "depends on MTK_INFRACFG" in the Kconfig.
[PATCH v2 2/2] soc: mediatek: pm-domains: Add support for mt8167
Add the needed board data to support mt8167 SoC.
Signed-off-by: Fabien Parent
---
This patch depends on the SCPSYS PM domains driver [0].
v2:
* Implement on top of new SCPSYS PM domains driver [0]
[0] https://patchwork.kernel.org/project/linux-mediatek/list/?series=370737
drivers/soc/mediatek/mt8167-pm-domains.h | 86
drivers/soc/mediatek/mtk-pm-domains.c| 5 ++
drivers/soc/mediatek/mtk-pm-domains.h| 1 +
include/linux/soc/mediatek/infracfg.h| 8 +++
4 files changed, 100 insertions(+)
create mode 100644 drivers/soc/mediatek/mt8167-pm-domains.h
diff --git a/drivers/soc/mediatek/mt8167-pm-domains.h
b/drivers/soc/mediatek/mt8167-pm-domains.h
new file mode 100644
index ..ff18139d0d6c
--- /dev/null
+++ b/drivers/soc/mediatek/mt8167-pm-domains.h
@@ -0,0 +1,86 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_MT8167_PM_DOMAINS_H
+#define __SOC_MEDIATEK_MT8167_PM_DOMAINS_H
+
+#include "mtk-pm-domains.h"
+#include
+
+#define MT8167_PWR_STATUS_MFG_2D BIT(24)
+#define MT8167_PWR_STATUS_MFG_ASYNCBIT(25)
+
+/*
+ * MT8167 power domain support
+ */
+
+static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = {
+ [MT8167_POWER_DOMAIN_DISP] = {
+ .sta_mask = PWR_STATUS_DISP,
+ .ctl_offs = SPM_DIS_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .bp_infracfg = {
+ BUS_PROT_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_MM_EMI |
+ MT8167_TOP_AXI_PROT_EN_MCU_MM),
+ },
+ .caps = MTK_SCPD_ACTIVE_WAKEUP,
+ },
+ [MT8167_POWER_DOMAIN_VDEC] = {
+ .sta_mask = PWR_STATUS_VDEC,
+ .ctl_offs = SPM_VDE_PWR_CON,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .caps = MTK_SCPD_ACTIVE_WAKEUP,
+ },
+ [MT8167_POWER_DOMAIN_ISP] = {
+ .sta_mask = PWR_STATUS_ISP,
+ .ctl_offs = SPM_ISP_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(13, 12),
+ .caps = MTK_SCPD_ACTIVE_WAKEUP,
+ },
+ [MT8167_POWER_DOMAIN_MFG_ASYNC] = {
+ .sta_mask = MT8167_PWR_STATUS_MFG_ASYNC,
+ .ctl_offs = SPM_MFG_ASYNC_PWR_CON,
+ .sram_pdn_bits = 0,
+ .sram_pdn_ack_bits = 0,
+ .bp_infracfg = {
+ BUS_PROT_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_MCU_MFG |
+ MT8167_TOP_AXI_PROT_EN_MFG_EMI),
+ },
+ },
+ [MT8167_POWER_DOMAIN_MFG_2D] = {
+ .sta_mask = MT8167_PWR_STATUS_MFG_2D,
+ .ctl_offs = SPM_MFG_2D_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ },
+ [MT8167_POWER_DOMAIN_MFG] = {
+ .sta_mask = PWR_STATUS_MFG,
+ .ctl_offs = SPM_MFG_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ },
+ [MT8167_POWER_DOMAIN_CONN] = {
+ .sta_mask = PWR_STATUS_CONN,
+ .ctl_offs = SPM_CONN_PWR_CON,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = 0,
+ .caps = MTK_SCPD_ACTIVE_WAKEUP,
+ .bp_infracfg = {
+ BUS_PROT_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_CONN_EMI |
+ MT8167_TOP_AXI_PROT_EN_CONN_MCU |
+ MT8167_TOP_AXI_PROT_EN_MCU_CONN),
+ },
+ },
+};
+
+static const struct scpsys_soc_data mt8167_scpsys_data = {
+ .domains = scpsys_domain_data_mt8167,
+ .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8167),
+ .pwr_sta_offs = SPM_PWR_STATUS,
+ .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
+};
+
+#endif /* __SOC_MEDIATEK_MT8167_PM_DOMAINS_H */
+
diff --git a/drivers/soc/mediatek/mtk-pm-domains.c
b/drivers/soc/mediatek/mtk-pm-domains.c
index 293efa27b6ce..34c704865f01 100644
--- a/drivers/soc/mediatek/mtk-pm-domains.c
+++ b/drivers/soc/mediatek/mtk-pm-domains.c
@@ -15,6 +15,7 @@
#include
#include
+#include "mt8167-pm-domains.h"
#include "mt8173-pm-domains.h"
#include "mt8183-pm-domains.h"
#include "mt8192-pm-domains.h"
@@ -515,6 +516,10 @@ static void scpsys_domain_cleanup(struct scpsys *scpsys)
}
static const struct of_device_id scpsys_of_match[] = {
+ {
+ .compatible = "mediatek,mt8167-power-controller",
+ .data = _scpsys_data,
+ },
{
.compatible = "mediatek,mt8173-power-controller",
.data = _scpsys_data,
diff --git
[PATCH v2 1/2] dt-bindings: power: Add MT8167 power domains
Add power domains dt-bindings for MT8167. Signed-off-by: Fabien Parent --- This patch depends on the SCPSYS PM domains driver [0]. v2: * Implement on top of new SCPSYS PM domains driver [0] [0] https://patchwork.kernel.org/project/linux-mediatek/list/?series=370737 .../power/mediatek,power-controller.yaml | 2 ++ include/dt-bindings/power/mt8167-power.h | 18 ++ 2 files changed, 20 insertions(+) create mode 100644 include/dt-bindings/power/mt8167-power.h diff --git a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml index 0318ffb1133c..73e5452c3a5d 100644 --- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml +++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml @@ -23,6 +23,7 @@ properties: compatible: enum: + - mediatek,mt8167-power-controller - mediatek,mt8173-power-controller - mediatek,mt8183-power-controller - mediatek,mt8192-power-controller @@ -59,6 +60,7 @@ patternProperties: reg: description: | Power domain index. Valid values are defined in: + "include/dt-bindings/power/mt8167-power.h" - for MT8167 type power domain. "include/dt-bindings/power/mt8173-power.h" - for MT8173 type power domain. "include/dt-bindings/power/mt8183-power.h" - for MT8183 type power domain. "include/dt-bindings/power/mt8192-power.h" - for MT8192 type power domain. diff --git a/include/dt-bindings/power/mt8167-power.h b/include/dt-bindings/power/mt8167-power.h new file mode 100644 index ..7e3babfc2eef --- /dev/null +++ b/include/dt-bindings/power/mt8167-power.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (c) 2020 MediaTek Inc. + */ + +#ifndef _DT_BINDINGS_POWER_MT8167_POWER_H +#define _DT_BINDINGS_POWER_MT8167_POWER_H + +#define MT8167_POWER_DOMAIN_MM 0 +#define MT8167_POWER_DOMAIN_DISP 0 +#define MT8167_POWER_DOMAIN_VDEC 1 +#define MT8167_POWER_DOMAIN_ISP2 +#define MT8167_POWER_DOMAIN_CONN 3 +#define MT8167_POWER_DOMAIN_MFG_ASYNC 4 +#define MT8167_POWER_DOMAIN_MFG_2D 5 +#define MT8167_POWER_DOMAIN_MFG6 + +#endif /* _DT_BINDINGS_POWER_MT8167_POWER_H */ -- 2.28.0
Re: [PATCH v4 2/4] dts: arm64: mt8183: Add Mediatek MDP3 nodes
Hi Daoyuan,
> Depend on:
>[1] https://lore.kernel.org/patchwork/patch/1164746/
>[2] https://patchwork.kernel.org/patch/11703299/
>[3] https://patchwork.kernel.org/patch/11283773/
Can you provide an updated list of dependencies because it seems this
patch depends on more than the patch aboves. I applied the related
patch series above but there is still missing node
ERROR (phandle_references): /soc/mdp-rdma0@14001000: Reference to
non-existent node or label "scp"
ERROR (phandle_references): /soc/mdp-rdma0@14001000: Reference to
non-existent node or label "mutex"
It would be even better if you could provide a branch with all the
dependencies included.
> mmsys: syscon@1400 {
> compatible = "mediatek,mt8183-mmsys", "syscon";
> + mdp-comps = "mediatek,mt8183-mdp-dl",
> + "mediatek,mt8183-mdp-dl";
> + mdp-comp-ids = <0 1>;
> reg = <0 0x1400 0 0x1000>;
> + mediatek,gce-client-reg = < SUBSYS_1400 0
> 0x1000>;
> #clock-cells = <1>;
> + clocks = < CLK_MM_MDP_DL_TXCK>,
> +< CLK_MM_MDP_DL_RX>,
> +< CLK_MM_IPU_DL_TXCK>,
> +< CLK_MM_IPU_DL_RX>;
> + };
The kernel is not booting anymore when the 4 clocks above are added,
if I remove them I can boot again. See the following log:
[0.401314] Unable to handle kernel paging request at virtual
address fffe
[0.402320] Mem abort info:
[0.402674] ESR = 0x9604
[0.403062] EC = 0x25: DABT (current EL), IL = 32 bits
[0.403741] SET = 0, FnV = 0
[0.404128] EA = 0, S1PTW = 0
[0.404526] Data abort info:
[0.404890] ISV = 0, ISS = 0x0004
[0.405374] CM = 0, WnR = 0
[0.405751] swapper pgtable: 4k pages, 48-bit VAs, pgdp=415ee000
[0.406595] [fffe] pgd=, p4d=
[0.407457] Internal error: Oops: 9604 [#1] PREEMPT SMP
[0.408160] Modules linked in:
[0.408551] CPU: 4 PID: 51 Comm: kworker/4:1 Not tainted
5.9.0-mtk-00010-g121ba830623e-dirty #2
[0.409646] Hardware name: MediaTek MT8183 evaluation board (DT)
[0.410416] Workqueue: events deferred_probe_work_func
[0.411067] pstate: 2005 (nzCv daif -PAN -UAO BTYPE=--)
[0.411772] pc : clk_prepare+0x18/0x44
[0.412252] lr : scpsys_power_on+0x1e8/0x470
[0.412791] sp : 800011fa3a20
[0.413209] x29: 800011fa3a20 x28:
[0.413881] x27: x26:
[0.414551] x25: 7a23ade0 x24: 7a223b80
[0.415222] x23: 800011f5d30c x22: 7a23a888
[0.415892] x21: fffe x20:
[0.416563] x19: x18: 0020
[0.417233] x17: 0020 x16: 52d9c4c7
[0.417904] x15: 0059 x14: 7a23a640
[0.418575] x13: 7a23a5c0 x12:
[0.419245] x11: 8000108331c0 x10: 800010833030
[0.419916] x9 : x8 : 7a751c00
[0.420587] x7 : 800011fa3a70 x6 : 130f968d
[0.421257] x5 : 8000110043f0 x4 : 0184
[0.421927] x3 : x2 : 0008
[0.422598] x1 : 000d x0 : fffe
[0.423268] Call trace:
[0.423581] clk_prepare+0x18/0x44
[0.424014] scpsys_power_on+0x1e8/0x470
[0.424511] scpsys_probe+0x3f4/0x66c
[0.424975] platform_drv_probe+0x54/0xb0
[0.425483] really_probe+0xe4/0x490
[0.425937] driver_probe_device+0x58/0xc0
[0.426456] __device_attach_driver+0xa8/0x10c
[0.427019] bus_for_each_drv+0x78/0xcc
[0.427504] __device_attach+0xdc/0x180
[0.427990] device_initial_probe+0x14/0x20
[0.428521] bus_probe_device+0x9c/0xa4
[0.429007] deferred_probe_work_func+0x74/0xb0
[0.429582] process_one_work+0x1cc/0x350
[0.430090] worker_thread+0x2c0/0x470
[0.430565] kthread+0x154/0x160
[0.430976] ret_from_fork+0x10/0x30
[0.431431] Code: 910003fd f9000bf3 52800013 b4e0 (f9400013)
[0.432200] ---[ end trace d3ecf925b254a559 ]---
[PATCH v3 3/3] iommu/mediatek: add support for MT8167
Add support for the IOMMU on MT8167
Signed-off-by: Fabien Parent
---
V3:
* use LEGACY_IVRP_PADDR flag instead of using a platform data member
V2:
* removed if based on m4u_plat, and using instead the new
has_legacy_ivrp_paddr member that was introduced in patch 2.
---
drivers/iommu/mtk_iommu.c | 8
drivers/iommu/mtk_iommu.h | 1 +
2 files changed, 9 insertions(+)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index b1f85a7e9346..6079f6a23c74 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -817,6 +817,13 @@ static const struct mtk_iommu_plat_data mt6779_data = {
.larbid_remap = {{0}, {1}, {2}, {3}, {5}, {7, 8}, {10}, {9}},
};
+static const struct mtk_iommu_plat_data mt8167_data = {
+ .m4u_plat = M4U_MT8167,
+ .flags= HAS_4GB_MODE | RESET_AXI | HAS_LEGACY_IVRP_PADDR,
+ .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
+ .larbid_remap = {{0}, {1}, {2}}, /* Linear mapping. */
+};
+
static const struct mtk_iommu_plat_data mt8173_data = {
.m4u_plat = M4U_MT8173,
.flags= HAS_4GB_MODE | HAS_BCLK | RESET_AXI |
@@ -835,6 +842,7 @@ static const struct mtk_iommu_plat_data mt8183_data = {
static const struct of_device_id mtk_iommu_of_ids[] = {
{ .compatible = "mediatek,mt2712-m4u", .data = _data},
{ .compatible = "mediatek,mt6779-m4u", .data = _data},
+ { .compatible = "mediatek,mt8167-m4u", .data = _data},
{ .compatible = "mediatek,mt8173-m4u", .data = _data},
{ .compatible = "mediatek,mt8183-m4u", .data = _data},
{}
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index 122925dbe547..df32b3e3408b 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -39,6 +39,7 @@ enum mtk_iommu_plat {
M4U_MT2701,
M4U_MT2712,
M4U_MT6779,
+ M4U_MT8167,
M4U_MT8173,
M4U_MT8183,
};
--
2.28.0
[PATCH v3 1/3] dt-bindings: iommu: Add binding for MediaTek MT8167 IOMMU
This commit adds IOMMU binding documentation and larb port definitions for the MT8167 SoC. Signed-off-by: Fabien Parent Acked-by: Rob Herring --- V3: Added mt8167-larb-port.h file for iommu port definitions V2: no change --- .../bindings/iommu/mediatek,iommu.txt | 1 + include/dt-bindings/memory/mt8167-larb-port.h | 49 +++ 2 files changed, 50 insertions(+) create mode 100644 include/dt-bindings/memory/mt8167-larb-port.h diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt index c1ccd8582eb2..f7a348f48e0d 100644 --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt @@ -61,6 +61,7 @@ Required properties: "mediatek,mt6779-m4u" for mt6779 which uses generation two m4u HW. "mediatek,mt7623-m4u", "mediatek,mt2701-m4u" for mt7623 which uses generation one m4u HW. + "mediatek,mt8167-m4u" for mt8167 which uses generation two m4u HW. "mediatek,mt8173-m4u" for mt8173 which uses generation two m4u HW. "mediatek,mt8183-m4u" for mt8183 which uses generation two m4u HW. - reg : m4u register base and size. diff --git a/include/dt-bindings/memory/mt8167-larb-port.h b/include/dt-bindings/memory/mt8167-larb-port.h new file mode 100644 index ..4dd44d1037a7 --- /dev/null +++ b/include/dt-bindings/memory/mt8167-larb-port.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 BayLibre, SAS + * Author: Fabien Parent + */ +#ifndef __DTS_IOMMU_PORT_MT8167_H +#define __DTS_IOMMU_PORT_MT8167_H + +#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port)) + +#define M4U_LARB0_ID 0 +#define M4U_LARB1_ID 1 +#define M4U_LARB2_ID 2 + +/* larb0 */ +#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0) +#define M4U_PORT_DISP_RDMA0MTK_M4U_ID(M4U_LARB0_ID, 1) +#define M4U_PORT_DISP_WDMA0MTK_M4U_ID(M4U_LARB0_ID, 2) +#define M4U_PORT_DISP_RDMA1MTK_M4U_ID(M4U_LARB0_ID, 3) +#define M4U_PORT_MDP_RDMA MTK_M4U_ID(M4U_LARB0_ID, 4) +#define M4U_PORT_MDP_WDMA MTK_M4U_ID(M4U_LARB0_ID, 5) +#define M4U_PORT_MDP_WROT MTK_M4U_ID(M4U_LARB0_ID, 6) +#define M4U_PORT_DISP_FAKE MTK_M4U_ID(M4U_LARB0_ID, 7) + +/* IMG larb1*/ +#define M4U_PORT_CAM_IMGO MTK_M4U_ID(M4U_LARB1_ID, 0) +#define M4U_PORT_CAM_IMG2O MTK_M4U_ID(M4U_LARB1_ID, 1) +#define M4U_PORT_CAM_LSCI MTK_M4U_ID(M4U_LARB1_ID, 2) +#define M4U_PORT_CAM_ESFKO MTK_M4U_ID(M4U_LARB1_ID, 3) +#define M4U_PORT_CAM_AAO MTK_M4U_ID(M4U_LARB1_ID, 4) +#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB1_ID, 5) +#define M4U_PORT_VENC_BSDMAMTK_M4U_ID(M4U_LARB1_ID, 6) +#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB1_ID, 7) +#define M4U_PORT_CAM_IMGI MTK_M4U_ID(M4U_LARB1_ID, 8) +#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB1_ID, 9) +#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB1_ID, 10) +#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB1_ID, 11) +#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB1_ID, 12) + +/* VDEC larb2*/ +#define M4U_PORT_HW_VDEC_MC_EXTMTK_M4U_ID(M4U_LARB2_ID, 0) +#define M4U_PORT_HW_VDEC_PP_EXTMTK_M4U_ID(M4U_LARB2_ID, 1) +#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB2_ID, 2) +#define M4U_PORT_HW_VDEC_AVC_MV_EXTMTK_M4U_ID(M4U_LARB2_ID, 3) +#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB2_ID, 4) +#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB2_ID, 5) +#define M4U_PORT_HW_VDEC_PPWRAP_EXTMTK_M4U_ID(M4U_LARB2_ID, 6) + +#endif -- 2.28.0
[PATCH v3 2/3] iommu/mediatek: add flag for legacy ivrp paddr
Add a new flag in order to select which IVRP_PADDR format is used
by an SoC.
Signed-off-by: Fabien Parent
---
v3: set LEGACY_IVRP_PADDR as a flag instead of platform data
v2: new patch
---
drivers/iommu/mtk_iommu.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 785b228d39a6..b1f85a7e9346 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -116,6 +116,7 @@
#define OUT_ORDER_WR_ENBIT(4)
#define HAS_SUB_COMM BIT(5)
#define WR_THROT_ENBIT(6)
+#define HAS_LEGACY_IVRP_PADDR BIT(7)
#define MTK_IOMMU_HAS_FLAG(pdata, _x) \
pdata)->flags) & (_x)) == (_x))
@@ -582,7 +583,7 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data
*data)
F_INT_PRETETCH_TRANSATION_FIFO_FAULT;
writel_relaxed(regval, data->base + REG_MMU_INT_MAIN_CONTROL);
- if (data->plat_data->m4u_plat == M4U_MT8173)
+ if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_LEGACY_IVRP_PADDR))
regval = (data->protect_base >> 1) | (data->enable_4GB << 31);
else
regval = lower_32_bits(data->protect_base) |
@@ -818,7 +819,8 @@ static const struct mtk_iommu_plat_data mt6779_data = {
static const struct mtk_iommu_plat_data mt8173_data = {
.m4u_plat = M4U_MT8173,
- .flags= HAS_4GB_MODE | HAS_BCLK | RESET_AXI,
+ .flags= HAS_4GB_MODE | HAS_BCLK | RESET_AXI |
+ HAS_LEGACY_IVRP_PADDR,
.inv_sel_reg = REG_MMU_INV_SEL_GEN1,
.larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */
};
--
2.28.0
Re: [PATCH v3 3/3] iommu/mediatek: add support for MT8167
On Sun, Sep 6, 2020 at 5:19 PM Fabien Parent wrote:
>
> Add support for the IOMMU on MT8167
>
> Signed-off-by: Fabien Parent
> ---
>
> V3:
> * use LEGACY_IVRP_PADDR flag instead of using a platform data member
Forgot to mention a change here: .larbid_remap has been fixed to only
contain the number of larb present on MT8167
> V2:
> * removed if based on m4u_plat, and using instead the new
> has_legacy_ivrp_paddr member that was introduced in patch 2.
>
> ---
> drivers/iommu/mtk_iommu.c | 8
> drivers/iommu/mtk_iommu.h | 1 +
> 2 files changed, 9 insertions(+)
>
> diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> index b1f85a7e9346..6079f6a23c74 100644
> --- a/drivers/iommu/mtk_iommu.c
> +++ b/drivers/iommu/mtk_iommu.c
> @@ -817,6 +817,13 @@ static const struct mtk_iommu_plat_data mt6779_data = {
> .larbid_remap = {{0}, {1}, {2}, {3}, {5}, {7, 8}, {10}, {9}},
> };
>
> +static const struct mtk_iommu_plat_data mt8167_data = {
> + .m4u_plat = M4U_MT8167,
> + .flags= HAS_4GB_MODE | RESET_AXI | HAS_LEGACY_IVRP_PADDR,
> + .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
> + .larbid_remap = {{0}, {1}, {2}}, /* Linear mapping. */
> +};
> +
> static const struct mtk_iommu_plat_data mt8173_data = {
> .m4u_plat = M4U_MT8173,
> .flags= HAS_4GB_MODE | HAS_BCLK | RESET_AXI |
> @@ -835,6 +842,7 @@ static const struct mtk_iommu_plat_data mt8183_data = {
> static const struct of_device_id mtk_iommu_of_ids[] = {
> { .compatible = "mediatek,mt2712-m4u", .data = _data},
> { .compatible = "mediatek,mt6779-m4u", .data = _data},
> + { .compatible = "mediatek,mt8167-m4u", .data = _data},
> { .compatible = "mediatek,mt8173-m4u", .data = _data},
> { .compatible = "mediatek,mt8183-m4u", .data = _data},
> {}
> diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
> index 122925dbe547..df32b3e3408b 100644
> --- a/drivers/iommu/mtk_iommu.h
> +++ b/drivers/iommu/mtk_iommu.h
> @@ -39,6 +39,7 @@ enum mtk_iommu_plat {
> M4U_MT2701,
> M4U_MT2712,
> M4U_MT6779,
> + M4U_MT8167,
> M4U_MT8173,
> M4U_MT8183,
> };
> --
> 2.28.0
>
[PATCH 2/2] soc: mediatek: add SCPSYS power dmain for MT8167 SoC
Add SCPSYS power domain support for MT8167 SoC.
Signed-off-by: Fabien Parent
---
drivers/soc/mediatek/mtk-scpsys.c | 99 +++
include/linux/soc/mediatek/infracfg.h | 8 +++
2 files changed, 107 insertions(+)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c
b/drivers/soc/mediatek/mtk-scpsys.c
index f669d3754627..ce897720ef17 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -18,6 +18,7 @@
#include
#include
#include
+#include
#include
#define MTK_POLL_DELAY_US 10
@@ -89,6 +90,7 @@ enum clk_id {
CLK_HIFSEL,
CLK_JPGDEC,
CLK_AUDIO,
+ CLK_AXI_MFG,
CLK_MAX,
};
@@ -103,6 +105,7 @@ static const char * const clk_names[] = {
"hif_sel",
"jpgdec",
"audio",
+ "axi_mfg",
NULL,
};
@@ -911,6 +914,87 @@ static const struct scp_domain_data
scp_domain_data_mt7623a[] = {
},
};
+/*
+ * MT8167 power domain support
+ */
+#define PWR_STATUS_MFG_2D_MT8167 BIT(24)
+#define PWR_STATUS_MFG_ASYNC_MT8167BIT(25)
+
+static const struct scp_domain_data scp_domain_data_mt8167[] = {
+ [MT8167_POWER_DOMAIN_DISP] = {
+ .name = "disp",
+ .sta_mask = PWR_STATUS_DISP,
+ .ctl_offs = SPM_DIS_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .bus_prot_mask = MT8167_TOP_AXI_PROT_EN_MM_EMI |
+MT8167_TOP_AXI_PROT_EN_MCU_MM,
+ .clk_id = {CLK_MM},
+ .caps = MTK_SCPD_ACTIVE_WAKEUP,
+ },
+ [MT8167_POWER_DOMAIN_VDEC] = {
+ .name = "vdec",
+ .sta_mask = PWR_STATUS_VDEC,
+ .ctl_offs = SPM_VDE_PWR_CON,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .clk_id = {CLK_MM, CLK_VDEC},
+ .caps = MTK_SCPD_ACTIVE_WAKEUP,
+ },
+ [MT8167_POWER_DOMAIN_ISP] = {
+ .name = "isp",
+ .sta_mask = PWR_STATUS_ISP,
+ .ctl_offs = SPM_ISP_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(13, 12),
+ .clk_id = {CLK_MM},
+ .caps = MTK_SCPD_ACTIVE_WAKEUP,
+ },
+ [MT8167_POWER_DOMAIN_MFG_ASYNC] = {
+ .name = "mfg_async",
+ .sta_mask = PWR_STATUS_MFG_ASYNC_MT8167,
+ .ctl_offs = SPM_MFG_ASYNC_PWR_CON,
+ .sram_pdn_bits = 0,
+ .sram_pdn_ack_bits = 0,
+ .bus_prot_mask = MT8167_TOP_AXI_PROT_EN_MCU_MFG |
+MT8167_TOP_AXI_PROT_EN_MFG_EMI,
+ .clk_id = {CLK_MFG, CLK_AXI_MFG},
+ },
+ [MT8167_POWER_DOMAIN_MFG_2D] = {
+ .name = "mfg_2d",
+ .sta_mask = PWR_STATUS_MFG_2D_MT8167,
+ .ctl_offs = SPM_MFG_2D_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ .clk_id = {CLK_NONE},
+ },
+ [MT8167_POWER_DOMAIN_MFG] = {
+ .name = "mfg",
+ .sta_mask = PWR_STATUS_MFG,
+ .ctl_offs = SPM_MFG_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ .clk_id = {CLK_NONE},
+ },
+ [MT8167_POWER_DOMAIN_CONN] = {
+ .name = "conn",
+ .sta_mask = PWR_STATUS_CONN,
+ .ctl_offs = SPM_CONN_PWR_CON,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = 0,
+ .bus_prot_mask = MT8167_TOP_AXI_PROT_EN_CONN_EMI |
+MT8167_TOP_AXI_PROT_EN_CONN_MCU |
+MT8167_TOP_AXI_PROT_EN_MCU_CONN,
+ .clk_id = {CLK_NONE},
+ .caps = MTK_SCPD_ACTIVE_WAKEUP,
+ },
+};
+
+static const struct scp_subdomain scp_subdomain_mt8167[] = {
+ {MT8167_POWER_DOMAIN_MFG_ASYNC, MT8167_POWER_DOMAIN_MFG_2D},
+ {MT8167_POWER_DOMAIN_MFG_2D, MT8167_POWER_DOMAIN_MFG},
+};
+
/*
* MT8173 power domain support
*/
@@ -1064,6 +1148,18 @@ static const struct scp_soc_data mt7623a_data = {
.bus_prot_reg_update = true,
};
+static const struct scp_soc_data mt8167_data = {
+ .domains = scp_domain_data_mt8167,
+ .num_domains = ARRAY_SIZE(scp_domain_data_mt8167),
+ .subdomains = scp_subdomain_mt8167,
+ .num_subdomains = ARRAY_SIZE(scp_subdomain_mt8167),
+ .regs = {
+ .pwr_sta_offs = SPM_PWR_STATUS,
+ .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
+ },
+ .bus_prot_reg_update = true,
+};
+
static const struct scp_soc_data mt8173_data = {
.domains = scp_domain_dat
[PATCH 1/2] dt-bindings: mediatek: add MT8167 power dt-bindings
Add the SCPSYS binding documentation for MediaTek MT8167 SoCs. Signed-off-by: Fabien Parent --- .../devicetree/bindings/soc/mediatek/scpsys.txt| 3 +++ include/dt-bindings/power/mt8167-power.h | 14 ++ 2 files changed, 17 insertions(+) create mode 100644 include/dt-bindings/power/mt8167-power.h diff --git a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt index 2bc367793aec..08cb8438a35d 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt +++ b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt @@ -10,6 +10,7 @@ domain control. The driver implements the Generic PM domain bindings described in power/power-domain.yaml. It provides the power domains defined in - include/dt-bindings/power/mt8173-power.h +- include/dt-bindings/power/mt8167-power.h - include/dt-bindings/power/mt6797-power.h - include/dt-bindings/power/mt6765-power.h - include/dt-bindings/power/mt2701-power.h @@ -26,6 +27,7 @@ Required properties: - "mediatek,mt7623-scpsys", "mediatek,mt2701-scpsys": For MT7623 SoC - "mediatek,mt7623a-scpsys": For MT7623A SoC - "mediatek,mt7629-scpsys", "mediatek,mt7622-scpsys": For MT7629 SoC + - "mediatek,mt8167-scpsys" - "mediatek,mt8173-scpsys" - #power-domain-cells: Must be 1 - reg: Address range of the SCPSYS unit @@ -42,6 +44,7 @@ Required properties: Required clocks for MT6797: "mm", "mfg", "vdec" Required clocks for MT7622 or MT7629: "hif_sel" Required clocks for MT7623A: "ethif" + Required clocks for MT8167: "mm", "mfg", "vdec", "axi_mfg" Required clocks for MT8173: "mm", "mfg", "venc", "venc_lt" Optional properties: diff --git a/include/dt-bindings/power/mt8167-power.h b/include/dt-bindings/power/mt8167-power.h new file mode 100644 index ..8e7bcb4834dc --- /dev/null +++ b/include/dt-bindings/power/mt8167-power.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _DT_BINDINGS_POWER_MT8167_POWER_H +#define _DT_BINDINGS_POWER_MT8167_POWER_H + +#define MT8167_POWER_DOMAIN_MM 0 +#define MT8167_POWER_DOMAIN_DISP 0 +#define MT8167_POWER_DOMAIN_VDEC 1 +#define MT8167_POWER_DOMAIN_ISP2 +#define MT8167_POWER_DOMAIN_CONN 3 +#define MT8167_POWER_DOMAIN_MFG_ASYNC 4 +#define MT8167_POWER_DOMAIN_MFG_2D 5 +#define MT8167_POWER_DOMAIN_MFG6 + +#endif /* _DT_BINDINGS_POWER_MT8167_POWER_H */ -- 2.28.0
[PATCH 1/2] dt-bindings: mediatek: Add binding for MT8167 SMI
Add device tree bindings documentation for MT8167 SMI. Signed-off-by: Fabien Parent --- .../bindings/memory-controllers/mediatek,smi-common.txt| 3 ++- .../bindings/memory-controllers/mediatek,smi-larb.txt | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt index b64573680b42..dbafffe3f41e 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt @@ -5,7 +5,7 @@ The hardware block diagram please check bindings/iommu/mediatek,iommu.txt Mediatek SMI have two generations of HW architecture, here is the list which generation the SoCs use: generation 1: mt2701 and mt7623. -generation 2: mt2712, mt6779, mt8173 and mt8183. +generation 2: mt2712, mt6779, mt8167, mt8173 and mt8183. There's slight differences between the two SMI, for generation 2, the register which control the iommu port is at each larb's register base. But @@ -20,6 +20,7 @@ Required properties: "mediatek,mt2712-smi-common" "mediatek,mt6779-smi-common" "mediatek,mt7623-smi-common", "mediatek,mt2701-smi-common" + "mediatek,mt8167-smi-common" "mediatek,mt8173-smi-common" "mediatek,mt8183-smi-common" - reg : the register and size of the SMI block. diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt index 8f19dfe7d80e..0c5de12b5496 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt @@ -8,6 +8,7 @@ Required properties: "mediatek,mt2712-smi-larb" "mediatek,mt6779-smi-larb" "mediatek,mt7623-smi-larb", "mediatek,mt2701-smi-larb" + "mediatek,mt8167-smi-larb" "mediatek,mt8173-smi-larb" "mediatek,mt8183-smi-larb" - reg : the register and size of this local arbiter. @@ -22,7 +23,7 @@ Required properties: - "gals": the clock for GALS(Global Async Local Sync). Here is the list which has this GALS: mt8183. -Required property for mt2701, mt2712, mt6779 and mt7623: +Required property for mt2701, mt2712, mt6779, mt7623 and mt8167: - mediatek,larb-id :the hardware id of this larb. Example: -- 2.28.0
[PATCH 2/2] memory: mtk-smi: add support for MT8167
Add support for the SMI IP on MT8167
Signed-off-by: Fabien Parent
---
drivers/memory/mtk-smi.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
index c21262502581..691e4c344cf8 100644
--- a/drivers/memory/mtk-smi.c
+++ b/drivers/memory/mtk-smi.c
@@ -19,6 +19,9 @@
/* mt8173 */
#define SMI_LARB_MMU_EN0xf00
+/* mt8167 */
+#define MT8167_SMI_LARB_MMU_EN 0xfc0
+
/* mt2701 */
#define REG_SMI_SECUR_CON_BASE 0x5c0
@@ -179,6 +182,13 @@ static void mtk_smi_larb_config_port_mt8173(struct device
*dev)
writel(*larb->mmu, larb->base + SMI_LARB_MMU_EN);
}
+static void mtk_smi_larb_config_port_mt8167(struct device *dev)
+{
+ struct mtk_smi_larb *larb = dev_get_drvdata(dev);
+
+ writel(*larb->mmu, larb->base + MT8167_SMI_LARB_MMU_EN);
+}
+
static void mtk_smi_larb_config_port_gen1(struct device *dev)
{
struct mtk_smi_larb *larb = dev_get_drvdata(dev);
@@ -226,6 +236,11 @@ static const struct mtk_smi_larb_gen mtk_smi_larb_mt8173 =
{
.config_port = mtk_smi_larb_config_port_mt8173,
};
+static const struct mtk_smi_larb_gen mtk_smi_larb_mt8167 = {
+ /* mt8167 do not need the port in larb */
+ .config_port = mtk_smi_larb_config_port_mt8167,
+};
+
static const struct mtk_smi_larb_gen mtk_smi_larb_mt2701 = {
.port_in_larb = {
LARB0_PORT_OFFSET, LARB1_PORT_OFFSET,
@@ -254,6 +269,10 @@ static const struct mtk_smi_larb_gen mtk_smi_larb_mt8183 =
{
};
static const struct of_device_id mtk_smi_larb_of_ids[] = {
+ {
+ .compatible = "mediatek,mt8167-smi-larb",
+ .data = _smi_larb_mt8167
+ },
{
.compatible = "mediatek,mt8173-smi-larb",
.data = _smi_larb_mt8173
@@ -418,6 +437,10 @@ static const struct of_device_id mtk_smi_common_of_ids[] =
{
.compatible = "mediatek,mt8173-smi-common",
.data = _smi_common_gen2,
},
+ {
+ .compatible = "mediatek,mt8167-smi-common",
+ .data = _smi_common_gen2,
+ },
{
.compatible = "mediatek,mt2701-smi-common",
.data = _smi_common_gen1,
--
2.28.0
Re: [PATCH v3 3/3] iommu/mediatek: add support for MT8167
> > +static const struct mtk_iommu_plat_data mt8167_data = {
> > + .m4u_plat = M4U_MT8167,
> > + .flags= HAS_4GB_MODE | RESET_AXI | HAS_LEGACY_IVRP_PADDR,
>
> The 4GB mode flow was improved at[1] which has just been applied.
>
> If you add 4gb_mode flag but don't have "mt8167-infracfg", the probe may
> be failed.
Looking back at the datasheet I don't think HAS_4GB_MODE should have
been enabled for MT8167 anyway. I just removed it and retested the
patch. I will fix it in v4. Thanks
> [1]
> https://lore.kernel.org/linux-iommu/20200904112117.gc16...@8bytes.org/T/#m613e9926735d07ad004fddbbcedaa50b5afacca1
[PATCH v4 3/3] iommu/mediatek: add support for MT8167
Add support for the IOMMU on MT8167
Signed-off-by: Fabien Parent
---
V4;
* Removed HAS_4GB_MODE flag since this SoC does not seem to support it
V3:
* use LEGACY_IVRP_PADDR flag instead of using a platform data member
V2:
* removed if based on m4u_plat, and using instead the new
has_legacy_ivrp_paddr member that was introduced in patch 2.
---
drivers/iommu/mtk_iommu.c | 8
drivers/iommu/mtk_iommu.h | 1 +
2 files changed, 9 insertions(+)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index b1f85a7e9346..4ff071eb5279 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -817,6 +817,13 @@ static const struct mtk_iommu_plat_data mt6779_data = {
.larbid_remap = {{0}, {1}, {2}, {3}, {5}, {7, 8}, {10}, {9}},
};
+static const struct mtk_iommu_plat_data mt8167_data = {
+ .m4u_plat = M4U_MT8167,
+ .flags= RESET_AXI | HAS_LEGACY_IVRP_PADDR,
+ .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
+ .larbid_remap = {{0}, {1}, {2}}, /* Linear mapping. */
+};
+
static const struct mtk_iommu_plat_data mt8173_data = {
.m4u_plat = M4U_MT8173,
.flags= HAS_4GB_MODE | HAS_BCLK | RESET_AXI |
@@ -835,6 +842,7 @@ static const struct mtk_iommu_plat_data mt8183_data = {
static const struct of_device_id mtk_iommu_of_ids[] = {
{ .compatible = "mediatek,mt2712-m4u", .data = _data},
{ .compatible = "mediatek,mt6779-m4u", .data = _data},
+ { .compatible = "mediatek,mt8167-m4u", .data = _data},
{ .compatible = "mediatek,mt8173-m4u", .data = _data},
{ .compatible = "mediatek,mt8183-m4u", .data = _data},
{}
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index 122925dbe547..df32b3e3408b 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -39,6 +39,7 @@ enum mtk_iommu_plat {
M4U_MT2701,
M4U_MT2712,
M4U_MT6779,
+ M4U_MT8167,
M4U_MT8173,
M4U_MT8183,
};
--
2.28.0
[PATCH v4 2/3] iommu/mediatek: add flag for legacy ivrp paddr
Add a new flag in order to select which IVRP_PADDR format is used
by an SoC.
Signed-off-by: Fabien Parent
Reviewed-by: Yong Wu
---
v4: no change
v3: set LEGACY_IVRP_PADDR as a flag instead of platform data
v2: new patch
---
drivers/iommu/mtk_iommu.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 785b228d39a6..b1f85a7e9346 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -116,6 +116,7 @@
#define OUT_ORDER_WR_ENBIT(4)
#define HAS_SUB_COMM BIT(5)
#define WR_THROT_ENBIT(6)
+#define HAS_LEGACY_IVRP_PADDR BIT(7)
#define MTK_IOMMU_HAS_FLAG(pdata, _x) \
pdata)->flags) & (_x)) == (_x))
@@ -582,7 +583,7 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data
*data)
F_INT_PRETETCH_TRANSATION_FIFO_FAULT;
writel_relaxed(regval, data->base + REG_MMU_INT_MAIN_CONTROL);
- if (data->plat_data->m4u_plat == M4U_MT8173)
+ if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_LEGACY_IVRP_PADDR))
regval = (data->protect_base >> 1) | (data->enable_4GB << 31);
else
regval = lower_32_bits(data->protect_base) |
@@ -818,7 +819,8 @@ static const struct mtk_iommu_plat_data mt6779_data = {
static const struct mtk_iommu_plat_data mt8173_data = {
.m4u_plat = M4U_MT8173,
- .flags= HAS_4GB_MODE | HAS_BCLK | RESET_AXI,
+ .flags= HAS_4GB_MODE | HAS_BCLK | RESET_AXI |
+ HAS_LEGACY_IVRP_PADDR,
.inv_sel_reg = REG_MMU_INV_SEL_GEN1,
.larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */
};
--
2.28.0
[PATCH v4 1/3] dt-bindings: iommu: Add binding for MediaTek MT8167 IOMMU
This commit adds IOMMU binding documentation and larb port definitions for the MT8167 SoC. Signed-off-by: Fabien Parent Acked-by: Rob Herring --- V4: * Added path to mt8167 larb header file * Added Honghui Zhang in copyright header V3: Added mt8167-larb-port.h file for iommu port definitions V2: no change --- .../bindings/iommu/mediatek,iommu.txt | 2 + include/dt-bindings/memory/mt8167-larb-port.h | 51 +++ 2 files changed, 53 insertions(+) create mode 100644 include/dt-bindings/memory/mt8167-larb-port.h diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt index c1ccd8582eb2..ac949f7fe3d4 100644 --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt @@ -61,6 +61,7 @@ Required properties: "mediatek,mt6779-m4u" for mt6779 which uses generation two m4u HW. "mediatek,mt7623-m4u", "mediatek,mt2701-m4u" for mt7623 which uses generation one m4u HW. + "mediatek,mt8167-m4u" for mt8167 which uses generation two m4u HW. "mediatek,mt8173-m4u" for mt8173 which uses generation two m4u HW. "mediatek,mt8183-m4u" for mt8183 which uses generation two m4u HW. - reg : m4u register base and size. @@ -80,6 +81,7 @@ Required properties: dt-binding/memory/mt2701-larb-port.h for mt2701, mt7623 dt-binding/memory/mt2712-larb-port.h for mt2712, dt-binding/memory/mt6779-larb-port.h for mt6779, + dt-binding/memory/mt8167-larb-port.h for mt8167, dt-binding/memory/mt8173-larb-port.h for mt8173, and dt-binding/memory/mt8183-larb-port.h for mt8183. diff --git a/include/dt-bindings/memory/mt8167-larb-port.h b/include/dt-bindings/memory/mt8167-larb-port.h new file mode 100644 index ..000fb299a408 --- /dev/null +++ b/include/dt-bindings/memory/mt8167-larb-port.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 MediaTek Inc. + * Copyright (c) 2020 BayLibre, SAS + * Author: Honghui Zhang + * Author: Fabien Parent + */ +#ifndef __DTS_IOMMU_PORT_MT8167_H +#define __DTS_IOMMU_PORT_MT8167_H + +#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port)) + +#define M4U_LARB0_ID 0 +#define M4U_LARB1_ID 1 +#define M4U_LARB2_ID 2 + +/* larb0 */ +#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0) +#define M4U_PORT_DISP_RDMA0MTK_M4U_ID(M4U_LARB0_ID, 1) +#define M4U_PORT_DISP_WDMA0MTK_M4U_ID(M4U_LARB0_ID, 2) +#define M4U_PORT_DISP_RDMA1MTK_M4U_ID(M4U_LARB0_ID, 3) +#define M4U_PORT_MDP_RDMA MTK_M4U_ID(M4U_LARB0_ID, 4) +#define M4U_PORT_MDP_WDMA MTK_M4U_ID(M4U_LARB0_ID, 5) +#define M4U_PORT_MDP_WROT MTK_M4U_ID(M4U_LARB0_ID, 6) +#define M4U_PORT_DISP_FAKE MTK_M4U_ID(M4U_LARB0_ID, 7) + +/* larb1*/ +#define M4U_PORT_CAM_IMGO MTK_M4U_ID(M4U_LARB1_ID, 0) +#define M4U_PORT_CAM_IMG2O MTK_M4U_ID(M4U_LARB1_ID, 1) +#define M4U_PORT_CAM_LSCI MTK_M4U_ID(M4U_LARB1_ID, 2) +#define M4U_PORT_CAM_ESFKO MTK_M4U_ID(M4U_LARB1_ID, 3) +#define M4U_PORT_CAM_AAO MTK_M4U_ID(M4U_LARB1_ID, 4) +#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB1_ID, 5) +#define M4U_PORT_VENC_BSDMAMTK_M4U_ID(M4U_LARB1_ID, 6) +#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB1_ID, 7) +#define M4U_PORT_CAM_IMGI MTK_M4U_ID(M4U_LARB1_ID, 8) +#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB1_ID, 9) +#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB1_ID, 10) +#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB1_ID, 11) +#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB1_ID, 12) + +/* larb2*/ +#define M4U_PORT_HW_VDEC_MC_EXTMTK_M4U_ID(M4U_LARB2_ID, 0) +#define M4U_PORT_HW_VDEC_PP_EXTMTK_M4U_ID(M4U_LARB2_ID, 1) +#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB2_ID, 2) +#define M4U_PORT_HW_VDEC_AVC_MV_EXTMTK_M4U_ID(M4U_LARB2_ID, 3) +#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB2_ID, 4) +#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB2_ID, 5) +#define M4U_PORT_HW_VDEC_PPWRAP_EXTMTK_M4U_ID(M4U_LARB2_ID, 6) + +#endif -- 2.28.0
[PATCH v5 2/3] dt-bindings: input: mtk-pmic-keys: add MT6392 binding definition
Add the binding documentation of the mtk-pmic-keys for the MT6392 PMICs. Signed-off-by: Fabien Parent Reviewed-by: Rob Herring --- v5: * rebased * Rename MT6397/MT6392/MT6323 into MT63XX to make it more readable when the list of support PMIC increase * Removed Reviewed-by from Rob Herring because of the new extra changes made to this patch * change the compatible for MT6392 to also contains MT6397 since MT6392 PMIC key driver is compatible with mt6397. v4: * Patch was previously sent separately but merge to this patch series since there is a hard dependency on the MFD patch. --- .../devicetree/bindings/input/mtk-pmic-keys.txt | 13 - 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/input/mtk-pmic-keys.txt b/Documentation/devicetree/bindings/input/mtk-pmic-keys.txt index 535d92885372..71c82687ab92 100644 --- a/Documentation/devicetree/bindings/input/mtk-pmic-keys.txt +++ b/Documentation/devicetree/bindings/input/mtk-pmic-keys.txt @@ -1,15 +1,18 @@ -MediaTek MT6397/MT6323 PMIC Keys Device Driver +MediaTek MT63xx PMIC Keys Device Driver -There are two key functions provided by MT6397/MT6323 PMIC, pwrkey +There are two key functions provided by MT63xx PMIC, pwrkey and homekey. The key functions are defined as the subnode of the function -node provided by MT6397/MT6323 PMIC that is being defined as one kind +node provided by MT63xx PMIC that is being defined as one kind of Muti-Function Device (MFD) -For MT6397/MT6323 MFD bindings see: +For MT63xx MFD bindings see: Documentation/devicetree/bindings/mfd/mt6397.txt Required properties: -- compatible: "mediatek,mt6397-keys" or "mediatek,mt6323-keys" +- compatible: Should be one of: + - "mediatek,mt6323-keys" for MT6323 PMIC + - "mediatek,mt6392-keys", "mediatek,mt6397-keys" for MT6392 PMIC + - "mediatek,mt6397-keys" for MT6397 PMIC - linux,keycodes: See Documentation/devicetree/bindings/input/input.yaml Optional Properties: -- 2.28.0
[PATCH v5 3/3] mfd: mt6397: Add support for MT6392 pmic
Update the MT6397 MFD driver to support the MT6392 PMIC.
Signed-off-by: Fabien Parent
---
V5:
* Rebased
* removed mt6392-regulator compatible. This will be send in another
series to make this series easier to merge.
V4:
* Use DEFINE_RES_* macro to define RTC ressources.
* Use PLATFORM_DEVID_NONE instead of -1 value when registering devices.
V3:
* No change
V2:
* Pass IRQ comain to fix invalid MFD devices IRQs.
* Remove resources and mfd cells for device we don't support.
* Rename IRQ names to follow what's done for MT6397.
---
drivers/mfd/mt6397-core.c| 40 +++
drivers/mfd/mt6397-irq.c | 9 +
include/linux/mfd/mt6392/core.h | 42 +++
include/linux/mfd/mt6392/registers.h | 487 +++
include/linux/mfd/mt6397/core.h | 1 +
5 files changed, 579 insertions(+)
create mode 100644 include/linux/mfd/mt6392/core.h
create mode 100644 include/linux/mfd/mt6392/registers.h
diff --git a/drivers/mfd/mt6397-core.c b/drivers/mfd/mt6397-core.c
index f6cd8a660602..6ba3585b1b36 100644
--- a/drivers/mfd/mt6397-core.c
+++ b/drivers/mfd/mt6397-core.c
@@ -13,9 +13,11 @@
#include
#include
#include
+#include
#include
#include
#include
+#include
#include
#define MT6323_RTC_BASE0x8000
@@ -27,6 +29,9 @@
#define MT6397_RTC_BASE0xe000
#define MT6397_RTC_SIZE0x3e
+#define MT6392_RTC_BASE0x8000
+#define MT6392_RTC_SIZE0x3e
+
#define MT6323_PWRC_BASE 0x8000
#define MT6323_PWRC_SIZE 0x40
@@ -40,6 +45,11 @@ static const struct resource mt6358_rtc_resources[] = {
DEFINE_RES_IRQ(MT6358_IRQ_RTC),
};
+static const struct resource mt6392_rtc_resources[] = {
+ DEFINE_RES_MEM(MT6392_RTC_BASE, MT6392_RTC_SIZE),
+ DEFINE_RES_IRQ(MT6392_IRQ_RTC),
+};
+
static const struct resource mt6397_rtc_resources[] = {
DEFINE_RES_MEM(MT6397_RTC_BASE, MT6397_RTC_SIZE),
DEFINE_RES_IRQ(MT6397_IRQ_RTC),
@@ -50,6 +60,11 @@ static const struct resource mt6323_keys_resources[] = {
DEFINE_RES_IRQ(MT6323_IRQ_STATUS_FCHRKEY),
};
+static const struct resource mt6392_keys_resources[] = {
+ DEFINE_RES_IRQ(MT6392_IRQ_PWRKEY),
+ DEFINE_RES_IRQ(MT6392_IRQ_FCHRKEY),
+};
+
static const struct resource mt6397_keys_resources[] = {
DEFINE_RES_IRQ(MT6397_IRQ_PWRKEY),
DEFINE_RES_IRQ(MT6397_IRQ_HOMEKEY),
@@ -99,6 +114,20 @@ static const struct mfd_cell mt6358_devs[] = {
},
};
+static const struct mfd_cell mt6392_devs[] = {
+ {
+ .name = "mt6397-rtc",
+ .num_resources = ARRAY_SIZE(mt6392_rtc_resources),
+ .resources = mt6392_rtc_resources,
+ .of_compatible = "mediatek,mt6392-rtc",
+ }, {
+ .name = "mtk-pmic-keys",
+ .num_resources = ARRAY_SIZE(mt6392_keys_resources),
+ .resources = mt6392_keys_resources,
+ .of_compatible = "mediatek,mt6392-keys"
+ },
+};
+
static const struct mfd_cell mt6397_devs[] = {
{
.name = "mt6397-rtc",
@@ -149,6 +178,14 @@ static const struct chip_data mt6358_core = {
.irq_init = mt6358_irq_init,
};
+static const struct chip_data mt6392_core = {
+ .cid_addr = MT6392_CID,
+ .cid_shift = 0,
+ .cells = mt6392_devs,
+ .cell_size = ARRAY_SIZE(mt6392_devs),
+ .irq_init = mt6397_irq_init,
+};
+
static const struct chip_data mt6397_core = {
.cid_addr = MT6397_CID,
.cid_shift = 0,
@@ -218,6 +255,9 @@ static const struct of_device_id mt6397_of_match[] = {
}, {
.compatible = "mediatek,mt6358",
.data = _core,
+ }, {
+ .compatible = "mediatek,mt6392",
+ .data = _core,
}, {
.compatible = "mediatek,mt6397",
.data = _core,
diff --git a/drivers/mfd/mt6397-irq.c b/drivers/mfd/mt6397-irq.c
index 2924919da991..9bf95e2ddf02 100644
--- a/drivers/mfd/mt6397-irq.c
+++ b/drivers/mfd/mt6397-irq.c
@@ -12,6 +12,8 @@
#include
#include
#include
+#include
+#include
#include
#include
@@ -181,6 +183,13 @@ int mt6397_irq_init(struct mt6397_chip *chip)
chip->int_status[1] = MT6397_INT_STATUS1;
break;
+ case MT6392_CHIP_ID:
+ chip->int_con[0] = MT6392_INT_CON0;
+ chip->int_con[1] = MT6392_INT_CON1;
+ chip->int_status[0] = MT6392_INT_STATUS0;
+ chip->int_status[1] = MT6392_INT_STATUS1;
+ break;
+
default:
dev_err(chip->dev, "unsupported chip: 0x%x\n", chip->chip_id);
return -ENODEV;
diff --git a/include/linux/mfd/mt6392/core.h b/include/linux/mfd/mt6392/c
[PATCH v5 1/3] dt-bindings: mfd: mt6397: Add bindings for MT6392 PMIC
Add the currently supported bindings for the MT6392 PMIC. Signed-off-by: Fabien Parent Reviewed-by: Rob Herring Acked-for-mfd-by: Lee Jones --- V5: * Rebased, removed regulator documentation because it will be send later on in another patch series V4: * No change V3: * No change V2: * New patch --- Documentation/devicetree/bindings/mfd/mt6397.txt | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mfd/mt6397.txt b/Documentation/devicetree/bindings/mfd/mt6397.txt index 2661775a3825..f051a951ba72 100644 --- a/Documentation/devicetree/bindings/mfd/mt6397.txt +++ b/Documentation/devicetree/bindings/mfd/mt6397.txt @@ -21,6 +21,7 @@ Required properties: compatible: "mediatek,mt6323" for PMIC MT6323 "mediatek,mt6358" for PMIC MT6358 + "mediatek,mt6392" for PMIC MT6392 "mediatek,mt6397" for PMIC MT6397 Optional subnodes: @@ -52,7 +53,10 @@ Optional subnodes: - keys Required properties: - - compatible: "mediatek,mt6397-keys" or "mediatek,mt6323-keys" + - compatible: + - "mediatek,mt6323-keys" + - "mediatek,mt6392-keys", "mediatek,mt6397-keys" + - "mediatek,mt6397-keys" see ../input/mtk-pmic-keys.txt - power-controller -- 2.28.0
[PATCH 2/2] clk: mediatek: Add MT8167 clock support
Add the following clock support for MT8167 SoC: topckgen, apmixedsys,
infracfg, audsys, imgsys, mfgcfg, mmsys, vdecsys.
Signed-off-by: Fabien Parent
---
drivers/clk/mediatek/Kconfig | 48 +
drivers/clk/mediatek/Makefile|6 +
drivers/clk/mediatek/clk-mt8167-aud.c| 66 ++
drivers/clk/mediatek/clk-mt8167-img.c| 60 ++
drivers/clk/mediatek/clk-mt8167-mfgcfg.c | 58 ++
drivers/clk/mediatek/clk-mt8167-mm.c | 132 +++
drivers/clk/mediatek/clk-mt8167-vdec.c | 73 ++
drivers/clk/mediatek/clk-mt8167.c| 1069 ++
8 files changed, 1512 insertions(+)
create mode 100644 drivers/clk/mediatek/clk-mt8167-aud.c
create mode 100644 drivers/clk/mediatek/clk-mt8167-img.c
create mode 100644 drivers/clk/mediatek/clk-mt8167-mfgcfg.c
create mode 100644 drivers/clk/mediatek/clk-mt8167-mm.c
create mode 100644 drivers/clk/mediatek/clk-mt8167-vdec.c
create mode 100644 drivers/clk/mediatek/clk-mt8167.c
diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 89ceb2fbc7c4..ce8475098b31 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -352,6 +352,54 @@ config COMMON_CLK_MT8135
help
This driver supports MediaTek MT8135 clocks.
+config COMMON_CLK_MT8167
+ bool "Clock driver for MediaTek MT8167"
+ depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
+ select COMMON_CLK_MEDIATEK
+ default ARCH_MEDIATEK
+ help
+ This driver supports MediaTek MT8167 basic clocks.
+
+config COMMON_CLK_MT8167_AUDSYS
+ bool "Clock driver for MediaTek MT8167 audsys"
+ depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
+ select COMMON_CLK_MEDIATEK
+ default ARCH_MEDIATEK
+ help
+ This driver supports MediaTek MT8167 audsys clocks.
+
+config COMMON_CLK_MT8167_IMGSYS
+ bool "Clock driver for MediaTek MT8167 imgsys"
+ depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
+ select COMMON_CLK_MEDIATEK
+ default ARCH_MEDIATEK
+ help
+ This driver supports MediaTek MT8167 imgsys clocks.
+
+config COMMON_CLK_MT8167_MFGCFG
+ bool "Clock driver for MediaTek MT8167 mfgcfg"
+ depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
+ select COMMON_CLK_MEDIATEK
+ default ARCH_MEDIATEK
+ help
+ This driver supports MediaTek MT8167 mfgcfg clocks.
+
+config COMMON_CLK_MT8167_MMSYS
+ bool "Clock driver for MediaTek MT8167 mmsys"
+ depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
+ select COMMON_CLK_MEDIATEK
+ default ARCH_MEDIATEK
+ help
+ This driver supports MediaTek MT8167 mmsys clocks.
+
+config COMMON_CLK_MT8167_VDECSYS
+ bool "Clock driver for MediaTek MT8167 vdecsys"
+ depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
+ select COMMON_CLK_MEDIATEK
+ default ARCH_MEDIATEK
+ help
+ This driver supports MediaTek MT8167 vdecsys clocks.
+
config COMMON_CLK_MT8173
bool "Clock driver for MediaTek MT8173"
depends on ARCH_MEDIATEK || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 959b556d32ea..3b0c2be73824 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -47,6 +47,12 @@ obj-$(CONFIG_COMMON_CLK_MT7629) += clk-mt7629.o
obj-$(CONFIG_COMMON_CLK_MT7629_ETHSYS) += clk-mt7629-eth.o
obj-$(CONFIG_COMMON_CLK_MT7629_HIFSYS) += clk-mt7629-hif.o
obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
+obj-$(CONFIG_COMMON_CLK_MT8167) += clk-mt8167.o
+obj-$(CONFIG_COMMON_CLK_MT8167_AUDSYS) += clk-mt8167-aud.o
+obj-$(CONFIG_COMMON_CLK_MT8167_IMGSYS) += clk-mt8167-img.o
+obj-$(CONFIG_COMMON_CLK_MT8167_MFGCFG) += clk-mt8167-mfgcfg.o
+obj-$(CONFIG_COMMON_CLK_MT8167_MMSYS) += clk-mt8167-mm.o
+obj-$(CONFIG_COMMON_CLK_MT8167_VDECSYS) += clk-mt8167-vdec.o
obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173.o
obj-$(CONFIG_COMMON_CLK_MT8173_MMSYS) += clk-mt8173-mm.o
obj-$(CONFIG_COMMON_CLK_MT8183) += clk-mt8183.o
diff --git a/drivers/clk/mediatek/clk-mt8167-aud.c
b/drivers/clk/mediatek/clk-mt8167-aud.c
new file mode 100644
index ..3f7bf6485792
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8167-aud.c
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2020 MediaTek Inc.
+ * Copyright (c) 2020 BayLibre, SAS
+ * Author: James Liao
+ * Fabien Parent
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include
+
+static const struct mtk_gate_regs aud_cg_regs = {
+ .set_ofs = 0x0,
+ .clr_ofs = 0x0,
+ .sta_ofs = 0x0,
+};
+
+#define GATE_AUD(_id, _name, _parent, _shift) {\
+ .id = _id, \
+ .name = _name,
[PATCH 1/2] dt-bindings: clock: mediatek: add bindings for MT8167 clocks
Add binding documentation for topckgen, apmixedsys, infracfg, audsys, imgsys, mfgcfg, mmsys, vdecsys on MT8167 SoC. Signed-off-by: Fabien Parent --- .../arm/mediatek/mediatek,apmixedsys.txt | 1 + .../bindings/arm/mediatek/mediatek,audsys.txt | 1 + .../bindings/arm/mediatek/mediatek,imgsys.txt | 1 + .../arm/mediatek/mediatek,infracfg.txt| 1 + .../bindings/arm/mediatek/mediatek,mfgcfg.txt | 1 + .../arm/mediatek/mediatek,topckgen.txt| 1 + .../arm/mediatek/mediatek,vdecsys.txt | 1 + include/dt-bindings/clock/mt8167-clk.h| 131 ++ 8 files changed, 138 insertions(+) create mode 100644 include/dt-bindings/clock/mt8167-clk.h diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt index bd7a0fa5801b..ea827e8763de 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt @@ -15,6 +15,7 @@ Required Properties: - "mediatek,mt7623-apmixedsys", "mediatek,mt2701-apmixedsys" - "mediatek,mt7629-apmixedsys" - "mediatek,mt8135-apmixedsys" + - "mediatek,mt8167-apmixedsys", "syscon" - "mediatek,mt8173-apmixedsys" - "mediatek,mt8183-apmixedsys", "syscon" - "mediatek,mt8516-apmixedsys" diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt index 38309db115f5..b32d374193c7 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt @@ -11,6 +11,7 @@ Required Properties: - "mediatek,mt6779-audio", "syscon" - "mediatek,mt7622-audsys", "syscon" - "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon" + - "mediatek,mt8167-audiosys", "syscon" - "mediatek,mt8183-audiosys", "syscon" - "mediatek,mt8516-audsys", "syscon" - #clock-cells: Must be 1 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt index 1e1f00718a7d..dce4c9241932 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt @@ -12,6 +12,7 @@ Required Properties: - "mediatek,mt6779-imgsys", "syscon" - "mediatek,mt6797-imgsys", "syscon" - "mediatek,mt7623-imgsys", "mediatek,mt2701-imgsys", "syscon" + - "mediatek,mt8167-imgsys", "syscon" - "mediatek,mt8173-imgsys", "syscon" - "mediatek,mt8183-imgsys", "syscon" - #clock-cells: Must be 1 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt index 49a968be1a80..eb3523c7a7be 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt @@ -16,6 +16,7 @@ Required Properties: - "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon" - "mediatek,mt7629-infracfg", "syscon" - "mediatek,mt8135-infracfg", "syscon" + - "mediatek,mt8167-infracfg", "syscon" - "mediatek,mt8173-infracfg", "syscon" - "mediatek,mt8183-infracfg", "syscon" - "mediatek,mt8516-infracfg", "syscon" diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt index ad5f9d2f6818..054424fb64b4 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt @@ -8,6 +8,7 @@ Required Properties: - compatible: Should be one of: - "mediatek,mt2712-mfgcfg", "syscon" - "mediatek,mt6779-mfgcfg", "syscon" + - "mediatek,mt8167-mfgcfg", "syscon" - "mediatek,mt8183-mfgcfg", "syscon" - #clock-cells: Must be 1 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt index 9b0394cbbdc9..5ce7578cf274 100644 --- a/Documentation/devicetree/bindin
Re: [PATCH 1/2] dt-bindings: clock: mediatek: add bindings for MT8167 clocks
Hi Chun-Kuang, > Why don't you add compatible of "mediatek,mt8167-mmsys"? I forgot to remove 'mmsys' from the commit message. I decided to add the documentation as part of the series that add support for MT8167 to drivers/soc/mediatek/mtk-mmsys.c. If you think it would be better to document it here I can add the bindings in the V2.
[PATCH 2/2] pinctrl: mediatek: Add MT8167 Pinctrl driver
This commit adds the pinctrl driver for the MediaTek's MT8167 SoC.
Signed-off-by: Fabien Parent
---
drivers/pinctrl/mediatek/Kconfig |7 +
drivers/pinctrl/mediatek/Makefile |1 +
drivers/pinctrl/mediatek/pinctrl-mt8167.c | 362 +
drivers/pinctrl/mediatek/pinctrl-mtk-mt8167.h | 1248 +
4 files changed, 1618 insertions(+)
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt8167.c
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt8167.h
diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
index 1cedc5f2aadb..dc5a2be2e415 100644
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -119,6 +119,13 @@ config PINCTRL_MT7622
default ARM64 && ARCH_MEDIATEK
select PINCTRL_MTK_MOORE
+config PINCTRL_MT8167
+ bool "Mediatek MT8167 pin control"
+ depends on OF
+ depends on ARM64 || COMPILE_TEST
+ default ARM64 && ARCH_MEDIATEK
+ select PINCTRL_MTK
+
config PINCTRL_MT8173
bool "Mediatek MT8173 pin control"
depends on OF
diff --git a/drivers/pinctrl/mediatek/Makefile
b/drivers/pinctrl/mediatek/Makefile
index b0b07c541d11..94db8cdc999d 100644
--- a/drivers/pinctrl/mediatek/Makefile
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_PINCTRL_MT6797) += pinctrl-mt6797.o
obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o
obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o
obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
+obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o
obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o
obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o
obj-$(CONFIG_PINCTRL_MT8516) += pinctrl-mt8516.o
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8167.c
b/drivers/pinctrl/mediatek/pinctrl-mt8167.c
new file mode 100644
index ..7b68886bad16
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8167.c
@@ -0,0 +1,362 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2020 MediaTek Inc.
+ * Author: Min.Guo
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "pinctrl-mtk-common.h"
+#include "pinctrl-mtk-mt8167.h"
+
+static const struct mtk_drv_group_desc mt8167_drv_grp[] = {
+ /* 0E4E8SR 4/8/12/16 */
+ MTK_DRV_GRP(4, 16, 1, 2, 4),
+ /* 0E2E4SR 2/4/6/8 */
+ MTK_DRV_GRP(2, 8, 1, 2, 2),
+ /* E8E4E2 2/4/6/8/10/12/14/16 */
+ MTK_DRV_GRP(2, 16, 0, 2, 2)
+};
+
+static const struct mtk_pin_drv_grp mt8167_pin_drv[] = {
+ MTK_PIN_DRV_GRP(0, 0xd00, 0, 0),
+ MTK_PIN_DRV_GRP(1, 0xd00, 0, 0),
+ MTK_PIN_DRV_GRP(2, 0xd00, 0, 0),
+ MTK_PIN_DRV_GRP(3, 0xd00, 0, 0),
+ MTK_PIN_DRV_GRP(4, 0xd00, 0, 0),
+
+ MTK_PIN_DRV_GRP(5, 0xd00, 4, 0),
+ MTK_PIN_DRV_GRP(6, 0xd00, 4, 0),
+ MTK_PIN_DRV_GRP(7, 0xd00, 4, 0),
+ MTK_PIN_DRV_GRP(8, 0xd00, 4, 0),
+ MTK_PIN_DRV_GRP(9, 0xd00, 4, 0),
+ MTK_PIN_DRV_GRP(10, 0xd00, 4, 0),
+
+ MTK_PIN_DRV_GRP(11, 0xd00, 8, 0),
+ MTK_PIN_DRV_GRP(12, 0xd00, 8, 0),
+ MTK_PIN_DRV_GRP(13, 0xd00, 8, 0),
+
+ MTK_PIN_DRV_GRP(14, 0xd00, 12, 2),
+ MTK_PIN_DRV_GRP(15, 0xd00, 12, 2),
+ MTK_PIN_DRV_GRP(16, 0xd00, 12, 2),
+ MTK_PIN_DRV_GRP(17, 0xd00, 12, 2),
+
+ MTK_PIN_DRV_GRP(18, 0xd10, 0, 0),
+ MTK_PIN_DRV_GRP(19, 0xd10, 0, 0),
+ MTK_PIN_DRV_GRP(20, 0xd10, 0, 0),
+
+ MTK_PIN_DRV_GRP(21, 0xd00, 12, 2),
+ MTK_PIN_DRV_GRP(22, 0xd00, 12, 2),
+ MTK_PIN_DRV_GRP(23, 0xd00, 12, 2),
+
+ MTK_PIN_DRV_GRP(24, 0xd00, 8, 0),
+ MTK_PIN_DRV_GRP(25, 0xd00, 8, 0),
+
+ MTK_PIN_DRV_GRP(26, 0xd10, 4, 1),
+ MTK_PIN_DRV_GRP(27, 0xd10, 4, 1),
+ MTK_PIN_DRV_GRP(28, 0xd10, 4, 1),
+ MTK_PIN_DRV_GRP(29, 0xd10, 4, 1),
+ MTK_PIN_DRV_GRP(30, 0xd10, 4, 1),
+
+ MTK_PIN_DRV_GRP(31, 0xd10, 8, 1),
+ MTK_PIN_DRV_GRP(32, 0xd10, 8, 1),
+ MTK_PIN_DRV_GRP(33, 0xd10, 8, 1),
+
+ MTK_PIN_DRV_GRP(34, 0xd10, 12, 0),
+ MTK_PIN_DRV_GRP(35, 0xd10, 12, 0),
+
+ MTK_PIN_DRV_GRP(36, 0xd20, 0, 0),
+ MTK_PIN_DRV_GRP(37, 0xd20, 0, 0),
+ MTK_PIN_DRV_GRP(38, 0xd20, 0, 0),
+ MTK_PIN_DRV_GRP(39, 0xd20, 0, 0),
+
+ MTK_PIN_DRV_GRP(40, 0xd20, 4, 1),
+
+ MTK_PIN_DRV_GRP(41, 0xd20, 8, 1),
+ MTK_PIN_DRV_GRP(42, 0xd20, 8, 1),
+ MTK_PIN_DRV_GRP(43, 0xd20, 8, 1),
+
+ MTK_PIN_DRV_GRP(44, 0xd20, 12, 1),
+ MTK_PIN_DRV_GRP(45, 0xd20, 12, 1),
+ MTK_PIN_DRV_GRP(46, 0xd20, 12, 1),
+ MTK_PIN_DRV_GRP(47, 0xd20, 12, 1),
+
+ MTK_PIN_DRV_GRP(48, 0xd30, 0, 1),
+ MTK_PIN_DRV_GRP(49, 0xd30, 0, 1),
+ MTK_PIN_DRV_GRP(50, 0xd30, 0, 1),
+ MTK_PIN_DRV_GRP(51, 0xd30, 0, 1),
+
+ MTK_PIN_DRV_GRP(54, 0xd30, 8, 1),
+
+ MTK_PIN_DRV_GRP(55, 0xd30, 12, 1),
+ MTK_PIN_DRV_GRP(56, 0xd30, 12, 1),
+ MTK_PIN
[PATCH 1/2] pinctrl: mt65xx: add OF bindings for MT8167
Add binding documentation of pinctrl-mt65xx for MT8167 SoC. Signed-off-by: Fabien Parent --- Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt index 205be98ae078..931a18cd1e23 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt @@ -10,6 +10,7 @@ Required properties: "mediatek,mt7623-pinctrl", compatible with mt7623 pinctrl. "mediatek,mt8127-pinctrl", compatible with mt8127 pinctrl. "mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl. + "mediatek,mt8167-pinctrl", compatible with mt8167 pinctrl. "mediatek,mt8173-pinctrl", compatible with mt8173 pinctrl. "mediatek,mt8516-pinctrl", compatible with mt8516 pinctrl. - pins-are-numbered: Specify the subnodes are using numbered pinmux to -- 2.28.0
