ng irq)
> {
> orion_sata.dev.platform_data = sata_data;
> - fill_resources(_sata, orion_sata_resources,
> + fill_resources_irq(_sata, orion_sata_resources,
> mapbase, 0x5000 - 1, irq);
>
> platform_device_register(_sata);
> @@ -
t spi_board_info __initdata
> rd88f6183ap_ge_spi_slave_info[] = {
> {
> .modalias = "m25p80",
> .platform_data = _ge_spi_slave_data,
> - .irq= NO_IRQ,
> .max_speed_hz = 2000,
> .bus_num= 0,
>
dio.dev;
> - orion_switch_device.dev.platform_data = d;
>
> - platform_device_register(_switch_device);
> + platform_device_register_data(NULL, "dsa", 0, d, sizeof(d));
> }
>
>
> /*
> diff --git a/arch/arm/plat-orion/include/plat/common.h
> b/arch/arm/plat-orion/include/plat/common.h
> index 8519727faa5e..9347f3c58a6d 100644
> --- a/arch/arm/plat-orion/include/plat/common.h
> +++ b/arch/arm/plat-orion/include/plat/common.h
> @@ -57,8 +57,7 @@ void __init orion_ge11_init(struct
> mv643xx_eth_platform_data *eth_data,
> unsigned long mapbase,
> unsigned long irq);
>
> -void __init orion_ge00_switch_init(struct dsa_platform_data *d,
> -int irq);
> +void __init orion_ge00_switch_init(struct dsa_platform_data *d);
>
> void __init orion_i2c_init(unsigned long mapbase,
> unsigned long irq,
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
code more readable by helping abstract away some
> of the Kconfig built-in and module enable details.
>
> Signed-off-by: Javier Martinez Canillas <jav...@osg.samsung.com>
Acked-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
Thanks,
Gregory
> ---
>
> driv
While trying using a peripheral clock on a driver, I saw that the clock
pointer returned by the provider was NULL.
The problem was a missing indirection. It was the pointer stored in the
hws array which needed to be updated not the value it contains.
Signed-off-by: Gregory CLEMENT <gregory.c
For the gate part of the peripheral clock setting the bit disables the
clock and clearing it enables the clock. This is not the default behavior
of clk_gate component, so we need to use the CLK_GATE_SET_TO_DISABLE flag.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.
From: Ziji Hu <huz...@marvell.com>
Export sdhci_execute_tuning() from sdhci.c.
Thus vendor sdhci driver can execute its own tuning process.
Signed-off-by: Hu Ziji <huz...@marvell.com>
Reviewed-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
Signed-off-by: Gregory CLE
From: Ziji Hu <huz...@marvell.com>
Add maintainer entry for Marvell Xenon eMMC/SD/SDIO Host
Controller drivers.
Signed-off-by: Hu Ziji <huz...@marvell.com>
Reviewed-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clem.
This patch enables the driver for the SDHCI controller found on the
Marvell Armada 3700 and 7K/8K ARM64 SoCs.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+), 0 deletions(-)
diff --git a/arch
Add the eMMC support for Armada 37xx SoC and enable it in the Armada 3720
DB board.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 7 +++
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 11 +++
2
From: Ziji Hu <huz...@marvell.com>
Export sdhci_start_signal_voltage_switch() from sdhci.c.
Thus vendor sdhci driver can implement its own signal voltage
switch routine.
Signed-off-by: Hu Ziji <huz...@marvell.com>
Reviewed-by: Gregory CLEMENT <gregory.clem...@free-electrons.
From: Ziji Hu <huz...@marvell.com>
Marvell Xenon eMMC/SD/SDIO Host Controller contains PHY.
Three types of PHYs are supported.
Add support to multiple types of PHYs init and configuration.
Add register definitions of PHYs.
Signed-off-by: Hu Ziji <huz...@marvell.com>
Reviewed-by: Gre
rding to the guidelines provided in the SD Host
Controller Standard Specification Version 3.00.
Xenon SDHC IP contains PHY. There are tree types of Xenon PHY in use.
Each Xenon SDHC only contain one type of PHY."
Thanks,
Gregory
Gregory CLEMENT (3):
arm64: dts: marvell: add eMMC support for A
Also enable it on the Armada 7040 DB board
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-7040-db.dts | 7 +++
arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 9 +
2 files changed, 16 insertions(+), 0 deletions(-)
From: Ziji Hu <huz...@marvell.com>
Marvell Xenon SDHC can support eMMC/SD/SDIO.
Add Xenon-specific properties.
Also add properties for Xenon PHY setting.
Signed-off-by: Hu Ziji <huz...@marvell.com>
Reviewed-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
Signed-off-b
From: Ziji Hu <huz...@marvell.com>
Export sdhci_set_ios() in sdhci.c.
Thus vendor sdhci driver can implement its own set_ios() routine.
Signed-off-by: Hu Ziji <huz...@marvell.com>
Reviewed-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
Signed-off-by: Gregory CLE
Xenon SDHC conforms to SD Physical Layer Specification
Version 3.01 and is designed according to the guidelines provided
in the SD Host Controller Standard Specification Version 3.00.
Signed-off-by: Hu Ziji <huz...@marvell.com>
Reviewed-by: Gregory CLEMENT <gregory.clem...@free-electrons.
Hi Stephen and Mike
On jeu., sept. 29 2016, Gregory CLEMENT <gregory.clem...@free-electrons.com>
wrote:
> While trying using a peripheral clock on a driver, I saw that the clock
> pointer returned by the provider was NULL.
>
> The problem was a missing indirection. It was
Hi Stephen,
On mar., sept. 20 2016, Stephen Boyd <sb...@codeaurora.org> wrote:
> On 09/20, Gregory CLEMENT wrote:
>> From: Jamie Lentin <j...@lentin.co.uk>
>>
>> Referring to the u-boot sources for the Netgear WNR854T, add support
>> for the
by: Rob Herring <r...@kernel.org>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
Hi Stephen and Mike,
do you agree to give your acked-by on this patch. It is part of a
convertion of old orion5x Socv to the device tree. If you acked-by
this one, then I will
a proper value.
>
> Fixes: c749b8d9de32 ("arm64: dts: marvell: add description for the ...")
> Signed-off-by: Marcin Wojtas <m...@semihalf.com>
Acked-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
Could you take this patch for 4.9? I didn't realized at f
clocks = <_syscon0 0 3>;
> + clocks = <_syscon0 1 21>;
> status = "disabled";
> };
>
> --
> 1.8.3.1
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
reg = <0x3f0100 0x10>;
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + interrupts = ;
> + };
> +
> xor@40 {
> compatible
the last time."
>>
>
> If you use the ordering by address as main argument for the revert there
> will be nothing to argue about.
>
>> To be blunt, I think our best path forward is to just hold our noses
>> and let it stand as is. Some will fix their userspace to a
"mpp32";
> + marvell,function = "dev";
> + };
> +
> uart0_pins: uart-pins-0 {
> marvell,pins = "mpp0", "mpp1";
> marvell,function = "ua0";
> --
> 2.9.2.518.ged577c6.dirty
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
+ "jedec,spi-nor";
> + reg = <0>; /* Chip select 0 */
> + spi-max-frequency = <10800>;
> +
> + partitions {
> + compatible = "fixed-partitions";
> + #address-cells = <1>;
> +
ocksource
for CP110 slave SPI0" which didn't find his way to mainline yet.
Thanks,
Gregory
>
> Thomas
> --
> Thomas Petazzoni, CTO, Free Electrons
> Embedded Linux and Kernel engineering
> http://free-electrons.com
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
gt;;
[...]
xenon,slotno = <0>;
bus-width = <8>;
xenon,pad-type = "fixed-1-8v";
};
sdhci@bb {
/* slot1 is an SD Card */
compatible = "marvell,armada-3700-sdhci";
rate->reg = reg + (u64)rate->reg;
+ rate->width = order_base_2(table_size);
+ rate->lock = lock;
+ } else {
+ rate_hw = NULL;
+ rate_ops = NULL;
+ }
}
}
Gregory
> }
> }
>
>
>
> Arnd
>
> ___
> linux-arm-kernel mailing list
> linux-arm-ker...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
tation depend on the per cpu interrupts.
[gregory.clem...@free-electrons.com: extract from a larger patch, replace
some ifdef and port to net-next for v4.10]
Signed-off-by: Marcin Wojtas <m...@semihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
Docume
ihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/ethernet/marvell/mvneta.c | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/marvell/mvneta.c
b/drivers/net/ethernet/marvell/mvneta.c
Actually only the mvneta_bm support is not 64-bits compatible.
The mvneta code itself can run on 64-bits architecture.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/ethernet/marvell/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff
(no more need to use the DMA API). Thanks to this, it is
possible to use cache contrary to the access of the rx descriptor member.
The change is done in the swbm path only because the hwbm uses the cookie
field, this also means that currently the hwbm is not usable in 64-bits.
Signed-off-by: Gregory
by patch 4.
In patch 5 the dt support is added.
Beside Armada 37xx, the series have been tested on Armada XP and
Armada 38x (with Hardware Buffer Management and with Software Buffer
Managment).
Thanks,
Gregory
Gregory CLEMENT (3):
net: mvneta: Use cacheable memory to store the rx buffer
Add neta nodes for network support both in device tree for the SoC and
the board.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 23 +++-
arch/arm64/boot/dts/marvell/armada-37xx.dtsi
Hi Ulf,
On lun., oct. 31 2016, Gregory CLEMENT <gregory.clem...@free-electrons.com>
wrote:
> Hello,
>
> This the second version of the series adding support for the SDHCI
> Xenon controller. It can be currently found on the Armada 37xx and the
> Armada 7K/8K but will
vember 22, 2016 5:48:41 PM CET Gregory CLEMENT wrote:
>> > > +#ifdef CONFIG_64BIT
>> > > + void *data_tmp;
>> > > +
>> > > + /* In Neta HW only 32 bits data is supported, so in order to
>> > > +* obtain whole 64 bits addre
---help---
> @@ -81,6 +82,7 @@ config MVPP2
> tristate "Marvell Armada 375 network interface support"
> depends on MACH_ARMADA_375 || COMPILE_TEST
> depends on HAS_DMA
> + depends on !64BIT
> select MVMDIO
> ---help---
> T
Actually only the mvneta_bm support is not 64-bits compatible.
The mvneta code itself can run on 64-bits architecture.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/ethernet/marvell/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff
Hi,
On mar., nov. 22 2016, Gregory CLEMENT <gregory.clem...@free-electrons.com>
wrote:
> Actually only the mvneta_bm support is not 64-bits compatible.
> The mvneta code itself can run on 64-bits architecture.
I have just realized that my topic prefix was wrong (net-next was
mi
Actually only the mvneta_bm support is not 64-bits compatible.
The mvneta code itself can run on 64-bits architecture.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/ethernet/marvell/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff
Hi David,
On mar., nov. 22 2016, David Miller <da...@davemloft.net> wrote:
> From: Gregory CLEMENT <gregory.clem...@free-electrons.com>
> Date: Tue, 22 Nov 2016 17:00:37 +0100
>
>> Actually only the mvneta_bm support is not 64-bits compatible.
>> The mvne
ke the implementation which put multiple slots behind PCIe EP
> interface. sdhci-pci.c will handle each slot init one by one.
> If Xenon SDHC slots are represented as child nodes, there should also
> be a main entry in Xenon driver to init each child node one by one.
> In my very own opinion, it is inconvenient and unnecessary.
Gregory
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
related to the Armada
3700 SoC. The main one being the used of shared interrupt instead of
the private ones. It has been addressed in the 3rd patch.
Not all the feature supported on the older Soc have been ported yet
for this new SoC.
Gregory CLEMENT (2):
net: mvneta: Only disable mvneta_bm for 64
tation depend on precpu interrupt.
[gregory.clem...@free-electrons.com: extract from a larger patch, replace
some ifdef and port to net-next for v4.10]
Signed-off-by: Marcin Wojtas <m...@semihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
.../bindings/net/
Actually only the mvneta_bm support is not 64-bits compatible.
The mvneta code itself can run on 64-bits architecture.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/ethernet/marvell/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff
Add neta nodes for network support both in device tree for the SoC and
the board.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 23 +++
arch/arm64/boot/dts/marvell/armada-37xx.dtsi
ihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/ethernet/marvell/mvneta.c | 77 ---
1 file changed, 71 insertions(+), 6 deletions(-)
diff --git a/drivers/net/ethernet/marvell/mvneta.c
b/drivers/net/etherne
ns to encapsulate multiple MMC host controllers, and possibly
> provides some shared registers to them.
I don't have an option for mmc in general, but using child node do not
fit at all the xenon controller.
For this controller each slot has its own set of register, so there is
no common resso
Hi Jisheng,
On lun., nov. 28 2016, Jisheng Zhang <jszh...@marvell.com> wrote:
> Hi Gregory,
>
> On Fri, 25 Nov 2016 16:30:14 +0100 Gregory CLEMENT wrote:
>
>> Until now the virtual address of the received buffer were stored in the
>> cookie field of the rx descrip
ecommend using READ_ONCE()/WRITE_ONCE()
> to access the descriptor fields, to ensure the compiler doesn't
> add extra references as well as to annotate the expensive
> operations.
>
> Arnd
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
1113
>
> Although all mvebu_mbus_common_init() callers seem to actually use
> _state in the 1st argument, this is still a bug that could be
> triggered by future changes.
>
> Signed-off-by: Luis Henriques <hen...@camandro.org>
Acked-by: Gregory CLEMENT <gregory.clem...@free
From: Ziji Hu <huz...@marvell.com>
Export sdhci_execute_tuning() from sdhci.c.
Thus vendor sdhci driver can execute its own tuning process.
Signed-off-by: Hu Ziji <huz...@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/mm
From: Ziji Hu <huz...@marvell.com>
Marvell Xenon SDHC can support eMMC/SD/SDIO.
Add Xenon-specific properties.
Also add properties for Xenon PHY setting.
Signed-off-by: Hu Ziji <huz...@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
Docume
From: Ziji Hu <huz...@marvell.com>
Marvell Xenon eMMC/SD/SDIO Host Controller contains PHY.
Three types of PHYs are supported.
Add support to multiple types of PHYs init and configuration.
Add register definitions of PHYs.
Signed-off-by: Hu Ziji <huz...@marvell.com>
Signed-off
Add the eMMC support for Armada 37xx SoC and enable it in the Armada 3720
DB board.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 8
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 11 +++
2
uirks SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 in Xenon platform data
Add support to HS400 retuning."
I think the main open point which remains is about issuing commands
from the ->set_ios() callback (in patch 7).
Ulf, could you comment about it?
Thanks,
Gregory
Gregory CLEMENT (3):
arm64: dts: marvell: add
From: Ziji Hu <huz...@marvell.com>
Export sdhci_start_signal_voltage_switch() from sdhci.c.
Thus vendor sdhci driver can implement its own signal voltage
switch routine.
Signed-off-by: Hu Ziji <huz...@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.co
This patch enables the driver for the SDHCI controller found on the
Marvell Armada 3700 and 7K/8K ARM64 SoCs.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+), 0 deletions(-)
diff --git a/arch
Xenon SDHC conforms to SD Physical Layer Specification
Version 3.01 and is designed according to the guidelines provided
in the SD Host Controller Standard Specification Version 3.00.
Signed-off-by: Hu Ziji <huz...@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@fre
From: Ziji Hu <huz...@marvell.com>
Export sdhci_set_ios() in sdhci.c.
Thus vendor sdhci driver can implement its own set_ios() routine.
Signed-off-by: Hu Ziji <huz...@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/mmc/host/sdhci.
Also enable it on the Armada 7040 DB board
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-7040-db.dts | 8
arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 9 +
2 files changed, 17 insertions(+), 0 deletions(-)
From: Ziji Hu <huz...@marvell.com>
Add maintainer entry for Marvell Xenon eMMC/SD/SDIO Host
Controller drivers.
Signed-off-by: Hu Ziji <huz...@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
MAINTAINERS | 5 +
1 file changed, 5 insertio
rch/arm/boot/dts/armada-39x.dtsi
> index 34cba87f9200..de171baffcf6 100644
> --- a/arch/arm/boot/dts/armada-39x.dtsi
> +++ b/arch/arm/boot/dts/armada-39x.dtsi
> @@ -573,7 +573,7 @@
> };
>
> clocks {
> - /* 2 GHz fixed main PLL */
> + /* 1 GHz fixed
Hi,
On lun., oct. 31 2016, Gregory CLEMENT <gregory.clem...@free-electrons.com>
wrote:
> Hello,
>
> This the second version of the series adding support for the SDHCI
> Xenon controller. It can be currently found on the Armada 37xx and the
> Armada 7K/8K but will be also
s, " edge ");
> + seq_puts(s, " edge ");
> if (lvl_msk & msk)
> - seq_printf(s, " level");
> + seq_puts(s, " level");
> seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear ");
> }
> }
> --
> 2.10.1
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
by patch 4.
In patch 5 the dt support is added.
Beside Armada 37xx, the series have been tested on Armada XP and
Armada 38x (with Hardware Buffer Management and with Software Buffer
Managment).
Thanks,
Gregory
Gregory CLEMENT (4):
net: mvneta: Optimize rx path for small frame
net: mvneta
Hi Marcin,
On mar., nov. 29 2016, Marcin Wojtas <m...@semihalf.com> wrote:
> Gregory,
>
> 2016-11-29 11:19 GMT+01:00 Gregory CLEMENT
> <gregory.clem...@free-electrons.com>:
>> Hi Marcin,
>>
>> On mar., nov. 29 2016, Marcin Wojtas <m...@semihalf.c
(no more need to use the DMA API). Thanks to this, it is
possible to use cache contrary to the access of the rx descriptor member.
The change is done in the swbm path only because the hwbm uses the cookie
field, this also means that currently the hwbm is not usable in 64-bits.
Signed-off-by: Gregory
Hi Marcin,
On mar., nov. 29 2016, Marcin Wojtas <m...@semihalf.com> wrote:
> Hi Gregory,
>
> Another remark below, sorry for noise.
>
> 2016-11-29 10:37 GMT+01:00 Gregory CLEMENT
> <gregory.clem...@free-electrons.com>:
>> Until now the virtual addres
Add neta nodes for network support both in device tree for the SoC and
the board.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 23 +++-
arch/arm64/boot/dts/marvell/armada-37xx.dtsi
tation depend on the per cpu interrupts.
[gregory.clem...@free-electrons.com: extract from a larger patch, replace
some ifdef and port to net-next for v4.10]
Signed-off-by: Marcin Wojtas <m...@semihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
Docume
ihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/ethernet/marvell/mvneta.c | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/marvell/mvneta.c
b/drivers/net/ethernet/marvell/mvneta.c
For small frame reuse the phys_addr variable instead of accessing the
uncacheable value in the rx descriptor.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/ethernet/marvell/mvneta.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/d
Actually only the mvneta_bm support is not 64-bits compatible.
The mvneta code itself can run on 64-bits architecture.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/ethernet/marvell/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff
Hi,
On mar., nov. 29 2016, Gregory CLEMENT <gregory.clem...@free-electrons.com>
wrote:
> Hi,
>
> The Armada 37xx is a new ARMv8 SoC from Marvell using same network
> controller as the older Armada 370/38x/XP SoCs. This series adapts the
> driver in order to be able to u
Hi Marcin,
On mar., nov. 29 2016, Marcin Wojtas <m...@semihalf.com> wrote:
> Hi Gregory,
>
> Apparently HWBM had a mistake in implementation, please see below.
>
> 2016-11-29 10:37 GMT+01:00 Gregory CLEMENT
> <gregory.clem...@free-electrons.com>:
&g
++-
> 4 files changed, 20 insertions(+), 20 deletions(-)
>
> --
> 2.10.2
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Hi Russell King,
On ven., janv. 13 2017, Russell King - ARM Linux <li...@armlinux.org.uk> wrote:
> On Fri, Jan 13, 2017 at 05:36:42PM +0100, Gregory CLEMENT wrote:
>> Hi Sebastian,
>>
>> On lun., janv. 09 2017, Bhumika Goyal <bhumi...@gmail.com> wrote:
&
tic struct reset_control_ops pmu_reset_ops = {
> +static const struct reset_control_ops pmu_reset_ops = {
> .reset = pmu_reset_reset,
> .assert = pmu_reset_assert,
> .deassert = pmu_reset_deassert,
> --
> 1.9.1
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
+ b/arch/arm/mach-mv78xx0/pcie.c
> @@ -29,7 +29,7 @@ struct pcie_port {
> u8 root_bus_nr;
> void __iomem*base;
> spinlock_t conf_lock;
> - charmem_space_name[16];
> + charmem_spac
Xenon SDHC conforms to SD Physical Layer Specification
Version 3.01 and is designed according to the guidelines provided
in the SD Host Controller Standard Specification Version 3.00.
Signed-off-by: Hu Ziji <huz...@marvell.com>
Tested-by: Russell King <rmk+ker...@armlinux.org.uk>
Sign
From: Hu Ziji <huz...@marvell.com>
Add maintainer entry for Marvell Xenon eMMC/SD/SDIO
Host Controller drivers.
Signed-off-by: Hu Ziji <huz...@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
MAINTAINERS | 7 +++
1 file changed, 7 i
From: Hu Ziji <huz...@marvell.com>
Export sdhci_enable_sdio_irq() from sdhci.c.
Thus vendor SDHC driver can implement its specific SDIO irq
control.
Signed-off-by: Hu Ziji <huz...@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/mm
From: Hu Ziji <huz...@marvell.com>
Export sdhci_start_signal_voltage_switch() from sdhci.c.
Thus vendor sdhci driver can implement its own signal voltage
switch routine.
Signed-off-by: Hu Ziji <huz...@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.co
From: Hu Ziji <huz...@marvell.com>
Export sdhci_set_ios() in sdhci.c.
Thus vendor sdhci driver can implement its own set_ios() routine.
Signed-off-by: Hu Ziji <huz...@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/mmc/host/sdhci.
ot; Changes in V2:
rebase on v4.9-rc2.
Re-write Xenon bindings. Ajust Xenon DT property naming.
Add a new DT property to indicate eMMC card type, instead of using
variable card_candidate.
Clear quirks SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 in Xenon platform data
Add support to HS400 retuni
lement Xenon PHY in MMC host directory.
Signed-off-by: Hu Ziji <huz...@marvell.com>
Tested-by: Russell King <rmk+ker...@armlinux.org.uk>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/mmc/host/Makefile | 2 +-
drivers/mmc/host
m>
Tested-by: Russell King <rmk+ker...@armlinux.org.uk>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/mmc/host/sdhci-xenon-phy.c | 116 +-
drivers/mmc/host/sdhci-xenon.c | 2 +-
drivers/mmc/host/sdhci-xenon.h | 2
Add the eMMC support for Armada 37xx SoC and enable it in the Armada 3720
DB board.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 16
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 11
lt;han...@marvell.com>
[fixed up conflicts, added error handling --rmk]
Signed-off-by: Russell King <rmk+ker...@armlinux.org.uk>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 3 ++-
drivers/clk/mv
This patch enables the driver for the SDHCI controller found on the
Marvell Armada 3700 and 7K/8K ARM64 SoCs.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defco
Also enable it on the Armada 7040 DB board
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-7040-db.dts | 14 +-
arch/arm64/boot/dts/marvell/armada-ap806.dtsi| 10 +-
arch/arm64/boot/dts/marvell/
From: Hu Ziji <huz...@marvell.com>
Marvell Xenon SDHC can support eMMC/SD/SDIO.
Add Xenon-specific properties.
Also add properties for Xenon PHY setting.
Signed-off-by: Hu Ziji <huz...@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
Docume
anks, I am going to send a new version with tour tested-by and the dts
fix for the second port.
Gregory
>
> Best regards,
> Marcin
>
> 2016-11-30 22:42 GMT+01:00 Gregory CLEMENT
> <gregory.clem...@free-electrons.com>:
>> Hi,
>>
>> The Armada 37xx is a new ARM
is introduced.
- Move the memory allocation of the buf_virt_addr of the rxq to be
called by the probe function in order to avoid a memory leak.
Thanks,
Gregory
Gregory CLEMENT (5):
net: mvneta: Optimize rx path for small frame
net: mvneta: Do not allocate buffer in rxq init with HWBM
net: mvneta: Use ca
For HWBM all buffers are allocated in mvneta_bm_construct() and in runtime
they are put into descriptors by hardware. There is no need to fill them
at this point.
Suggested-by: Marcin Wojtas <m...@semihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
Teste
Add neta nodes for network support both in device tree for the SoC and
the board.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 23 +++-
arch/arm64/boot/dts/marvell/armada-37xx.dtsi
For small frame reuse the phys_addr variable instead of accessing the
uncacheable value in the rx descriptor.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
Tested-by: Marcin Wojtas <m...@semihalf.com>
---
drivers/net/ethernet/marvell/mvneta.c | 2 +-
1 fil
ihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
Tested-by: Marcin Wojtas <m...@semihalf.com>
---
drivers/net/ethernet/marvell/mvneta.c | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/marvell
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