On Wed, Apr 25, 2018 at 11:16:07PM +0200, Alexandre Belloni wrote:
> Allow not building any DTB in the generic kernel so it gets smaller. This
> is necessary for ocelot because it can be built as a legacy platform that
> needs a built-in DTB and it can also handle a separate DTB once it is
> update
> + from Microsemi in the FIT kernel image.
> + This require u-boot on the platform.
nit: s/require/requires/
Reviewed-by: James Hogan
Cheers
James
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On Fri, Jun 15, 2018 at 02:12:58PM +0800, Greentime Hu wrote:
> Thank you James and Guenter.
> Should I pick it in my tree? It will be ok to put in your tree. :)
>
> Acked-by: Greentime Hu
I think your tree makes most sense for this patch, since it only touches
nds32 code and it was nds32 that g
; \
ARM doesn't do this for DEFINE_ABORT. Is it intentional that we do for
MIPS?
Otherwise this whole series looks reasonable to me, so feel free to add
my rb on the whole series if you do apply youself:
Reviewed-by: James Hogan
Thanks
James
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git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux")
Signed-off-by: Guenter Roeck
[jho...@kernel.org: Rename all 6 symbols, sort, update commit message]
Signed-off-by: James Hogan
Cc: Greentime Hu
Cc: Vincent Chen
Cc: Matt Redfearn
Cc: Palmer Dabbelt
---
Changes in v2:
- Rename all 6 symb
On Wed, Jun 13, 2018 at 02:28:08PM -0700, Guenter Roeck wrote:
> On Wed, Jun 13, 2018 at 10:06:13PM +0100, James Hogan wrote:
> > Thanks Guenter,
> >
> > On Wed, Jun 13, 2018 at 12:43:52PM -0700, Guenter Roeck wrote:
> > > GENERIC_ASHLDI3, GENERIC_ASHRDI3, and G
Thanks Guenter,
On Wed, Jun 13, 2018 at 12:43:52PM -0700, Guenter Roeck wrote:
> GENERIC_ASHLDI3, GENERIC_ASHRDI3, and GENERIC_LSHRDI3 were renamed to
> GENERIC_LIB_ASHLDI3, GENERIC_LIB_ASHRDI3, and GENERIC_LIB_LSHRDI3
> without making the matching changes in arch/nds32.
Well, thats a little misl
Hi,
Good to see this patch!
On Tue, Jun 12, 2018 at 01:40:30PM +0800, Songjun Wu wrote:
> diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms
> index ac7ad54f984f..bcd647060f3e 100644
> --- a/arch/mips/Kbuild.platforms
> +++ b/arch/mips/Kbuild.platforms
> @@ -12,6 +12,7 @@ platfo
On Tue, May 15, 2018 at 11:03:09PM +0100, Maciej W. Rozycki wrote:
> Correct comments across ptrace(2) handlers about an FPU register context
> layout discrepancy between MIPS I and later ISAs, which was fixed with
> `linux-mips.org' (LMO) commit 42533948caac ("Major pile of FP emulator
> changes."
On Wed, May 16, 2018 at 04:39:58PM +0100, Maciej W. Rozycki wrote:
> Use 64-bit accesses for 64-bit floating-point general registers with
> PTRACE_PEEKUSR, removing the truncation of their upper halves in the
> FR=1 mode, caused by commit bbd426f542cb ("MIPS: Simplify FP context
> access"), whic
On Tue, May 15, 2018 at 11:04:44PM +0100, Maciej W. Rozycki wrote:
> Having PR_FP_MODE_FRE (i.e. Config5.FRE) set without PR_FP_MODE_FR (i.e.
> Status.FR) is not supported as the lone purpose of Config5.FRE is to
> emulate Status.FR=0 handling on FPU hardware that has Status.FR=1
> hardwired[1][
On Wed, May 16, 2018 at 04:39:58PM +0100, Maciej W. Rozycki wrote:
> Use 64-bit accesses for 64-bit floating-point general registers with
> PTRACE_PEEKUSR, removing the truncation of their upper halves in the
> FR=1 mode, caused by commit bbd426f542cb ("MIPS: Simplify FP context
> access"), whic
On Mon, May 21, 2018 at 05:39:32PM +0100, James Hogan wrote:
> On Sun, Apr 08, 2018 at 10:30:03AM +0200, Mathias Kresin wrote:
> > While doing a global software reset, these bits are not cleared and let
> > some bootloader fail to initialise the GPHYs. The bootloader don't
>
%s not available "
> -"because of resource collisions\n",
> -pci_name(dev));
> + pci_err(dev, "can't enable device: resource
> collisions\n");
The pedantic side of me wants to point out that you could wrap tha
On Sun, Apr 08, 2018 at 10:30:03AM +0200, Mathias Kresin wrote:
> While doing a global software reset, these bits are not cleared and let
> some bootloader fail to initialise the GPHYs. The bootloader don't
> expect the GPHYs in reset, as they aren't during power on.
>
> The asserts were a workaro
On Tue, Apr 17, 2018 at 04:40:03PM +0100, Matt Redfearn wrote:
> diff --git a/arch/mips/lib/memset.S b/arch/mips/lib/memset.S
> index 1cc306520a55..a06dabe99d4b 100644
> --- a/arch/mips/lib/memset.S
> +++ b/arch/mips/lib/memset.S
> @@ -231,16 +231,25 @@
>
> #ifdef CONFIG_CPU_MIPSR6
> .Lbyte_fix
Given this:
On Wed, May 02, 2018 at 11:14:48PM +0200, Christoph Hellwig wrote:
> +struct __aio_sigset {
> + sigset_t __user *sigmask;
> + size_t sigsetsize;
> +};
and:
> +asmlinkage long sys_io_pgetevents(aio_context_t ctx_id,
> + long min_nr,
> +
On Fri, Jan 05, 2018 at 10:31:05AM +, Matt Redfearn wrote:
> The current location of ehb() in mipsmtregs.h does not make sense, since
> it is not strictly related to multi-threading, and may be used in code
> which does not include mipsmtregs.h
> arch/mips/include/asm/barrier.h| 13 ++
On Fri, Apr 20, 2018 at 11:23:07AM +0100, Matt Redfearn wrote:
> Previously when performance counters are per-core, rather than
> per-thread, the number available were divided by 2 on detection, and the
> counters used by each thread in a core were "swizzled" to ensure
> separation. However, this s
On Fri, Apr 20, 2018 at 11:23:06AM +0100, Matt Redfearn wrote:
> diff --git a/arch/mips/kernel/perf_event_mipsxx.c
> b/arch/mips/kernel/perf_event_mipsxx.c
> index 7e2b7d38a774..fe50986e83c6 100644
> --- a/arch/mips/kernel/perf_event_mipsxx.c
> +++ b/arch/mips/kernel/perf_event_mipsxx.c
> @@ -323,
On Mon, May 14, 2018 at 04:49:43PM +0100, Maciej W. Rozycki wrote:
> Check the TIF_32BIT_FPREGS task setting of the tracee rather than the
> tracer in determining the layout of floating-point general registers in
> the floating-point context, correcting access to odd-numbered registers
> for o32
On Wed, Apr 25, 2018 at 11:10:35PM +0200, Alexandre Belloni wrote:
> a dtb.o is generated from nexys4ddr.dts but this is never used since it has
> been moved to mips/generic with commit b35565bb16a5 ("MIPS: generic: Add
> support
> for MIPSfpga")
>
> Signed-off-by: Alexandre Belloni
Both applie
On Mon, May 14, 2018 at 06:23:50PM +0100, Colin King wrote:
> From: Colin Ian King
>
> Trivial fix to spelling mistake in debugfs_entries text
>
> Signed-off-by: Colin Ian King
Adding KVM folk. Its a fairly trivial change so I'll just take it as a
fix via the MIPS tree unless anybody objects.
On Mon, May 14, 2018 at 10:58:44PM +0200, Andrew Lunn wrote:
> Hi Alexandre
> >
> > The ocelot dts changes are here for reference and should probably go
> > through the MIPS tree once the bindings are accepted.
>
> For your next version, you probably want to drop those patches, so
> that David ca
gpr.c
> > @@ -29,7 +29,7 @@
> > #include
> > #include
> > #include
> > -#include
> > +#include
> > #include
> > #include
> > #include
Acked-by: James Hogan
Cheers
James
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On Tue, May 08, 2018 at 11:22:36AM +1000, NeilBrown wrote:
> On Mon, May 07 2018, James Hogan wrote:
>
> > On Mon, May 07, 2018 at 07:40:49AM +1000, NeilBrown wrote:
> >>
> >> Hi James,
> >> this hasn't appear in linux-next yet, or in any branch
&
On Wed, Mar 28, 2018 at 05:38:12PM +0200, Paul Cercueil wrote:
> The debug definitions were missing for MACH_JZ4770, resulting in a build
> failure when DEBUG_ZBOOT was set.
>
> Since the UART addresses are the same across all Ingenic SoCs, we just
> use a #ifdef CONFIG_MACH_INGENIC instead of che
On Fri, May 11, 2018 at 02:14:16PM -0700, Guenter Roeck wrote:
> On Fri, May 11, 2018 at 09:54:14PM +0100, James Hogan wrote:
> > On Fri, May 11, 2018 at 01:17:04PM -0300, Paul Cercueil wrote:
> > > Le 11 mai 2018 11:52, James Hogan a écrit :
> > > > Otherwise
On Fri, May 11, 2018 at 01:17:04PM -0300, Paul Cercueil wrote:
> Le 11 mai 2018 11:52, James Hogan a écrit :
> > Otherwise
> > Acked-by: James Hogan
> >
> > I'm happy to apply for 4.18 with that change if you want it to go
> > through the MIPS tree.
he subject says since thats
meant to summarise the body.
> -struct platform_device jz4740_wdt_device = {
There's an extern in arch/mips/include/asm/mach-jz4740/platform.h that
should perhaps be removed also?
Otherwise
Acked-by: James Hogan
I'm happy to apply for 4.18 with that chang
On Thu, May 10, 2018 at 05:59:00PM +0100, Colin King wrote:
> From: Colin Ian King
>
> Trivial fix to spelling mistake in pr_warn message text
>
> Signed-off-by: Colin Ian King
> - pr_warn("VPE loader: elf size too big. Perhaps strip uneeded
> symbols\n");
> + pr_warn(
On Mon, May 07, 2018 at 05:28:27PM +0800, Baolin Wang wrote:
> Since struct timespec is not y2038 safe on 32bit machines, this patch
> converts read_persistent_clock() to read_persistent_clock64() using
> struct timespec64, as well as converting mktime() to mktime64().
>
> Signed-off-by: Baolin Wa
On Thu, Apr 19, 2018 at 03:21:06PM +0800, Baolin Wang wrote:
> The dummy read_persistent_clock() uses a timespec, which is not year 2038
> safe on 32bit systems. Thus remove this obsolete interface.
>
> Signed-off-by: Baolin Wang
Thanks, Applied for 4.18
Cheers
James
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On Mon, May 07, 2018 at 07:40:49AM +1000, NeilBrown wrote:
>
> Hi James,
> this hasn't appear in linux-next yet, or in any branch
> of
>git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/mips.git
>
> Should I expect it to?
Sorry Neil, I haven't applied it yet. I'm planning to get a few
On Sun, May 06, 2018 at 12:33:21PM -0700, Matt Turner wrote:
> On Tue, Apr 17, 2018 at 3:11 AM, James Hogan wrote:
> > Use CONFIG_ARCH_SUPPORTS_OPTIMIZED_INLINING and CONFIG_OPTIMIZE_INLINING
> > instead of undefining the inline macros in the alpha specific
> > asm/compile
On Thu, May 03, 2018 at 06:40:07PM -0400, Arnd Bergmann wrote:
> On Wed, May 2, 2018 at 5:51 PM, James Hogan wrote:
>
> > Due to the binary incompatibility between previous MIPS architecture
> > generations and nanoMIPS, and the significantly revamped compiler ABI,
> >
rton, James Hogan, Matt Redfearn, Marcin Nowakowski
[1]
https://www.mips.com/press/new-mips-i7200-processor-core-delivers-unmatched-performance-and-efficiency-for-advanced-lte5g-communications-and-networking-ic-designs/
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On Thu, Apr 26, 2018 at 08:00:18AM +1000, NeilBrown wrote:
> On Wed, Apr 25 2018, James Hogan wrote:
> > So I'm thinking "!mips_cm_present()" should probably be replaced with
> > "!r4k_op_needs_ipi(R4K_INDEX)" (and the comment updated to mention th
Hi NeilBrown,
On Wed, Apr 25, 2018 at 02:08:15PM +1000, NeilBrown wrote:
> Cc: sta...@vger.kernel.org (v4.8)
FYI my preferred form of this is:
Cc: # 4.8+
> /*
>* Either no secondary cache or the available caches don't have the
>* subset property so we have to flush the pr
On Tue, Apr 24, 2018 at 01:55:54PM +0100, Matt Redfearn wrote:
> Since it appears that MIPS oprofile support is currently broken, core
> oprofile is not getting many updates and not as many architectures
> implement support for it compared to perf, remove the MIPS support.
That sounds reasonable t
ady contained in
> a2, the andi placing a value in v1 is not necessary and actively
> harmful in clobbering v1.
>
> Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2")
> Cc: sta...@vger.kernel.org
> Reported-by: James Hogan
> Signed-off-by: Matt Redfearn
Thanks, Patches 1 & 2 applied to my fixes branch.
Cheers
James
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On Thu, Apr 12, 2018 at 10:36:21AM +0100, Matt Redfearn wrote:
> Processors implementing the MIPS MT ASE may have performance counters
> implemented per core or per TC. Processors implemented by MIPS
> Technologies signify presence per TC through a bit in the implementation
> specific Config7 regis
On Sun, Apr 08, 2018 at 10:57:32PM +0200, Rafał Miłecki wrote:
> From: Rafał Miłecki
>
> This adds support for detecting this model board and registers some LEDs
> and buttons.
>
> There are two uncommon things regarding this device:
> 1) It can use two different "board_id" ID values.
>Unit
On Wed, Apr 11, 2018 at 08:50:18AM +0100, Matt Redfearn wrote:
> diff --git a/arch/mips/boot/compressed/Makefile
> b/arch/mips/boot/compressed/Makefile
> index adce180f3ee4..e03f522c33ac 100644
> --- a/arch/mips/boot/compressed/Makefile
> +++ b/arch/mips/boot/compressed/Makefile
> @@ -46,9 +46,12
On Tue, Apr 17, 2018 at 12:41:30AM +0900, Masahiro Yamada wrote:
> arch/mips/boot/dts/Makefile collects objects from sub-directories
> into built-in.a only when CONFIG_BUILTIN_DTB is enabled. Reflect
> it also to the sub-directory Makefiles. This suppresses unneeded
> built-in.a creation in arch/
Hi kbuild test robot,
On Wed, Apr 18, 2018 at 03:19:47AM +0800, kbuild test robot wrote:
>In file included from ./arch/x86/include/generated/asm/compiler.h:1:0,
> from include/linux/compiler_types.h:58,
> from :0:
> >> include/asm-generic/compiler.h:2:2:
%d) returned %d\n", j, k);
> }
> }
> Which now passes on Creator Ci40 (MIPS32) and Cavium Octeon II (MIPS64).
>
> Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2")
> Cc: sta...@vger.kernel.org
> Suggested-by: James Hogan
> Signed-off-by: Matt Redfearn
Applied, thanks
James
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348 --348
Total: Before=5823709, After=5823625, chg -0.00%
Cc: Arnd Bergmann
Cc: Richard Henderson
Cc: Ivan Kokshaysky
Cc: Matt Turner
Cc: Ralf Baechle
Cc: Paul Burton
Cc: Matthew Fortune
Cc: Robert Suchanek
Cc: linux-al...@vger.kernel.org
Cc: linux-m...@linux-mips.org
Cc: linux-a.
ead of
asm/compiler-gcc.h]
Signed-off-by: James Hogan
Reviewed-by: Paul Burton
Cc: Matthew Fortune
Cc: Robert Suchanek
Cc: Ralf Baechle
Cc: Arnd Bergmann
Cc: linux-m...@linux-mips.org
---
This is an alternative approach to this earlier patch which seems to
have been rejected:
https://patc
344 +16
cap_capset 488 500 +12
nonroot_raised_pE.constprop 348 --348
Total: Before=5823709, After=5823625, chg -0.00%
Suggested-by: Arnd Bergmann
Signed-off-by: James Hogan
Cc: Richard Henderson
Cc: Ivan Kokshaysky
Cc:
all architectures except alpha, arm, arm64, and mips
(which already have an asm/compiler.h) and leaves the architecture
specifics to a further patch.
Signed-off-by: Paul Burton
[jho...@kernel.org: Forward port and use asm/compiler.h instead of
asm/compiler-gcc.h]
Signed-off-by: James Hogan
On Thu, Mar 29, 2018 at 10:28:24AM +0100, Matt Redfearn wrote:
> The __clear_user function is defined to return the number of bytes that
> could not be cleared. From the underlying memset / bzero implementation
> this means setting register a2 to that number on return. Currently if a
> page fault i
On Thu, Mar 29, 2018 at 10:28:23AM +0100, Matt Redfearn wrote:
> @@ -260,6 +260,11 @@
> jr ra
> andiv1, a2, STORMASK
This patch looks good, well spotted!
But whats that v1 write about? Any ideas? Seems to go back to the git
epoch, and $3 isn't in the clobber l
On Thu, Apr 12, 2018 at 10:33:42PM -0400, Sinan Kaya wrote:
> On 4/12/2018 10:30 PM, Sinan Kaya wrote:
> > + /* prevent prefetching of coherent DMA dma prematurely */ \
>
> I tried to write DMA data but my keyboard is not cooperating. I'll hold onto
> posting another version until I hear b
On Thu, Apr 12, 2018 at 10:51:49PM +0100, James Hogan wrote:
> On Tue, Apr 03, 2018 at 08:55:04AM -0400, Sinan Kaya wrote:
> > While a barrier is present in writeX() function before the register write,
> > a similar barrier is missing in the readX() function after the register
>
On Tue, Apr 03, 2018 at 08:55:04AM -0400, Sinan Kaya wrote:
> While a barrier is present in writeX() function before the register write,
> a similar barrier is missing in the readX() function after the register
> read. This could allow memory accesses following readX() to observe
> stale data.
>
>
On Wed, Apr 11, 2018 at 01:10:41PM -0400, Sinan Kaya wrote:
> How is the likelihood of getting this fixed on 4.17 kernel?
High.
Thanks
James
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On Wed, Apr 11, 2018 at 12:08:51PM +0200, Arnd Bergmann wrote:
> On Wed, Apr 11, 2018 at 11:54 AM, James Hogan wrote:
> > On Wed, Apr 11, 2018 at 09:30:56AM +0200, Arnd Bergmann wrote:
> >> On Wed, Apr 11, 2018 at 12:48 AM, James Hogan wrote:
> >> > Before I for
On Wed, Apr 11, 2018 at 09:30:56AM +0200, Arnd Bergmann wrote:
> On Wed, Apr 11, 2018 at 12:48 AM, James Hogan wrote:
> > Before I forward port those patches to add .insn for MIPS, is that sort
> > of approach (an arch specific asm/compiler-gcc.h to allow MIPS
Hi Arnd,
On Tue, Dec 19, 2017 at 12:39:33PM +0100, Arnd Bergmann wrote:
> diff --git a/include/linux/compiler-gcc.h b/include/linux/compiler-gcc.h
> index 5d595cfdb2c4..66cfdad68f7e 100644
> --- a/include/linux/compiler-gcc.h
> +++ b/include/linux/compiler-gcc.h
> @@ -205,6 +205,15 @@
> #endif
>
On Mon, Apr 09, 2018 at 12:25:09AM +, Sasha Levin wrote:
> From: Paul Burton
>
> [ Upstream commit f39878cc5b09c75d35eaf52131e920b872e3feb4 ]
>
> In systems where there are multiple actors updating the TLB, the
> potential exists for a race condition wherein a CPU hits a TLB exception
> but
On Mon, Apr 09, 2018 at 12:24:58AM +, Sasha Levin wrote:
> From: David Daney
>
> [ Upstream commit 669c4092225f0ed5df12ebee654581b558a5e3ed ]
>
> KProbes of __seccomp_filter() are not very useful without access to
> the syscall arguments.
>
> Do what x86 does, and populate a struct seccomp_
On Mon, Apr 09, 2018 at 12:17:24AM +, Sasha Levin wrote:
> From: Paul Cercueil
>
> [ Upstream commit e6cfa64375d34a6c8c1861868a381013b2d3b921 ]
>
> Previously, the clocks with a fixed divider would report their rate
> as being the same as the one of their parent, independently of the
> divid
On Mon, Apr 09, 2018 at 12:20:20AM +, Sasha Levin wrote:
> From: Maarten ter Huurne
>
> [ Upstream commit 1f7412e0e2f327fe7dc5a0c2fc36d7b319d05d47 ]
>
> According to config2, the associativity would be 5-ways, but the
> documentation states 4-ways, which also matches the documented
> L2 cach
Hi Sasha,
On Mon, Apr 09, 2018 at 12:20:18AM +, Sasha Levin wrote:
> From: James Hogan
>
> [ Upstream commit 5f2483eb2423152445b39f2db59d372f523e664e ]
>
> Make doesn't expand shell style "vmlinuz.{32,ecoff,bin,srec}" to the 4
> separate files, so none of t
On Thu, Apr 05, 2018 at 10:42:19PM +0100, James Hogan wrote:
> On Thu, Apr 05, 2018 at 11:13:14AM +0100, Matt Redfearn wrote:
> > Actually, this patch would be better inserted as patch 3 in the series
> > since it can pull in the generic ashldi3 before the MIPS one is removed
&
On Fri, Apr 06, 2018 at 02:15:57PM -0400, Sinan Kaya wrote:
> On 4/5/2018 9:34 PM, Sinan Kaya wrote:
> > Can we get these merged to 4.17?
> >
> > There was a consensus to fix the architectures having API violation issues.
> > https://www.mail-archive.com/netdev@vger.kernel.org/msg225971.html
> >
On Thu, Apr 05, 2018 at 11:13:14AM +0100, Matt Redfearn wrote:
> Actually, this patch would be better inserted as patch 3 in the series
> since it can pull in the generic ashldi3 before the MIPS one is removed
> in the final patch. Here's an updated commit message:
Thanks Matt, applied.
Cheers
On Tue, Apr 03, 2018 at 03:39:34PM -0700, Palmer Dabbelt wrote:
> Sorry, I'm not sure if this is the right patch -- someone suggested acking
> this, but it's already Review-By me and if I understand correctly it's going
> through your tree. I'm a bit new to this, but if it helps then here's a
>
On Wed, Apr 04, 2018 at 10:38:41AM +0200, Arnd Bergmann wrote:
> Also, now that the other architectures are gone, a lot of changes can
> be done more easily that will be incompatible with a pure revert, so
> the more time passes, the harder it will get to do that.
Yes, and an out-of-tree arch port
commit removes several generic GCC library routines from
> arch/mips/lib/ in favour of similar routines from lib/.
>
> Signed-off-by: Antony Pavlov
> [Matt Redfearn] Use GENERIC_LIB_* named Kconfig entries
> Signed-off-by: Matt Redfearn
> Cc: Palmer Dabbelt
> Cc: Matt R
On Tue, Apr 03, 2018 at 02:51:06PM +0100, Matt Redfearn wrote:
> On 29/03/18 22:59, Palmer Dabbelt wrote:
> > Ah, thanks, I think I must have forgotten about this. I assume these
> > three are going through your tree?
>
> Yeah I think that's the plan - James will need your ack to patch 2 if
> t
On Thu, Mar 29, 2018 at 11:41:23AM +0100, Matt Redfearn wrote:
> This commit removes several generic GCC library routines from
> arch/mips/lib/ in favour of similar routines from lib/.
> diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile
> index e84e12655fa8..6537e022ef62 100644
> --- a/
rt = (unsigned long)(&__image_begin);
> zimage_size = (unsigned long)(&__image_end) -
> (unsigned long)(&__image_begin);
This looks good to me, though I've Cc'd Kees as apparently the original
author from commit 8779657d29c0 ("stackprotector: Introduce
CONF
On Fri, Mar 23, 2018 at 11:50:55AM +0800, Jiaxun Yang wrote:
> 在 2018-03-22四的 22:21 +0000，James Hogan写道：
> > Also I think it worth mentioning in the commit message the MIPS
> > configuration you hit this with, presumably a Loongson one? For me
> > decompress_kernel()
On Fri, Mar 16, 2018 at 03:55:16PM +0800, Huacai Chen wrote:
> diff --git a/arch/mips/boot/compressed/decompress.c
> b/arch/mips/boot/compressed/decompress.c
> index fdf99e9..5ba431c 100644
> --- a/arch/mips/boot/compressed/decompress.c
> +++ b/arch/mips/boot/compressed/decompress.c
> @@ -78,11 +7
On Wed, Mar 21, 2018 at 10:53:03PM +0800, Jiaxun Yang wrote:
> Some processors support user mode instructions ISA level witch is
nit: s/witch/which/ here, below, and in the comment.
Otherwise it doesn't look unreasonable.
Cheers
James
> different with the ISA level it should be treated in kerne
On Wed, Mar 21, 2018 at 10:53:04PM +0800, Jiaxun Yang wrote:
> All loongson-3 processors support mips64r2 usermode instructions.
> However 3A1000 3B1000 3B1500 should be treated as mips64r1 in kernel.
>
> Signed-off-by: Jiaxun Yang
> ---
> arch/mips/include/asm/mach-loongson64/cpu-feature-overri
On Sat, Mar 17, 2018 at 09:11:09PM +0100, Paul Cercueil wrote:
> Since the UART addresses are the same across all Ingenic SoCs, we just
> use a #ifdef CONFIG_MACH_INGENIC instead of checking for indifidual
> Ingenic SoCs.
s/indifidual/individual/
> --- a/arch/mips/boot/compressed/uart-16550.c
> +
On Wed, Mar 21, 2018 at 02:02:10PM +1100, NeilBrown wrote:
>
> Since commit 3af5a67c86a3 ("MIPS: Fix early CM probing") the MT7621
> has not been able to boot.
>
> This patched caused mips_cm_probe() to be called before
> mt7621.c::proc_soc_init().
>
> prom_soc_init() has a comment explaining th
On Tue, Mar 20, 2018 at 07:29:51PM +1100, NeilBrown wrote:
>
> ralink_halt() does nothing that machine_halt()
> doesn't already do, so it adds no value.
>
> It actually causes incorrect behaviour due to the
> "unreachable()" at the end. This tell the compiler that the
> end of the function will
On Tue, Mar 20, 2018 at 02:07:55PM +0100, Alexandre Belloni wrote:
> Hi,
>
> This patch series adds initial support for the Microsemi MIPS SoCs. It
> is currently focusing on the Microsemi Ocelot (VSC7513, VSC7514).
>
> Changes in v6:
> - Fixup SPDX identifiers
> - remove unit-address for cpuin
On Wed, Mar 14, 2018 at 11:15:47AM +, Marc Zyngier wrote:
> Hi Matt,
>
> On 05/01/18 10:31, Matt Redfearn wrote:
> >
> > This series enables the MIPS GIC driver to make use of the EIC mode
> > supported in some MIPS cores. In this mode, the cores 6 interrupt lines
> > are switched to represen
On Tue, Jan 23, 2018 at 05:40:09PM -0800, Florian Fainelli wrote:
> @@ -71,15 +83,19 @@ static inline void plat_post_dma_flush(struct device *dev)
> #endif
>
> #ifdef CONFIG_SWIOTLB
> +#ifndef phys_to_dma
> static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
> {
>
On Tue, Jan 23, 2018 at 05:40:10PM -0800, Florian Fainelli wrote:
> diff --git a/arch/mips/include/asm/mach-ath25/dma-coherence.h
> b/arch/mips/include/asm/mach-ath25/dma-coherence.h
> index d5defdde32db..63bce15fa54d 100644
> --- a/arch/mips/include/asm/mach-ath25/dma-coherence.h
> +++ b/arch/mip
On Wed, Feb 14, 2018 at 09:36:33PM +, Keller, Jacob E wrote:
> > -Original Message-
> > From: Michael, Alice
> > Sent: Wednesday, February 14, 2018 1:03 PM
> > To: Guenter Roeck ; James Hogan ;
> > Keller, Jacob E
> > Cc: Ralf Baechle ; linux
On Mon, Jan 15, 2018 at 06:28:38PM -0500, Jim Quinlan wrote:
> From: Florian Fainelli
>
> This commit adds a memory API suitable for ascertaining the sizes of
> each of the N memory controllers in a Broadcom STB chip. Its first
> user will be the Broadcom STB PCIe root complex driver, which need
On Mon, Jan 15, 2018 at 06:28:44PM -0500, Jim Quinlan wrote:
> diff --git a/arch/mips/boot/dts/brcm/bcm7425.dtsi
> b/arch/mips/boot/dts/brcm/bcm7425.dtsi
> index e4fb9b6..02168d0 100644
> --- a/arch/mips/boot/dts/brcm/bcm7425.dtsi
> +++ b/arch/mips/boot/dts/brcm/bcm7425.dtsi
> @@ -495,4 +495,30 @@
On Tue, Feb 20, 2018 at 09:58:16AM +, Matt Redfearn wrote:
> If a JTAG probe is connected to a MIPS cluster, then the CPC detects it
> and latches the CPC.STAT_CONF.EJTAG_PROBE bit to 1. While set,
> attempting to send a power-down command to a core will be blocked, and
> the CPC will instead s
On Mon, Feb 26, 2018 at 05:02:41PM +, Matt Redfearn wrote:
> There are multiple instances in the kernel where we need to include or
> exclude particular instructions based on the ISA revision of the target
> processor. For MIPS32 / MIPS64, the compiler exports a __mips_isa_rev
> define. However
admittedly shouldn't really build all the dtb.o files, but thats a
separate issue).
Fixes: 695835511f96 ("MIPS: BMIPS: rename bcm96358nb4ser to
bcm6358-neufbox4-sercom")
Signed-off-by: James Hogan
Reviewed-by: Frank Rowand
Cc: Rob Herring
Cc: Masahiro Yamada
Cc: Michal Marek
Cc: Ral
On Wed, Mar 07, 2018 at 03:19:11PM -0800, Frank Rowand wrote:
> On 03/07/18 12:25, James Hogan wrote:
> > On Wed, Mar 07, 2018 at 12:11:41PM -0800, Frank Rowand wrote:
> >> On 03/07/18 06:06, James Hogan wrote:
> >>> Quite a lot of dts files have hyphens, but its only
Hi Rob,
On Wed, Mar 07, 2018 at 10:08:28AM -0600, Rob Herring wrote:
> Please compile with W=1 and fix any issues like this one which is a
> unit-address without a reg property. Drop the unit-address.
I was just giving the BMIPS W=1 DT warnings a look, and a few look
spurious. I'd value your opin
On Wed, Mar 07, 2018 at 12:11:41PM -0800, Frank Rowand wrote:
> I initially misread the patch description (and imagined an entirely
> different problem).
>
>
> On 03/07/18 06:06, James Hogan wrote:
> > On dtb files which contain hyphens, the dt_S_dtb command to build the>
On Wed, Mar 07, 2018 at 04:27:51PM +0100, Alexandre Belloni wrote:
> On 07/03/2018 at 15:17:56 +0000, James Hogan wrote:
> > On Tue, Mar 06, 2018 at 01:16:04PM +0100, Alexandre Belloni wrote:
> > > diff --git a/arch/mips/boot/dts/mscc/ocelot.dtsi
> > > b/arch/mip
On Tue, Mar 06, 2018 at 01:16:06PM +0100, Alexandre Belloni wrote:
> diff --git a/arch/mips/Makefile b/arch/mips/Makefile
> index d1ca839c3981..d2882244cf1f 100644
> --- a/arch/mips/Makefile
> +++ b/arch/mips/Makefile
> @@ -543,6 +543,10 @@ generic_defconfig:
> # now that the boards have been conv
On Tue, Mar 06, 2018 at 01:16:04PM +0100, Alexandre Belloni wrote:
> diff --git a/arch/mips/boot/dts/mscc/ocelot.dtsi
> b/arch/mips/boot/dts/mscc/ocelot.dtsi
> new file mode 100644
> index ..8c3210577410
> --- /dev/null
> +++ b/arch/mips/boot/dts/mscc/ocelot.dtsi
> @@ -0,0 +1,117 @@
>
On Wed, Mar 07, 2018 at 08:35:00PM +0530, PrasannaKumar Muralidharan wrote:
> On 7 March 2018 at 20:05, James Hogan wrote:
> > On Wed, Mar 07, 2018 at 07:14:49PM +0530, PrasannaKumar Muralidharan wrote:
> >> > Does X1000 use a different PRID, or is it basically just a JZ
On Wed, Mar 07, 2018 at 07:14:49PM +0530, PrasannaKumar Muralidharan wrote:
> > Does X1000 use a different PRID, or is it basically just a JZ4780 core
> > with different SoC peripherals?
>
> Yes X1000 does have a different PRID (PRID = 0x2ed1024f). X1000 has
Right, so thats 0x2e00 | PRID_COMP
a separate issue).
Fixes: 695835511f96 ("MIPS: BMIPS: rename bcm96358nb4ser to
bcm6358-neufbox4-sercom")
Signed-off-by: James Hogan
Cc: Rob Herring
Cc: Frank Rowand
Cc: Masahiro Yamada
Cc: Michal Marek
Cc: Ralf Baechle
Cc: Florian Fainelli
Cc: Kevin Cernekee
Cc: devic
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