t/compressed/uart-16550.c needs updating for JZ4770 like
commit ba9e72c2290f ("MIPS: Fix build with DEBUG_ZBOOT and MACH_JZ4780")
does for JZ4780.
Otherwise the non-DT bits look reasonable (I've not really looked
properly at the DT):
Reviewed-by: James Hogan
Cheers
James
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On Wed, Nov 29, 2017 at 05:38:19PM +0100, Alexandre Belloni wrote:
> Hi Paul,
>
> On 28/11/2017 at 11:50:02 -0800, Paul Burton wrote:
> > On Tue, Nov 28, 2017 at 05:31:51PM +0000, James Hogan wrote:
> > > On Tue, Nov 28, 2017 at 05:53:59PM +0100, Alexandre Belloni wrote:
On Sun, Jan 07, 2018 at 08:12:16PM -0800, Guenter Roeck wrote:
> On Sun, Jan 07, 2018 at 09:50:31AM +0100, Michal Hocko wrote:
> > On Sat 06-01-18 17:07:33, Guenter Roeck wrote:
> > > The following build error is seen when building metag:meta2_defconfig
> > > or metag:tz1090_defconfig.
> > >
> > >
configuration.
But yes clearly the mentioned commit does also expose that existing
problem more widely and to the default allmodconfig, and it looks like a
reasonable approach for now, so if some mention of the other two commits
is added:
Reviewed-by: James Hogan
Having it in 4.15 would be great.
Chee
On Mon, Jan 15, 2018 at 12:05:48PM -0800, Guenter Roeck wrote:
> On 01/15/2018 09:10 AM, Paul Burton wrote:
> > Hello,
> >
> > On Mon, Jan 15, 2018 at 10:23:37AM +, James Hogan wrote:
> >> On Sun, Jan 14, 2018 at 01:34:02PM -0800, Guenter Roeck wrote:
> &g
dfish: Add RTC driver for Android emulator")
Signed-off-by: James Hogan
Cc: Miodrag Dinic
Cc: Alessandro Zummo
Cc: Alexandre Belloni
Cc: linux-...@vger.kernel.org
---
drivers/rtc/rtc-goldfish.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/rtc/rtc-goldfish.c b/drive
On Wed, Feb 14, 2018 at 09:36:33PM +, Keller, Jacob E wrote:
> > -Original Message-
> > From: Michael, Alice
> > Sent: Wednesday, February 14, 2018 1:03 PM
> > To: Guenter Roeck ; James Hogan ;
> > Keller, Jacob E
> > Cc: Ralf Baechle ; linux
/devicetree/bindings/watchdog/ingenic,jz4740-wdt.txt be
updated too?
Regardless,
Acked-by: James Hogan
Cheers
James
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ts the case.
>
> This commit enables the Kconfig option in the qi_lb60 defconfig.
>
> Signed-off-by: Paul Cercueil
The change looks good to me though
Acked-by: James Hogan
Cheers
James
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On Sat, Dec 30, 2017 at 02:51:08PM +0100, Paul Cercueil wrote:
> This work is now performed by the watchdog driver directly.
>
> Signed-off-by: Paul Cercueil
Acked-by: James Hogan
Cheers
James
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On Thu, Nov 23, 2017 at 10:49:55PM +0100, Vasyl Gomonovych wrote:
> Add the missing iounmap() before put_device and
> return from txx9_sramc_init().
>
> Signed-off-by: Vasyl Gomonovych
> ---
> arch/mips/txx9/generic/setup.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/mips/tx
On Wed, Sep 27, 2017 at 08:45:26PM +0530, PrasannaKumar Muralidharan wrote:
> Add initial Ingenic X1000 SoC support. Provide minimum necessary
> information to boot kernel to an initramfs userspace.
>
> Signed-off-by: PrasannaKumar Muralidharan
> ---
> arch/mips/boot/dts/ingenic/x1000.dtsi | 93
a separate issue).
Fixes: 695835511f96 ("MIPS: BMIPS: rename bcm96358nb4ser to
bcm6358-neufbox4-sercom")
Signed-off-by: James Hogan
Cc: Rob Herring
Cc: Frank Rowand
Cc: Masahiro Yamada
Cc: Michal Marek
Cc: Ralf Baechle
Cc: Florian Fainelli
Cc: Kevin Cernekee
Cc: devic
On Wed, Mar 07, 2018 at 07:14:49PM +0530, PrasannaKumar Muralidharan wrote:
> > Does X1000 use a different PRID, or is it basically just a JZ4780 core
> > with different SoC peripherals?
>
> Yes X1000 does have a different PRID (PRID = 0x2ed1024f). X1000 has
Right, so thats 0x2e00 | PRID_COMP
On Wed, Mar 07, 2018 at 08:35:00PM +0530, PrasannaKumar Muralidharan wrote:
> On 7 March 2018 at 20:05, James Hogan wrote:
> > On Wed, Mar 07, 2018 at 07:14:49PM +0530, PrasannaKumar Muralidharan wrote:
> >> > Does X1000 use a different PRID, or is it basically just a JZ
On Tue, Mar 06, 2018 at 01:16:04PM +0100, Alexandre Belloni wrote:
> diff --git a/arch/mips/boot/dts/mscc/ocelot.dtsi
> b/arch/mips/boot/dts/mscc/ocelot.dtsi
> new file mode 100644
> index ..8c3210577410
> --- /dev/null
> +++ b/arch/mips/boot/dts/mscc/ocelot.dtsi
> @@ -0,0 +1,117 @@
>
On Tue, Mar 06, 2018 at 01:16:06PM +0100, Alexandre Belloni wrote:
> diff --git a/arch/mips/Makefile b/arch/mips/Makefile
> index d1ca839c3981..d2882244cf1f 100644
> --- a/arch/mips/Makefile
> +++ b/arch/mips/Makefile
> @@ -543,6 +543,10 @@ generic_defconfig:
> # now that the boards have been conv
On Wed, Mar 07, 2018 at 04:27:51PM +0100, Alexandre Belloni wrote:
> On 07/03/2018 at 15:17:56 +0000, James Hogan wrote:
> > On Tue, Mar 06, 2018 at 01:16:04PM +0100, Alexandre Belloni wrote:
> > > diff --git a/arch/mips/boot/dts/mscc/ocelot.dtsi
> > > b/arch/mip
On Wed, Mar 07, 2018 at 12:11:41PM -0800, Frank Rowand wrote:
> I initially misread the patch description (and imagined an entirely
> different problem).
>
>
> On 03/07/18 06:06, James Hogan wrote:
> > On dtb files which contain hyphens, the dt_S_dtb command to build the>
Hi Rob,
On Wed, Mar 07, 2018 at 10:08:28AM -0600, Rob Herring wrote:
> Please compile with W=1 and fix any issues like this one which is a
> unit-address without a reg property. Drop the unit-address.
I was just giving the BMIPS W=1 DT warnings a look, and a few look
spurious. I'd value your opin
On Fri, Mar 23, 2018 at 11:50:55AM +0800, Jiaxun Yang wrote:
> 在 2018-03-22四的 22:21 +0000，James Hogan写道：
> > Also I think it worth mentioning in the commit message the MIPS
> > configuration you hit this with, presumably a Loongson one? For me
> > decompress_kernel()
On Thu, Apr 05, 2018 at 11:13:14AM +0100, Matt Redfearn wrote:
> Actually, this patch would be better inserted as patch 3 in the series
> since it can pull in the generic ashldi3 before the MIPS one is removed
> in the final patch. Here's an updated commit message:
Thanks Matt, applied.
Cheers
On Fri, Apr 06, 2018 at 02:15:57PM -0400, Sinan Kaya wrote:
> On 4/5/2018 9:34 PM, Sinan Kaya wrote:
> > Can we get these merged to 4.17?
> >
> > There was a consensus to fix the architectures having API violation issues.
> > https://www.mail-archive.com/netdev@vger.kernel.org/msg225971.html
> >
On Thu, Apr 05, 2018 at 10:42:19PM +0100, James Hogan wrote:
> On Thu, Apr 05, 2018 at 11:13:14AM +0100, Matt Redfearn wrote:
> > Actually, this patch would be better inserted as patch 3 in the series
> > since it can pull in the generic ashldi3 before the MIPS one is removed
&
On Wed, Apr 11, 2018 at 09:30:56AM +0200, Arnd Bergmann wrote:
> On Wed, Apr 11, 2018 at 12:48 AM, James Hogan wrote:
> > Before I forward port those patches to add .insn for MIPS, is that sort
> > of approach (an arch specific asm/compiler-gcc.h to allow MIPS
On Wed, Apr 11, 2018 at 12:08:51PM +0200, Arnd Bergmann wrote:
> On Wed, Apr 11, 2018 at 11:54 AM, James Hogan wrote:
> > On Wed, Apr 11, 2018 at 09:30:56AM +0200, Arnd Bergmann wrote:
> >> On Wed, Apr 11, 2018 at 12:48 AM, James Hogan wrote:
> >> > Before I for
On Wed, Apr 11, 2018 at 01:10:41PM -0400, Sinan Kaya wrote:
> How is the likelihood of getting this fixed on 4.17 kernel?
High.
Thanks
James
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On Tue, Apr 03, 2018 at 08:55:04AM -0400, Sinan Kaya wrote:
> While a barrier is present in writeX() function before the register write,
> a similar barrier is missing in the readX() function after the register
> read. This could allow memory accesses following readX() to observe
> stale data.
>
>
On Thu, Apr 12, 2018 at 10:51:49PM +0100, James Hogan wrote:
> On Tue, Apr 03, 2018 at 08:55:04AM -0400, Sinan Kaya wrote:
> > While a barrier is present in writeX() function before the register write,
> > a similar barrier is missing in the readX() function after the register
>
On Tue, Mar 20, 2018 at 02:07:55PM +0100, Alexandre Belloni wrote:
> Hi,
>
> This patch series adds initial support for the Microsemi MIPS SoCs. It
> is currently focusing on the Microsemi Ocelot (VSC7513, VSC7514).
>
> Changes in v6:
> - Fixup SPDX identifiers
> - remove unit-address for cpuin
On Tue, Mar 20, 2018 at 07:29:51PM +1100, NeilBrown wrote:
>
> ralink_halt() does nothing that machine_halt()
> doesn't already do, so it adds no value.
>
> It actually causes incorrect behaviour due to the
> "unreachable()" at the end. This tell the compiler that the
> end of the function will
On Wed, Mar 21, 2018 at 02:02:10PM +1100, NeilBrown wrote:
>
> Since commit 3af5a67c86a3 ("MIPS: Fix early CM probing") the MT7621
> has not been able to boot.
>
> This patched caused mips_cm_probe() to be called before
> mt7621.c::proc_soc_init().
>
> prom_soc_init() has a comment explaining th
On Sat, Mar 17, 2018 at 09:11:09PM +0100, Paul Cercueil wrote:
> Since the UART addresses are the same across all Ingenic SoCs, we just
> use a #ifdef CONFIG_MACH_INGENIC instead of checking for indifidual
> Ingenic SoCs.
s/indifidual/individual/
> --- a/arch/mips/boot/compressed/uart-16550.c
> +
On Wed, Mar 21, 2018 at 10:53:04PM +0800, Jiaxun Yang wrote:
> All loongson-3 processors support mips64r2 usermode instructions.
> However 3A1000 3B1000 3B1500 should be treated as mips64r1 in kernel.
>
> Signed-off-by: Jiaxun Yang
> ---
> arch/mips/include/asm/mach-loongson64/cpu-feature-overri
On Wed, Mar 21, 2018 at 10:53:03PM +0800, Jiaxun Yang wrote:
> Some processors support user mode instructions ISA level witch is
nit: s/witch/which/ here, below, and in the comment.
Otherwise it doesn't look unreasonable.
Cheers
James
> different with the ISA level it should be treated in kerne
On Fri, Mar 16, 2018 at 03:55:16PM +0800, Huacai Chen wrote:
> diff --git a/arch/mips/boot/compressed/decompress.c
> b/arch/mips/boot/compressed/decompress.c
> index fdf99e9..5ba431c 100644
> --- a/arch/mips/boot/compressed/decompress.c
> +++ b/arch/mips/boot/compressed/decompress.c
> @@ -78,11 +7
Hi Sasha,
On Mon, Apr 09, 2018 at 12:20:18AM +, Sasha Levin wrote:
> From: James Hogan
>
> [ Upstream commit 5f2483eb2423152445b39f2db59d372f523e664e ]
>
> Make doesn't expand shell style "vmlinuz.{32,ecoff,bin,srec}" to the 4
> separate files, so none of t
On Mon, Apr 09, 2018 at 12:20:20AM +, Sasha Levin wrote:
> From: Maarten ter Huurne
>
> [ Upstream commit 1f7412e0e2f327fe7dc5a0c2fc36d7b319d05d47 ]
>
> According to config2, the associativity would be 5-ways, but the
> documentation states 4-ways, which also matches the documented
> L2 cach
On Mon, Apr 09, 2018 at 12:17:24AM +, Sasha Levin wrote:
> From: Paul Cercueil
>
> [ Upstream commit e6cfa64375d34a6c8c1861868a381013b2d3b921 ]
>
> Previously, the clocks with a fixed divider would report their rate
> as being the same as the one of their parent, independently of the
> divid
On Mon, Apr 09, 2018 at 12:24:58AM +, Sasha Levin wrote:
> From: David Daney
>
> [ Upstream commit 669c4092225f0ed5df12ebee654581b558a5e3ed ]
>
> KProbes of __seccomp_filter() are not very useful without access to
> the syscall arguments.
>
> Do what x86 does, and populate a struct seccomp_
On Mon, Apr 09, 2018 at 12:25:09AM +, Sasha Levin wrote:
> From: Paul Burton
>
> [ Upstream commit f39878cc5b09c75d35eaf52131e920b872e3feb4 ]
>
> In systems where there are multiple actors updating the TLB, the
> potential exists for a race condition wherein a CPU hits a TLB exception
> but
Hi Arnd,
On Tue, Dec 19, 2017 at 12:39:33PM +0100, Arnd Bergmann wrote:
> diff --git a/include/linux/compiler-gcc.h b/include/linux/compiler-gcc.h
> index 5d595cfdb2c4..66cfdad68f7e 100644
> --- a/include/linux/compiler-gcc.h
> +++ b/include/linux/compiler-gcc.h
> @@ -205,6 +205,15 @@
> #endif
>
On Wed, Mar 07, 2018 at 03:19:11PM -0800, Frank Rowand wrote:
> On 03/07/18 12:25, James Hogan wrote:
> > On Wed, Mar 07, 2018 at 12:11:41PM -0800, Frank Rowand wrote:
> >> On 03/07/18 06:06, James Hogan wrote:
> >>> Quite a lot of dts files have hyphens, but its only
admittedly shouldn't really build all the dtb.o files, but thats a
separate issue).
Fixes: 695835511f96 ("MIPS: BMIPS: rename bcm96358nb4ser to
bcm6358-neufbox4-sercom")
Signed-off-by: James Hogan
Reviewed-by: Frank Rowand
Cc: Rob Herring
Cc: Masahiro Yamada
Cc: Michal Marek
Cc: Ral
On Mon, Feb 26, 2018 at 05:02:41PM +, Matt Redfearn wrote:
> There are multiple instances in the kernel where we need to include or
> exclude particular instructions based on the ISA revision of the target
> processor. For MIPS32 / MIPS64, the compiler exports a __mips_isa_rev
> define. However
On Tue, Feb 20, 2018 at 09:58:16AM +, Matt Redfearn wrote:
> If a JTAG probe is connected to a MIPS cluster, then the CPC detects it
> and latches the CPC.STAT_CONF.EJTAG_PROBE bit to 1. While set,
> attempting to send a power-down command to a core will be blocked, and
> the CPC will instead s
On Mon, Jan 15, 2018 at 06:28:44PM -0500, Jim Quinlan wrote:
> diff --git a/arch/mips/boot/dts/brcm/bcm7425.dtsi
> b/arch/mips/boot/dts/brcm/bcm7425.dtsi
> index e4fb9b6..02168d0 100644
> --- a/arch/mips/boot/dts/brcm/bcm7425.dtsi
> +++ b/arch/mips/boot/dts/brcm/bcm7425.dtsi
> @@ -495,4 +495,30 @@
On Mon, Jan 15, 2018 at 06:28:38PM -0500, Jim Quinlan wrote:
> From: Florian Fainelli
>
> This commit adds a memory API suitable for ascertaining the sizes of
> each of the N memory controllers in a Broadcom STB chip. Its first
> user will be the Broadcom STB PCIe root complex driver, which need
On Tue, Jan 23, 2018 at 05:40:10PM -0800, Florian Fainelli wrote:
> diff --git a/arch/mips/include/asm/mach-ath25/dma-coherence.h
> b/arch/mips/include/asm/mach-ath25/dma-coherence.h
> index d5defdde32db..63bce15fa54d 100644
> --- a/arch/mips/include/asm/mach-ath25/dma-coherence.h
> +++ b/arch/mip
On Tue, Jan 23, 2018 at 05:40:09PM -0800, Florian Fainelli wrote:
> @@ -71,15 +83,19 @@ static inline void plat_post_dma_flush(struct device *dev)
> #endif
>
> #ifdef CONFIG_SWIOTLB
> +#ifndef phys_to_dma
> static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
> {
>
On Wed, Mar 14, 2018 at 11:15:47AM +, Marc Zyngier wrote:
> Hi Matt,
>
> On 05/01/18 10:31, Matt Redfearn wrote:
> >
> > This series enables the MIPS GIC driver to make use of the EIC mode
> > supported in some MIPS cores. In this mode, the cores 6 interrupt lines
> > are switched to represen
On Mon, May 21, 2018 at 05:39:32PM +0100, James Hogan wrote:
> On Sun, Apr 08, 2018 at 10:30:03AM +0200, Mathias Kresin wrote:
> > While doing a global software reset, these bits are not cleared and let
> > some bootloader fail to initialise the GPHYs. The bootloader don't
>
On Wed, May 16, 2018 at 04:39:58PM +0100, Maciej W. Rozycki wrote:
> Use 64-bit accesses for 64-bit floating-point general registers with
> PTRACE_PEEKUSR, removing the truncation of their upper halves in the
> FR=1 mode, caused by commit bbd426f542cb ("MIPS: Simplify FP context
> access"), whic
On Thu, May 10, 2018 at 05:59:00PM +0100, Colin King wrote:
> From: Colin Ian King
>
> Trivial fix to spelling mistake in pr_warn message text
>
> Signed-off-by: Colin Ian King
> - pr_warn("VPE loader: elf size too big. Perhaps strip uneeded
> symbols\n");
> + pr_warn(
he subject says since thats
meant to summarise the body.
> -struct platform_device jz4740_wdt_device = {
There's an extern in arch/mips/include/asm/mach-jz4740/platform.h that
should perhaps be removed also?
Otherwise
Acked-by: James Hogan
I'm happy to apply for 4.18 with that chang
On Fri, May 11, 2018 at 01:17:04PM -0300, Paul Cercueil wrote:
> Le 11 mai 2018 11:52, James Hogan a écrit :
> > Otherwise
> > Acked-by: James Hogan
> >
> > I'm happy to apply for 4.18 with that change if you want it to go
> > through the MIPS tree.
On Fri, May 11, 2018 at 02:14:16PM -0700, Guenter Roeck wrote:
> On Fri, May 11, 2018 at 09:54:14PM +0100, James Hogan wrote:
> > On Fri, May 11, 2018 at 01:17:04PM -0300, Paul Cercueil wrote:
> > > Le 11 mai 2018 11:52, James Hogan a écrit :
> > > > Otherwise
On Wed, Mar 28, 2018 at 05:38:12PM +0200, Paul Cercueil wrote:
> The debug definitions were missing for MACH_JZ4770, resulting in a build
> failure when DEBUG_ZBOOT was set.
>
> Since the UART addresses are the same across all Ingenic SoCs, we just
> use a #ifdef CONFIG_MACH_INGENIC instead of che
On Tue, May 08, 2018 at 11:22:36AM +1000, NeilBrown wrote:
> On Mon, May 07 2018, James Hogan wrote:
>
> > On Mon, May 07, 2018 at 07:40:49AM +1000, NeilBrown wrote:
> >>
> >> Hi James,
> >> this hasn't appear in linux-next yet, or in any branch
&
gpr.c
> > @@ -29,7 +29,7 @@
> > #include
> > #include
> > #include
> > -#include
> > +#include
> > #include
> > #include
> > #include
Acked-by: James Hogan
Cheers
James
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On Mon, May 14, 2018 at 10:58:44PM +0200, Andrew Lunn wrote:
> Hi Alexandre
> >
> > The ocelot dts changes are here for reference and should probably go
> > through the MIPS tree once the bindings are accepted.
>
> For your next version, you probably want to drop those patches, so
> that David ca
On Tue, May 15, 2018 at 11:04:44PM +0100, Maciej W. Rozycki wrote:
> Having PR_FP_MODE_FRE (i.e. Config5.FRE) set without PR_FP_MODE_FR (i.e.
> Status.FR) is not supported as the lone purpose of Config5.FRE is to
> emulate Status.FR=0 handling on FPU hardware that has Status.FR=1
> hardwired[1][
On Wed, May 16, 2018 at 04:39:58PM +0100, Maciej W. Rozycki wrote:
> Use 64-bit accesses for 64-bit floating-point general registers with
> PTRACE_PEEKUSR, removing the truncation of their upper halves in the
> FR=1 mode, caused by commit bbd426f542cb ("MIPS: Simplify FP context
> access"), whic
On Tue, May 15, 2018 at 11:03:09PM +0100, Maciej W. Rozycki wrote:
> Correct comments across ptrace(2) handlers about an FPU register context
> layout discrepancy between MIPS I and later ISAs, which was fixed with
> `linux-mips.org' (LMO) commit 42533948caac ("Major pile of FP emulator
> changes."
Hi,
Good to see this patch!
On Tue, Jun 12, 2018 at 01:40:30PM +0800, Songjun Wu wrote:
> diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms
> index ac7ad54f984f..bcd647060f3e 100644
> --- a/arch/mips/Kbuild.platforms
> +++ b/arch/mips/Kbuild.platforms
> @@ -12,6 +12,7 @@ platfo
Thanks Guenter,
On Wed, Jun 13, 2018 at 12:43:52PM -0700, Guenter Roeck wrote:
> GENERIC_ASHLDI3, GENERIC_ASHRDI3, and GENERIC_LSHRDI3 were renamed to
> GENERIC_LIB_ASHLDI3, GENERIC_LIB_ASHRDI3, and GENERIC_LIB_LSHRDI3
> without making the matching changes in arch/nds32.
Well, thats a little misl
On Wed, Jun 13, 2018 at 02:28:08PM -0700, Guenter Roeck wrote:
> On Wed, Jun 13, 2018 at 10:06:13PM +0100, James Hogan wrote:
> > Thanks Guenter,
> >
> > On Wed, Jun 13, 2018 at 12:43:52PM -0700, Guenter Roeck wrote:
> > > GENERIC_ASHLDI3, GENERIC_ASHRDI3, and G
git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux")
Signed-off-by: Guenter Roeck
[jho...@kernel.org: Rename all 6 symbols, sort, update commit message]
Signed-off-by: James Hogan
Cc: Greentime Hu
Cc: Vincent Chen
Cc: Matt Redfearn
Cc: Palmer Dabbelt
---
Changes in v2:
- Rename all 6 symb
; \
ARM doesn't do this for DEFINE_ABORT. Is it intentional that we do for
MIPS?
Otherwise this whole series looks reasonable to me, so feel free to add
my rb on the whole series if you do apply youself:
Reviewed-by: James Hogan
Thanks
James
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On Fri, Jun 15, 2018 at 02:12:58PM +0800, Greentime Hu wrote:
> Thank you James and Guenter.
> Should I pick it in my tree? It will be ok to put in your tree. :)
>
> Acked-by: Greentime Hu
I think your tree makes most sense for this patch, since it only touches
nds32 code and it was nds32 that g
On Fri, Jan 05, 2018 at 10:31:05AM +, Matt Redfearn wrote:
> The current location of ehb() in mipsmtregs.h does not make sense, since
> it is not strictly related to multi-threading, and may be used in code
> which does not include mipsmtregs.h
> arch/mips/include/asm/barrier.h| 13 ++
Given this:
On Wed, May 02, 2018 at 11:14:48PM +0200, Christoph Hellwig wrote:
> +struct __aio_sigset {
> + sigset_t __user *sigmask;
> + size_t sigsetsize;
> +};
and:
> +asmlinkage long sys_io_pgetevents(aio_context_t ctx_id,
> + long min_nr,
> +
therwise:
Acked-by: James Hogan
Cheers
James
>
> Signed-off-by: Sifan Naeem
> ---
> drivers/media/rc/img-ir/img-ir-hw.c |8 +---
> drivers/media/rc/img-ir/img-ir-hw.h |2 ++
> 2 files changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/media/r
On 04/12/14 15:38, Sifan Naeem wrote:
> Biphase decoding in the current img-ir has got a quirk, where multiple
> Interrupts are generated when an incomplete IR code is received by the
> decoder.
>
> Patch adds a work around for the quirk and enables biphase decoding.
>
> Signed-off-by: Sifan Naee
nyo,
> Aiwa, Chinon remotes) in the ImgTec infrared decoder block.
> +
> +config IR_IMG_RC5
> + bool "Phillips RC5 protocol support"
I think that should be "Philips" (if wikipedia is anything to go by).
Same elsewhere in this patch and patch 5.
Other th
On 04/12/14 15:38, Sifan Naeem wrote:
> Add img-ir module for decoding Philips rc6 protocol.
>
> Signed-off-by: Sifan Naeem
Aside from the "Philips" thing:
Acked-by: James Hogan
(It's unpleasant having unexplained timings for RC-6, but it's better
than no RC-6
On 01/01/15 17:48, Rickard Strandqvist wrote:
> Removes some functions that are not used anywhere:
> do_bp() do_ftlb() do_dsp() do_mcheck() do_mdmx() do_msa() do_msa_fpe()
>
> This was partially found by using a static code analysis program called
> cppcheck.
To elaborate on Leonid's comment, Th
On 02/01/15 11:20, Rickard Strandqvist wrote:
> 2015-01-02 11:38 GMT+01:00 James Hogan <mailto:james.ho...@imgtec.com>>:
>
> On 01/01/15 17:48, Rickard Strandqvist wrote:
> > Removes some functions that are not used anywhere:
> > do_bp() do_ftlb(
__(*(ptr)))__gu_val; \
> + (x) = (__force __typeof__(*(ptr)))__gu_val;
> \
same here (this one causes a checkpatch error due to 80 column limit)
> __gu_err; \
> })
On 24/12/14 12:22, Kirill A. Shutemov wrote:
> We've replaced remap_file_pages(2) implementation with emulation.
> Nobody creates non-linear mapping anymore.
>
> Signed-off-by: Kirill A. Shutemov
> Cc: James Hogan
Acked-by: James Hogan
Cheers
James
> ---
> arch/m
On 04/01/15 10:52, Michael S. Tsirkin wrote:
> On Fri, Jan 02, 2015 at 03:41:02PM +0000, James Hogan wrote:
>> Hi,
>>
>> On 25/12/14 09:29, Michael S. Tsirkin wrote:
>>> virtio wants to read bitwise types from userspace using get_user. At the
>>> moment
On 5 January 2015 at 13:00, Michael S. Tsirkin wrote:
> On Mon, Jan 05, 2015 at 09:44:14AM +0000, James Hogan wrote:
>> On 04/01/15 10:52, Michael S. Tsirkin wrote:
>> > On Fri, Jan 02, 2015 at 03:41:02PM +, James Hogan wrote:
>> >> Hi,
>> >>
>>
ows it to be extended more easily without
> touching all the hardware decode callbacks.
>
> Signed-off-by: Sifan Naeem
Acked-by: James Hogan
Cheers
James
> ---
> drivers/media/rc/img-ir/img-ir-hw.c| 16 +---
> drivers/media/rc/img-ir/img-ir-hw.h| 16 ++
On Wed, Dec 24, 2014 at 01:21:11AM +0200, Aaro Koskinen wrote:
> Hi,
>
> On Thu, Sep 11, 2014 at 08:30:20AM +0100, Paul Burton wrote:
> > Hybrid FPRs is a scheme where scalar FP registers are 64b wide, but
> > accesses to odd indexed single registers use bits 63:32 of the
> > preceeding even index
Hi,
A few general things below (I'll leave the actual networking bits for
others to comment about).
On Friday 23 January 2015 10:07:01 Stathis Voukelatos wrote:
> ---
> .../bindings/net/linn-ether-packet-sniffer.txt | 27 ++
> .../devicetree/bindings/vendor-prefixes.txt| 1 +
> MA
70/0xac
> [<40025d84>] _process_one_work+0x110/0x364
> [<402034d8>] _device_bind_driver+0x2c/0x30
> [<40046150>] _mod_timer+0xc4/0x178
> [<400286a4>] _worker_thread+0x14c/0x4d4
> [<4002b90c>] _kthread_parkme+0x14/0x18
> [<40028554>] _pool_ma
Hi Andrew,
On 18/09/14 22:47, Andrew Bresticker wrote:
> Now that the GIC properly uses IRQ domains, kill off the per-platform
> routing tables that were used to make the GIC appear transparent.
>
> This includes:
> - removing the mapping tables and the support for applying them,
> - moving GIC
On 15/01/15 11:59, James Hogan wrote:
> Hi Andrew,
>
> On 18/09/14 22:47, Andrew Bresticker wrote:
>> Now that the GIC properly uses IRQ domains, kill off the per-platform
>> routing tables that were used to make the GIC appear transparent.
>>
>> This includes:
On 15/01/15 16:36, Qais Yousef wrote:
> On 01/15/2015 04:29 PM, James Hogan wrote:
>> On 15/01/15 11:59, James Hogan wrote:
>>> Hi Andrew,
>>>
>>> On 18/09/14 22:47, Andrew Bresticker wrote:
>>>> Now that the GIC properly uses IRQ domains, kill of
On 15/01/15 16:58, Andrew Bresticker wrote:
> Hi James, Qais,
>
> On Thu, Jan 15, 2015 at 8:36 AM, Qais Yousef wrote:
>> On 01/15/2015 04:29 PM, James Hogan wrote:
>>>
>>> On 15/01/15 11:59, James Hogan wrote:
>>>>
>>>> Hi And
ze(__gu_val, __gu_addr, (size), __gu_err); \
> - (x) = (__typeof__(*(ptr)))__gu_val; \
> + (x) = (__force __typeof__(*(ptr)))__gu_val;
> \
same here (this one causes checkpatch error due to 80 column limit).
> __gu_err;
ast (__typeof__(*(ptr))) (x) which in turn forces all the
> necessary type checks.
>
> Suggested-by: James Hogan
> Signed-off-by: Michael S. Tsirkin
> ---
> arch/metag/include/asm/uaccess.h | 21 +
> 1 file changed, 13 insertions(+), 8 deletions(-)
>
>
Hi,
On 01/12/14 23:19, James Hogan wrote:
> This patchset adds common clock framework support for the TZ1090 SoC.
Any further comments on these patches? It'd be nice to be able to get
them into v3.20 if possible.
Cheers
James
>
> Patch 1 adds common code to simplify TZ1090 c
ovided to allow early boot
or particularly low level code to set up the CDMM region and probe for a
specific device type, for example early console or KGDB IO drivers for
the EJTAG Fast Debug Channel (FDC) CDMM device.
Signed-off-by: James Hogan
Cc: Ralf Baechle
Cc: Greg Kroah-Hartman
Cc: l
the feature is present, and
a CDMMBase CP0 register allows the region to be enabled at a particular
physical address.
Signed-off-by: James Hogan
Cc: Ralf Baechle
Cc: linux-m...@linux-mips.org
---
arch/mips/include/asm/cpu-features.h | 4
arch/mips/include/asm/cpu.h | 1 +
arch
Baechle
Cc: Greg Kroah-Hartman
Cc: linux-m...@linux-mips.org
James Hogan (3):
MIPS: Add arch CDMM definitions and probing
MIPS: Add CDMM bus support
MIPS: Malta: Implement mips_cdmm_phys_base()
arch/mips/include/asm/cdmm.h | 87 +
arch/mips/include/asm/cpu-features.h | 4 +
arch
EJTAG) to be discovered.
Signed-off-by: James Hogan
Cc: Ralf Baechle
Cc: linux-m...@linux-mips.org
---
arch/mips/mti-malta/malta-memory.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/mips/mti-malta/malta-memory.c
b/arch/mips/mti-malta/malta-memory.c
index 8fddd2cdbff7..32
port, including cevt-smtc.c,
leaving cevt-r4k.c once again the sole user of handle_perf_irq(),
therefore move it back into cevt-r4k.c from the header.
Signed-off-by: James Hogan
Cc: Ralf Baechle
Cc: linux-m...@linux-mips.org
---
arch/mips/include/asm/cevt-r4k.h | 19 ---
arch/mi
other handlers to run, and passing IRQF_SHARED when
setting up the IRQ handler so that other handlers (with compatible
flags) can be registered.
Signed-off-by: James Hogan
Cc: Ralf Baechle
Cc: linux-m...@linux-mips.org
---
arch/mips/kernel/cevt-r4k.c | 8 +++-
1 file changed, 7 insertions
Add missing VPE_PEND, VPE_RMASK and VPE_SMASK definitions for the local
FDC interrupt.
These local interrupt definitions aren't directly used, but if they
exist they should be complete.
Signed-off-by: James Hogan
Cc: Ralf Baechle
Cc: Andrew Bresticker
Cc: Thomas Gleixner
Cc: Jason Coope
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