Dne sobota, 24. avgust 2019 ob 14:56:12 CEST je Ondřej Jirman napisal(a):
> Hi,
>
> On Sat, Aug 24, 2019 at 10:06:14AM +0200, Jernej Škrabec wrote:
> > Dne sobota, 24. avgust 2019 ob 10:04:24 CEST je Jernej Škrabec napisal(a):
> > > Hi!
> > >
> > > Dne
Dne sobota, 24. avgust 2019 ob 15:05:44 CEST je Ondřej Jirman napisal(a):
> On Sat, Aug 24, 2019 at 02:51:54PM +0200, Jernej Škrabec wrote:
> > Dne sobota, 24. avgust 2019 ob 14:46:54 CEST je Ondřej Jirman napisal(a):
> > > Hi,
> > >
> > > On Sat, Aug 24, 2019
Dne sobota, 24. avgust 2019 ob 15:30:57 CEST je Ondřej Jirman napisal(a):
> On Sat, Aug 24, 2019 at 03:16:41PM +0200, Jernej Škrabec wrote:
> > Dne sobota, 24. avgust 2019 ob 15:05:44 CEST je Ondřej Jirman napisal(a):
> > > On Sat, Aug 24, 2019 at 02:51:54PM +0200, Je
Dne sobota, 24. avgust 2019 ob 23:27:46 CEST je Ondřej Jirman napisal(a):
> Hello Jernej,
>
> On Sat, Aug 24, 2019 at 11:09:49PM +0200, Jernej Škrabec wrote:
> > > Visually?
> > >
> > > That would explain why it doesn't work for you. The mainline RTC drive
Dne ponedeljek, 26. avgust 2019 ob 20:28:31 CEST je Boris Brezillon
napisal(a):
> Hi Jernej,
>
> On Thu, 22 Aug 2019 21:44:57 +0200
>
> Jernej Skrabec wrote:
> > When codec supports multiple slices in one frame, VPU has to know when
> > first slice of each frame is being processed, presumably
Dne ponedeljek, 29. julij 2019 ob 20:51:08 CEST je Uwe Kleine-König
napisal(a):
> On Mon, Jul 29, 2019 at 08:46:25PM +0200, Jernej Škrabec wrote:
> > Dne ponedeljek, 29. julij 2019 ob 20:40:41 CEST je Uwe Kleine-König
> >
> > napisal(a):
> > > On Mon, Jul 29, 20
Hi!
Dne torek, 04. junij 2019 ob 11:38:44 CEST je Code Kipper napisal(a):
> On Tue, 4 Jun 2019 at 11:02, Christopher Obbard wrote:
> > On Tue, 4 Jun 2019 at 09:43, Code Kipper wrote:
> > > On Tue, 4 Jun 2019 at 09:58, Maxime Ripard
wrote:
> > > > On Mon, Jun 03, 2019 at 07:47:32PM +0200,
Dne sreda, 14. avgust 2019 ob 15:28:53 CEST je Clément Péron napisal(a):
> Hi,
>
> On Wed, 14 Aug 2019 at 15:20, Corentin Labbe
wrote:
> > On Mon, Aug 12, 2019 at 12:56:56PM +0200, Jernej Škrabec wrote:
> > > Dne četrtek, 08. avgust 2019 ob 10:42:53 CEST je
Dne nedelja, 18. avgust 2019 ob 20:42:49 CEST je kbuild test robot napisal(a):
> Hi Jernej,
>
> Thank you for the patch! Yet something to improve:
>
> [auto build test ERROR on linus/master]
> [cannot apply to v5.3-rc4 next-20190816]
> [if your patch is applied to the wrong git tree, please drop
Dne ponedeljek, 24. avgust 2020 ob 22:54:01 CEST je Pablo Sebastián Greco
napisal(a):
> On 24/8/20 16:36, Jernej Skrabec wrote:
> > DCDC1 regulator powers many different subsystems. While some of them can
> > work at 3.0 V, some of them can not. For example, VCC-HDMI can only work
> > between
Dne torek, 25. avgust 2020 ob 16:46:31 CEST je Chen-Yu Tsai napisal(a):
> On Tue, Aug 25, 2020 at 9:11 PM Jernej Skrabec
wrote:
> > Audio cores need specific clock rates which can't be simply obtained by
> > adjusting integer multipliers and dividers. HW for such cases supports
> > delta-sigma
Dne sreda, 02. september 2020 ob 09:01:17 CEST je Roman Stratiienko
napisal(a):
> ср, 2 сент. 2020 г. в 00:58, Jernej Skrabec :
> > Function sun8i_vi_layer_get_csc_mode() is supposed to return CSC mode
> > but due to inproper return type (bool instead of u32) it returns just 0
> > or 1. Colors
Hi Samuel!
Dne petek, 10. julij 2020 ob 07:44:51 CEST je Samuel Holland napisal(a):
> On 7/4/20 6:38 AM, Clément Péron wrote:
> > From: Marcus Cooper
> >
> > Extend the functionality of the driver to include support of 20 and
> > 24 bits per sample.
> >
> > Signed-off-by: Marcus Cooper
> >
Dne petek, 28. avgust 2020 ob 13:24:44 CEST je Ondrej Jirman napisal(a):
> It's writing too much data. regmap_bulk_write expects number of
> register sized chunks to write, not a byte sized length of the
> bounce buffer. Bounce buffer needs to be padded too, so that
> regmap_bulk_write will not
Dne petek, 28. avgust 2020 ob 14:21:19 CEST je Ondřej Jirman napisal(a):
> On Fri, Aug 28, 2020 at 02:16:36PM +0200, Clément Péron wrote:
> > Hi Maxime,
> >
> > On Tue, 25 Aug 2020 at 15:35, Maxime Ripard wrote:
> > > Hi Clement,
> > >
> > > On Mon, Aug 03, 2020 at 09:54:05AM +0200, Clément
Hi!
Dne četrtek, 06. avgust 2020 ob 17:47:07 CEST je Paul Kocialkowski napisal(a):
> Hi,
>
> On Thu 06 Aug 20, 12:12, Ezequiel Garcia wrote:
> > From: Jernej Skrabec
> >
> > When dealing with with interlaced frames, reference lists must tell if
> > each particular reference is meant for top or
>Better guess. Secondary CSC registers are from 0xF.
>
>Signed-off-by: Martin Cerveny
Reviewed-by: Jernej Skrabec
Best regards,
Jernej
>"Allwinner V3s" has secondary video layer (VI).
>Decoded video is displayed in wrong colors until
>secondary CSC registers are programmed correctly.
>
>Signed-off-by: Martin Cerveny
Following tag should be added:
Fixes: 883029390550 ("drm/sun4i: Add DE2 CSC library")
Reviewed-by: Jernej
Dne sreda, 28. oktober 2020 ob 12:58:17 CET je Nenad Peric napisal(a):
> RX and TX delay are provided by ethernet PHY. Reflect that in ethernet
> node.
>
> Fixes: 44a94c7ef989 ("arm64: dts: allwinner: H5: Restore EMAC changes")
> Signed-off-by: Nenad Peric
Acked-by: Jernej Skrabec
Thanks!
Dne petek, 09. oktober 2020 ob 09:36:51 CEST je Maxime Ripard napisal(a):
> On Thu, Oct 08, 2020 at 10:00:06PM +0200, Clément Péron wrote:
> > Hi Maxime,
> >
> > Adding linux-sunxi and Jernej Skrabec to this discussion.
> >
> > On Thu, 8 Oct 2020 at 17:10, Maxime Ripard wrote:
> > >
> > > Hi
Dne nedelja, 01. november 2020 ob 01:34:17 CET je Pablo Greco napisal(a):
> Ethernet PHY on BananaPi M2 Berry provides RX and TX delays. Fix ethernet
> node to reflect that fact.
>
> Fixes: 27e81e1970a8 ("ARM: dts: sun8i: v40: bananapi-m2-berry: Enable GMAC
ethernet controller")
> Signed-off-by:
Dne nedelja, 01. november 2020 ob 01:34:16 CET je Pablo Greco napisal(a):
> DCDC1 regulator powers many different subsystems. While some of them can
> work at 3.0 V, some of them can not. For example, VCC-HDMI can only work
> between 3.24 V and 3.36 V. According to OS images provided by the board
Dne nedelja, 01. november 2020 ob 01:34:15 CET je Pablo Greco napisal(a):
> The Ethernet PHY on the Bananapi M1 has the RX and TX delays enabled on
> the PHY, using pull-ups on the RXDLY and TXDLY pins.
>
> Fix the phy-mode description to correct reflect this so that the
> implementation doesn't
Hi!
Dne sreda, 27. januar 2021 ob 18:24:52 CET je Andre Przywara napisal(a):
> Add the obvious compatible name to the existing RTC binding, and pair
> it with the existing H6 fallback compatible string, as the devices are
> compatible.
After close lookup I would disagree with this observation.
Dne torek, 17. september 2019 ob 08:54:08 CEST je Chen-Yu Tsai napisal(a):
> On Sat, Sep 14, 2019 at 9:51 PM Jernej Skrabec
wrote:
> > Audio devices needs exact clock rates in order to correctly reproduce
> > the sound. Until now, only integer factors were used to configure H6
> > audio PLL
Dne četrtek, 05. september 2019 ob 11:43:25 CEST je Cheng-Yi Chiang
napisal(a):
> From: Yakir Yang
>
> When transmitting IEC60985 linear PCM audio, we configure the
> Aduio Sample Channel Status information of all the channel
> status bits in the IEC60958 frame.
> Refer to 60958-3 page 10 for
Dne petek, 05. junij 2020 ob 19:16:35 CEST je Nicolas Dufresne napisal(a):
> Le jeudi 04 juin 2020 à 20:57 +0200, Jernej Skrabec a écrit :
> > When interlaced H264 content is being decoded, references must indicate
> > which field is being referenced. Currently this was done by checking
> >
Dne petek, 05. junij 2020 ob 19:13:24 CEST je Nicolas Dufresne napisal(a):
> Sorry, missed one thing.
>
> Le vendredi 05 juin 2020 à 13:08 -0400, Nicolas Dufresne a écrit :
> > Le jeudi 04 juin 2020 à 20:57 +0200, Jernej Skrabec a écrit :
> > > When dealing with with interlaced frames, reference
Hi,
Dne ponedeljek, 29. januar 2018 ob 19:05:26 CET je Rob Herring napisal(a):
> On Wed, Jan 17, 2018 at 09:14:15PM +0100, Jernej Skrabec wrote:
> > This commit adds all necessary compatibles and descriptions needed to
> > implement A83T HDMI pipeline.
> >
> > Mixer is already properly
Dne četrtek, 08. februar 2018 ob 10:15:35 CET je Icenowy Zheng napisal(a):
> 在 2018-02-08 17:00，Maxime Ripard 写道：
>
> > On Tue, Feb 06, 2018 at 09:16:47PM +0800, Icenowy Zheng wrote:
> >> Banana Pi M2 Zero board is a H2+-based board by Sinovoip, with a form
> >> factor and GPIO holes similar to
Hi,
Dne četrtek, 18. januar 2018 ob 11:58:41 CET je Maxime Ripard napisal(a):
> Hi,
>
> On Wed, Jan 17, 2018 at 09:14:11PM +0100, Jernej Skrabec wrote:
> > This commit changes formula from this:
> >
> > Freq = (parent_freq * N * K) / (M * P)
> >
> > to this:
> >
> > Freq = (parent_freq / M) *
Dne sreda, 31. julij 2019 ob 14:29:53 CEST je Maxime Ripard napisal(a):
> On Tue, Jul 30, 2019 at 07:57:10PM +0200, Jernej Škrabec wrote:
> > Dne torek, 04. junij 2019 ob 11:38:44 CEST je Code Kipper napisal(a):
> > > On Tue, 4 Jun 2019 at 11:02, Christopher Obbard
wrote:
>
Dne četrtek, 12. september 2019 ob 22:26:47 CEST je Maxime Ripard napisal(a):
> Hi,
>
> On Thu, Sep 12, 2019 at 07:51:31PM +0200, Jernej Skrabec wrote:
> > + dev->regmap = devm_regmap_init_mmio(dev->dev, dev->base,
> > +
_regmap_config);
> > + if
Dne ponedeljek, 30. september 2019 ob 10:14:32 CEST je Hans Verkuil
napisal(a):
> On 9/29/19 10:00 PM, Jernej Skrabec wrote:
> > When frame contains multiple slices and driver works in slice mode, it's
> > more efficient to hold capture buffer in queue until all slices of a
> > same frame are
Dne ponedeljek, 30. september 2019 ob 10:10:48 CEST je Hans Verkuil
napisal(a):
> On 9/29/19 10:00 PM, Jernej Skrabec wrote:
> > This series adds support for decoding multi-slice H264 frames along with
> > support for V4L2_DEC_CMD_FLUSH and V4L2_BUF_FLAG_M2M_HOLD_CAPTURE_BUF.
> >
> > Code was
Dne torek, 01. oktober 2019 ob 00:43:34 CEST je Hans Verkuil napisal(a):
> On 10/1/19 12:27 AM, Jernej Škrabec wrote:
> > Dne ponedeljek, 30. september 2019 ob 10:10:48 CEST je Hans Verkuil
> >
> > napisal(a):
> >> On 9/29/19 10:00 PM, Jernej Skrabec wrote:
Dne torek, 01. oktober 2019 ob 00:43:34 CEST je Hans Verkuil napisal(a):
> On 10/1/19 12:27 AM, Jernej Škrabec wrote:
> > Dne ponedeljek, 30. september 2019 ob 10:10:48 CEST je Hans Verkuil
> >
> > napisal(a):
> >> On 9/29/19 10:00 PM, Jernej Skrabec wrote:
Dne ponedeljek, 26. avgust 2019 ob 20:28:31 CEST je Boris Brezillon
napisal(a):
> Hi Jernej,
>
> On Thu, 22 Aug 2019 21:44:57 +0200
>
> Jernej Skrabec wrote:
> > When codec supports multiple slices in one frame, VPU has to know when
> > first slice of each frame is being processed, presumably
Dne četrtek, 12. september 2019 ob 22:20:57 CEST je Maxime Ripard napisal(a):
> Hi,
>
> On Thu, Sep 12, 2019 at 07:51:29PM +0200, Jernej Skrabec wrote:
> > Both, H3 and H5, contain MBUS, which is the bus used by DMA devices to
> > access system memory.
> >
> > MBUS controller is responsible for
Dne četrtek, 12. september 2019 ob 22:26:47 CEST je Maxime Ripard napisal(a):
> Hi,
>
> On Thu, Sep 12, 2019 at 07:51:31PM +0200, Jernej Skrabec wrote:
> > + dev->regmap = devm_regmap_init_mmio(dev->dev, dev->base,
> > +
_regmap_config);
> > + if
Dne četrtek, 12. september 2019 ob 22:34:27 CEST je Maxime Ripard napisal(a):
> On Thu, Sep 12, 2019 at 10:28:37PM +0200, Jernej Škrabec wrote:
> > Dne četrtek, 12. september 2019 ob 22:20:57 CEST je Maxime Ripard
napisal(a):
> > > Hi,
> > >
> > > On Thu, Sep
Hi!
Dne petek, 13. september 2019 ob 11:11:47 CEST je Maxime Ripard napisal(a):
> Hi,
>
> On Thu, Sep 12, 2019 at 10:43:28PM +0200, Jernej Škrabec wrote:
> > Dne četrtek, 12. september 2019 ob 22:26:47 CEST je Maxime Ripard
napisal(a):
> > > > + clk_set_r
Hi!
Dne četrtek, 12. september 2019 ob 22:26:47 CEST je Maxime Ripard napisal(a):
> Hi,
>
> On Thu, Sep 12, 2019 at 07:51:31PM +0200, Jernej Skrabec wrote:
> > + dev->regmap = devm_regmap_init_mmio(dev->dev, dev->base,
> > +
_regmap_config);
> > + if
Dne četrtek, 03. oktober 2019 ob 00:06:50 CEST je Paul Kocialkowski
napisal(a):
> Hi,
>
> On Wed 02 Oct 19, 21:35, Jernej Skrabec wrote:
> > Reference index count in VE_H264_PPS should come from PPS control.
> > However, this is not really important, because reference index count is
> > in our
Dne četrtek, 03. oktober 2019 ob 00:23:07 CEST je Paul Kocialkowski
napisal(a):
> Hi,
>
> On Wed 02 Oct 19, 21:35, Jernej Skrabec wrote:
> > This is continuation of https://lkml.org/lkml/2019/5/30/1459 with several
> > patches removed (2 merged, others needs redesign) and one added.
>
> Thanks
Hi!
Dne sreda, 14. avgust 2019 ob 08:08:50 CEST je codekip...@gmail.com
napisal(a):
> From: Jernej Skrabec
>
> H6 I2S is very similar to that in H3, except it supports up to 16
> channels.
>
> Signed-off-by: Jernej Skrabec
Your Signed-off-by is missing here and on all other patches made
Hi!
Dne sreda, 14. avgust 2019 ob 08:08:51 CEST je codekip...@gmail.com
napisal(a):
> From: Marcus Cooper
>
> The i2s block supports multi-lane i2s output however this functionality
> is only possible in earlier SoCs where the pins are exposed and for
> the i2s block used for HDMI audio on the
Hi!
Dne sreda, 14. avgust 2019 ob 08:08:53 CEST je codekip...@gmail.com
napisal(a):
> From: Marcus Cooper
>
> Extend the functionality of the driver to include support of 20 and
> 24 bits per sample for the earlier SoCs.
>
> Newer SoCs can also handle 32bit samples.
>
> Signed-off-by: Marcus
Hi!
Dne sreda, 14. avgust 2019 ob 08:08:54 CEST je codekip...@gmail.com
napisal(a):
> From: Marcus Cooper
>
> Bypass the regmap cache when flushing the i2s FIFOs and modify the tables
> to reflect this.
>
> Signed-off-by: Marcus Cooper
> ---
> sound/soc/sunxi/sun4i-i2s.c | 31
Dne sreda, 14. avgust 2019 ob 09:20:07 CEST je Maxime Ripard napisal(a):
> On Wed, Aug 14, 2019 at 08:08:54AM +0200, codekip...@gmail.com wrote:
> > From: Marcus Cooper
> >
> > Bypass the regmap cache when flushing the i2s FIFOs and modify the tables
> > to reflect this.
> >
> > Signed-off-by:
Dne četrtek, 03. oktober 2019 ob 22:28:46 CEST je Paul Kocialkowski
napisal(a):
> Hi,
>
> On Thu 03 Oct 19, 07:16, Jernej Škrabec wrote:
> > Dne četrtek, 03. oktober 2019 ob 00:06:50 CEST je Paul Kocialkowski
> >
> > napisal(a):
> > > Hi,
> > >
Dne četrtek, 03. oktober 2019 ob 22:58:57 CEST je Paul Kocialkowski
napisal(a):
> Hi,
>
> On Thu 03 Oct 19, 22:44, Jernej Škrabec wrote:
> > Dne četrtek, 03. oktober 2019 ob 22:28:46 CEST je Paul Kocialkowski
> >
> > napisal(a):
> > > Hi,
> > >
Dne ponedeljek, 12. avgust 2019 ob 12:47:00 CEST je Uwe Kleine-König
napisal(a):
> Hello Maxime,
>
> the idea of my mail was to summarize quickly the discussion for the dt
> people to give their judgement to stop us circling in a discussion about
> the always same points.
>
> I suggest we stop
Dne četrtek, 08. avgust 2019 ob 10:42:53 CEST je Corentin Labbe napisal(a):
> This patch adds the evaluation variant of the model A of the PineH64.
> The model A has the same size of the pine64 and has a PCIE slot.
>
> The only devicetree difference with current pineH64, is the PHY
> regulator.
Dne ponedeljek, 12. avgust 2019 ob 14:12:21 CEST je Hans Verkuil napisal(a):
> On 5/30/19 11:15 PM, Jernej Skrabec wrote:
> > Here is first batch of random Cedrus improvements/cleanups. Only patch 2
> > has a change which raises a question about H264 controls.
> >
> > Changes were tested on H3
Dne petek, 04. oktober 2019 ob 11:21:12 CEST je Hans Verkuil napisal(a):
> On 9/29/19 10:00 PM, Jernej Skrabec wrote:
> > These helpers are used by stateless codecs when they support multiple
> > slices per frame and hold capture buffer flag is set. It's expected that
> > all such codecs will use
Dne ponedeljek, 07. oktober 2019 ob 12:44:24 CEST je Hans Verkuil napisal(a):
> Hi Jernej,
>
> On 9/29/19 10:00 PM, Jernej Skrabec wrote:
> > This series adds support for decoding multi-slice H264 frames along with
> > support for V4L2_DEC_CMD_FLUSH and V4L2_BUF_FLAG_M2M_HOLD_CAPTURE_BUF.
> >
>
Dne petek, 27. september 2019 ob 16:34:08 CEST je Paul Kocialkowski
napisal(a):
> HEVC/H.265 stateless support for V4L2 and Cedrus
>
> This is early support for HEVC/H.265 stateless decoding in V4L2,
> including both definitions and driver support for the Cedrus VPU
> driver, which concerns
Dne sreda, 09. oktober 2019 ob 12:18:45 CEST je Hans Verkuil napisal(a):
> On 10/7/19 9:01 PM, Jernej Škrabec wrote:
> > Dne ponedeljek, 07. oktober 2019 ob 12:44:24 CEST je Hans Verkuil
napisal(a):
> >> Hi Jernej,
> >>
> >> On 9/29/19 10:00 PM, Jernej S
Dne četrtek, 17. oktober 2019 ob 09:51:28 CEST je Hans Verkuil napisal(a):
> On 10/16/19 9:28 PM, Jernej Skrabec wrote:
> > Allwinner H3 SoC contains deinterlace unit, which has several modes of
> > operation - bypass, weave, bob and mixed (advanced) mode. I don't know
> > how mixed mode works,
Dne četrtek, 17. oktober 2019 ob 11:28:00 CEST je Maxime Ripard napisal(a):
> Hi,
>
> I have a small comment that can definitely be addressed in a subsequent
> patch
> On Wed, Oct 16, 2019 at 09:28:06PM +0200, Jernej Skrabec wrote:
> > + dev->bus_clk = devm_clk_get(dev->dev, "bus");
> > + if
Dne sreda, 29. april 2020 ob 12:43:06 CEST je Robin Murphy napisal(a):
> On 2020-04-29 9:17 am, Maxime Ripard wrote:
> > On Wed, Apr 29, 2020 at 02:24:00PM +0800, Chen-Yu Tsai wrote:
> >> On Wed, Apr 29, 2020 at 1:11 AM Robin Murphy
wrote:
> >>> On 2020-04-28 5:49 pm, Clément Péron wrote:
>
Hi!
Sorry for late reponse, technical issues...
Dne sreda, 02. oktober 2019 ob 23:54:47 CEST je Paul Kocialkowski napisal(a):
> Hi,
>
> On Wed 02 Oct 19, 21:35, Jernej Skrabec wrote:
> > It seems that for some H264 videos at least one bitstream parsing
> > trigger must be called in order to be
Dne četrtek, 29. avgust 2019 ob 13:23:29 CEST je Hans Verkuil napisal(a):
> On 8/22/19 9:44 PM, Jernej Skrabec wrote:
> > When frame contains multiple slices and driver works in slice mode, it's
> > more efficient to hold capture buffer in queue until all slices of a
> > same frame are decoded.
>
Hi Ezequiel!
Dne sobota, 25. julij 2020 ob 15:08:37 CEST je Ezequiel Garcia napisal(a):
> Hi Jernej,
>
> As you know, I'm not familiar with this hardware,
> but I've tried to take a detailed look anyway.
>
Thanks, any review is welcome.
> The driver looks mostly good to me, I just have
> some
Hi!
Dne sreda, 15. julij 2020 ob 22:22:26 CEST je Ezequiel Garcia napisal(a):
> The prediction weight parameters are only required under
> certain conditions, which depend on slice header parameters.
>
> The slice header syntax specifies that the prediction
> weight table is present if:
>
>
Hi!
Dne sreda, 15. julij 2020 ob 22:22:29 CEST je Ezequiel Garcia napisal(a):
> As discussed recently, the current interface for the
> Decoded Picture Buffer is not enough to properly
> support field coding.
>
> This commit introduces enough semantics to support
> frame and field coding, and to
Hi!
Dne petek, 24. maj 2019 ob 11:36:33 CEST je Paul Kocialkowski napisal(a):
> Introduce the V4L2_PIX_FMT_HEVC_SLICE pixel format, which currently
> describes an output buffer with enough appended slice data for
> producing one decoded frame with a stateless video decoder.
>
> This will need to
Dne ponedeljek, 24. junij 2019 ob 11:08:51 CEST je Neil Armstrong napisal(a):
> Add myself as co-maintainer of DRM Bridge Drivers then add Jonas Karlman
> and Jernej Škrabec as Reviewers of DRM Bridge Drivers.
>
> Cc: Laurent Pinchart
> Cc: Jonas Karlman
> Cc: Andrzej H
Dne sreda, 05. junij 2019 ob 23:10:17 CEST je Paul Kocialkowski napisal(a):
> Hi,
>
> Le lundi 03 juin 2019 à 17:48 +0200, Jernej Škrabec a écrit :
> > Dne ponedeljek, 03. junij 2019 ob 14:18:59 CEST je Maxime Ripard
napisal(a):
> > > Hi,
> > >
> > >
Dne ponedeljek, 03. junij 2019 ob 13:46:20 CEST je Maxime Ripard napisal(a):
> On Thu, May 30, 2019 at 11:15:11PM +0200, Jernej Skrabec wrote:
> > Reference index count in VE_H264_PPS reg should come from PPS control.
> > However, this is not really important because reference index count is
> >
Dne ponedeljek, 03. junij 2019 ob 13:55:36 CEST je Maxime Ripard napisal(a):
> Hi,
>
> On Thu, May 30, 2019 at 11:15:12PM +0200, Jernej Skrabec wrote:
> > It seems that for some H264 videos at least one bitstream parsing
> > trigger must be called in order to be decoded correctly. There is no
> >
Dne ponedeljek, 03. junij 2019 ob 14:18:59 CEST je Maxime Ripard napisal(a):
> Hi,
>
> On Thu, May 30, 2019 at 11:15:15PM +0200, Jernej Skrabec wrote:
> > H264 and HEVC engines need additional buffers for each capture buffer.
> > H264 engine has this currently solved by allocating fixed size
Dne ponedeljek, 03. junij 2019 ob 14:23:28 CEST je Maxime Ripard napisal(a):
> On Thu, May 30, 2019 at 11:15:16PM +0200, Jernej Skrabec wrote:
> > H264 decoder driver preallocated pretty big worst case mv col buffer
> > pool. It turns out that pool is most of the time much bigger than it
> > needs
Dne torek, 04. junij 2019 ob 17:00:54 CEST je megous via linux-sunxi
napisal(a):
> From: Ondrej Jirman
>
> The current code defines W1 clock gate to be at 0x1cc, overlaying it
> with the IR gate.
>
> Clock gate for r-apb1-w1 is at 0x1ec. This fixes issues with IR receiver
> causing interrupt
Hi!
Dne torek, 04. junij 2019 ob 17:31:20 CEST je 'Ondřej Jirman' via linux-sunxi
napisal(a):
> Hi Jernej,
>
> On Tue, Jun 04, 2019 at 05:03:55PM +0200, Jernej Škrabec wrote:
> > Dne torek, 04. junij 2019 ob 17:00:54 CEST je megous via linux-sunxi
> >
> > napisal(a)
Dne sobota, 06. julij 2019 ob 13:21:44 CEST je Mark Brown napisal(a):
> On Sat, Jul 06, 2019 at 12:05:44PM +0200, Jernej Skrabec wrote:
> > Refactoring of the driver introduced few bugs in AXP806's DCDCA and
> > DCDCD regulator definitions.
>
> This is not a great changelog - what are the bugs
Dne ponedeljek, 21. oktober 2019 ob 13:16:24 CEST je Hans Verkuil napisal(a):
> Hi Jernej,
>
> I found something odd in the compliance output:
>
> On 10/17/19 8:37 PM, Jernej Skrabec wrote:
> > Starting with H3, Allwinner began to include standalone deinterlace
> > core in multimedia oriented
Dne ponedeljek, 21. oktober 2019 ob 13:13:20 CEST je Hans Verkuil napisal(a):
> On 10/17/19 8:37 PM, Jernej Skrabec wrote:
> > Allwinner H3 SoC contains deinterlace unit, which has several modes of
> > operation - bypass, weave, bob and mixed (advanced) mode. I don't know
> > how mixed mode works,
Dne sobota, 27. julij 2019 ob 12:46:28 CEST je Maxime Ripard napisal(a):
> Hi,
>
> On Fri, Jul 26, 2019 at 08:40:42PM +0200, Jernej Skrabec wrote:
> > H6 PWM core needs bus clock to be enabled in order to work.
> >
> > Add a quirk for it.
> >
> > Signed-off-by: Jernej Skrabec
> > ---
> >
> >
Dne sobota, 27. julij 2019 ob 12:50:08 CEST je Maxime Ripard napisal(a):
> On Fri, Jul 26, 2019 at 08:40:44PM +0200, Jernej Skrabec wrote:
> > PWM core has an option to bypass whole logic and output unchanged source
> > clock as PWM output. This is achieved by enabling bypass bit.
> >
> > Note
Hi Uwe,
Dne ponedeljek, 29. julij 2019 ob 08:38:25 CEST je Uwe Kleine-König
napisal(a):
> Hello,
>
> On Fri, Jul 26, 2019 at 08:40:42PM +0200, Jernej Skrabec wrote:
> > H6 PWM core needs bus clock to be enabled in order to work.
> >
> > Add a quirk for it.
> >
> > Signed-off-by: Jernej
Hi Uwe,
Dne ponedeljek, 29. julij 2019 ob 08:40:30 CEST je Uwe Kleine-König
napisal(a):
> On Fri, Jul 26, 2019 at 08:40:43PM +0200, Jernej Skrabec wrote:
> > Now that sun4i PWM driver supports deasserting reset line and enabling
> > bus clock, support for H6 PWM can be added.
> >
> > Note that
Hi Uwe,
Dne ponedeljek, 29. julij 2019 ob 09:06:05 CEST je Uwe Kleine-König
napisal(a):
> On Fri, Jul 26, 2019 at 08:40:44PM +0200, Jernej Skrabec wrote:
> > PWM core has an option to bypass whole logic and output unchanged source
> > clock as PWM output. This is achieved by enabling bypass bit.
Dne ponedeljek, 29. julij 2019 ob 18:24:28 CEST je Uwe Kleine-König
napisal(a):
> Hello,
>
> On Tue, Jul 30, 2019 at 12:09:40AM +0800, Chen-Yu Tsai wrote:
> > On Tue, Jul 30, 2019 at 12:07 AM Uwe Kleine-König
> >
> > wrote:
> > > On Mon, Jul 29, 2019 at 05
Dne ponedeljek, 29. julij 2019 ob 20:40:41 CEST je Uwe Kleine-König
napisal(a):
> On Mon, Jul 29, 2019 at 06:40:15PM +0200, Jernej Škrabec wrote:
> > Dne ponedeljek, 29. julij 2019 ob 18:24:28 CEST je Uwe Kleine-König
> >
> > napisal(a):
> > > Hello,
> > &g
Hi!
Dne sreda, 08. julij 2020 ob 15:28:52 CEST je Ezequiel Garcia napisal(a):
> Hello Jernej,
>
> I'd like to post a new H264 uAPI cleanup series soon,
> would you mind resending this, or otherwise do you
> mind if I include this patch in the series?
I don't mind at all. Currently my focus was
Hi!
Dne ponedeljek, 06. julij 2020 ob 07:31:23 CEST je Maxime Ripard napisal(a):
> On Sat, Jul 04, 2020 at 01:38:59PM +0200, Clément Péron wrote:
> > From: Marcus Cooper
> >
> > Add a simple-soundcard to link audio between HDMI and I2S.
> >
> > Signed-off-by: Jernej Skrabec
> > Signed-off-by:
Hi!
Dne ponedeljek, 06. julij 2020 ob 07:29:37 CEST je Maxime Ripard napisal(a):
> Hi,
>
> On Sat, Jul 04, 2020 at 01:38:54PM +0200, Clément Péron wrote:
> > From: Jernej Skrabec
> >
> > Add a simple-soundcard to link audio between HDMI and I2S.
> >
> > Signed-off-by: Jernej Skrabec
> >
Hi Samuel!
Dne petek, 10. julij 2020 ob 07:44:33 CEST je Samuel Holland napisal(a):
> On 7/4/20 6:38 AM, Clément Péron wrote:
> > From: Jernej Skrabec
> >
> > H6 I2S is very similar to that in H3, except it supports up to 16
> > channels.
> >
> > Signed-off-by: Jernej Skrabec
> >
Dne sreda, 20. maj 2020 ob 23:43:40 CEST je Nicolas Dufresne napisal(a):
> Le mercredi 20 mai 2020 à 23:01 +0200, Jernej Skrabec a écrit :
> > VP8 in Cedrus shares same engine as H264.
> >
> > Note that it seems necessary to call bitstream parsing functions,
> > to parse frame header, otherwise
Hi,
Dne ponedeljek, 21. maj 2018 ob 10:12:53 CEST je Maxime Ripard napisal(a):
> On Sat, May 19, 2018 at 08:31:24PM +0200, Jernej Skrabec wrote:
> > Expand HDMI PHY clock driver to support second clock parent.
> >
> > Signed-off-by: Jernej Skrabec
> > ---
> >
> >
Hi,
Dne ponedeljek, 21. maj 2018 ob 10:01:47 CEST je Maxime Ripard napisal(a):
> Hi,
>
> On Sat, May 19, 2018 at 08:31:16PM +0200, Jernej Skrabec wrote:
> > TCON TOP main purpose is to configure whole display pipeline. It
> > determines relationships between mixers and TCONs, selects source TCON
Hi,
Dne ponedeljek, 21. maj 2018 ob 10:05:17 CEST je Maxime Ripard napisal(a):
> On Sat, May 19, 2018 at 08:31:17PM +0200, Jernej Skrabec wrote:
> > As already described in DT binding, TCON TOP is responsible for
> > configuring display pipeline. In this initial driver focus is on HDMI
> >
Hi,
Dne ponedeljek, 21. maj 2018 ob 10:07:59 CEST je Maxime Ripard napisal(a):
> On Sat, May 19, 2018 at 08:31:18PM +0200, Jernej Skrabec wrote:
> > If SoC has TCON TOP unit, it has to be configured from TCON, since it
> > has all information needed. Additionally, if it is TCON TV, it must also
>
Dne ponedeljek, 11. februar 2019 ob 15:39:03 CET je Maxime Ripard napisal(a):
> Introduce some basic H264 decoding support in cedrus. So far, only the
> baseline profile videos have been tested, and some more advanced features
> used in higher profiles are not even implemented.
>
> Signed-off-by:
Dne ponedeljek, 11. februar 2019 ob 15:39:03 CET je Maxime Ripard napisal(a):
> Introduce some basic H264 decoding support in cedrus. So far, only the
> baseline profile videos have been tested, and some more advanced features
> used in higher profiles are not even implemented.
>
> Signed-off-by:
Dne sreda, 16. januar 2019 ob 13:09:58 CET je Priit Laes napisal(a):
> On Thu, Jan 10, 2019 at 06:10:59PM +0100, Jernej Škrabec wrote:
> > Dne četrtek, 10. januar 2019 ob 10:15:48 CET je Priit Laes napisal(a):
> > > On Sun, Nov 04, 2018 at 07:26:39PM +0100, Jernej Skrabec wrote:
Dne četrtek, 17. januar 2019 ob 08:24:02 CET je Priit Laes napisal(a):
> On Wed, Jan 16, 2019 at 06:00:32PM +0100, Jernej Škrabec wrote:
> > Dne sreda, 16. januar 2019 ob 13:09:58 CET je Priit Laes napisal(a):
> > > On Thu, Jan 10, 2019 at 06:10:59PM +0100, Jernej Škrabec
Dne ponedeljek, 21. januar 2019 ob 10:57:57 CET je Chen-Yu Tsai napisal(a):
> On Mon, Jan 21, 2019 at 5:50 PM Maxime Ripard
wrote:
> > Hi,
> >
> > I'm a bit late to the party, sorry for that.
> >
> > On Sat, Jan 12, 2019 at 09:56:11AM +0800, Chen-Yu Tsai wrote:
> > > On Sat, Jan 12, 2019 at
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