On 11/18/2014 10:17 AM, Felipe Balbi wrote:
Hi,
On Tue, Nov 18, 2014 at 09:19:36AM -0500, Jorge Ramirez-Ortiz wrote:
Hi Felipe/Greg
Thanks for your comments on my previous attempt.
I think I addressed them here.
no you haven't. Read Documentation/SubmittingPatches, read the mailing
list
This patch adds USB3 support to the printer driver.
Tests used two binaries (host/device) to handle the file transfer
[gadget] $ dmesg
net2280 :02:00.0: usb_reset_338x: Defect 7374 FsmValue 0xf000
net2280 :02:00.0: usb_reinit_338x: Defect 7374 FsmValue f000
net2280
Add SS descriptors to support the capabilities provided by USB3 controller
drivers; unit tests run using a PLX 3380 [max transfer speed measured of 1Gbps]
This driver shall fallback to lower operating modes when the higher ones are
not available.
Signed-off-by: Jorge Ramirez-Ortiz jorge.ramirez
On 11/18/2014 01:00 PM, Felipe Balbi wrote:
Hi,
(fix your mailer, lines should be broken at 80-characters.
Documentation/email-clients.txt has tips)
On Tue, Nov 18, 2014 at 12:52:11PM -0500, Jorge Ramirez-Ortiz wrote:
On 11/18/2014 10:17 AM, Felipe Balbi wrote:
Hi,
On Tue, Nov 18, 2014
On 11/18/2014 03:47 PM, Felipe Balbi wrote:
Hi,
On Tue, Nov 18, 2014 at 03:41:43PM -0500, Jorge Ramirez-Ortiz wrote:
you have no clue what these mean, do you ? How about reading the USB
specification of even http://www.beyondlogic.org/usbnutshell/usb1.shtml
Unfortunately I do.
It was easier
Hi,
This patch adds USB3 support to the legacy gadget printer driver.
Applies cleanly on fc14f9c Linux 3.18-rc5.
Please could it be considered for inclusion?
regards,
Jorge
From f46d9b0d2160b30f14dee104657de865e9e2bc38 Mon Sep 17 00:00:00 2001
From: Jorge Ramirez-Ortiz jorge.ramirez
On 11/17/2014 07:54 PM, Greg KH wrote:
On Mon, Nov 17, 2014 at 06:30:28PM -0600, Felipe Balbi wrote:
Hi,
On Mon, Nov 17, 2014 at 06:19:54PM -0500, Jorge Ramirez-Ortiz wrote:
Hi,
This patch adds USB3 support to the legacy gadget printer driver.
Applies cleanly on fc14f9c Linux 3.18-rc5
the g_printer driver.
0) enable the net2280 on the g_printer:
--
From 8e306693839a77bfe3411a842d4d20acb9dae9e3 Mon Sep 17 00:00:00 2001
From: Jorge Ramirez-Ortiz jorge.ramirez-or...@linaro.org
Date: Mon, 17 Nov 2014 22:31:59 -0500
Subject
Doug/Jaehoon,
Were there any follow ups to this thread [1] from March 30, 2015?
We are seeing HLE errors on 3.18 and we are trying to determine if a solution
was ever delivered.
On inspection, I can't find anything specific in recent kernels that address
this particular issue (was the actual root
On 11/23/2015 07:11 PM, Jaehoon Chung wrote:
> Dear, Jorge.
>
> On 11/24/2015 02:29 AM, Jorge Ramirez-Ortiz wrote:
>> On 11/23/2015 11:57 AM, Doug Anderson wrote:
>>> Jorge,
>>>
>>> On Mon, Nov 23, 2015 at 6:10 AM, Jorge Ramirez-Ortiz
>>> <jo
On 11/23/2015 11:57 AM, Doug Anderson wrote:
> Jorge,
>
> On Mon, Nov 23, 2015 at 6:10 AM, Jorge Ramirez-Ortiz
> <jorge.ramirez-or...@linaro.org> wrote:
>> Doug/Jaehoon,
>>
>> Were there any follow ups to this thread [1] from March 30, 2015?
>> We are s
Enable support for higher baud rates (up to 3Mbps) in UART1 - required
for bluetooth transfers.
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-or...@linaro.org>
Tested-by: Jorge Ramirez-Ortiz <jorge.ramirez-or...@linaro.org>
---
arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts |
Allow to specify the clock frequency for any given port via the
assigned-clock-rates device tree property.
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-or...@linaro.org>
Tested-by: Jorge Ramirez-Ortiz <jorge.ramirez-or...@linaro.org>
---
drivers/tty/serial/amba-pl011.c | 5 +
On 08/19/2016 10:29 AM, Wei Xu wrote:
On 19/08/2016 07:57, Jorge Ramirez wrote:
On 07/11/2016 11:53 AM, Wei Xu wrote:
Hi Jorge,
On 08/07/2016 09:11, Jorge Ramirez-Ortiz wrote:
Enable support for higher baud rates (up to 3Mbps) in UART1 - required
for bluetooth transfers.
Signed-off
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-or...@linaro.org>
---
tools/spi/Makefile | 2 ++
1 file changed, 2 insertions(+)
diff --git a/tools/spi/Makefile b/tools/spi/Makefile
index cd0db62..3815b18 100644
--- a/tools/spi/Makefile
+++ b/tools/spi/Makefile
@@ -1,3 +1,5
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-or...@linaro.org>
---
tools/spi/Makefile | 4
1 file changed, 4 insertions(+)
diff --git a/tools/spi/Makefile b/tools/spi/Makefile
index cd0db62..d1845b0 100644
--- a/tools/spi/Makefile
+++ b/tools/spi/Makefile
@@ -1,4 +1,8
callback.
Signed-off-by: Jorge Ramirez-Ortiz <jrami...@baylibre.com>
---
drivers/base/regmap/internal.h | 1 +
drivers/base/regmap/regcache.c | 10 +-
drivers/base/regmap/regmap-debugfs.c | 17 +++--
drivers/base/regmap/regmap.c | 11 +++
4 files c
On 05/09/2018 10:39 AM, Mark Brown wrote:
On Wed, May 09, 2018 at 12:06:09AM +0200, Jorge Ramirez-Ortiz wrote:
Regmap only allows volatile access to registers when the client
supports both reads and writes.
This commit bypasses that limitation and enables volatile writes to
selected registers
On 05/11/2018 04:00 AM, Mark Brown wrote:
On Wed, May 09, 2018 at 01:49:21PM +0200, Jorge Ramirez-Ortiz wrote:
On 05/09/2018 10:39 AM, Mark Brown wrote:
I don't understand what voltile access means for write only devices.
Volatile means that we don't read the cache but go direct
On 05/13/2018 04:22 AM, Mark Brown wrote:
On Fri, May 11, 2018 at 12:29:42PM +0200, Jorge Ramirez-Ortiz wrote:
On 05/11/2018 04:00 AM, Mark Brown wrote:
We don't currently suppress writes except when regmap_update_bits()
notices that the modification was a noop. You probably want to be using
read errors.
Signed-off-by: Jorge Ramirez-Ortiz
---
drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c
b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c
index 4994f92..4959923 100644
-by: Jorge Ramirez-Ortiz <jrami...@baylibre.com>
Signed-off-by: Jorge Ramirez-Ortiz <jrami...@baylibre.com>
---
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
b/arch/
Extend configuring the MAC address from u-boot to all meson boards.
I didn't test this changeset but having checked libretech's u-boot
tree I believe it should just work.
Signed-off-by: Jorge Ramirez-Ortiz <jrami...@baylibre.com>
---
arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20
On 05/11/2018 04:00 AM, Mark Brown wrote:
On Wed, May 09, 2018 at 01:49:21PM +0200, Jorge Ramirez-Ortiz wrote:
On 05/09/2018 10:39 AM, Mark Brown wrote:
I don't understand what voltile access means for write only devices.
Volatile means that we don't read the cache but go direct
On 05/13/2018 04:22 AM, Mark Brown wrote:
On Fri, May 11, 2018 at 12:29:42PM +0200, Jorge Ramirez-Ortiz wrote:
On 05/11/2018 04:00 AM, Mark Brown wrote:
We don't currently suppress writes except when regmap_update_bits()
notices that the modification was a noop. You probably want to be using
callback.
Signed-off-by: Jorge Ramirez-Ortiz
---
drivers/base/regmap/internal.h | 1 +
drivers/base/regmap/regcache.c | 10 +-
drivers/base/regmap/regmap-debugfs.c | 17 +++--
drivers/base/regmap/regmap.c | 11 +++
4 files changed, 36 insertions(+), 3
On 05/09/2018 10:39 AM, Mark Brown wrote:
On Wed, May 09, 2018 at 12:06:09AM +0200, Jorge Ramirez-Ortiz wrote:
Regmap only allows volatile access to registers when the client
supports both reads and writes.
This commit bypasses that limitation and enables volatile writes to
selected registers
On 22/07/20, Jorge Ramirez-Ortiz wrote:
> Some secure elements like NXP's SE050 sit on I2C buses. For OP-TEE to
> control this type of cryptographic devices it needs coordinated access
> to the bus, so collisions and RUNTIME_PM dont get in the way.
>
> This trampoline driv
On 23/07/20, Jorge Ramirez-Ortiz wrote:
> The current code waits for data to be available before attempting a
> second read. However the second read would not be executed as the
> while loop exits.
>
> This fix does not wait if all data has been read and reads a second
> time if
On 05/08/20, Jens Wiklander wrote:
> On Wed, Aug 05, 2020 at 03:35:01PM +0200, Jorge Ramirez-Ortiz, Foundries
> wrote:
> > On 22/07/20, Jorge Ramirez-Ortiz wrote:
> > > Some secure elements like NXP's SE050 sit on I2C buses. For OP-TEE to
> > > control this type of
On 05/08/20, Sumit Garg wrote:
> Apologies for my delayed response as I was busy with some other tasks
> along with holidays.
no pb! was just making sure this wasnt falling through some cracks.
>
> On Fri, 24 Jul 2020 at 19:53, Jorge Ramirez-Ortiz, Foundries
> wrote:
> >
&
On 06/08/20, Sumit Garg wrote:
> On Thu, 6 Aug 2020 at 02:08, Jorge Ramirez-Ortiz, Foundries
> wrote:
> >
> > On 05/08/20, Sumit Garg wrote:
> > > Apologies for my delayed response as I was busy with some other tasks
> > > along with holidays.
> >
Allow OP-TEE to specify the number of retries in the adaptor.
Signed-off-by: Jorge Ramirez-Ortiz
---
drivers/tee/optee/rpc.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/tee/optee/rpc.c b/drivers/tee/optee/rpc.c
index 1e3614e4798f..2d46a9ecb1de 100644
--- a/drivers/tee
Some secure elements like NXP's SE050 sit on I2C buses. For OP-TEE to
control this type of cryptographic devices it needs coordinated access
to the bus, so collisions and RUNTIME_PM dont get in the way.
This trampoline driver allow OP-TEE to access them.
Signed-off-by: Jorge Ramirez-Ortiz
On 12/08/20, Jens Wiklander wrote:
> On Tue, Aug 11, 2020 at 07:55:31PM +0200, Jorge Ramirez-Ortiz wrote:
> > Some secure elements like NXP's SE050 sit on I2C buses. For OP-TEE to
> > control this type of cryptographic devices it needs coordinated access
> > to t
Some secure elements like NXP's SE050 sit on I2C buses. For OP-TEE to
control this type of cryptographic devices it needs coordinated access
to the bus, so collisions and RUNTIME_PM dont get in the way.
This trampoline driver allow OP-TEE to access them.
Signed-off-by: Jorge Ramirez-Ortiz
On 13/08/20, Jens Wiklander wrote:
> On Wed, Aug 12, 2020 at 02:06:52PM +0200, Jorge Ramirez-Ortiz wrote:
> > Some secure elements like NXP's SE050 sit on I2C buses. For OP-TEE to
> > control this type of cryptographic devices it needs coordinated access
> > to t
Some secure elements like NXP's SE050 sit on I2C buses. For OP-TEE to
control this type of cryptographic devices it needs coordinated access
to the bus, so collisions and RUNTIME_PM dont get in the way.
This trampoline driver allow OP-TEE to access them.
Signed-off-by: Jorge Ramirez-Ortiz
On 31/08/20, Randy Dunlap wrote:
> On 8/31/20 8:23 AM, Jorge Ramirez-Ortiz wrote:
> > When the optee driver is compiled into the kernel while the i2c core
> > is configured as a module, the i2c symbols are not available.
> >
> > This commit addresses the situation b
, optee=m
i2c=m, optee=y (not supported)
Reported-by: kernel test robot
Signed-off-by: Jorge Ramirez-Ortiz
---
v2: uses IS_REACHABLE instead of macro combination
This patch applies on top of
https://git.linaro.org/people/jens.wiklander/linux-tee.git/tag/?h=optee-i2c-for-v5.10
drivers
Signed-off-by: Niklas Cassel
Signed-off-by: Jorge Ramirez-Ortiz
Reviewed-by: Bjorn Andersson
---
drivers/clk/qcom/apcs-msm8916.c | 23 ---
1 file changed, 20 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/qcom/apcs-msm8916.c b/drivers/clk/qcom/apcs-msm8916.c
index
Make the output of the high frequency pll a clock provider.
On the QCS404 this PLL controls cpu frequency scaling.
Co-developed-by: Niklas Cassel
Signed-off-by: Niklas Cassel
Signed-off-by: Jorge Ramirez-Ortiz
Reviewed-by: Bjorn Andersson
Acked-by: Stephen Boyd
---
drivers/clk/qcom/hfpll.c
Signed-off-by: Niklas Cassel
Signed-off-by: Jorge Ramirez-Ortiz
Reviewed-by: Bjorn Andersson
---
drivers/clk/qcom/hfpll.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/clk/qcom/hfpll.c b/drivers/clk/qcom/hfpll.c
index a6de7101430c..87b7f46d27e0 100644
--- a/drivers/clk/qcom
k critical and
forcing the clock to be always enabled, addresses the above scenario
making sure the clock is not disabled but it continues to rely on the
firmware to enable the clock.
Co-developed-by: Niklas Cassel
Signed-off-by: Niklas Cassel
Signed-off-by: Jorge Ramirez-Ortiz
Reviewed-by: Bjorn
Limit the GPLL0_AO_OUT_MAIN operating frequency as per its hardware
specifications.
Co-developed-by: Niklas Cassel
Signed-off-by: Niklas Cassel
Signed-off-by: Jorge Ramirez-Ortiz
Reviewed-by: Bjorn Andersson
Acked-by: Stephen Boyd
---
drivers/clk/qcom/clk-alpha-pll.c | 8
drivers
Use the correct macro when registering the platform device.
Co-developed-by: Niklas Cassel
Signed-off-by: Niklas Cassel
Signed-off-by: Jorge Ramirez-Ortiz
Reviewed-by: Bjorn Andersson
---
drivers/mailbox/qcom-apcs-ipc-mailbox.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff
There is clock controller functionality in the APCS hardware block of
qcs404 devices similar to msm8916.
Co-developed-by: Niklas Cassel
Signed-off-by: Niklas Cassel
Signed-off-by: Jorge Ramirez-Ortiz
Reviewed-by: Bjorn Andersson
---
drivers/mailbox/qcom-apcs-ipc-mailbox.c | 8 +---
1
in the clock driver source code.
Co-developed-by: Niklas Cassel
Signed-off-by: Niklas Cassel
Signed-off-by: Jorge Ramirez-Ortiz
Reviewed-by: Rob Herring
Reviewed-by: Bjorn Andersson
---
.../mailbox/qcom,apcs-kpss-global.txt | 24 ---
1 file changed, 21 insertions(+), 3
Specify the clocks that feed the APCS mux/divider instead of using
default hardcoded values in the source code.
Co-developed-by: Niklas Cassel
Signed-off-by: Niklas Cassel
Signed-off-by: Jorge Ramirez-Ortiz
Reviewed-by: Bjorn Andersson
---
arch/arm64/boot/dts/qcom/qcs404.dtsi | 3 +++
1 file
node.
Signed-off-by: Jorge Ramirez-Ortiz
Reviewed-by: Bjorn Andersson
---
arch/arm64/boot/dts/qcom/msm8916.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi
b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 5ea9fb8f2f87..96dc7a12aa94
The high frequency pll functionality is required to enable CPU
frequency scaling operation.
Co-developed-by: Niklas Cassel
Signed-off-by: Niklas Cassel
Signed-off-by: Jorge Ramirez-Ortiz
Reviewed-by: Bjorn Andersson
---
arch/arm64/boot/dts/qcom/qcs404.dtsi | 9 +
1 file changed, 9
- the following commit will need to be
reverted to enable CPUFreq support
Author: Jorge Ramirez-Ortiz
Date: Thu Jul 25 12:41:36 2019 +0200
cpufreq: Add qcs404 to cpufreq-dt-platdev blacklist
Co-developed-by: Niklas Cassel
Signed-off-by: Niklas Cassel
Signed-off-by: Jorge Ramirez-Ortiz
The high frequency pll is required on compatible Qualcomm SoCs to
support the CPU frequency scaling feature.
Co-developed-by: Niklas Cassel
Signed-off-by: Niklas Cassel
Signed-off-by: Jorge Ramirez-Ortiz
Reviewed-by: Bjorn Andersson
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1
Remove unnecessary condition check and associated goto.
Signed-off-by: Jorge Ramirez-Ortiz
---
drivers/spi/spi-qup.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
index 974a8ce58b68..314d91b95a16 100644
--- a/drivers/spi/spi-qup.c
+++ b
On 21/08/20, Jens Wiklander wrote:
> On Fri, Aug 14, 2020 at 01:12:21PM +0200, Jorge Ramirez-Ortiz wrote:
> > Some secure elements like NXP's SE050 sit on I2C buses. For OP-TEE to
> > control this type of cryptographic devices it needs coordinated access
> > to t
, optee=m
i2c=m, optee=y (not supported)
Reported-by: kernel test robot
Signed-off-by: Jorge Ramirez-Ortiz
---
This patch applies on top of
https://git.linaro.org/people/jens.wiklander/linux-tee.git/tag/?h=optee-i2c-for-v5.10
drivers/tee/optee/rpc.c | 2 ++
1 file changed, 2 insertions
On 06/08/20, Sumit Garg wrote:
> On Thu, 6 Aug 2020 at 12:00, Jorge Ramirez-Ortiz, Foundries
> wrote:
> >
> > On 06/08/20, Sumit Garg wrote:
> > > On Thu, 6 Aug 2020 at 02:08, Jorge Ramirez-Ortiz, Foundries
> > > wrote:
> > > >
> > > &g
on
the first read.
Worth noticing that since msleep(0) schedules a one jiffy timeout is
better to skip such a call.
Signed-off-by: Jorge Ramirez-Ortiz
Reviewed-by: Sumit Garg
---
drivers/char/hw_random/optee-rng.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/char
on
the first read.
Worth noticing that since msleep(0) schedules a one jiffy timeout is
better to skip such a call.
Signed-off-by: Jorge Ramirez-Ortiz
Reviewed-by: Sumit Garg
---
drivers/char/hw_random/optee-rng.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/char
Data rates of MAX_UINT32 will schedule an unnecessary one jiffy
timeout on the call to msleep. Avoid this scenario by using 0 as the
unlimited data rate.
Signed-off-by: Jorge Ramirez-Ortiz
Reviewed-by: Sumit Garg
---
drivers/char/hw_random/optee-rng.c | 2 +-
1 file changed, 1 insertion(+), 1
On 22/09/20, Jens Wiklander wrote:
> On Wed, Sep 16, 2020 at 05:27:32PM +0200, Jorge Ramirez-Ortiz wrote:
> > Allow OP-TEE to specify the number of retries in the adaptor.
> >
> > Signed-off-by: Jorge Ramirez-Ortiz
> > ---
> > drivers/tee/optee/rpc.c |
On 23/09/20, Jorge Ramirez-Ortiz, Foundries wrote:
> On 22/09/20, Jens Wiklander wrote:
> > On Wed, Sep 16, 2020 at 05:27:32PM +0200, Jorge Ramirez-Ortiz wrote:
> > > Allow OP-TEE to specify the number of retries in the adaptor.
> > >
> > >
On 23/09/20, Jens Wiklander wrote:
> On Wed, Sep 23, 2020 at 01:26:31PM +0200, Jorge Ramirez-Ortiz, Foundries
> wrote:
> > On 23/09/20, Jorge Ramirez-Ortiz, Foundries wrote:
> > > On 22/09/20, Jens Wiklander wrote:
> > > > On Wed, Sep 16, 2020 at 05:27:32PM
On 26/01/21, Arnd Bergmann wrote:
> On Tue, Jan 26, 2021 at 9:08 AM Jorge Ramirez-Ortiz, Foundries
> wrote:
> >
> > On 25/01/21, Arnd Bergmann wrote:
> > > From: Arnd Bergmann
> > >
> > > Storing a bogus i2c_client structure on the stack adds ove
On 25/01/21, Arnd Bergmann wrote:
> From: Arnd Bergmann
>
> Storing a bogus i2c_client structure on the stack adds overhead and
> causes a compile-time warning:
>
> drivers/tee/optee/rpc.c:493:6: error: stack frame size of 1056 bytes in
> function 'optee_handle_rpc'
On 26/01/21, Sai Prakash Ranjan wrote:
> As per register documentation, QCOM_WDT_ENABLE_IRQ which is BIT(1)
> of watchdog control register is wakeup interrupt enable bit and
> not related to bark interrupt at all, BIT(0) is used for that.
> So remove incorrect usage of this bit when supporting
The mailbox length is 0x1000 hence the max_register value is 0xFFC.
Signed-off-by: Jorge Ramirez-Ortiz
---
drivers/mailbox/qcom-apcs-ipc-mailbox.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
b/drivers/mailbox/qcom-apcs-ipc
The max register is 0x23004 as per the manual (the current
max_register that this commit is fixing is actually out of bounds).
Fixes: 892df0191b29 ("clk: qcom: Add QCS404 TuringCC")
Signed-off-by: Jorge Ramirez-Ortiz
---
v2: add Fixes tag
drivers/clk/qcom/turingcc-qcs404.c | 2
The mailbox length is 0x1000 hence the max_register value is 0xFFC.
Fixes: c6a8b171ca8e ("mailbox: qcom: Convert APCS IPC driver to use
regmap")
Signed-off-by: Jorge Ramirez-Ortiz
---
v2: added Fixes tag
drivers/mailbox/qcom-apcs-ipc-mailbox.c | 2 +-
1 file changed, 1 inser
On 09/09/19 03:21:16, Stephen Boyd wrote:
> Quoting Jorge Ramirez-Ortiz (2019-08-26 09:45:07)
> > @@ -76,10 +88,11 @@ static int qcom_apcs_msm8916_clk_probe(struct
> > platform_device *pdev)
> > a53cc->src_shift = 8;
> > a53cc->parent_map = gpll0_a
On 09/09/19 09:17:03, Stephen Boyd wrote:
> Quoting Jorge Ramirez-Ortiz, Linaro (2019-09-09 07:17:40)
> > On 09/09/19 03:21:16, Stephen Boyd wrote:
> > > Quoting Jorge Ramirez-Ortiz (2019-08-26 09:45:07)
> > > > @@ -76,10 +88,11 @@ static int qcom
On 01/06/20, Sumit Garg wrote:
> Hi Jorge,
hey
>
> On Mon, 1 Jun 2020 at 04:41, Jorge Ramirez-Ortiz wrote:
> >
> > Some secure elements like NXP's SE050 sit on I2C buses. For OP-TEE to
> > control this type of cryptographic devices it needs coordinated access
&g
Some secure elements like NXP's SE050 sit on I2C buses. For OP-TEE to
control this type of cryptographic devices it needs coordinated access
to the bus, so collisions and RUNTIME_PM dont get in the way.
This trampoline driver allow OP-TEE to access them.
Signed-off-by: Jorge Ramirez-Ortiz
Some secure elements like NXP's SE050 sit on I2C buses. For OP-TEE to
control this type of cryptographic devices it needs coordinated access
to the bus, so collisions and RUNTIME_PM dont get in the way.
This trampoline driver allow OP-TEE to access them.
Signed-off-by: Jorge Ramirez-Ortiz
-by: Jorge Ramirez-Ortiz
Signed-off-by: Jorge Ramirez-Ortiz
---
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc
Extend configuring the MAC address from u-boot to all meson boards.
I didn't test this changeset but having checked libretech's u-boot
tree I believe it should just work.
Signed-off-by: Jorge Ramirez-Ortiz
---
arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi| 1 +
arch/arm64
no further information dumped to the console).
This patch replaces the PIO byte accessor with the word accessor
already used in PIO mode.
Signed-off-by: Jorge Ramirez-Ortiz
---
drivers/tty/serial/msm_serial.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/
no further information dumped to the console).
This patch replaces the PIO byte accessor with the word accessor
already used in PIO mode.
Fixes: 68252424a7c7 ("tty: serial: msm: Support big-endian CPUs")
Cc: sta...@vger.kernel.org
Signed-off-by: Jorge Ramirez-Ortiz
Reviewed-by: Bjorn And
.
Signed-off-by: Jorge Ramirez-Ortiz
---
drivers/spi/spi-qup.c | 51 ++-
1 file changed, 45 insertions(+), 6 deletions(-)
diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
index 974a8ce58b68..0a2ffd2f968a 100644
--- a/drivers/spi/spi-qup.c
+++ b/drivers
The function msm_wait_for_xmitr can be taken with interrupts
disabled. In order to avoid a potential system lockup - demonstrated
under stress testing conditions on SoC QCS404/5 - make sure we wait
for a bounded amount of time.
Tested on SoC QCS404.
Signed-off-by: Jorge Ramirez-Ortiz
The function msm_wait_for_xmitr can be taken with interrupts
disabled. In order to avoid a potential system lockup - demonstrated
under stress testing conditions on SoC QCS404/5 - make sure we wait
for a bounded amount of time.
Tested on SoC QCS404.
Signed-off-by: Jorge Ramirez-Ortiz
The function msm_wait_for_xmitr can be taken with interrupts
disabled. In order to avoid a potential system lockup - demonstrated
under stress testing conditions on SoC QCS404/5 - make sure we wait
for a bounded amount of time.
Tested on SoC QCS404.
Signed-off-by: Jorge Ramirez-Ortiz
---
v2
Limit the GPLL0_AO_OUT_MAIN operating frequency as per its hardware
specifications.
Co-developed-by: Niklas Cassel
Signed-off-by: Niklas Cassel
Signed-off-by: Jorge Ramirez-Ortiz
Reviewed-by: Bjorn Andersson
Acked-by: Stephen Boyd
---
drivers/clk/qcom/clk-alpha-pll.c | 8
drivers
k critical and
forcing the clock to be always enabled, addresses the above scenario
making sure the clock is not disabled but it continues to rely on the
firmware to enable the clock.
Co-developed-by: Niklas Cassel
Signed-off-by: Niklas Cassel
Signed-off-by: Jorge Ramirez-Ortiz
Reviewed-by: Bjorn
Signed-off-by: Niklas Cassel
Signed-off-by: Jorge Ramirez-Ortiz
Reviewed-by: Bjorn Andersson
---
drivers/clk/qcom/hfpll.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/clk/qcom/hfpll.c b/drivers/clk/qcom/hfpll.c
index a6de7101430c..87b7f46d27e0 100644
--- a/drivers/clk/qcom
Signed-off-by: Niklas Cassel
Signed-off-by: Jorge Ramirez-Ortiz
Reviewed-by: Bjorn Andersson
---
drivers/clk/qcom/apcs-msm8916.c | 23 ---
1 file changed, 20 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/qcom/apcs-msm8916.c b/drivers/clk/qcom/apcs-msm8916.c
index
- the following commit will need to be
reverted to enable CPUFreq support
Author: Jorge Ramirez-Ortiz
Date: Thu Jul 25 12:41:36 2019 +0200
cpufreq: Add qcs404 to cpufreq-dt-platdev blacklist
Co-developed-by: Niklas Cassel
Signed-off-by: Niklas Cassel
Signed-off-by: Jorge Ramirez-Ortiz
Specify the clocks that feed the APCS mux/divider instead of using
default hardcoded values in the source code.
Co-developed-by: Niklas Cassel
Signed-off-by: Niklas Cassel
Signed-off-by: Jorge Ramirez-Ortiz
Reviewed-by: Bjorn Andersson
---
arch/arm64/boot/dts/qcom/qcs404.dtsi | 3 +++
1 file
The high frequency pll functionality is required to enable CPU
frequency scaling operation.
Co-developed-by: Niklas Cassel
Signed-off-by: Niklas Cassel
Signed-off-by: Jorge Ramirez-Ortiz
Reviewed-by: Bjorn Andersson
---
arch/arm64/boot/dts/qcom/qcs404.dtsi | 9 +
1 file changed, 9
node.
Signed-off-by: Jorge Ramirez-Ortiz
Reviewed-by: Bjorn Andersson
---
arch/arm64/boot/dts/qcom/msm8916.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi
b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 5ea9fb8f2f87..96dc7a12aa94
The high frequency pll is required on compatible Qualcomm SoCs to
support the CPU frequency scaling feature.
Co-developed-by: Niklas Cassel
Signed-off-by: Niklas Cassel
Signed-off-by: Jorge Ramirez-Ortiz
Reviewed-by: Bjorn Andersson
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1
Make the output of the high frequency pll a clock provider.
On the QCS404 this PLL controls cpu frequency scaling.
Co-developed-by: Niklas Cassel
Signed-off-by: Niklas Cassel
Signed-off-by: Jorge Ramirez-Ortiz
Reviewed-by: Bjorn Andersson
Acked-by: Stephen Boyd
---
drivers/clk/qcom/hfpll.c
in the clock driver source code.
Co-developed-by: Niklas Cassel
Signed-off-by: Niklas Cassel
Signed-off-by: Jorge Ramirez-Ortiz
Reviewed-by: Rob Herring
Reviewed-by: Bjorn Andersson
---
.../mailbox/qcom,apcs-kpss-global.txt | 24 ---
1 file changed, 21 insertions(+), 3
There is clock controller functionality in the APCS hardware block of
qcs404 devices similar to msm8916.
Co-developed-by: Niklas Cassel
Signed-off-by: Niklas Cassel
Signed-off-by: Jorge Ramirez-Ortiz
Reviewed-by: Bjorn Andersson
---
drivers/mailbox/qcom-apcs-ipc-mailbox.c | 8 +---
1
Use the correct macro when registering the platform device.
Co-developed-by: Niklas Cassel
Signed-off-by: Niklas Cassel
Signed-off-by: Jorge Ramirez-Ortiz
Reviewed-by: Bjorn Andersson
---
drivers/mailbox/qcom-apcs-ipc-mailbox.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff
to support CPR do conflict with the
configuration required for CPUFreq.
In particular, the following commit for CPR - already merged - will
need to be reverted in order to enable CPUFreq.
Author: Jorge Ramirez-Ortiz
Date: Thu Jul 25 12:41:36 2019 +0200
cpufreq: Add qcs404
ng support
Jorge Ramirez-Ortiz (14):
clk: qcom: gcc: limit GPLL0_AO_OUT operating frequency
mbox: qcom: add APCS child device for QCS404
mbox: qcom: replace integer with valid macro
dt-bindings: mailbox: qcom: Add clock-name optional property
clk: qcom: apcs-msm8916: get parent clock nam
Support dynamic voltage and frequency scaling on qcs404.
Co-developed-by: Niklas Cassel
Signed-off-by: Niklas Cassel
Signed-off-by: Jorge Ramirez-Ortiz
---
arch/arm64/boot/dts/qcom/qcs404.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs404
Use the correct macro when registering the platform device.
Co-developed-by: Niklas Cassel
Signed-off-by: Niklas Cassel
Signed-off-by: Jorge Ramirez-Ortiz
---
drivers/mailbox/qcom-apcs-ipc-mailbox.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mailbox/qcom-apcs
The high frequency pll is required on compatible Qualcomm SoCs to
support the CPU frequency scaling feature.
Co-developed-by: Niklas Cassel
Signed-off-by: Niklas Cassel
Signed-off-by: Jorge Ramirez-Ortiz
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch
1 - 100 of 235 matches
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