Add an API to get the next unreserved BAR starting from a given BAR
number that can be used by the endpoint function.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/endpoint/pci-epc-core.c | 26 ++
include/linux/pci-epc.h | 2 ++
2 files changed, 24
Remove unused pci_epf_match_device() function added in pci-epf-core.c
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/endpoint/pci-epf-core.c | 16
include/linux/pci-epf.h | 2 --
2 files changed, 18 deletions(-)
diff --git a/drivers/pci/endpoint/pci-epf
ount 64 bit BAR while
returning the first free unreserved BAR.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/endpoint/pci-epc-core.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/endpoint/pci-epc-core.c
b/drivers/pci/endpoint/pci-e
Hi Randy,
On 06/09/20 3:38 am, Randy Dunlap wrote:
> On 9/4/20 12:50 AM, Kishon Vijay Abraham I wrote:
>> Add documentation to help users use pci-epf-ntb function driver and
>> existing host side NTB infrastructure for NTB functionality.
>>
>> Signed-off
Add PCIe device tree nodes (both RC and EP) for the four
PCIe instances here.
Also add the missing translations required in the "ranges"
DT property of cbass_main to access all the four PCIe
instances.
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm64/boot/dts/ti/k3-j721e-main.
syscon dt-nodes to "syscon" instead of pcieX-ctrl.
2) Add TI specific compatible for "syscon" DT nodes
3) Add information about appending "ranges" property to access all PCIe
instances in commit log.
Kishon Vijay Abraham I (2):
arm64: dts: ti: k3-j721e-main: Add
J721E Common Processor Board has PCIe connectors for the 1st three PCIe
instances. Configure the three PCIe instances in RC mode and disable the
4th PCIe instance.
Signed-off-by: Kishon Vijay Abraham I
---
.../dts/ti/k3-j721e-common-proc-board.dts | 80 +++
1 file changed
Hi Nishanth,
On 14/09/20 6:44 pm, Nishanth Menon wrote:
> On 17:43-20200914, Kishon Vijay Abraham I wrote:
>> Hi Nishanth,
>>
>> On 14/09/20 5:22 pm, Nishanth Menon wrote:
>>> On 16:53-20200914, Kishon Vijay Abraham I wrote:
>>>> Hi Rob,
>>>>
Hi Nishanth,
On 14/09/20 5:22 pm, Nishanth Menon wrote:
> On 16:53-20200914, Kishon Vijay Abraham I wrote:
>> Hi Rob,
>>
>> On 02/09/20 1:07 pm, Kishon Vijay Abraham I wrote:
>>> Hi Rob,
>>>
>>> On 02/09/20 10:24 am, Kishon Vijay Abraham I wrote:
Hi Rob,
On 02/09/20 1:07 pm, Kishon Vijay Abraham I wrote:
> Hi Rob,
>
> On 02/09/20 10:24 am, Kishon Vijay Abraham I wrote:
>> Hi Nishanth,
>>
>> On 01/09/20 8:22 pm, Nishanth Menon wrote:
>>> On 19:36-20200901, Kishon Vijay Abraham I wrote:
>>>>
Hi Jason,
On 01/09/20 2:20 pm, Jason Wang wrote:
>
> On 2020/9/1 下午1:24, Kishon Vijay Abraham I wrote:
>> Hi,
>>
>> On 28/08/20 4:04 pm, Cornelia Huck wrote:
>>> On Thu, 9 Jul 2020 14:26:53 +0800
>>> Jason Wang wrote:
>>>
>>> [Let
c, to enable DMA support
> - MCU CPSW2g DT nodes to enable networking
https://pastebin.ubuntu.com/p/FPVggcdQ6T/
Tested-by: Kishon Vijay Abraham I
Thanks
Kishon
>
> This series depends on:
> - [PATCH v2 0/4] arm64: Initial support for Texas Instrument's J7200
> Platform [1]
&
Hi Milind,
On 08/09/20 7:45 pm, Milind Parab wrote:
Hi Kishon,
-Original Message-
From: Laurent Pinchart
Sent: Thursday, September 3, 2020 9:00 PM
To: Kishon Vijay Abraham I
Cc: Swapnil Kashinath Jakhade ; vk...@kernel.org;
linux-kernel@vger.kernel.org; max...@cerno.tech; Milind
be populated by the function driver if it has to
expose any function specific attributes and pci_epf_type_add_cfs() to
be invoked by pci-ep-cfs.c when sub-directory to main function directory
is created.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/endpoint/pci-epf-core.c |
ount 64 bit BAR while
returning the first free unreserved BAR.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/endpoint/pci-epc-core.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/endpoint/pci-epc-core.c
b/drivers/pci/endpoint/pci-e
directly write to the physical address (in outbound
region) of the other interface to ring doorbell using MSI.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/endpoint/pci-epc-core.c | 40 +
include/linux/pci-epc.h | 7 +
2 files changed, 47 insertions
ributes that has to be exposed to the user.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/endpoint/pci-ep-cfs.c | 23 +++
include/linux/pci-epf.h | 3 +++
2 files changed, 26 insertions(+)
diff --git a/drivers/pci/endpoint/pci-ep-cfs.c
b/drivers/p
device has configurable number of memory windows
(Max 4), configurable number of doorbell (Max 32), and configurable
number of scratch-pad registers.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/ntb/hw/Kconfig | 1 +
drivers/ntb/hw/Makefile | 1 +
drivers/ntb/hw/epf
Add documentation to help users use pci-epf-ntb function driver and
existing host side NTB infrastructure for NTB functionality.
Signed-off-by: Kishon Vijay Abraham I
---
Documentation/PCI/endpoint/index.rst | 1 +
Documentation/PCI/endpoint/pci-ntb-howto.rst | 160
Implement ->msi_map_irq() ops in order to map physical address to
MSI address and return MSI data.
Signed-off-by: Kishon Vijay Abraham I
---
.../pci/controller/cadence/pcie-cadence-ep.c | 50 +++
drivers/pci/endpoint/pci-epc-core.c | 7 ++-
include/linux/pci-ep
Invoke ntb_link_enable() to enable the NTB/PCIe link on the local
or remote side of the bridge.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/ntb/test/ntb_tool.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/ntb/test/ntb_tool.c b/drivers/ntb/test/ntb_tool.c
index b7bf3f863d79
Add binding documentation for pci-ntb endpoint function that helps in
adding and configuring pci-ntb endpoint function.
Signed-off-by: Kishon Vijay Abraham I
---
.../PCI/endpoint/function/binding/pci-ntb.rst | 38 +++
Documentation/PCI/endpoint/index.rst | 1 +
2 files
Add TI J721E device to the pci id database. Since this device has
a configurable PCIe endpoint, it could be used with different
drivers.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/misc/pci_endpoint_test.c | 1 -
include/linux/pci_ids.h | 1 +
2 files changed, 1 insertion(+), 1
Add a new endpoint function driver to provide NTB functionality
using multiple PCIe endpoint instances.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/endpoint/functions/Kconfig | 12 +
drivers/pci/endpoint/functions/Makefile |1 +
drivers/pci/endpoint/functions/pci-epf
/contributions/395/attachments/284/481/Implementing_NTB_Controller_Using_PCIe_Endpoint_-_final.pdf
[2] -> http://lore.kernel.org/r/20190926112933.8922-1-kis...@ti.com
[3] -> http://lore.kernel.org/r/20200514145927.17555-1-kis...@ti.com
[4] -> http://lore.kernel.org/r/20200611130525.22746-1-
. This is in
preparation for adding NTB endpoint function driver.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/endpoint/functions/pci-epf-test.c | 11 ++--
drivers/pci/endpoint/pci-ep-cfs.c | 6 +-
drivers/pci/endpoint/pci-epc-core.c | 50
drivers/pci
Add specification for the *PCI NTB* function device. The endpoint function
driver and the host PCI driver should be created based on this
specification.
Signed-off-by: Kishon Vijay Abraham I
---
Documentation/PCI/endpoint/index.rst | 1 +
.../PCI/endpoint/pci-ntb-function.rst
Add an API to get the next unreserved BAR starting from a given BAR
number that can be used by the endpoint function.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/endpoint/pci-epc-core.c | 26 ++
include/linux/pci-epc.h | 2 ++
2 files changed, 24
single EPC device with a EPF device will continue to work.
Signed-off-by: Kishon Vijay Abraham I
---
.../PCI/endpoint/pci-endpoint-cfs.rst | 10 ++
drivers/pci/endpoint/pci-ep-cfs.c | 147 ++
2 files changed, 157 insertions(+)
diff --git a/Documentat
Remove unused pci_epf_match_device() function added in pci-epf-core.c
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/endpoint/pci-epf-core.c | 16
include/linux/pci-epf.h | 2 --
2 files changed, 18 deletions(-)
diff --git a/drivers/pci/endpoint/pci-epf
Modify pci_epc_get_next_free_bar() and pci_epc_get_first_free_bar() to
return error values if there are no free BARs available.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/endpoint/functions/pci-epf-test.c | 2 ++
drivers/pci/endpoint/pci-epc-core.c | 12
Jakhade wrote:
>>>>> Use generic PHY framework function phy_set_attrs() to set number
>>>>> of lanes and maximum link rate supported by PHY.
>>>>>
>>>>> Signed-off-by: Swapnil Jakhade
>>>>> Acked-by: Kishon Vijay Abraham I
Hi Rob,
On 02/09/20 10:24 am, Kishon Vijay Abraham I wrote:
Hi Nishanth,
On 01/09/20 8:22 pm, Nishanth Menon wrote:
On 19:36-20200901, Kishon Vijay Abraham I wrote:
Add PCIe device tree node (both RC and EP) for the four
PCIe instances here.
Signed-off-by: Kishon Vijay Abraham I
---
arch
Hi Nishanth,
On 01/09/20 8:22 pm, Nishanth Menon wrote:
On 19:36-20200901, Kishon Vijay Abraham I wrote:
Add PCIe device tree node (both RC and EP) for the four
PCIe instances here.
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 218
version sent to
http://lore.kernel.org/r/20200724055604.31498-1-kis...@ti.com
Kishon Vijay Abraham I (2):
arm64: dts: ti: k3-j721e-main: Add PCIe device tree nodes
arm64: dts: ti: k3-j721e-common-proc-board: Configure the PCIe
instances
.../dts/ti/k3-j721e-common-proc-board.dts | 80
Add PCIe device tree node (both RC and EP) for the four
PCIe instances here.
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 218 ++
arch/arm64/boot/dts/ti/k3-j721e.dtsi | 5 +-
2 files changed, 222 insertions(+), 1 deletion
J721E Common Processor Board has PCIe connectors for the 1st three PCIe
instances. Configure the three PCIe instances in RC mode and disable the
4th PCIe instance.
Signed-off-by: Kishon Vijay Abraham I
---
.../dts/ti/k3-j721e-common-proc-board.dts | 80 +++
1 file changed
ogize beforehand for
any confusion I might spread.]
On 2020/7/8 下午9:13, Kishon Vijay Abraham I wrote:
Hi Jason,
On 7/8/2020 4:52 PM, Jason Wang wrote:
On 2020/7/7 下午10:45, Kishon Vijay Abraham I wrote:
Hi Jason,
On 7/7/2020 3:17 PM, Jason Wang wrote:
On 2020/7/6 下午5:32, Kishon Vijay Abraham I wrote
Hi Mathieu,
On 15/07/20 10:45 pm, Mathieu Poirier wrote:
Hey Kishon,
On Wed, Jul 08, 2020 at 06:43:45PM +0530, Kishon Vijay Abraham I wrote:
Hi Jason,
On 7/8/2020 4:52 PM, Jason Wang wrote:
On 2020/7/7 下午10:45, Kishon Vijay Abraham I wrote:
Hi Jason,
On 7/7/2020 3:17 PM, Jason Wang wrote
Hi Swapnil,
On 8/7/2020 3:42 PM, Swapnil Jakhade wrote:
> Torrent PHY can be used in different multi-link multi-protocol
> configurations including protocols other than DisplayPort also,
> such as PCIe, USB, SGMII, QSGMII etc. Update the bindings to have
> support for these configurations.
>
> Si
Add PCIe device tree node (both RC and EP) for the four
PCIe instances here.
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 218 ++
arch/arm64/boot/dts/ti/k3-j721e.dtsi | 5 +-
2 files changed, 222 insertions(+), 1 deletion
J721E Common Processor Board has PCIe connectors for the 1st three PCIe
instances. Configure the three PCIe instances in RC mode and disable the
4th PCIe instance.
Signed-off-by: Kishon Vijay Abraham I
---
.../dts/ti/k3-j721e-common-proc-board.dts | 80 +++
1 file changed
ux/kernel/git/lpieralisi/pci.git/log/?h=pci/cadence
[2] ->
https://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux.git/log/?h=ti-k3-next
Kishon Vijay Abraham I (2):
arm64: dts: ti: k3-j721e-main: Add PCIe device tree nodes
arm64: dts: ti: k3-j721e-common-proc-board: Configure the PCIe
ins
J721E Common Processor Board has PCIe connectors for the 1st three PCIe
instances. Configure the three PCIe instances in RC mode and disable the
4th PCIe instance.
Signed-off-by: Kishon Vijay Abraham I
---
.../dts/ti/k3-j721e-common-proc-board.dts | 80 +++
1 file changed
ux/kernel/git/lpieralisi/pci.git/log/?h=pci/cadence
[2] ->
https://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux.git/log/?h=ti-k3-next
Kishon Vijay Abraham I (2):
arm64: dts: ti: k3-j721e-main: Add PCIe device tree nodes
arm64: dts: ti: k3-j721e-common-proc-board: Configure the PCIe
ins
Add PCIe device tree node (both RC and EP) for the four
PCIe instances here.
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 218 ++
arch/arm64/boot/dts/ti/k3-j721e.dtsi | 5 +-
2 files changed, 222 insertions(+), 1 deletion
On 7/23/2020 3:32 PM, Lorenzo Pieralisi wrote:
> On Wed, Jul 22, 2020 at 04:33:02PM +0530, Kishon Vijay Abraham I wrote:
>> TI's J721E SoC uses Cadence PCIe core to implement both RC mode
>> and EP mode.
>>
>> The high level features are:
>> *) Su
On 7/17/2020 12:20 PM, Swapnil Jakhade wrote:
> Use generic PHY framework function phy_set_attrs() to set number
> of lanes and maximum link rate supported by PHY.
>
> Signed-off-by: Swapnil Jakhade
Acked-by: Kishon Vijay Abraham I
> ---
> drivers/phy/cadence/phy-cad
f-by: Yuti Amonkar
> Signed-off-by: Swapnil Jakhade
Acked-by: Kishon Vijay Abraham I
> ---
> include/linux/phy/phy.h | 26 ++
> 1 file changed, 26 insertions(+)
>
> diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
> index bcee8eba62b3..5d
"mem" is not a memory resource and it overlaps with PCIe config space
and memory region. Remove "mem" from reg binding.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Rob Herring
---
.../devicetree/bindings/pci/cdns,cdns-pcie-host.yaml | 8 +++-
1 file changed
Add host mode dt-bindings for TI's J721E SoC.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Rob Herring
---
.../bindings/pci/ti,j721e-pci-host.yaml | 113 ++
1 file changed, 113 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/ti,j721
to disable interrupts while modifying PCI_STATUS
register while raising legacy interrupt since PCI_STATUS is accessible
by both remote RC and EP and time between read and write should be
minimized.
Signed-off-by: Kishon Vijay Abraham I
---
.../pci/controller/cadence/pcie-cadence-ep.c | 4 +
d
Add PCIe EP mode dt-bindings for TI's J721E SoC.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Rob Herring
---
.../bindings/pci/ti,j721e-pci-ep.yaml | 94 +++
1 file changed, 94 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/ti,j721
) from "struct cdns_pcie_epf" that gets initialized in
->set_bar() call back function.
Signed-off-by: Alan Douglas
[kis...@ti.com: Re-implement MSIX support in accordance with the
re-designed core MSI-X interfaces]
Signed-off-by: Kishon Vijay Abraham I
---
.../pci/controller/cadenc
SoC require the absolute address to be programmed in the ATU and
not just the offset. Add new *ops* for CPU addr fixup for the platform
drivers to provide the correct address to be programmed in the ATU.
Signed-off-by: Kishon Vijay Abraham I
---
.../pci/controller/cadence/pcie-cadence
management register to configure Vendor ID and Subsystem Vendor
ID.
Fixes: 1b79c5284439 ("PCI: cadence: Add host driver for Cadence PCIe
controller")
Reviewed-by: Rob Herring
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/cadence/pcie-cadence-host.c | 9 +++--
1 file c
Add J721E in pci_device_id table so that pci-epf-test can be used
for testing PCIe EP in J721E.
Reviewed-by: Rob Herring
Signed-off-by: Kishon Vijay Abraham I
---
drivers/misc/pci_endpoint_test.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/misc/pci_endpoint_test.c b
Add Kishon Vijay Abraham I as MAINTAINER for TI J721E SoC PCIe.
Acked-by: Rob Herring
Signed-off-by: Kishon Vijay Abraham I
---
MAINTAINERS | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 68f21d46614c..6df9b54d3003 100644
--- a/MAINTAINERS
support
*) Supports upto GEN3 speed mode
*) Supports SR-IOV capability
*) Ability to route all transactions via SMMU (support will be added
in a later patch).
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/cadence/Kconfig| 23 +
drivers/pci/controller/cadence
Add a macro for aligning down a pointer. This is useful to get an
aligned register address when a device allows only word access and
doesn't allow half word or byte access.
Acked-by: Rob Herring
Signed-off-by: Kishon Vijay Abraham I
---
include/linux/kernel.h | 1 +
1 file changed, 1 inse
c() in the error path. Fix it here.
Fixes: bd22885aa188 ("PCI: cadence: Refactor driver to use as a core library")
Reviewed-by: Rob Herring
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/cadence/pcie-cadence-ep.c | 9 ++---
drivers/pci/controller/cadence/pci
: Kishon Vijay Abraham I
Reviewed-by: Rob Herring
---
.../pci/controller/cadence/pcie-cadence-ep.c | 8
.../controller/cadence/pcie-cadence-host.c| 28 ++
drivers/pci/controller/cadence/pcie-cadence.h | 37 ++-
3 files changed, 72 insertions(+), 1 deletion
Certain platforms like TI's J721E allows only 32-bit configuration
space access. In such cases pci_generic_config_read and
pci_generic_config_write cannot be used. Add support in Cadence core
to let pci_host_bridge have custom pci_ops.
Signed-off-by: Kishon Vijay Abraham I
---
driver
@ti.com
[8] -> http://lore.kernel.org/r/20200708093018.28474-1-kis...@ti.com
[9] -> http://lore.kernel.org/r/20200713110141.13156-1-kis...@ti.com
[10] -> http://lore.kernel.org/r/20200521080153.5902-1-kis...@ti.com
Alan Douglas (1):
PCI: cadence: Add MSI-X support to Endpoint driver
<0x0200 0x0 0x0 0x0 0x0 0x1 0x0>;
Since there is no BAR which can hold 2^48 size, NO_MATCH_BAR will be
used here.
Legacy device tree binding compatibility is maintained by retaining
support for "cdns,no-bar-match-nbits".
Signed-off-by: Kishon Vijay Abraham I
---
Cha
Hi Lorenzo,
On 7/21/2020 9:19 PM, Lorenzo Pieralisi wrote:
> On Mon, Jul 13, 2020 at 04:31:30PM +0530, Kishon Vijay Abraham I wrote:
>> Certain platforms like TI's J721E using Cadence PCIe IP can perform only
>> 32-bit accesses for reading or writing to Cadence registers. Con
Hi Rob/Lorenzo,
On 7/13/2020 4:31 PM, Kishon Vijay Abraham I wrote:
> TI's J721E SoC uses Cadence PCIe core to implement both RC mode
> and EP mode.
Any comments on this series?
Thanks
Kishon
>
> The high level features are:
> *) Supports Legacy, MSI and MSI-X interrupt
On 7/13/2020 4:41 PM, Vinod Koul wrote:
> On 13-07-20, 11:38, Swapnil Jakhade wrote:
>> Add new PHY attribute max_link_rate to struct phy_attrs.
>> Add a pair of PHY APIs to get/set all the PHY attributes.
>> Use phy_set_attrs() to set attribute values in the PHY provider driver.
>> Use phy_get_
Add host mode dt-bindings for TI's J721E SoC.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Rob Herring
---
.../bindings/pci/ti,j721e-pci-host.yaml | 113 ++
1 file changed, 113 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/ti,j721
management register to configure Vendor ID and Subsystem Vendor
ID.
Fixes: 1b79c5284439 ("PCI: cadence: Add host driver for Cadence PCIe
controller")
Reviewed-by: Rob Herring
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/cadence/pcie-cadence-host.c | 9 +++--
1 file c
"mem" is not a memory resource and it overlaps with PCIe config space
and memory region. Remove "mem" from reg binding.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Rob Herring
---
.../devicetree/bindings/pci/cdns,cdns-pcie-host.yaml | 8 +++-
1 file changed
) from "struct cdns_pcie_epf" that gets initialized in
->set_bar() call back function.
Signed-off-by: Alan Douglas
[kis...@ti.com: Re-implement MSIX support in accordance with the
re-designed core MSI-X interfaces]
Signed-off-by: Kishon Vijay Abraham I
---
.../pci/controller/cadenc
Certain platforms like TI's J721E allows only 32-bit configuration
space access. In such cases pci_generic_config_read and
pci_generic_config_write cannot be used. Add support in Cadence core
to let pci_host_bridge have custom pci_ops.
Signed-off-by: Kishon Vijay Abraham I
---
driver
Add PCIe EP mode dt-bindings for TI's J721E SoC.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Rob Herring
---
.../bindings/pci/ti,j721e-pci-ep.yaml | 94 +++
1 file changed, 94 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/ti,j721
support
*) Supports upto GEN3 speed mode
*) Supports SR-IOV capability
*) Ability to route all transactions via SMMU (support will be added
in a later patch).
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/cadence/Kconfig| 23 +
drivers/pci/controller/cadence
SoC require the absolute address to be programmed in the ATU and
not just the offset. Add new *ops* for CPU addr fixup for the platform
drivers to provide the correct address to be programmed in the ATU.
Signed-off-by: Kishon Vijay Abraham I
---
.../pci/controller/cadence/pcie-cadence
Add Kishon Vijay Abraham I as MAINTAINER for TI J721E SoC PCIe.
Acked-by: Rob Herring
Signed-off-by: Kishon Vijay Abraham I
---
MAINTAINERS | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 5bbc2649566b..bdec73c3069e 100644
--- a/MAINTAINERS
Add J721E in pci_device_id table so that pci-epf-test can be used
for testing PCIe EP in J721E.
Reviewed-by: Rob Herring
Signed-off-by: Kishon Vijay Abraham I
---
drivers/misc/pci_endpoint_test.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/misc/pci_endpoint_test.c b
: Kishon Vijay Abraham I
Reviewed-by: Rob Herring
---
.../pci/controller/cadence/pcie-cadence-ep.c | 8
.../controller/cadence/pcie-cadence-host.c| 28 ++
drivers/pci/controller/cadence/pcie-cadence.h | 37 ++-
3 files changed, 72 insertions(+), 1 deletion
to disable interrupts while modifying PCI_STATUS
register while raising legacy interrupt since PCI_STATUS is accessible
by both remote RC and EP and time between read and write should be
minimized.
Signed-off-by: Kishon Vijay Abraham I
---
.../pci/controller/cadence/pcie-cadence-ep.c | 4 +
d
c() in the error path. Fix it here.
Fixes: bd22885aa188 ("PCI: cadence: Refactor driver to use as a core library")
Reviewed-by: Rob Herring
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/cadence/pcie-cadence-ep.c | 9 ++---
drivers/pci/controller/cadence/pci
Add a macro for aligning down a pointer. This is useful to get an
aligned register address when a device allows only word access and
doesn't allow half word or byte access.
Acked-by: Rob Herring
Signed-off-by: Kishon Vijay Abraham I
---
include/linux/kernel.h | 1 +
1 file changed, 1 inse
; http://lore.kernel.org/r/20200506151429.12255-1-kis...@ti.com
[7] -> http://lore.kernel.org/r/20200522033631.32574-1-kis...@ti.com
[8] -> http://lore.kernel.org/r/20200708093018.28474-1-kis...@ti.com
Alan Douglas (1):
PCI: cadence: Add MSI-X support to Endpoint driver
Kishon Vijay A
Hi Rob,
On 7/10/2020 3:15 AM, Rob Herring wrote:
> On Wed, Jul 08, 2020 at 03:00:12PM +0530, Kishon Vijay Abraham I wrote:
>> Commit 1b79c5284439 ("PCI: cadence: Add host driver for Cadence PCIe
>> controller") in order to update Vendor ID, directly wrote to
>>
Hi Jason,
On 7/8/2020 4:52 PM, Jason Wang wrote:
>
> On 2020/7/7 下午10:45, Kishon Vijay Abraham I wrote:
>> Hi Jason,
>>
>> On 7/7/2020 3:17 PM, Jason Wang wrote:
>>> On 2020/7/6 下午5:32, Kishon Vijay Abraham I wrote:
>>>> Hi Jason,
>>>>
>
Add host mode dt-bindings for TI's J721E SoC.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Rob Herring
---
.../bindings/pci/ti,j721e-pci-host.yaml | 113 ++
1 file changed, 113 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/ti,j721
SoC require the absolute address to be programmed in the ATU and not
just the offset.
Signed-off-by: Kishon Vijay Abraham I
---
.../pci/controller/cadence/pcie-cadence-host.c| 15 ---
.../pci/controller/cadence/pcie-cadence-plat.c| 13 +
drivers/pci/controll
) from "struct cdns_pcie_epf" that gets initialized in
->set_bar() call back function.
Signed-off-by: Alan Douglas
[kis...@ti.com: Re-implement MSIX support in accordance with the
re-designed core MSI-X interfaces]
Signed-off-by: Kishon Vijay Abraham I
---
.../pci/controller/cadenc
Add PCIe EP mode dt-bindings for TI's J721E SoC.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Rob Herring
---
.../bindings/pci/ti,j721e-pci-ep.yaml | 89 +++
1 file changed, 89 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/ti,j721
to disable interrupts while modifying PCI_STATUS
register while raising legacy interrupt since PCI_STATUS is accessible
by both remote RC and EP and time between read and write should be
minimized.
Signed-off-by: Kishon Vijay Abraham I
---
.../pci/controller/cadence/pcie-cadence-ep.c | 4 +
d
Add J721E in pci_device_id table so that pci-epf-test can be used
for testing PCIe EP in J721E.
Reviewed-by: Rob Herring
Signed-off-by: Kishon Vijay Abraham I
---
drivers/misc/pci_endpoint_test.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/misc/pci_endpoint_test.c b
management register to configure Vendor ID and Subsystem Vendor
ID.
Fixes: 1b79c5284439 ("PCI: cadence: Add host driver for Cadence PCIe
controller")
Reviewed-by: Rob Herring
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/cadence/pcie-cadence-host.c | 9 +++--
1 file c
support
*) Supports upto GEN3 speed mode
*) Supports SR-IOV capability
*) Ability to route all transactions via SMMU (support will be added
in a later patch).
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/cadence/Kconfig| 23 +
drivers/pci/controller/cadence
Add Kishon Vijay Abraham I as MAINTAINER for TI J721E SoC PCIe.
Acked-by: Rob Herring
Signed-off-by: Kishon Vijay Abraham I
---
MAINTAINERS | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 5bbc2649566b..bdec73c3069e 100644
--- a/MAINTAINERS
Certain platforms like TI's J721E allows only 32-bit configuration
space access. In such cases pci_generic_config_read and
pci_generic_config_write cannot be used. Add support in Cadence core
to let pci_host_bridge have custom pci_ops.
Signed-off-by: Kishon Vijay Abraham I
---
driver
"mem" is not a memory resource and it overlaps with PCIe config space
and memory region. Removve "mem" from reg binding.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Rob Herring
---
.../devicetree/bindings/pci/cdns,cdns-pcie-host.yaml | 8 +++-
1 file changed
: Kishon Vijay Abraham I
Reviewed-by: Rob Herring
---
.../pci/controller/cadence/pcie-cadence-ep.c | 8
.../controller/cadence/pcie-cadence-host.c| 28 ++
drivers/pci/controller/cadence/pcie-cadence.h | 37 ++-
3 files changed, 72 insertions(+), 1 deletion
Add a macro for aligning down a pointer. This is useful to get an
aligned register address when a device allows only word access and
doesn't allow half word or byte access.
Acked-by: Rob Herring
Signed-off-by: Kishon Vijay Abraham I
---
include/linux/kernel.h | 1 +
1 file changed, 1 inse
c() in the error path. Fix it here.
Fixes: bd22885aa188 ("PCI: cadence: Refactor driver to use as a core library")
Reviewed-by: Rob Herring
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/cadence/pcie-cadence-ep.c | 9 ++---
drivers/pci/controller/cadence/pci
is...@ti.com
Alan Douglas (1):
PCI: cadence: Add MSI-X support to Endpoint driver
Kishon Vijay Abraham I (13):
PCI: cadence: Fix cdns_pcie_{host|ep}_setup() error path
linux/kernel.h: Add PTR_ALIGN_DOWN macro
PCI: cadence: Convert all r/w accessors to perform only 32-bit
accesses
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