Hi Dave,
/proc/net/{tcp,udp,raw} show IPv4 addresses with host order, while
port is shown with network order. The included patch adds the needed
ntohl(). Not very usefull, but hopefully correct.
Tested on 2.4.0-pre8/Alpha.
M.
--- linux/net/ipv4/tcp_ipv4.c.old Mon Sep 11 12:15:54
Hi all,
Having just started playing with IrDA on my dual celeron (Abit "APIC
error..." BP6), I managed to kill it every single time (NMI watchdog
in handle_IRQ_event) while connecting to my mobile phone (in fact,
when closing the connection to the phone. even 'cat /dev/ircomm0' will
do...). This
"AM" == Andrew Morton [EMAIL PROTECTED] writes:
Hi Andrew,
AM Try this:
AM --- linux-2.4.0-prerelease/net/irda/irqueue.c Tue Nov 21 20:11:22 2000
AM +++ linux-akpm/net/irda/irqueue.c Thu Jan 4 10:14:10 2001
AM @@ -436,7 +436,7 @@
AM /* Release lock */
AM if (
Jun 9 13:29:31 1998
* Modified at: Sun Dec 12 13:48:22 1999
* Modified by: Dag Brattli [EMAIL PROTECTED]
+ * Modified at: Thu Jan 4 14:29:10 CET 2001
+ * Modified by: Marc Zyngier [EMAIL PROTECTED]
*
* Copyright (C) 1998-1999, Aage Kvalnes [EMAIL PROTECTED]
* Copyright (C
On 25/09/12 20:08, Rohit Vaswani wrote:
Any comments ?
Marc, would it be possible for you to pull this into your timers-next tree ?
Hi Rohit,
Sorry for the delay.
I'll give these patches a whirl first thing tomorrow.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
--
To
On 23/10/12 15:48, Kukjin Kim wrote:
Hi all,
Now, v3.7-rc2 happens following build error with s3c2410_defconfig...
ERROR: read_current_timer [fs/ext4/ext4.ko] undefined!
make[2]: *** [__modpost] Error 1
make[1]: *** [modules] Error 2
make[1]: *** Waiting for unfinished jobs
Any
Hi Pranavkumar,
On Thu, 18 Apr 2013 11:22:24 +0530, PranavkumarSawargaonkar
pranavku...@linaro.org wrote:
From: Pranavkumar Sawargaonkar pranavku...@linaro.org
This patch implements early printk support for virtio-mmio console
devices
without using any hypercalls.
The current virtio early
On Thu, 18 Apr 2013 12:47:18 +0530, Pranavkumar Sawargaonkar
pranavku...@linaro.org wrote:
Hi Marc,
On 18 April 2013 12:19, Marc Zyngier m...@misterjones.org wrote:
Hi Pranavkumar,
On Thu, 18 Apr 2013 11:22:24 +0530, PranavkumarSawargaonkar
pranavku...@linaro.org wrote:
From
On Thu, 18 Apr 2013 09:30:52 +0100, Peter Maydell
peter.mayd...@linaro.org wrote:
On 18 April 2013 07:49, Marc Zyngier m...@misterjones.org wrote:
If you need an early console, why not simply wire the 8250 emulation in
kvmtool to be useable from the MMIO bus? I reckon this would solve your
On Thu, 18 Apr 2013 11:25:56 -0400, Christopher Covington
c...@codeaurora.org wrote:
Hi Pranavkumar,
On 04/18/2013 01:52 AM, PranavkumarSawargaonkar wrote:
From: Pranavkumar Sawargaonkar pranavku...@linaro.org
This patch implements early printk support for virtio-mmio console
devices
-preemptible context though,
so use __this_cpu_ptr() instead to avoid the preemptible checks
and silence the warning.
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Marc Zyngier marc.zyng...@arm.com
Signed-off-by: Stephen Boyd sb...@codeaurora.org
---
Anyone else seeing this one?
Haven't seen
to
actually use the pointer in non-preemptible context though, so
push the this_cpu_ptr() access down into the cases to force the
checks to occur only in non-preemptible contexts.
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Marc Zyngier marc.zyng...@arm.com
Signed-off-by: Stephen Boyd sb
Hi Joe,
On Sat, 13 Apr 2013 22:55:45 -0700, Joe Perches j...@perches.com wrote:
commit 3401d54696f (KVM: ARM: Introduce KVM_ARM_SET_DEVICE_ADDR ioctl)
added the case, but omitted adding break;
[...]
Already reported here:
On 21/03/13 11:06, Mark Rutland wrote:
Hi Rob,
(adding Marc to Cc as he may have comments).
On Wed, Mar 20, 2013 at 10:34:35PM +, Rob Herring wrote:
From: Rob Herring rob.herr...@calxeda.com
This converts arm and arm64 to use CLKSRC_OF DT based initialization for
the arch timer. A
On 21/03/13 19:16, Stefano Stabellini wrote:
xenvm is based on mach-vexpress, move it to mach-virt.
Signed-off-by: Stefano Stabellini stefano.stabell...@eu.citrix.com
CC: marc.zyng...@arm.com
CC: will.dea...@arm.com
CC: a...@arndb.de
CC: rob.herr...@calxeda.com
Awesome!
Acked-by: Marc
On 27/03/13 12:50, Stefano Stabellini wrote:
Check for the presence of PSCI before setting smp_ops, use PSCI if it is
available.
This is useful because at least when running on Xen it's possible to have a
PSCI node for example on a Versatile Express or an Exynos5 machine. In these
cases the
: Michael S. Tsirkin m...@redhat.com
Cc: Pawel Moll pawel.m...@arm.com
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
So I'm not completely sure this is the right fix, and I can imagine
other ways to cure the problem:
- Reading the MAGIC register byte by byte. Is that allowed? The spec
only says
On 13/02/13 15:08, Pawel Moll wrote:
On Wed, 2013-02-13 at 14:25 +, Marc Zyngier wrote:
Using readl() to read the magic value and then memcmp() to check it
fails on BE, as bytes will be the other way around (by virtue of
the registers to follow the endianess of the guest).
Hm
On 13/02/13 15:46, Pawel Moll wrote:
On Wed, 2013-02-13 at 15:28 +, Marc Zyngier wrote:
Fix it by encoding the magic as an integer instead of a string.
So I'm not completely sure this is the right fix,
It seems right, however...
- Using __raw_readl() instead. Is that a generic enough
On 13/02/13 16:53, Michael S. Tsirkin wrote:
On Wed, Feb 13, 2013 at 03:28:52PM +, Marc Zyngier wrote:
On 13/02/13 15:08, Pawel Moll wrote:
On Wed, 2013-02-13 at 14:25 +, Marc Zyngier wrote:
Using readl() to read the magic value and then memcmp() to check it
fails on BE, as bytes
On 14/02/13 10:54, Pawel Moll wrote:
To solve the never-ending confusions between hosts and guests
of different endianess, define all virtio-mmio registers as LE.
This change should be safe at this stage, because no known
working mixed-endian system exists so there is virtually no
risk of
On 01/03/13 10:50, Pawel Moll wrote:
On Fri, 2013-03-01 at 10:41 +, Marc Zyngier wrote:
On 14/02/13 10:54, Pawel Moll wrote:
To solve the never-ending confusions between hosts and guests
of different endianess, define all virtio-mmio registers as LE.
This change should be safe
On 01/03/13 12:37, Pawel Moll wrote:
On Fri, 2013-03-01 at 11:21 +, Marc Zyngier wrote:
Having said that, Rusty was contemplating enforcing LE config space in
the new PCI layout...
I wouldn't complain about that, and would like to see a similar thing on
MMIO.
Wherever PCI goes, MMIO
On 20/09/12 13:15, Stefano Stabellini wrote:
On Thu, 20 Sep 2012, Pawel Moll wrote:
On Thu, 2012-09-20 at 12:39 +0100, Stefano Stabellini wrote:
There are no peripherals apart from the ones that are already described
here (timer, gic). All the peripherals that the guest sees are virtual
On 20/09/12 14:30, Ian Campbell wrote:
On Thu, 2012-09-20 at 13:28 +0100, Marc Zyngier wrote:
I think the important thing here is that the memory map is RS1. As this
is a (very limited) subset of a vexpress A15, it seems to make some sense.
Looking at arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
On 12/09/12 15:58, Arnd Bergmann wrote:
As I promised at the ARM mini summit, I've updated Marc's series
for smp operations according to my complaints. Unfortunately,
I could not find version 7 of the patches when I started this,
so I based my work on version 6 and had to redo the same
On 14/09/12 12:13, Stefano Stabellini wrote:
Use r12 to pass the hypercall number to the hypervisor.
We need a register to pass the hypercall number because we might not
know it at compile time and HVC only takes an immediate argument.
Among the available registers r12 seems to be the best
On 14/09/12 12:13, Stefano Stabellini wrote:
Reset the IRQ_NOAUTOEN and IRQ_NOREQUEST flags that are enabled by
default on ARM. If IRQ_NOAUTOEN is set, __setup_irq doesn't call
irq_startup, that is responsible for calling irq_unmask at startup time.
As a result event channels remain masked.
On 14/09/12 15:02, Stefano Stabellini wrote:
On Fri, 14 Sep 2012, Marc Zyngier wrote:
+/* HVC 0xEA1 */
+#ifdef CONFIG_THUMB2_KERNEL
+#define xen_hvc .word 0xf7e08ea1
+#else
+#define xen_hvc .word 0xe140ea71
+#endif
You should consider using Dave Martin's opcode injection series
On 14/09/12 15:13, Stefano Stabellini wrote:
On Fri, 14 Sep 2012, Marc Zyngier wrote:
On 14/09/12 12:13, Stefano Stabellini wrote:
Reset the IRQ_NOAUTOEN and IRQ_NOREQUEST flags that are enabled by
default on ARM. If IRQ_NOAUTOEN is set, __setup_irq doesn't call
irq_startup
On 14/09/12 15:28, Stefano Stabellini wrote:
On Fri, 14 Sep 2012, Marc Zyngier wrote:
On 14/09/12 15:13, Stefano Stabellini wrote:
On Fri, 14 Sep 2012, Marc Zyngier wrote:
On 14/09/12 12:13, Stefano Stabellini wrote:
Reset the IRQ_NOAUTOEN and IRQ_NOREQUEST flags that are enabled by
default
Hi Rohit,
On Fri, 10 Aug 2012 14:58:41 -0700, Rohit Vaswani
rvasw...@codeaurora.org
wrote:
The current arch_timer only support accessing through CP15 interface.
Add support for ARM processors that only support IO mapped register
interface
This is quite a departure from the current
On Fri, 10 Aug 2012 14:57:34 -0700, Rohit Vaswani
rvasw...@codeaurora.org
wrote:
Level triggered interrupt is deasserted when a new TVAL is written
only when the interrupt is unmasked. Make sure that the interrupt
is unmasked in CTL register before TVAL is written.
If this order is not
On Wed, 11 Jul 2012 12:57:55 +0100, Catalin Marinas
catalin.mari...@arm.com wrote:
On Wed, Jul 11, 2012 at 12:28:29PM +0100, Arnd Bergmann wrote:
On Wednesday 11 July 2012, James Bottomley wrote:
Hi All,
We have set aside the second day of the kernel summit (Tuesday 28
August) as
On Wed, 11 Jul 2012 20:06:28 +, Arnd Bergmann a...@arndb.de wrote:
On Wednesday 11 July 2012, Konrad Rzeszutek Wilk wrote:
contacts, with Grant and Olof joining in as time permits.
Acked-by: Grant Likely grant.lik...@secretlab.ca
I would be interested in attending it as well. I
On Thu, 12 Jul 2012 02:18:42 +0200, Linus Walleij
linus.ml.wall...@gmail.com wrote:
Hi Linus,
I'm reviewing the only patch I really understand...
2012/7/6 Catalin Marinas catalin.mari...@arm.com:
+/* This isn't really used any more */
+#define CLOCK_TICK_RATE 1000
Is it still
On Thu, 12 Jul 2012 09:57:33 -0700, John Stultz john.stu...@linaro.org
wrote:
On 07/12/2012 03:56 AM, Linus Walleij wrote:
On Thu, Jul 12, 2012 at 12:09 PM, Marc Zyngier marc.zyng...@arm.com
wrote:
On Thu, 12 Jul 2012 02:18:42 +0200, Linus Walleij
linus.ml.wall...@gmail.com wrote:
Hi Linus
On 20/12/12 09:44, Hiroshi Doyu wrote:
Add platform enabler for ARM arch_timer(TSC). TSC is more fine grained
timer than TMR0. If it's available, it will be used for clock source
and sched_clock. Otherwise, TMR0 is used. In any case TMR0 is
necessary for clock event.
Signed-off-by: Hiroshi
On 20/12/12 09:44, Hiroshi Doyu wrote:
The method to detect the number of CPU cores on Cortex-A9 MPCore and
Cortex-A15 MPCore is different. On Cortex-A9 MPCore we can get this
information from the Snoop Control Unit(SCU). On Cortex-A15 MPCore we
have to read it from the system
On 20/12/12 09:44, Hiroshi Doyu wrote:
Initial support for Tegra 114 SoC. This is expected to be included in
the board DTS files, Tegra 114 SoC based evaluation board family.
Signed-off-by: Hiroshi Doyu hd...@nvidia.com
You definitely need to add some cpu nodes here, or get someone to merge
On 20/12/12 11:26, Hiroshi Doyu wrote:
Marc Zyngier marc.zyng...@arm.com wrote @ Thu, 20 Dec 2012 12:17:08 +0100:
On 20/12/12 09:44, Hiroshi Doyu wrote:
The method to detect the number of CPU cores on Cortex-A9 MPCore and
Cortex-A15 MPCore is different. On Cortex-A9 MPCore we can get
On 20/12/12 11:57, Hiroshi Doyu wrote:
Marc Zyngier marc.zyng...@arm.com wrote @ Thu, 20 Dec 2012 12:01:15 +0100:
On 20/12/12 09:44, Hiroshi Doyu wrote:
Add platform enabler for ARM arch_timer(TSC). TSC is more fine grained
timer than TMR0. If it's available, it will be used for clock source
On 20/12/12 12:22, Peter De Schrijver wrote:
+
+ /* CNTFRQ */
+ asm(mcr p15, 0, %0, c14, c0, 0\n : : r (freq));
+ asm(mrc p15, 0, %0, c14, c0, 0\n : =r (val));
+ BUG_ON(val != freq);
This is scary. CNTFRQ is only writable from secure mode, and will
explode in any other situation.
Also,
On 20/12/12 12:55, Peter De Schrijver wrote:
On Thu, Dec 20, 2012 at 01:33:42PM +0100, Marc Zyngier wrote:
On 20/12/12 12:22, Peter De Schrijver wrote:
+
+ /* CNTFRQ */
+ asm(mcr p15, 0, %0, c14, c0, 0\n : : r (freq));
+ asm(mrc p15, 0, %0, c14, c0, 0\n : =r (val
On 20/12/12 13:25, Hiroshi Doyu wrote:
Marc Zyngier marc.zyng...@arm.com wrote @ Thu, 20 Dec 2012 13:05:45 +0100:
On 20/12/12 11:57, Hiroshi Doyu wrote:
Marc Zyngier marc.zyng...@arm.com wrote @ Thu, 20 Dec 2012 12:01:15 +0100:
On 20/12/12 09:44, Hiroshi Doyu wrote:
Add platform enabler
On 20/12/12 14:42, Hiroshi Doyu wrote:
Marc Zyngier marc.zyng...@arm.com wrote @ Thu, 20 Dec 2012 14:32:21 +0100:
On 20/12/12 12:55, Peter De Schrijver wrote:
On Thu, Dec 20, 2012 at 01:33:42PM +0100, Marc Zyngier wrote:
On 20/12/12 12:22, Peter De Schrijver wrote:
+
+ /* CNTFRQ
eric.y.m...@gmail.com
Cc: Marc Zyngier m...@misterjones.org
Acked-by: Marc Zyngier m...@misterjones.org
---
arch/arm/mach-pxa/viper.c |3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c
index 130379f..ac733e9 100644
...@arm.linux.org.uk
CC: Pawel Moll pawel.m...@arm.com
CC: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/mach-vexpress/v2m.c | 11 ++-
1 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index 37608f2..4e567f7 100644
Hi Daniel,
On 2013-08-14 09:50, Daniel Lezcano wrote:
On 08/13/2013 07:29 PM, Sudeep KarkadaNagesha wrote:
From: Sudeep KarkadaNagesha sudeep.karkadanage...@arm.com
Add macros to describe the bitfields in the ARM architected timer
control register to make code easy to understand.
Cc: Catalin
Cc: Pawel Moll pawel.m...@arm.com
Cc: Will Deacon will.dea...@arm.com
Cc: Catalin Marinas catalin.mari...@arm.com
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm64/include/asm/system_misc.h | 3 ++-
arch/arm64/kernel/process.c | 2 +-
kernel/reboot.c | 2
-by: Marc Zyngier marc.zyng...@arm.com
M.
--
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Please read
On 21/06/13 01:35, Tomasz Figa wrote:
Hi Tomasz,
Most ARM platforms have parts that should be initialized as early as
possible, which usually means as soon as memory management (kmalloc,
ioremap) starts to work,
However, currently there is no appropriate callback in machine_desc
struct to
On 12/09/13 17:07, cinifr wrote:
This cannot be a compile-time option as above in a multiplatform build.
Other paltforms (e.g. KVM guests) *must* use the virtual counters to get
any semblance of a consistent view of time.
Yes I accept compile-time option is not perfect in my pre email,
On 13/09/13 09:49, cinifr wrote:
On 13 September 2013 00:39, Marc Zyngier marc.zyng...@arm.com wrote:
On 12/09/13 17:07, cinifr wrote:
This cannot be a compile-time option as above in a multiplatform build.
Other paltforms (e.g. KVM guests) *must* use the virtual counters to get
any semblance
Hi Maxime,
On 23/07/13 23:25, Maxime Ripard wrote:
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/sun6i-a31.dtsi | 155
+++
2 files changed, 157 insertions(+), 1 deletion(-)
On 13/09/13 14:09, cinifr wrote:
I urge you to read the ARM ARM, and specifically the section dedicated
to trapping access to CP15 operations. If you do, you'll quickly notice
that you *cannot* trap accesses to the timer subsystem.
I read it again. The ARMv7 manual said Is accessible from
On 2013-09-14 13:14, Alexander Graf wrote:
Am 14.09.2013 um 07:10 schrieb Andrew Jones drjo...@redhat.com:
Signed-off-by: Andrew Jones drjo...@redhat.com
---
arch/arm/kvm/arm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
index
On 15/09/13 10:30, Gleb Natapov wrote:
On Sat, Sep 14, 2013 at 02:10:55PM +0200, Andrew Jones wrote:
Drop the _ARM_ part of the name. We can then introduce a config option
like this to aarch64 and other arches using the same name - allowing
grep to show them all. Also update the help text to
Hi Maxime,
On 14/09/13 13:05, maxime.rip...@free-electrons.com wrote:
Hi Marc, Fan,
On Fri, Sep 13, 2013 at 10:30:49AM +0100, Marc Zyngier wrote:
On 13/09/13 09:49, cinifr wrote:
On 13 September 2013 00:39, Marc Zyngier marc.zyng...@arm.com
wrote: I am wondering what is the principle
On 16/09/13 09:32, Gleb Natapov wrote:
On Mon, Sep 16, 2013 at 09:09:27AM +0100, Marc Zyngier wrote:
On 15/09/13 10:30, Gleb Natapov wrote:
On Sat, Sep 14, 2013 at 02:10:55PM +0200, Andrew Jones wrote:
Drop the _ARM_ part of the name. We can then introduce a config option
like this to aarch64
On 16/10/13 19:51, Thierry Reding wrote:
Today's linux-next merge of the kvm-arm tree got conflicts in
arch/arm/kvm/reset.c
caused by commits e8c2d99 (KVM: ARM: Add support for Cortex-A7) and ac570e0
(ARM: kvm: rename cpu_reset to avoid name clash).
I've fixed them up (see below).
On 23/11/13 08:41, Anup Patel wrote:
On Wed, Nov 20, 2013 at 4:28 PM, Marc Zyngier marc.zyng...@arm.com wrote:
[dropping patc...@apm.com from the CC list, as someone seems to have
tripped on the config file, and I'm tired of getting bounces]
Feng,
On 19/11/13 21:42, Feng Kan wrote
Hi Vinayak,
On 13/11/13 11:05, Vinayak Kale wrote:
This patch adds an accessor function for IRQ_PER_CPU flag.
The accessor function is useful to dertermine whether an IRQ is percpu or not.
Signed-off-by: Vinayak Kale vk...@apm.com
---
include/linux/irqdesc.h |8
1 file
Vinayak,
On 2013-11-18 13:22, Vinayak Kale wrote:
Add support for irq registration when pmu interrupt is percpu.
Signed-off-by: Vinayak Kale vk...@apm.com
Signed-off-by: Tuan Phan tp...@apm.com
---
arch/arm64/kernel/perf_event.c | 102
+---
1 file changed,
On 2013-11-18 14:18, Vinayak Kale wrote:
On Mon, Nov 18, 2013 at 7:16 PM, Marc Zyngier marc.zyng...@arm.com
wrote:
Vinayak,
On 2013-11-18 13:22, Vinayak Kale wrote:
Add support for irq registration when pmu interrupt is percpu.
Signed-off-by: Vinayak Kale vk...@apm.com
Signed-off-by: Tuan
[dropping patc...@apm.com from the CC list, as someone seems to have
tripped on the config file, and I'm tired of getting bounces]
Feng,
On 19/11/13 21:42, Feng Kan wrote:
The GIC-400 implementation allows for FIQ and IRQ bypass. In the
X-Gene implementation, the FIQ bypass must be enabled at
[dropped patc...@apm.com]
Vinayak,
Please keep reviewers on CC, as it makes easier to track the changes.
On 20/11/13 11:13, Vinayak Kale wrote:
Add support for irq registration when pmu interrupt is percpu.
Signed-off-by: Vinayak Kale vk...@apm.com
Signed-off-by: Tuan Phan tp...@apm.com
Hi Hanjun,
On 03/12/13 16:39, Hanjun Guo wrote:
In MADT table, there are GIC cpu interface base address and
GIC distributor base address, use them to convert GIC to ACPI.
Signed-off-by: Hanjun Guo hanjun@linaro.org
---
arch/arm64/kernel/irq.c |5
On 04/12/13 15:32, Hanjun Guo wrote:
On 2013年12月04日 01:26, Marc Zyngier wrote:
Hi Hanjun,
On 03/12/13 16:39, Hanjun Guo wrote:
In MADT table, there are GIC cpu interface base address and
GIC distributor base address, use them to convert GIC to ACPI.
Signed-off-by: Hanjun Guo hanjun
On 2014-02-22 10:21, Hanjun Guo wrote:
On 2014-2-21 20:37, Sudeep Holla wrote:
Hi Hanjun,
(Adding MarcZ for his views on GIC)
On 20/02/14 03:59, Hanjun Guo wrote:
Hi Sudeep,
Thanks for your comments, please refer to the replies below. :)
On 2014年02月19日 22:33, Sudeep Holla wrote:
Hi
[Fixing tglx's email address so he too can enjoy the fun...]
On 25/02/14 20:19, Feng Kan wrote:
On Wed, Feb 19, 2014 at 2:33 AM, Marc Zyngier marc.zyng...@arm.com wrote:
Hi Feng,
On 18/02/14 22:12, Feng Kan wrote:
This change is made to preserve the GIC v2 releated bits in the
GIC_CPU_CTRL
On Thu, Feb 27 2014 at 6:34:55 pm GMT, Feng Kan f...@apm.com wrote:
This change is made to preserve the GIC v2 releated bits in the
GIC_CPU_CTRL register (also known as the GICC_CTLR register in spec).
The original code only set the enable/disable group bit in this register.
This code will
On Thu, Feb 27 2014 at 9:00:07 pm GMT, Feng Kan f...@apm.com wrote:
On Thu, Feb 27, 2014 at 10:54 AM, Marc Zyngier marc.zyng...@arm.com wrote:
On Thu, Feb 27 2014 at 6:34:55 pm GMT, Feng Kan f...@apm.com wrote:
This change is made to preserve the GIC v2 releated bits in the
GIC_CPU_CTRL
Hi Feng,
On 18/02/14 22:12, Feng Kan wrote:
This change is made to preserve the GIC v2 releated bits in the
GIC_CPU_CTRL register (also known as the GICC_CTLR register in spec).
The original code only set the enable/disable group bit in this register.
This code will preserve all other bits
On 08/05/13 13:23, Giridhar Maruthy wrote:
On 7 May 2013 14:25, Marc Zyngier marc.zyng...@arm.com wrote:
On 07/05/13 06:54, Giridhar Maruthy wrote:
This patch is a modification from the Christoffer Dall's u-boot
patch. This is required to put the secondary processors in hyp
mode during cpu
Hi Stefano,
On 08/05/13 16:41, Stefano Stabellini wrote:
Introduce CONFIG_PARAVIRT and PARAVIRT_TIME_ACCOUNTING on ARM.
The only paravirt interface supported is pv_time_ops.steal_clock, so no
runtime pvops patching needed.
This allows us to make use of steal_account_process_tick for
Hi Stefano,
On 08/05/13 16:41, Stefano Stabellini wrote:
Register the runstate_memory_area with the hypervisor.
Use pv_time_ops.steal_clock to account for stolen ticks.
Signed-off-by: Stefano Stabellini stefano.stabell...@eu.citrix.com
Changes in v3:
- use BUG_ON and smp_processor_id.
-by: Marc Zyngier marc.zyng...@arm.com
M.
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Please read
On 17/06/13 09:42, Steve Capper wrote:
On Mon, Jun 17, 2013 at 05:45:28PM +1000, Stephen Rothwell wrote:
Hi Steve,
Hi Stephen,
Today's linux-next merge of the arm64-hugepages tree got conflicts in
arch/arm64/include/asm/pgtable-hwdef.h and
arch/arm64/include/asm/pgtable.h between commit
On 03/05/13 11:43, Stefano Stabellini wrote:
On Thu, 2 May 2013, Christopher Covington wrote:
So the virtual timer should appear to have been running even while time
is being stolen and therefore stolen time needs to be accounted via some
other means.
Something that's not currently obvious
that, and FWIW:
Acked-by: Marc Zyngier marc.zyng...@arm.com
M.
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On Thu, 30 May 2013 14:14:42 +0400, Sergey Yanovich ynv...@gmail.com
wrote:
On Wed, 2013-05-29 at 15:53 -0700, Andrew Morton wrote:
On Tue, 21 May 2013 03:21:30 +0400 Sergey Yanovich ynv...@gmail.com
wrote:
@@ -321,6 +326,7 @@ static int ds1302_rtc_remove(struct platform_device
*pdev)
{
time data is written.
Signed-off-by: Sergey Yanovich ynv...@gmail.com
FWIW,
Acked-by: Marc Zyngier m...@misterjones.org
M.
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on
most other platforms over the course of several months. If the platform
maintainers aren't responsive enough, fixing the issues becomes their
problem.
FWIW, have my
Acked-by: Marc Zyngier marc.zyng...@arm.com
M.
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On Mon, 03 Jun 2013 13:00:37 -0700, Stephen Boyd sb...@codeaurora.org
wrote:
On 06/03/13 01:54, Marc Zyngier wrote:
On 31/05/13 23:16, Stephen Boyd wrote:
On 05/31, John Stultz wrote:
On 05/31/2013 10:45 AM, Stephen Boyd wrote:
Comments have been light for this round so I think we're about
On 26/04/13 16:03, Arnd Bergmann wrote:
On Friday 26 April 2013, Anup Patel wrote:
I am curious about how smh-based or hypercall-based early prints would
be handled in following scenario:
A board is running KVM ARM enabled kernel and linux console on serial
port. Now a user remotely connects
On Mon, 20 May 2013 14:48:05 +0800, Chen Gang gang.c...@asianux.com
wrote:
Need 'EXPORT_SYMBOL_GPL(read_current_timer)' if build with allmodconfig.
The related error:
ERROR: read_current_timer [lib/rbtree_test.ko] undefined!
ERROR: read_current_timer [lib/interval_tree_test.ko]
On Tue, 21 May 2013 12:06:52 +0800, Chen Gang gang.c...@asianux.com
wrote:
On 05/20/2013 05:56 PM, Will Deacon wrote:
On Mon, May 20, 2013 at 08:15:04AM +0100, Marc Zyngier wrote:
On Mon, 20 May 2013 14:48:05 +0800, Chen Gang gang.c...@asianux.com
wrote:
Need 'EXPORT_SYMBOL_GPL
On 21/05/13 09:41, Chen Gang wrote:
On 05/21/2013 02:13 PM, Marc Zyngier wrote:
On Tue, 21 May 2013 12:06:52 +0800, Chen Gang gang.c...@asianux.com
wrote:
On 05/20/2013 05:56 PM, Will Deacon wrote:
On Mon, May 20, 2013 at 08:15:04AM +0100, Marc Zyngier wrote:
On Mon, 20 May 2013 14:48:05
...@chromium.org
Tested-by: Marc Zyngier marc.zyng...@arm.com
M.
---
arch/arm/boot/dts/cros5250-common.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/cros5250-common.dtsi
b/arch/arm/boot/dts/cros5250-common.dtsi
index dc259e8b..9b186ac 100644
--- a/arch
On 25/10/13 14:03, Thierry Reding wrote:
Today's linux-next merge of the kvm-arm tree got a conflict in
arch/arm/kvm/reset.c
caused by commits e8c2d99 (KVM: ARM: Add support for Cortex-A7) and 7999b4d
(ARM: KVM: drop limitation to 4 CPU VMs).
I fixed it up (see below). Please
On 2013-07-05 21:55, Dominik Dingel wrote:
Current common codes uses PAGE_OFFSET to indicate a bad host virtual
address.
As this check won't work on architectures that don't map kernel and
user memory
into the same address space (e.g. s390), it is moved into architcture
specific
code.
Hi Feng,
On 2013-09-27 02:19, Feng Kan wrote:
This driver setup the AHBC for SPI and SD drivers to use.
That's a bit thin for a description. What is AHBC? How does it relate
to SPI and SD? How is it used?
Signed-off-by: Feng Kan f...@apm.com
---
arch/arm64/boot/dts/apm-storm.dtsi |6
On 30/09/13 14:59, Sricharan R wrote:
In some socs the gic can be preceded by a crossbar IP which
routes the peripheral interrupts to the gic inputs. The peripheral
interrupts are associated with a fixed crossbar input line and the
crossbar routes that to one of the free gic input line.
The
On 30/09/13 15:22, Santosh Shilimkar wrote:
On Monday 30 September 2013 10:16 AM, Marc Zyngier wrote:
On 30/09/13 14:59, Sricharan R wrote:
In some socs the gic can be preceded by a crossbar IP which
routes the peripheral interrupts to the gic inputs. The peripheral
interrupts are associated
happy for this to go in.
Acked-by: Marc Zyngier marc.zyng...@arm.com
Thanks,
M.
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Kim, Christoffer,
On Tue, May 06 2014 at 7:04:48 pm BST, Christoffer Dall
christoffer.d...@linaro.org wrote:
On Tue, Mar 25, 2014 at 05:08:14PM -0500, Kim Phillips wrote:
Use the correct memory type for device MMIO mappings: PAGE_S2_DEVICE.
Signed-off-by: Kim Phillips
On Wed, May 07 2014 at 1:53:45 am BST, Feng Kan f...@apm.com wrote:
This change is made to preserve the GIC v2 bypass bits in the
GIC_CPU_CTRL register (also known as the GICC_CTLR register in spec).
This code will preserve all bits configured by the bootload regarding
On Wed, May 07 2014 at 3:53:27 pm BST, Will Deacon will.dea...@arm.com wrote:
Hi all,
Thanks for CC'ing me, Arnd.
On Wed, May 07, 2014 at 03:35:48PM +0100, Arnd Bergmann wrote:
On Wednesday 07 May 2014 17:21:13 Srikanth Thokala wrote:
On Wed, Apr 30, 2014 at 9:04 PM, Arnd Bergmann
On Thu, May 08 2014 at 1:01:50 am BST, Feng Kan f...@apm.com wrote:
This change is made to preserve the GIC v2 bypass bits in the
GIC_CPU_CTRL register (also known as the GICC_CTLR register in spec).
This code will preserve all bits configured by the bootload regarding
v2 bypass group bits.
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