On Sunday, December 14, 2014 at 06:16:17 PM, Stefan Wahren wrote:
Hi Marek,
Marek Vasut ma...@denx.de hat am 14. Dezember 2014 um 17:12 geschrieben:
static void __iomem *digctrl;
#define DIGCTRL digctrl
@@ -118,11 +119,12 @@ static void __init clk_misc_init(void)
/*
* 480 MHz
On Thursday, December 18, 2014 at 04:58:28 PM, Stefan Wahren wrote:
Hi Marek,
Hello Stefan,
Am 17.12.2014 um 17:00 schrieb Marek Vasut:
On Wednesday, December 17, 2014 at 08:58:23 AM, Stefan Wahren wrote:
Hi Fabio,
Am 17.12.2014 um 03:44 schrieb Fabio Estevam:
Hi Stefan,
On Sun
+ SET);
+ writeb(BF_CLKGATE, ref-reg + ref-idx + SET);
Same here and all around the place ?
Other than that, it looks pretty OK :)
Best regards,
Marek Vasut
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More
imx-bootlets.
I'll try to test it with U-Boot.
Please keep me in the loop, I'd be interested in what you find. Thanks!
Best regards,
Marek Vasut
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From: Olaf Mandel o.man...@menlosystems.com
Align the documentation with the include/linux/etherdevice.h ,
which is where this example comes from. The return value from
the check was inverted in the documentation.
Signed-off-by: Olaf Mandel o.man...@menlosystems.com
Signed-off-by: Marek Vasut ma
a brief skim over the code, I'd suggest to send the new
functionality and new chip IDs in separate patches.
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Marek Vasut
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be addressed by byte instructions. Addressing word or half-
word are not allowed.
I also recall seeing weird behavior when these registers were accessed by word
access in U-Boot, so I believe the datasheet is correct.
Best regards,
Marek Vasut
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On Monday, February 16, 2015 at 09:24:51 PM, Stefan Wahren wrote:
Hi Fabio,
Fabio Estevam feste...@gmail.com hat am 12. Februar 2015 um 20:08
geschrieben:
Hi Stefan,
On Thu, Feb 12, 2015 at 4:59 PM, Stefan Wahren stefan.wah...@i2se.com
wrote:
Hi Fabio,
Fabio Estevam
...@spectrumdigital.se
Makes sense, thanks!
Reviewed-by: Marek Vasut ma...@denx.de
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Marek Vasut
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_STABLE bit, so it means
the clock are not stable, right ? Why would that happen in the first place?
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Add new ID for ASUS N10 WiFi dongle.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Larry Finger larry.fin...@lwfinger.net
Cc: John W. Linville linvi...@tuxdriver.com
Cc: Chaoming Li chaoming...@realsil.com.cn
---
drivers/net/wireless/rtlwifi/rtl8192cu/sw.c | 1 +
1 file changed, 1 insertion
, but it is
different enough to merit its own driver. Also, this driver uses the
generic phy infrastructure.
Hi,
the register set looks very similar to MXS one indeed. How is it different
please ?
The driver looks OK.
Best regards,
Marek Vasut
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On Thursday, March 26, 2015 at 01:50:59 AM, Larry Finger wrote:
On 03/25/2015 04:18 PM, Marek Vasut wrote:
Add new ID for ASUS N10 WiFi dongle.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Larry Finger larry.fin...@lwfinger.net
Cc: John W. Linville linvi...@tuxdriver.com
Cc: Chaoming
Add new ID for ASUS N10 WiFi dongle.
Signed-off-by: Marek Vasut ma...@denx.de
Tested-by: Marek Vasut ma...@denx.de
Cc: Larry Finger larry.fin...@lwfinger.net
Cc: John W. Linville linvi...@tuxdriver.com
---
drivers/net/wireless/rtlwifi/rtl8192cu/sw.c | 1 +
1 file changed, 1 insertion(+)
V2
, I can say that even on my system
it's a 16bit value.
What kind of hardware are you testing this on ?
The problem here is that I'm not sure we can assume this as true in
general since the ACPI specification doesn't say anything.
Maybe someone more knowledgable can speak up.
Best regards,
Marek
On Thursday, April 30, 2015 at 01:27:43 PM, Gabriele Mazzotta wrote:
On Thursday 30 April 2015 11:44:36 Marek Vasut wrote:
On Wednesday, April 29, 2015 at 05:36:32 PM, Gabriele Mazzotta wrote:
[...]
I'm sorry, I've just noticed that I haven't changed the value of
realbits
/lkml/2015/4/24/156)
Feel free to apply for stable. I also tested the patch on Linux 3.10.5x
so it ought to work all the way back to at least 3.10.
Best regards,
Marek Vasut
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);
And, according to include/linux/module.h, this states the license is GPL
v2 or later. So I think either the comment at the top of this file or
the ident used in the MODULE_LICENSE() macro should be changed.
I'm OK with v2+ or later .
Best regards,
Marek Vasut
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do this.)
Yes, the intent is to fix this by adding dma support to the driver,
eventually.
The patch might be still useful for other hardware with developing SPI
support.
Please just fix the controller driver to correctly handle arbitrary transfer
lengths.
Best regards,
Marek Vasut
.
The 'retlen' points to a variable representing the number of data bytes
written/read (see include/linux/mtd/mtd.h) by the current invocation of
the function. This variable must be set, not incremented.
Otherwise, the patch is correct I believe:
Acked-by: Marek Vasut ma...@denx.de
Signed-off
On Friday, May 01, 2015 at 09:05:15 AM, Michal Suchanek wrote:
On 1 May 2015 at 01:13, Marek Vasut ma...@denx.de wrote:
On Thursday, April 30, 2015 at 11:13:12 PM, Michal Suchanek wrote:
The sector size of the flash memory is unclear from datasheet or may
possibly vary between chips so add
On Monday, May 04, 2015 at 01:11:03 PM, Michal Suchanek wrote:
Hello,
Hi!
On 1 May 2015 at 16:20, Marek Vasut ma...@denx.de wrote:
On Friday, May 01, 2015 at 09:05:15 AM, Michal Suchanek wrote:
On 1 May 2015 at 01:13, Marek Vasut ma...@denx.de wrote:
I can determine
On Monday, May 04, 2015 at 03:18:56 PM, Michal Suchanek wrote:
On 4 May 2015 at 14:12, Marek Vasut ma...@denx.de wrote:
On Monday, May 04, 2015 at 01:11:03 PM, Michal Suchanek wrote:
Hello,
Hi!
On 1 May 2015 at 16:20, Marek Vasut ma...@denx.de wrote:
On Friday, May 01, 2015 at 09
On Monday, May 04, 2015 at 03:39:44 PM, Michal Suchanek wrote:
On 4 May 2015 at 15:35, Marek Vasut ma...@denx.de wrote:
On Monday, May 04, 2015 at 03:18:56 PM, Michal Suchanek wrote:
On 4 May 2015 at 14:12, Marek Vasut ma...@denx.de wrote:
On Monday, May 04, 2015 at 01:11:03 PM, Michal
message
This V2 goes past the diffstat, so that when the patch is applied, it
doesn't end up in the log.
Signed-off-by: Michal Suchanek hramr...@gmail.com
Acked-by: Marek Vasut ma...@denx.de
---
drivers/mtd/devices/m25p80.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Aka. Vn changes
it should be all ones after
erasing).
3) Erase sector 0
4) Read some 128 KiB back
5) Observe what is the difference.
Best regards,
Marek Vasut
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to handle ALC, ALT, ALP ones as well.
Signed-off-by: Martin Liska marxin.li...@gmail.com
Signed-off-by: Marek Vasut ma...@denx.de
Signed-off-by: Gabriele Mazzotta gabriele@gmail.com
Cc: Zhang Rui rui.zh...@intel.com
---
This continues http://marc.info/?t=14016346322
I've
/ACPIspec50.pdf
Signed-off-by: Martin Liska marxin.li...@gmail.com
Signed-off-by: Marek Vasut ma...@denx.de
Signed-off-by: Gabriele Mazzotta gabriele@gmail.com
Cc: Zhang Rui rui.zh...@intel.com
Thank you guys for finally getting this mainline :)
Best regards,
Marek Vasut
you encounter another performance regression after upgrading
to a more modern kernel ;-)
Why don't you use the Altera VIP FB on SoCFPGA ?
Best regards,
Marek Vasut
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More
On Wednesday, June 03, 2015 at 11:26:42 PM, Michal Suchanek wrote:
The SPI NOR transfers mysteriously fail so add more debug prints about
SPI transactions.
Signed-off-by: Michal Suchanek hramr...@gmail.com
dev_dbg() and friends would certainly be nicer here.
Best regards,
Marek Vasut
data transfers are less likely
to be affected.
Sounds like the DMA engine driver should be fixed.
Best regards,
Marek Vasut
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. Change this condition to a warning so that flash without
partitions can be accessed on Exynos.
I have to admit the rationale for this patch is not very clear to me, sorry.
Can you please explain this a bit more ?
Best regards,
Marek Vasut
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. +
Using this option may severely degrade performance and
+ possibly flash memory life when max_tx_len is
smaller than + flash page size (typically 256 bytes)
Will we need similar patch for all other SPI slave drivers, like SPI NAND ?
Best regards,
Marek Vasut
On Thursday, June 04, 2015 at 05:40:58 PM, Michal Suchanek wrote:
On 4 June 2015 at 17:28, Marek Vasut ma...@denx.de wrote:
On Thursday, June 04, 2015 at 06:54:00 AM, Michal Suchanek wrote:
On 4 June 2015 at 00:58, Marek Vasut ma...@denx.de wrote:
On Wednesday, June 03, 2015 at 11:26:40 PM
On Thursday, June 04, 2015 at 06:31:45 AM, Michal Suchanek wrote:
On 4 June 2015 at 01:03, Marek Vasut ma...@denx.de wrote:
On Wednesday, June 03, 2015 at 11:26:41 PM, Michal Suchanek wrote:
On sunxi the SPI controller currently does not have DMA support and
fails any transfer larger than
nonsense.
Best regards,
Marek Vasut
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Please read the FAQ at http://www.tux.org/lkml/
On Thursday, June 04, 2015 at 06:21:32 AM, Michal Suchanek wrote:
On 4 June 2015 at 00:53, Marek Vasut ma...@denx.de wrote:
On Wednesday, June 03, 2015 at 11:26:39 PM, Michal Suchanek wrote:
Hello,
Hi,
this patch series makes it possible to access the SPI NOR flash in the
Samsung
On Thursday, June 04, 2015 at 06:54:00 AM, Michal Suchanek wrote:
On 4 June 2015 at 00:58, Marek Vasut ma...@denx.de wrote:
On Wednesday, June 03, 2015 at 11:26:40 PM, Michal Suchanek wrote:
On Exynos it is necessary to set SPI controller parameters that apply to
a SPI slave in a DT subnode
if the g_audio can
work well with an ubuntu PC (make sure your codec works well).
ci_hdrc.0 request length too big for isochronous
Doesn't this just mean it cannot transfer such a long buffer via ISO pipe ?
I guess the UAC should send smaller buffers to work with the CI HDRC?
Best regards,
Marek Vasut
On Saturday, May 23, 2015 at 06:41:50 PM, Dmitry Torokhov wrote:
On May 23, 2015 9:38:54 AM PDT, Marek Vasut ma...@denx.de wrote:
On Saturday, May 23, 2015 at 12:58:32 AM, Dmitry Torokhov wrote:
The STMPE MFD is only used with device tree configured systems (and
STMPE
MFD core depends
);
input_set_abs_params(idev, ABS_Y, 0, XY_MASK, 0, 0);
input_set_abs_params(idev, ABS_PRESSURE, 0x0, 0xff, 0, 0);
[...]
Best regards,
Marek Vasut
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On Tuesday, August 18, 2015 at 03:24:44 AM, Brian Norris wrote:
I'm not very helpful here, so hopefully Viet can be of more use:
Yup :)
On Mon, Aug 17, 2015 at 07:53:23PM +0200, Marek Vasut wrote:
On Monday, August 17, 2015 at 06:03:38 PM, Brian Norris wrote:
Also, I cannot find any
, I cannot find any documentation for this IP block even if I search
through
Quartus/QSys, is there any proper documentation available anywhere?
[...]
Best regards,
Marek Vasut
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On Thursday, August 20, 2015 at 08:55:05 AM, vn...@altera.com wrote:
From: VIET NGA DAO vn...@altera.com
Altera Quad SPI Controller is a soft IP which enables access to
Altera EPCS and EPCQ flash chips. This patch adds driver
for these devices.
Signed-off-by: VIET NGA DAO vn...@altera.com
On Monday, August 24, 2015 at 02:49:24 PM, Russell King - ARM Linux wrote:
Hi Russell,
On Mon, Aug 24, 2015 at 01:03:51PM +0200, Marek Vasut wrote:
These are functions, not macros :)
btw is there any reason for these ? I'd say, just put the read*() and
write*() functions directly
On Monday, August 24, 2015 at 07:04:38 PM, Cyrille Pitchen wrote:
Hi Marek,
Hi!
Le 24/08/2015 13:03, Marek Vasut a écrit :
On Monday, August 24, 2015 at 12:14:00 PM, Cyrille Pitchen wrote:
This driver add support to the new Atmel QSPI controller embedded into
sama5d2x SoCs. It expects
On Monday, August 24, 2015 at 06:42:46 PM, Cyrille Pitchen wrote:
Hi Marek,
Hi!
[...]
- * Dummy Cycle calculation for different type of read.
- * It can be used to support more commands with
- * different dummy cycle requirements.
- */
-static inline int
On Thursday, August 20, 2015 at 09:37:33 AM, Viet Nga Dao wrote:
Hi,
Hi,
On Tuesday, August 18, 2015 at 03:24:44 AM, Brian Norris wrote:
I'm not very helpful here, so hopefully Viet can be of more use:
Yup :)
On Mon, Aug 17, 2015 at 07:53:23PM +0200, Marek Vasut wrote:
On Monday
On Thursday, August 20, 2015 at 10:13:30 AM, Nga Chi wrote:
On Thu, Aug 20, 2015 at 4:03 PM, Marek Vasut ma...@denx.de wrote:
On Thursday, August 20, 2015 at 08:55:05 AM, vn...@altera.com wrote:
From: VIET NGA DAO vn...@altera.com
Altera Quad SPI Controller is a soft IP which enables
On Thursday, August 20, 2015 at 10:06:29 AM, Viet Nga Dao wrote:
On Thu, Aug 20, 2015 at 3:55 PM, Marek Vasut ma...@denx.de wrote:
On Thursday, August 20, 2015 at 09:37:33 AM, Viet Nga Dao wrote:
Hi,
Hi,
On Tuesday, August 18, 2015 at 03:24:44 AM, Brian Norris wrote:
I'm
is the problem ?
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Marek Vasut
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Please read the FAQ at http://www.tux.org/lkml/
to find out the
solution so that the driver does not need to do any dirty hacking. And
so, this table should still be here even hardware fix will take place
or not.
[...]
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Marek Vasut
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and keep on dialoging with the Micron memory.
Signed-off-by: Cyrille Pitchen cyrille.pitc...@atmel.com
Awesome,
Acked-by: Marek Vasut ma...@denx.de
If this could be applied separately (since I want to use the same functionality
for the Cadence QSPI driver), I'd be really happy too :)
Best
ack has any value in here, feel free to add it, the bindings look
pretty standard anyway:
Acked-by: Marek Vasut ma...@denx.de
Best regards,
Marek Vasut
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On Monday, August 24, 2015 at 12:13:58 PM, Cyrille Pitchen wrote:
The number of dummy cycles used during Fast Read commands can be reduced
to improve transfer performances. Each manufacturer has a dedicated set of
registers to provide the memory with the exact number of dummy cycles it
should
On Monday, August 24, 2015 at 12:14:00 PM, Cyrille Pitchen wrote:
This driver add support to the new Atmel QSPI controller embedded into
sama5d2x SoCs. It expects a NOR memory to be connected to the QSPI
controller.
Signed-off-by: Cyrille Pitchen cyrille.pitc...@atmel.com
Acked-by: Nicolas
On Thursday, August 20, 2015 at 10:19:25 PM, Brian Norris wrote:
On Thu, Aug 20, 2015 at 12:06:36PM +0200, Alexander Stein wrote:
On Thursday 20 August 2015 10:03:38, Marek Vasut wrote:
+Example:
+
+ quadspi_controller_0: quadspi@0x180014a0
On Wednesday, July 29, 2015 at 06:16:21 AM, Michal Suchanek wrote:
On 28 July 2015 at 20:15, Marek Vasut ma...@denx.de wrote:
On Tuesday, July 28, 2015 at 11:23:02 AM, Michal Suchanek wrote:
The spi_nor read and write functions pass thru the mtd retlen to the
chip-specific read and write
-nor prop for all
new SPI NORs without growing this table ?
Best regards,
Marek Vasut
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Please read the FAQ
) },
/* Spansion -- single (large) sector size only, at least
You might want to split this into two patches, but see my comment on 1/2
and please wait for Brian's confirmation there before you do anything.
Thanks!
Best regards,
Marek Vasut
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On Tuesday, July 28, 2015 at 04:36:29 PM, Michal Suchanek wrote:
On 28 July 2015 at 16:33, Marek Vasut ma...@denx.de wrote:
On Tuesday, July 28, 2015 at 11:07:57 AM, Michal Suchanek wrote:
This 1.8V SPI NOR flash is found on ARM Chromebook XE303C and reads
something like 25LQ32VIG
On Thursday, July 30, 2015 at 02:18:09 PM, Michal Suchanek wrote:
On 30 July 2015 at 13:24, Marek Vasut ma...@denx.de wrote:
On Monday, July 27, 2015 at 10:43:05 PM, Michal Suchanek wrote:
On 27 July 2015 at 19:43, Marek Vasut ma...@denx.de wrote:
On Monday, July 27, 2015 at 11:46:25 AM
,
the compiler will complain loudly about mismatching data types, right ? :)
Best regards,
Marek Vasut
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Please read
On Tuesday, July 28, 2015 at 05:19:18 PM, Rafał Miłecki wrote:
On 28 July 2015 at 16:33, Marek Vasut ma...@denx.de wrote:
On Tuesday, July 28, 2015 at 11:07:57 AM, Michal Suchanek wrote:
This 1.8V SPI NOR flash is found on ARM Chromebook XE303C and reads
something like 25LQ32VIG
On Tuesday, July 28, 2015 at 05:22:17 PM, Rafał Miłecki wrote:
On 28 July 2015 at 16:33, Marek Vasut ma...@denx.de wrote:
On Tuesday, July 28, 2015 at 11:07:58 AM, Michal Suchanek wrote:
First chip reads Pm25LD020 or Pm25L0020. Found on some WD HDD PCB.
Identified as PMC Pm25LD020.
Flash
= cqspi_read;
+ nor-write = cqspi_write;
+ nor-erase = cqspi_erase;
+
+ nor-prepare = cqspi_prep;
+
+ /*
+ * Here is a 'nasty hack' from Marek Vasut to pick
+ * up OF properties from flash device subnode
On Tuesday, July 28, 2015 at 11:23:02 AM, Michal Suchanek wrote:
The spi_nor read and write functions pass thru the mtd retlen to the
chip-specific read and write function. This makes it difficult to check
for errors in read and write functions and these errors are not checked.
This leads to
On Tuesday, July 28, 2015 at 07:38:02 PM, Graham Moore wrote:
A commit message would be really nice :-)
Signed-off-by: Graham Moore grmo...@opensource.altera.com
---
V2: Add cdns prefix to driver-specific bindings.
V3: Use existing property is-decoded-cs instead of creating a duplicate,
On Tuesday, July 28, 2015 at 08:22:05 PM, Graham Moore wrote:
On 07/28/2015 01:07 PM, Marek Vasut wrote:
On Tuesday, July 28, 2015 at 07:38:03 PM, Graham Moore wrote:
DTTO here.
Thanks a lot for working on the driver though -- would you like me to
continue reviewing or just take
On Wednesday, August 05, 2015 at 10:27:05 AM, Michal Suchanek wrote:
On 4 August 2015 at 18:42, Marek Vasut ma...@denx.de wrote:
On Tuesday, August 04, 2015 at 08:42:51 AM, Michal Suchanek wrote:
On 3 August 2015 at 23:46, Marek Vasut ma...@denx.de wrote:
On Monday, August 03, 2015 at 08
On Monday, July 27, 2015 at 10:43:05 PM, Michal Suchanek wrote:
On 27 July 2015 at 19:43, Marek Vasut ma...@denx.de wrote:
On Monday, July 27, 2015 at 11:46:25 AM, Michal Suchanek wrote:
On 24 July 2015 at 10:34, Marek Vasut ma...@denx.de wrote:
On Thursday, July 23, 2015 at 07:03:47 PM
On Tuesday, August 04, 2015 at 08:42:51 AM, Michal Suchanek wrote:
On 3 August 2015 at 23:46, Marek Vasut ma...@denx.de wrote:
On Monday, August 03, 2015 at 08:39:01 PM, Michal Suchanek wrote:
Change the return value of spi-nor device read and write methods to
allow returning amount of data
) },
Is the SST_WRITE not needed on this device ?
Otherwise, looks pretty obvious :)
{ sst25wf040, INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE)
},
{ sst25wf080, INFO(0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE)
},
Best regards,
Marek Vasut
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On Saturday, August 15, 2015 at 10:38:59 AM, Alexis Ballier wrote:
On Fri, 14 Aug 2015 22:45:14 +0200
Marek Vasut ma...@denx.de wrote:
On Friday, August 14, 2015 at 07:35:39 PM, Alexis Ballier wrote:
It is a 256KiB flash with 4 KiB erase sectors
and 64KiB overlay blocks
On Wednesday, August 12, 2015 at 03:05:48 AM, Vikas MANOCHA wrote:
Hi Marek,
Hi,
-Original Message-
From: Marek Vasut [mailto:ma...@denx.de]
Sent: Wednesday, August 05, 2015 4:15 PM
To: Vikas MANOCHA
Cc: Graham Moore; linux-...@lists.infradead.org; David Woodhouse; Brian
On Wednesday, August 05, 2015 at 08:29:11 PM, vikasm wrote:
Hi Graham,
Hi vikasm,
On 07/28/2015 10:38 AM, Graham Moore wrote:
Signed-off-by: Graham Moore grmo...@opensource.altera.com
---
V2: use NULL instead of modalias in spi_nor_scan call
V3: Use existing property is-decoded-cs
On Monday, July 27, 2015 at 10:41:37 AM, Cyrille Pitchen wrote:
Hi Marek,
Le 22/07/2015 15:50, Marek Vasut a écrit :
On Wednesday, July 22, 2015 at 03:17:10 PM, Cyrille Pitchen wrote:
This driver add support to the new Atmel QSPI controller embedded into
sama5d2x SoCs. It expects a NOR
On Monday, July 27, 2015 at 11:46:25 AM, Michal Suchanek wrote:
On 24 July 2015 at 10:34, Marek Vasut ma...@denx.de wrote:
On Thursday, July 23, 2015 at 07:03:47 PM, Michal Suchanek wrote:
Hi!
[...]
It's probably slower to set up DMA for 2-byte commands but it might
work
On Thursday, July 23, 2015 at 07:03:47 PM, Michal Suchanek wrote:
Hi!
[...]
It's probably slower to set up DMA for 2-byte commands but it might
work nonetheless.
It is, the overhead will be considerable. It might help the stability
though. I'm really looking forward to the results!
in
the next iteration.
Best regards,
Marek Vasut
From e305b9a9cd80e56aeaa19b3c2a5bb26ba3adf8d7 Mon Sep 17 00:00:00 2001
From: Marek Vasut ma...@denx.de
Date: Fri, 24 Jul 2015 10:10:23 +0200
Subject: [PATCH 1/2] mtd: spi-nor: Fix SRAM config on CQSPI
Make sure the SRAM configuration register is loaded
On Friday, July 24, 2015 at 06:12:01 PM, Graham Moore wrote:
On 07/24/2015 07:45 AM, Marek Vasut wrote:
On Monday, March 23, 2015 at 02:36:21 PM, Graham Moore wrote:
Signed-off-by: Graham Moore grmo...@opensource.altera.com
---
V2: Add cdns prefix to driver-specific bindings.
V3: Use
a formula would be needed that translates arbitrary
client settings to transfer size limit and there would be need to
somehow get the client settings to the formula in the dmaengine
driver.
Thanks
Michal
Best regards,
Marek Vasut
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On Wednesday, July 22, 2015 at 10:38:14 AM, Michal Suchanek wrote:
On 22 July 2015 at 10:24, Marek Vasut ma...@denx.de wrote:
On Wednesday, July 22, 2015 at 10:18:04 AM, Michal Suchanek wrote:
On 22 July 2015 at 09:58, Marek Vasut ma...@denx.de wrote:
On Wednesday, July 22, 2015 at 09:45
On Wednesday, July 22, 2015 at 09:45:27 AM, Michal Suchanek wrote:
On 22 July 2015 at 09:33, Marek Vasut ma...@denx.de wrote:
On Wednesday, July 22, 2015 at 09:30:54 AM, Michal Suchanek wrote:
On 22 July 2015 at 06:49, Vinod Koul vinod.k...@intel.com wrote:
On Tue, Jul 21, 2015 at 10:14
On Wednesday, July 22, 2015 at 03:17:10 PM, Cyrille Pitchen wrote:
This driver add support to the new Atmel QSPI controller embedded into
sama5d2x SoCs. It expects a NOR memory to be connected to the QSPI
controller.
Signed-off-by: Cyrille Pitchen cyrille.pitc...@atmel.com
---
[...]
+/*
*mtd)
{
return mtd-priv;
[...]
Best regards,
Marek Vasut
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Please read the FAQ at http
how low you can get with the negotiations ? This way, you'd
be able to effectively auto-detect this value at probe-time.
I might be wrong though :)
Best regards,
Marek Vasut
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On Wednesday, July 22, 2015 at 10:18:04 AM, Michal Suchanek wrote:
On 22 July 2015 at 09:58, Marek Vasut ma...@denx.de wrote:
On Wednesday, July 22, 2015 at 09:45:27 AM, Michal Suchanek wrote:
On 22 July 2015 at 09:33, Marek Vasut ma...@denx.de wrote:
On Wednesday, July 22, 2015 at 09:30
On Friday, July 24, 2015 at 07:16:48 PM, Graham Moore wrote:
On 07/24/2015 11:25 AM, Marek Vasut wrote:
On Friday, July 24, 2015 at 06:12:01 PM, Graham Moore wrote:
On 07/24/2015 07:45 AM, Marek Vasut wrote:
On Monday, March 23, 2015 at 02:36:21 PM, Graham Moore wrote:
Signed-off
On Wednesday, July 22, 2015 at 06:59:21 PM, Cyrille Pitchen wrote:
Hi Marek,
Le 22/07/2015 15:43, Marek Vasut a écrit :
On Wednesday, July 22, 2015 at 03:17:07 PM, Cyrille Pitchen wrote:
Depending on the SPI clock frequency, the Fast Read op code and the
Single/Dual Data Rate mode
On Wednesday, July 22, 2015 at 06:25:20 PM, Cyrille Pitchen wrote:
Hi Marek,
Le 22/07/2015 15:41, Marek Vasut a écrit :
On Wednesday, July 22, 2015 at 03:17:06 PM, Cyrille Pitchen wrote:
Once the Quad SPI mode has been enabled on a Micron flash memory, this
device expects ALL
latency code.
The latency code can be found into the memory datasheet and depends on the
SPI clock frequency, the Fast Read op code and the Single/Dual Data Rate
mode.
Shouldn't you be able to derive the latency code from the above information,
which you already know then ?
Best regards,
Marek
On Thursday, July 16, 2015 at 03:19:35 AM, Brian Norris wrote:
On Wed, Jul 15, 2015 at 07:15:50PM +0200, Marek Vasut wrote:
On Wednesday, July 15, 2015 at 05:59:46 PM, Brian Norris wrote:
1. Fix up the SPI driver so that it knows how to break large SPI
transfers up into smaller segments
On Wednesday, July 15, 2015 at 05:59:46 PM, Brian Norris wrote:
Hi Michal,
Hi all,
On Wed, Jul 15, 2015 at 01:52:27PM +0200, Marek Vasut wrote:
The problem is, if you add a new DT binding, you'd have to support it
forever, no matter how bad idea that binding turned out to be.
Agreed
On Monday, July 20, 2015 at 11:23:39 AM, Cyrille Pitchen wrote:
Hi Marek,
Hi!
Le 16/07/2015 19:44, Marek Vasut a écrit :
On Thursday, July 16, 2015 at 05:27:51 PM, Cyrille Pitchen wrote:
Hi!
Both the SPI controller and the NOR flash memory need to agree on the
number of dummy
with a suggested value which can be tuned depending on the system
seems more viable.
The problem is, if you add a new DT binding, you'd have to support it
forever, no matter how bad idea that binding turned out to be.
Best regards,
Marek Vasut
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On Thursday, October 29, 2015 at 08:24:48 AM, Boris Brezillon wrote:
> Hi Robert,
Hi!
> On Thu, 29 Oct 2015 07:32:33 +0100
>
> Robert Jarzmik <robert.jarz...@free.fr> wrote:
> > Marek Vasut <ma...@denx.de> writes:
> > >> Isn't there the case of
ter
> MTD device and a NAND device.
Do some sorts of chipselects come into play here ? Ie. you can have one master
with multiple NAND chips connected to it.
Best regards,
Marek Vasut
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On Wednesday, October 28, 2015 at 05:32:15 PM, Boris Brezillon wrote:
> Hi Marek,
Hi Boris,
> On Wed, 28 Oct 2015 17:11:14 +0100
>
> Marek Vasut <ma...@denx.de> wrote:
> > On Wednesday, October 28, 2015 at 08:58:13 AM, Boris Brezillon wrote:
>
le) will be programmed
> to handle both chips at the same time, and calculate CRC on both chips,
> etc ... I hope the assertion "physical chip should have its own instance
> of nand_chip + mtd_info" does take into account this example.
>
> I don't know if there is actually any u
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