On Thu, Jul 05, 2018 at 01:26:08PM +0100, Mark Rutland wrote:
> On Thu, Jul 05, 2018 at 01:27:56PM +0200, Tobias Tefke wrote:
> > These words are pronounced (and start) with a vowel sound.
> > Therefore the article we use has to be 'an' instead of 'a'.
> >
On Sun, Apr 15, 2018 at 12:26:44AM +0200, KarimAllah Ahmed wrote:
> Switch 'requests' to be explicitly 64-bit and update BUILD_BUG_ON check to
> use the size of "requests" instead of the hard-coded '32'.
>
> That gives us a bit more room again for arch-specific requests as we
> already ran out of
arm.com
[3] https://lkml.kernel.org/r/20180621121321.4761-1-mark.rutl...@arm.com
[4] git://git.kernel.org/pub/scm/linux/kernel/git/mark/linux.git
atomics/generated
Mark Rutland (11):
atomics/x86: reduce arch_cmpxchg64*() instrumentation
atomics: simplify cmpxchg() instrumentation
atomics
arm.com
[3] https://lkml.kernel.org/r/20180621121321.4761-1-mark.rutl...@arm.com
[4] git://git.kernel.org/pub/scm/linux/kernel/git/mark/linux.git
atomics/generated
Mark Rutland (11):
atomics/x86: reduce arch_cmpxchg64*() instrumentation
atomics: simplify cmpxchg() instrumentation
atomics
There should be no functional change as a result of this patch.
Signed-off-by: Mark Rutland
Acked-by: Peter Zijlstra (Intel)
Cc: Boqun Feng
Cc: Dmitry Vyukov
Cc: Ingo Molnar
Cc: Will Deacon
---
include/asm-generic/atomic-instrumented.h | 100 +-
1 file change
very thin (the only difference is not changing *old on success, which
most callers don't seem to care about).
So rework the whole thing to use atomic_long_t and its accessors
directly.
While there, fixup all the horrible comment styles.
Cc: Peter Hurley
Reported-by: Mark Rutland
Reviewed-by:
While we instrument all of the (non-relaxed) atomic_*() functions and
cmpxchg(), we missed xchg().
Let's add instrumentation for xchg(), fixing up x86 to implement
arch_xchg().
Signed-off-by: Mark Rutland
Acked-by: Peter Zijlstra (Intel)
Cc: Boqun Feng
Cc: Dmitry Vyukov
Cc: H. Peter
cmpxchg_double*() again. We can revisit the issue if build failures
reappear.
Signed-off-by: Mark Rutland
Acked-by: Peter Zijlstra (Intel)
Cc: Arnd Bergmann
Cc: Boqun Feng
Cc: Dmitry Vyukov
Cc: Ingo Molnar
Cc: Will Deacon
---
include/asm-generic/atomic-instrumented.h | 21 -
write()
arch_cmpxchg()
Let's fix this up and call the arch_ equivalents, resulting in:
cmpxchg64()
kasan_check_write()
arch_cmpxchg64()
arch_cmpxchg()
Signed-off-by: Mark Rutland
Acked-by: Peter Zijlstra (Intel)
Cc: Boqun Feng
Cc: Dmitry Vyukov
Cc: H. Peter Anvin
ce as static inline functions rather
than macros.
* The prototypes for fallbacks are arragned consistently with the return
type on a separate line to try to keep to a sensible line length.
There should be no functional change as a result of this patch.
Signed-off-by: Mark Rutland
Acked-by:
: Mark Rutland
Acked-by: Peter Zijlstra (Intel)
Cc: Andrea Parri
Cc: Boqun Feng
Cc: Ingo Molnar
Cc: Will Deacon
---
arch/alpha/include/asm/atomic.h | 8
arch/powerpc/include/asm/atomic.h | 17 +
arch/riscv/include/asm/atomic.h | 17 +
include/linux
infrastructure is updated to cover
the new scripts.
There should be no functional change as a result of this patch.
Signed-off-by: Mark Rutland
Acked-by: Peter Zijlstra (Intel)
Cc: Boqun Feng
Cc: Ingo Molnar
Cc: Will Deacon
---
MAINTAINERS | 1 +
scr
tures to make use of the instrumented
atomics.
Signed-off-by: Mark Rutland
Acked-by: Peter Zijlstra (Intel)
Cc: Alexander Potapenko
Cc: Andrey Ryabinin
Cc: Arnd Bergmann
Cc: Boqun Feng
Cc: Dmitry Vyukov
Cc: Ingo Molnar
Cc: Will Deacon
---
include/asm-generic/atomic-i
generated headers are up-to-date.
Signed-off-by: Mark Rutland
Cc: Boqun Feng
Cc: Ingo Molnar
Cc: Peter Zijlstra (Intel)
Cc: Will Deacon
---
Kbuild | 18 --
scripts/atomic/check-atomics.sh | 19 +++
2 files changed, 35 insertions(+), 2
pxchg wrappers).
Signed-off-by: Mark Rutland
Acked-by: Peter Zijlstra (Intel)
Cc: Catalin Marinas
Cc: Ingo Molnar
Cc: Will Deacon
---
arch/arm64/include/asm/atomic.h | 237 +-
arch/arm64/include/asm/atomic_ll_sc.h | 28 ++--
arch/arm64/include/asm/atomic_
On Thu, Jul 05, 2018 at 05:40:13PM +0100, Mark Rutland wrote:
> This series scripts the generation of the various atomic headers, to ensure
> that the various atomic APIs remain consistent, reducing the risk of human
> error, and simplifying future rework. This fleshes out the ins
ons into the atomic_long_* API, bringing it into line with the
atomic_* and atomic64_* APIs.
Signed-off-by: Mark Rutland
Acked-by: Peter Zijlstra (Intel)
Cc: Arnd Bergmann
Cc: Boqun Feng
Cc: Ingo Molnar
Cc: Will Deacon
---
include/asm-generic/atomic-long.h | 1173
On Mon, Jul 02, 2018 at 01:30:19AM +0800, Guo Ren wrote:
> +static int csky_of_cpu(struct device_node *node)
> +{
> + const char *status;
> + int cpu;
> +
> + if (of_property_read_u32(node, "reg", &cpu))
> + goto error;
> +
> + if (cpu >= NR_CPUS)
> + goto er
On Thu, Jul 05, 2018 at 02:14:28PM -0700, Joe Perches wrote:
> On Thu, 2018-07-05 at 11:19 -0700, Prakruthi Deepak Heragu wrote:
> > mb() API can relpace the dsb() API in the kernel code. So, dsb() usage
> > is discouraged. However, there are exceptions when dsb is used in a
> > variable or a funct
On Thu, Jul 05, 2018 at 07:23:06PM +0200, Peter Zijlstra wrote:
> On Thu, Jul 05, 2018 at 05:40:49PM +0100, Mark Rutland wrote:
>
> > * The fallbacks are not expected to change very often, and are not
> > affected by machine details or configuration options, so regenerat
evice_tree+0x38/0x4c
setup_arch+0x3b0/0xcc4
start_kernel+0xd8/0xb9c
In the dryrun pass we don't actually use the pprev value, so let's only
set it when !dryrun, and avoid the undefined behaviour.
Signed-
On Fri, Jul 06, 2018 at 07:32:01PM +0800, Guo Ren wrote:
> On Fri, Jul 06, 2018 at 06:24:33AM +0100, Mark Rutland wrote:
> > > + if (cpu >= NR_CPUS)
> > > + goto error;
> > > +
> > > + if (of_property_read_string(node, "stat
ation of offset into tag_get(), such
that this only happens when node is not NULL. Callers are updated to
pass the relevant slot, rather than the offset derived from it.
Signed-off-by: Mark Rutland
Cc: Andrew Morton
Cc: Matthew Wilcox
Cc: valdis.kletni...@vt.edu
---
lib/radix-tree.c | 9 -
On Fri, Jul 06, 2018 at 07:25:40AM -0700, Matthew Wilcox wrote:
> On Fri, Jul 06, 2018 at 02:41:44PM +0100, Mark Rutland wrote:
> > When idr_alloc() is called for the first time on an IDR (which has no
> > nodes in its radix tree), we end up with calculate_count() calling
>
On Fri, Jul 06, 2018 at 03:36:04PM +0100, Mark Rutland wrote:
> On Fri, Jul 06, 2018 at 07:25:40AM -0700, Matthew Wilcox wrote:
> > On Fri, Jul 06, 2018 at 02:41:44PM +0100, Mark Rutland wrote:
> > > When idr_alloc() is called for the first time on an IDR (which has no
> &
On Fri, Jul 06, 2018 at 08:26:31PM +0800, Guo Ren wrote:
> On Fri, Jul 06, 2018 at 12:43:52PM +0100, Mark Rutland wrote:
> > Please see the devicetree spec [1], section 2.3.4. Valid values are:
> >
> > * "okay" // equivalent to no status property present
> >
On Fri, Jul 06, 2018 at 09:20:44AM -0700, Eric Dumazet wrote:
>
>
> On 07/06/2018 08:54 AM, Mark Rutland wrote:
> > On Fri, Jul 06, 2018 at 08:39:11AM -0700, Eric Dumazet wrote:
> >>
> >>
> >> On 07/06/2018 07:57 AM, Mark Rutland wrote:
> >&
start_kernel(void)
Minor nit: can we please keep asmlinkage first, e.g.
asmlinkage notrace void secondary_start_kernel(void)
Either way:
Acked-by: Mark Rutland
Thanks,
Mark.
> {
> u64 mpidr = read_cpuid_mpidr() & MPIDR_HWID_BITMASK;
> struct mm_struct *mm = &init_mm;
> --
> 1.9.1
>
Hi,
On Thu, Jun 07, 2018 at 09:56:48AM -0400, Agustin Vega-Frias wrote:
> Selection of these events can be envisioned as indexing them from
> a 3D matrix:
> - the first index selects a Region Event Selection Register (PMRESRx_EL0)
> - the second index selects a group from which only one event at a
On Tue, Jun 12, 2018 at 04:41:32PM -0400, Agustin Vega-Frias wrote:
> On 2018-06-12 10:40, Mark Rutland wrote:
> > On Thu, Jun 07, 2018 at 09:56:48AM -0400, Agustin Vega-Frias wrote:
> > > +/*
> > > + * Qualcomm Technologies CPU PMU IMPLEMENTATION DEFIN
On Fri, Jun 15, 2018 at 06:03:22PM +0800, Jin Yao wrote:
> When doing sampling, for example:
>
> perf record -e cycles:u ...
>
> On workloads that do a lot of kernel entry/exits we see kernel
> samples, even though :u is specified. This is due to skid existing.
>
> This might be a security issue
On Mon, Dec 10, 2018 at 05:50:33PM +, Mark Rutland wrote:
> Hi Ingo,
>
> I hope that these atomic scripting patches address your concerns with
> the atomics scripting infrastructure. These are based on the tip
> locking/core branch, leaving the headers checked-in.
>
> Th
in the kernel.
Reported-by: Naresh Kamboju
Suggested-by: Will Deacon
Signed-off-by: Anders Roxell
[Mark: rework commit message]
Signed-off-by: Mark Rutland
---
scripts/atomic/atomic-tbl.sh | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/scripts/atomic/atomic-tbl.sh b
ion that
anyone actually sending patches will have a working coreutils.
Are you happy to pick these up?
Thanks,
Mark.
Anders Roxell (1):
locking/atomics: Change 'fold' to 'grep'
Mark Rutland (1):
locking/atomics: Check atomic headers with sha1sum
include/asm-generic/atomic
this case.
Presumably, most developers have a working coreutils installation.
Signed-off-by: Mark Rutland
Cc: Andrew Morton
Cc: Boqun Feng
Cc: Ingo Molnar
Cc: Peter Zijlstra
Cc: Will Deacon
---
include/asm-generic/atomic-instrumented.h | 1 +
include/asm-generic/atomic-long.h
Hi Ingo,
On Thu, Dec 06, 2018 at 05:15:28PM +0100, Ingo Molnar wrote:
>
> * Will Deacon wrote:
>
> > [+ Ingo and Mark]
> >
> > On Tue, Dec 04, 2018 at 10:47:13PM +0100, Anders Roxell wrote:
> > > Some distibutions and build systems doesn't include 'fold' from
> > > coreutils default.
> > >
>
Hi Ingo,
On Thu, Dec 06, 2018 at 05:13:44PM +0100, Ingo Molnar wrote:
>
> * Mark Rutland wrote:
>
> > Andrew and Ingo report that the check-atomics.sh script is simply too
> > slow to run for every kernel build, and it's impractical to make it
> > faster without
On Fri, Jan 04, 2019 at 10:33:40AM +0100, Pavel Machek wrote:
> On Fri 2019-01-04 09:21:30, Marc Zyngier wrote:
> > On 03/01/2019 20:29, Pavel Machek wrote:
> > > On Fri 2018-12-07 18:39:25, Kristina Martsenko wrote:
> > >> From: Mark Rutland
> > >>
On Fri, Jan 04, 2019 at 11:41:45PM +0100, Torsten Duwe wrote:
> On Fri, Jan 04, 2019 at 01:06:48PM -0500, Steven Rostedt wrote:
> > On Fri, 4 Jan 2019 17:50:18 +
> > Mark Rutland wrote:
> >
> > > At Linux Plumbers, I had a conversation with Steve Rostedt, and w
On Thu, Dec 13, 2018 at 03:18:23PM +, Mark Brown wrote:
> On Thu, Dec 13, 2018 at 01:29:10PM +0100, Anders Roxell wrote:
>
> > With this new config option, we can boot a allmodconfig kernel in qemu.
> > Config options SERIAL_AMBA_PL011, SERIAL_AMBA_PL011_CONSOLE, UNIX needs
> > to be enabled i
Hi,
As a general thing, please Cc LAKML on patches for arm64.
On Thu, Dec 13, 2018 at 01:29:10PM +0100, Anders Roxell wrote:
> With this new config option, we can boot a allmodconfig kernel in qemu.
> Config options SERIAL_AMBA_PL011, SERIAL_AMBA_PL011_CONSOLE, UNIX needs
> to be enabled in order
On Mon, Jan 07, 2019 at 07:21:20PM +0800, Miles Chen wrote:
> Current __virt_to_phys() only print warning messages for non-linear
> addresses. It's hard to catch all warnings by those messages.
Why? Are you seeing a large number of warnings somewhere?
> So add a VIRTUAL_BUG_ON() to trap all non-l
On Mon, Jan 07, 2019 at 05:55:31PM +, Mark Brown wrote:
> On Mon, Jan 07, 2019 at 02:43:57PM +0000, Mark Rutland wrote:
>
> > Is it possible to use an allyesconfig rather than an allmodconfig? That
> > would leave all relevant options built-in.
>
> The allyesc
On Tue, Jan 08, 2019 at 11:24:43AM +0800, Miles Chen wrote:
> On Mon, 2019-01-07 at 15:00 +0000, Mark Rutland wrote:
> > On Mon, Jan 07, 2019 at 07:21:20PM +0800, Miles Chen wrote:
> > > Current __virt_to_phys() only print warning messages for non-linear
> > > addres
Hi Torsten,
On Fri, Jan 04, 2019 at 03:10:53PM +0100, Torsten Duwe wrote:
> Use -fpatchable-function-entry (gcc8) to add 2 NOPs at the beginning
> of each function. Replace the first NOP thus generated with a quick LR
> saver (move it to scratch reg x9), so the 2nd replacement insn, the call
> to
On Tue, Oct 09, 2018 at 06:11:03PM +0800, Chunhui Li wrote:
> From: "chunhui.li"
>
>kasan detect unwind_frame out-of-bounds error when one task
> dump another, log as below
> BUG: KASAN: out-of-bounds in unwind_frame+0x140/0x20c Read of
> size 8 at addr ffea1e2378e0 by task AnrMonitorThre
On Wed, Oct 10, 2018 at 06:45:17AM +, Chunhui Li (李春辉) wrote:
> Hi Mark,
>
> kasan detect out-of-bounds in stacktrace.c line 70, it's already over
> READ_ONCE_NOCHECK, but still crash
> kernel-4.9/arch/arm64/kernel/stacktrace.c
> 69frame->sp = fp + 0x10;
> 70frame->fp = READ_ONCE_NOCHECK(*(un
On Mon, Oct 29, 2018 at 11:59:59AM +0530, Ashish Mhetre wrote:
> From: Alex Van Brunt
>
> Accessed bit is used to age a page and in generic implementation there is
> flush_tlb while clearing the accessed bit.
> Flushing a TLB is overhead on ARM64 as access flag faults don't get
> translation tabl
Hi Josh,
I also have a few concerns here, as it is not clear to me precisely what is
required from arch code. Is there any documentation I should look at?
On Fri, Oct 26, 2018 at 10:37:04AM -0500, Josh Poimboeuf wrote:
> On Fri, Oct 26, 2018 at 04:21:57PM +0200, Torsten Duwe wrote:
> > Enhance th
On Mon, Oct 29, 2018 at 02:20:51PM +, Wiebe, Wladislav (Nokia - DE/Ulm)
wrote:
> When running into situations like:
> "Unhandled fault: synchronous external abort (0x210) at 0xXXX"
> or
> "Unhandled prefetch abort: synchronous external abort (0x210) at 0xXXX"
> it is useful to know the content
Hi Torsten,
On Fri, Oct 26, 2018 at 04:21:48PM +0200, Torsten Duwe wrote:
> Use -fpatchable-function-entry (gcc8) to add 2 NOPs at the beginning
> of each function. Replace the first NOP thus generated with a quick LR
> saver (move it to scratch reg x9), so the 2nd replacement insn, the call
> to
On Wed, Oct 31, 2018 at 02:19:07PM +0100, Jiri Kosina wrote:
> On Wed, 31 Oct 2018, Mark Rutland wrote:
>
> > I guess skipping the original function prologue would simplify the
> > implementation of the replacement function (and would mean that the regs
> > held the fu
On Mon, Oct 15, 2018 at 06:28:32PM +0200, Jerome Brunet wrote:
> Since commit 50d7ba36b916 ("arm64: export memblock_reserve()d regions via
> /proc/iomem")
> was merged Amlogic's boards using mainline u-boot started showing the
> following warning:
>
> WARNING: CPU: 0 PID: 1 at arch/arm64/kernel/se
On Tue, Oct 16, 2018 at 10:23:50AM +0200, Neil Armstrong wrote:
> Hi Mark,
>
> On 15/10/2018 18:42, Mark Rutland wrote:
> > On Mon, Oct 15, 2018 at 06:28:32PM +0200, Jerome Brunet wrote:
> >> Since commit 50d7ba36b916 ("arm64: export memblock_reserve()d regions via
On Wed, Oct 10, 2018 at 12:45:59PM +0200, Peter Zijlstra wrote:
> Hi all,
>
> There have been various issues and limitations with the way perf uses
> (task) contexts to track events. Most notable is the single hardware PMU
> task context, which has resulted in a number of yucky things (both
> prop
Hi,
[adding devicetree]
On Wed, Oct 17, 2018 at 06:08:23PM +0800, Peng Hao wrote:
> Add a platform device driver, pvpanic-mmio that is similar
> to x86's pvpanic device.
It would be worth noting in the commit message that this is a
QEMU-specific device.
Is this already in upstream QEMU?
> Sign
On Tue, Nov 06, 2018 at 03:19:35PM +0800, Zhaoyang Huang wrote:
> From: Zhaoyang Huang
>
> In some cases, the instruction of "bl foo1" will be the last one of the
> foo2[1], which will cause the lr be the first instruction of the adjacent
> foo3[2]. Hence, the backtrace will show the weird result
On Tue, Nov 06, 2018 at 08:57:51AM +, Daniel Thompson wrote:
> On Tue, Nov 06, 2018 at 08:39:01AM +0000, Mark Rutland wrote:
> > On Tue, Nov 06, 2018 at 03:19:35PM +0800, Zhaoyang Huang wrote:
> > > From: Zhaoyang Huang
> > >
> > > In some cases, the instr
On Tue, Nov 06, 2018 at 12:03:17PM +0200, Nick Kossifidis wrote:
> Στις 2018-11-05 21:38, Palmer Dabbelt έγραψε:
> > On Fri, 02 Nov 2018 06:09:39 PDT (-0700), robh...@kernel.org wrote:
> > > On Thu, Nov 1, 2018 at 6:04 PM Atish Patra
> > > wrote:
> > > >
> > > > Define a RISC-V cpu topology. This
On Tue, Nov 06, 2018 at 11:32:50AM +, Dave P Martin wrote:
> On Tue, Nov 06, 2018 at 11:00:19AM +0000, Mark Rutland wrote:
> > On Tue, Nov 06, 2018 at 08:57:51AM +, Daniel Thompson wrote:
> > > On Tue, Nov 06, 2018 at 08:39:01AM +, Mark Rutland wrote:
> > > &
On Tue, Nov 06, 2018 at 05:26:01PM +0200, Nick Kossifidis wrote:
> Στις 2018-11-06 16:13, Sudeep Holla έγραψε:
> > On Fri, Nov 02, 2018 at 08:58:39PM +0200, Nick Kossifidis wrote:
> > > Στις 2018-11-02 01:04, Atish Patra έγραψε:
> > > > This patch series adds the cpu topology for RISC-V. It contain
On Wed, Nov 07, 2018 at 04:31:34AM +0200, Nick Kossifidis wrote:
> Mark and Sundeep thanks a lot for your feedback, I guess you convinced
> me that having a device tree binding for the scheduler is not a
> correct approach. It's not a device after all and I agree that the
> device tree shouldn't be
On Tue, Nov 06, 2018 at 06:30:24PM +0100, Andrey Konovalov wrote:
> This commit adds a few helper functions, that are meant to be used to
> work with tags embedded in the top byte of kernel pointers: to set, to
> get or to reset (set to 0xff) the top byte.
>
> Reviewed-by: Andrey Ryabinin
> Revie
ned for arm64 since commit:
a7314405d83c ("drop ARM_BIG_LITTLE_CPUFREQ support for ARM64")
... so it can be removed from defconfig.
With that:
Acked-by: Mark Rutland
Mark.
> ---
> arch/arm64/configs/defconfig | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git
NTRACK_IPV6 haven't existed since
commit:
a0ae2562c6c4 ("netfilter: conntrack: remove l3proto abstraction")
... so we can remove them from the arm64 defconfig.
With that:
Acked-by: Mark Rutland
For the rest of this series, please update the commit messages to describe wh
On Thu, Nov 08, 2018 at 03:45:36PM +0200, Nick Kossifidis wrote:
> Στις 2018-11-07 14:06, Mark Rutland έγραψε:
> > On Wed, Nov 07, 2018 at 04:31:34AM +0200, Nick Kossifidis wrote:
> > > Mark and Sundeep thanks a lot for your feedback, I guess you convinced
> > > m
On Fri, Oct 12, 2018 at 09:56:05AM +0100, Will Deacon wrote:
> On Fri, Oct 12, 2018 at 09:53:54AM +0100, Mark Rutland wrote:
> > On Thu, Oct 11, 2018 at 05:28:14PM +0100, Will Deacon wrote:
> > > On Fri, Oct 05, 2018 at 09:47:38AM +0100, Kristina Martsenko wrote:
>
On Mon, Oct 15, 2018 at 02:31:09PM +0200, Marek Szyprowski wrote:
> To get ARM Architected Timers working on Samsung Exynos SoCs, one has to
> first configure and enable Exynos Multi-Core Timer, because they both
> share some common hardware blocks.
Could you please elaborate on what exactly is sh
On Fri, Oct 05, 2018 at 10:15:57AM +0530, Manjeet Pawar wrote:
> From: Rohit Thapliyal
>
> During user undefined instruction exception, the arm exception
> handler currently results in application crash through SIGILL.
> The bad instruction can be due to ddr/hardware issue.
If the DDR controlle
On Tue, Sep 04, 2018 at 11:48:24AM +0100, Mark Rutland wrote:
> Hi Ingo,
>
> As previously requested, this is a (trivial) rebase of the remaining generated
> atomic patches atop of v4.19-rc2, avoiding any potential conflict with Peter's
> ldsem atomic cleanup patch that got t
: Permission denied
warning: include/linux/atomic-fallback.h is out-of-date.
Fix this by restoring execute permissions to all the atomics scripts.
Fixes: ace9bad4df2684f3 ("locking/atomics: Add common header generation files")
Signed-off-by: Mark Rutland
Cc: Peter Zijlstra
Cc: I
On Thu, Nov 01, 2018 at 06:16:22PM +0800, kbuild test robot wrote:
> tree: https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git
> locking/core
> head: 30bc7baa9de81efc0584b9290ce8040a1130f156
> commit: 85f8507192fbfb4ad2ac01de879cb50045f4247f [5/6] locking/atomics: Check
> generated he
Hi Mathieu, Richard,
On Fri, Nov 02, 2018 at 11:12:24AM -0400, Mathieu Desnoyers wrote:
> Hi Richard,
>
> I stumbled on these articles:
>
> -
> https://medium.com/@jadr2ddude/a-big-little-problem-a-tale-of-big-little-gone-wrong-e7778ce744bb
> - https://www.mono-project.com/news/2016/09/12/arm64
On Fri, Nov 02, 2018 at 10:09:52AM -0700, Paul Sorensen wrote:
> Instances of "less then" or "greater then" are corrected to "less than" or
> "greater than", respectively.
>
> Signed-off-by: Paul Sorensen
> ---
[...]
> diff --git a/mm/slab_common.c b/mm/slab_common.c
> index 7eb8dc136c1c..5e5aa
On Wed, Oct 24, 2018 at 01:25:35AM +0800, Peng Hao wrote:
> pvpanic device is a qemu-specific emulation device. Pvpanic
> devices are now available for ARM64. This patch supports the APCI
> way to get device information.
This woule be better described as:
pvpanic: add MMIO support
On some archi
On Wed, Oct 24, 2018 at 01:25:37AM +0800, Peng Hao wrote:
> Signed-off-by: Peng Hao
> ---
> .../devicetree/bindings/arm/pvpanic-mmio.txt | 26
> ++
> 1 file changed, 26 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/pvpanic-mmio.txt
>
> diff
On Thu, Oct 25, 2018 at 09:42:24PM +0530, Ashish Mhetre wrote:
> From: Alex Van Brunt
>
> Accessed bit is used to age a page and in generic implementation there is
> flush_tlb while clearing the accessed bit.
> Flushing a TLB is overhead on ARM64 as access flag faults don't get
> translation tabl
HI,
On Thu, Oct 18, 2018 at 04:43:13PM +0800, Nickhu wrote:
> +#define PFM_CTL_OVF(idx) PFM_CTL_mskOVF ## idx
> +#define PFM_CTL_EN(idx) PFM_CTL_mskEN ## idx
> +#define PFM_CTL_OFFSEL(idx) PFM_CTL_offSEL ## idx
> +#define PFM_CTL_IE(idx)
On Thu, Oct 18, 2018 at 04:43:14PM +0800, Nickhu wrote:
> There two bitfield bug for perfomance counter
> in bitfield.h:
>
> PFM_CTL_offSEL1 21 --> 16
> PFM_CTL_offSEL2 27 --> 22
>
> This commit fix it.
>
> Signed-off-by: Nickhu
This patch should probably be move be
On Thu, Oct 18, 2018 at 04:43:16PM +0800, Nickhu wrote:
> When there are multiple events map to the same counter, the counter
> counts inaccurately. This is because each counter only counts one event
> in the same time.
> So when there are multiple events map to same counter, they have to take
> tu
On Thu, Oct 18, 2018 at 04:43:17PM +0800, Nickhu wrote:
> The document for how to add NDS32 PMU
> in devicetree.
>
> Signed-off-by: Nickhu
> ---
> Documentation/devicetree/bindings/nds32/pmu.txt | 17 +
> 1 file changed, 17 insertions(+)
> create mode 100644 Documentation/device
On Thu, Oct 18, 2018 at 09:56:11AM +0800, peng.h...@zte.com.cn wrote:
> >Hi,
> >
> >[adding devicetree]
> >
> >On Wed, Oct 17, 2018 at 06:08:23PM +0800, Peng Hao wrote:
[...]
> >> +#define PVPANIC_MMIO_CRASHED(1 << 0)
> >
> >This looks like it's identical to PVPANIC_PANICKED in the existing A
On Mon, Oct 22, 2018 at 06:18:26PM +0800, Nick Hu wrote:
> On Thu, Oct 18, 2018 at 03:23:59PM +0100, Mark Rutland wrote:
> > On Thu, Oct 18, 2018 at 04:43:13PM +0800, Nickhu wrote:
> > > +static irqreturn_t nds32_pmu_handle_irq(int irq_num, void *dev)
> >
On Mon, Oct 22, 2018 at 06:23:08PM +0800, Nick Hu wrote:
> Hi Mark,
>
> On Thu, Oct 18, 2018 at 10:31:32PM +0800, Mark Rutland wrote:
> > On Thu, Oct 18, 2018 at 04:43:17PM +0800, Nickhu wrote:
> > > The document for how to add NDS32 PMU
> > > in devicetree.
&
: Mark Rutland
Acked-by: Peter Zijlstra (Intel)
Acked-by: Will Deacon
Cc: Andrea Parri
Cc: Boqun Feng
Cc: Ingo Molnar
---
arch/alpha/include/asm/atomic.h | 8
arch/powerpc/include/asm/atomic.h | 17 +
arch/riscv/include/asm/atomic.h | 17 +
include
While we instrument all of the (non-relaxed) atomic_*() functions and
cmpxchg(), we missed xchg().
Let's add instrumentation for xchg(), fixing up x86 to implement
arch_xchg().
Signed-off-by: Mark Rutland
Acked-by: Peter Zijlstra (Intel)
Acked-by: Will Deacon
Cc: Boqun Feng
Cc: Dmitry V
pxchg wrappers).
Signed-off-by: Mark Rutland
Acked-by: Peter Zijlstra (Intel)
Acked-by: Will Deacon
Cc: Catalin Marinas
Cc: Ingo Molnar
---
arch/arm64/include/asm/atomic.h | 237 +-
arch/arm64/include/asm/atomic_ll_sc.h | 28 ++--
arch/arm64/includ
c_long_* API, bringing it into line with the
atomic_* and atomic64_* APIs.
Signed-off-by: Mark Rutland
Acked-by: Peter Zijlstra (Intel)
Acked-by: Will Deacon
Cc: Arnd Bergmann
Cc: Boqun Feng
Cc: Ingo Molnar
---
include/asm-generic/atomic-long.h | 1173 ++---
of the instrumented
atomics.
Signed-off-by: Mark Rutland
Acked-by: Peter Zijlstra (Intel)
Acked-by: Will Deacon
Cc: Alexander Potapenko
Cc: Andrey Ryabinin
Cc: Arnd Bergmann
Cc: Boqun Feng
Cc: Dmitry Vyukov
Cc: Ingo Molnar
---
include/asm-generic/atomic-instrumented.h | 1688
Mark Rutland
Reviewed-by: Andy Shevchenko
Signed-off-by: Peter Zijlstra (Intel)
Signed-off-by: Mark Rutland
Cc: Ingo Molnar
---
drivers/tty/tty_ldsem.c | 82 ---
include/linux/tty_ldisc.h | 4 +--
2 files changed, 37 insertions(+), 49 deletions(-)
infrastructure is updated to cover
the new scripts.
There should be no functional change as a result of this patch.
Signed-off-by: Mark Rutland
Acked-by: Peter Zijlstra (Intel)
Cc: Boqun Feng
Cc: Ingo Molnar
Cc: Will Deacon
---
MAINTAINERS | 1 +
scr
cmpxchg_double*() again. We can revisit the issue if build failures
reappear.
Signed-off-by: Mark Rutland
Acked-by: Peter Zijlstra (Intel)
Acked-by: Will Deacon
Cc: Arnd Bergmann
Cc: Boqun Feng
Cc: Dmitry Vyukov
Cc: Ingo Molnar
---
include/asm-generic/atomic-instrumented.h | 21 --
write()
arch_cmpxchg()
Let's fix this up and call the arch_ equivalents, resulting in:
cmpxchg64()
kasan_check_write()
arch_cmpxchg64()
arch_cmpxchg()
Signed-off-by: Mark Rutland
Acked-by: Peter Zijlstra (Intel)
Acked-by: Will Deacon
Cc: Boqun Feng
Cc: Dmitry Vyu
nline functions rather
than macros.
* The prototypes for fallbacks are arragned consistently with the return
type on a separate line to try to keep to a sensible line length.
There should be no functional change as a result of this patch.
Signed-off-by: Mark Rutland
Acked-by: Peter Zijlstra (
There should be no functional change as a result of this patch.
Signed-off-by: Mark Rutland
Acked-by: Peter Zijlstra (Intel)
Acked-by: Will Deacon
Cc: Boqun Feng
Cc: Dmitry Vyukov
Cc: Ingo Molnar
---
include/asm-generic/atomic-instrumented.h | 100 +-
1 file ch
cm/linux/kernel/git/mark/linux.git
atomics/generated
Mark Rutland (11):
atomics/x86: reduce arch_cmpxchg64*() instrumentation
atomics: simplify cmpxchg() instrumentation
atomics/treewide: instrument xchg()
atomics: instrument cmpxchg_double*()
atomics/treewide: rework ordering barriers
generated headers are up-to-date.
Signed-off-by: Mark Rutland
Cc: Boqun Feng
Cc: Ingo Molnar
Cc: Peter Zijlstra (Intel)
Cc: Will Deacon
---
Kbuild | 18 --
scripts/atomic/check-atomics.sh | 19 +++
2 files changed, 35 insertions(+), 2
Hi Olof,
On Mon, Jul 16, 2018 at 07:34:05AM -0700, Olof Johansson wrote:
> On Mon, Jul 16, 2018 at 2:17 AM, Marc Zyngier wrote:
> > On 15/07/18 04:53, Olof Johansson wrote:
> >> There's some use in printing out what the implementer and part numbers
> >> decode to for cases where they're known.
>
On Mon, Dec 18, 2023 at 10:13:46PM +0900, Masami Hiramatsu (Google) wrote:
> From: Steven Rostedt (VMware)
>
> Allow for instances to have their own ftrace_ops part of the fgraph_ops
> that makes the funtion_graph tracer filter on the set_ftrace_filter file
> of the instance and not the top insta
u (Google)
Acked-by: Mark Rutland
Mark.
> ---
> Changes in v3:
> - Add instruction pointer
> Changes in v2:
> - newly added.
> ---
> include/linux/ftrace.h | 26 ++
> 1 file changed, 26 insertions(+)
>
> diff --git a/include
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