[PATCH] mfd: jz4740-adc: Init mask cache in generic IRQ chip

The mask cache must be initialised in the generic IRQ chip, otherwise enabling one channel will actually enable all channels when the empty mask cache is written. Signed-off-by: Matt Redfearn matt.redfe...@imgtec.com --- drivers/mfd/jz4740-adc.c | 3 ++- 1 file changed, 2 insertions(+), 1

[PATCH] MIPS: mm: Fix definition of R6 cache instruction

on. Fixes: a168b8f1cde6588ff7a67699fa11e01bc77a5ddd Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> Cc: <sta...@vger.kernel.org> # 4.x- --- arch/mips/mm/uasm-mips.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/mm/uasm-mips.c b/arch/mip

Re: [PATCH] MIPS: tools: Fix relocs tool compiler warnings

ereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing] rel_type(ELF_R_TYPE(rel->r_info)), ^~~~ Fix them by making Elf64_Mips_Rela a union Signed-off-by: Harvey Hunt <harvey.h...@imgtec.com> Cc: Matt Redfearn <matt.redfe...@imgtec.com> Cc: l

[PATCH v5] mmc: OCTEON: Add host driver for OCTEON MMC controller

vium.com> Signed-off-by: Aaron Williams <aaron.willi...@cavium.com> Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- v5: Incoroprate comments from review http://patchwork.linux-mips.org/patch/9558/ - Use standard property instead of <cavium,bus-max-width>. - Use stan

Re: [PATCH v5] mmc: OCTEON: Add host driver for OCTEON MMC controller

Hi David On 10/02/16 18:02, David Daney wrote: On 02/10/2016 09:36 AM, Matt Redfearn wrote: From: Aleksey Makarov<aleksey.maka...@caviumnetworks.com> The OCTEON MMC controller is currently found on cn61XX and cnf71XX devices. Device parameters are configured from device tree data. eMM

Re: [PATCH v5] mmc: OCTEON: Add host driver for OCTEON MMC controller

DT binding and the structure of the driver to more closely resemble the atmel-mci driver, which has the same concept of one controller, multiple slots. Thanks, Matt On 10/02/16 20:07, David Daney wrote: On 02/10/2016 11:01 AM, Ulf Hansson wrote: On 10 February 2016 at 18:36, Matt Redfe

Re: [PATCH v5] mmc: OCTEON: Add host driver for OCTEON MMC controller

Hi Florian. On 11/02/16 02:55, Florian Fainelli wrote: Le 10/02/2016 16:32, David Daney a écrit : On 02/10/2016 03:49 PM, Aaro Koskinen wrote: Hi, On Wed, Feb 10, 2016 at 10:02:23AM -0800, David Daney wrote: On 02/10/2016 09:36 AM, Matt Redfearn wrote: +pr_warn(FW_WARN "%s: L

Re: [PATCH v5] mmc: OCTEON: Add host driver for OCTEON MMC controller

Hi Rob, On 12/02/16 15:39, Rob Herring wrote: On Wed, Feb 10, 2016 at 05:36:15PM +, Matt Redfearn wrote: From: Aleksey Makarov <aleksey.maka...@caviumnetworks.com> The OCTEON MMC controller is currently found on cn61XX and cnf71XX devices. Device parameters are configured from

[PATCH] selftests/seccomp: add MIPS self-test support

the syscall return value when skipping, since both would need to set the same register. Therefore modify that test case to just detect the skipped test. Tested on MIPS32r2 with an O32 userland where 48/48 tests now pass. Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- tools/t

[PATCH v2 00/11] MIPS relocatable kernel & KASLR

EAD3 platforms Matt Redfearn (11): MIPS: tools: Add relocs tool MIPS: tools: Build relocs tool MIPS: Reserve space for relocation table MIPS: Generate relocation table when CONFIG_RELOCATABLE MIPS: Kernel: Add relocate.c MIPS: Call relocate_kernel if CONFIG_RELOCATABLE=y MIPS: bootmem: Wh

[PATCH v2 01/11] MIPS: tools: Add relocs tool

files as is done when building a 64 bit kernel. Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- Changes in v2: - Added support for MIPSr6 arch/mips/boot/tools/Makefile | 8 + arch/mips/boot/tools/relocs.c | 680 + arch/mips/boot

[PATCH v2 02/11] MIPS: tools: Build relocs tool

Build the relocs tool as part of the kbuild Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- Changes in v2: None arch/mips/Makefile | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/mips/Makefile b/arch/mips/Makefile index e78d60dbdffd..fa25d60bc717 100644 --- a/arc

[PATCH v2 03/11] MIPS: Reserve space for relocation table

is reserved within the elf by filling it with 0's, and an invalid entry is left at the start of the space such that kernel relocation will be aborted if the table is empty. Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- Changes in v2: None arch/mips/Kconfig

[PATCH v2 07/11] MIPS: bootmem: When relocatable, free memory below kernel

(4604K kernel code, 242K rwdata, 892K rodata, 1280K init, 183K bss, 8736K reserved, 0K cma-reserved) The 16Mb offset is removed from the reserved region and added back to the available region. Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- Changes in v2: None arch/mips/kernel/s

[PATCH v2 10/11] MIPS: Kernel: Implement KASLR using CONFIG_RELOCATABLE

-by: Matt Redfearn <matt.redfe...@imgtec.com> --- Changes in v2: - Accept the "nokaslr" command line option - Add a kernel panic notifier to print the relocation information - Accept entropy via the /chosen/kaslr-seed property in device tree - Tested on MIPS Malta, Boston and SEAD3

[PATCH v2 11/11] MIPS: KASLR: Print relocation Information on boot

When debugging a relocated kernel, the addresses of the relocated symbols and the offset applied is essential information. If the kernel is compiled with debugging information, then print this information during bootup using the same function as the panic notifer. Signed-off-by: Matt Redfearn

[PATCH v2 09/11] MIPS: Introduce plat_get_fdt a platform API to retrieve the FDT

a bunch of other stuff. This patch adds plat_get_ftd() for IMG platforms. Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- Changes in v2: None arch/mips/include/asm/bootinfo.h | 18 ++ arch/mips/mti-malta/malta-setup.c | 7 ++- arch/mips/mti-sead3/sead3-setup.

[PATCH v2 04/11] MIPS: Generate relocation table when CONFIG_RELOCATABLE

remove (mark as 0 length) the relocation sections added to vmlinux. When vmlinux is passed to the boot makefile for conversion into a boot image the now empty relocation sections will be removed and the populated relocation table will be included in the binary image. Signed-off-by: Matt Redfearn

[PATCH v2 06/11] MIPS: Call relocate_kernel if CONFIG_RELOCATABLE=y

If CONFIG_RELOCATABLE is enabled, call relocate_kernel. This function will return the entry point of the relocated kernel if copy/relocate is sucessful or the original entry point if not. The stack pointer must then be pointed into the new image. Signed-off-by: Matt Redfearn <matt.re

[PATCH v2 05/11] MIPS: Kernel: Add relocate.c

then the entry point of the new kernel is returned, otherwise fall back to starting the kernel in place. Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- Changes in v2: None arch/mips/kernel/Makefile | 2 + arch/mips/kernel/relocate.c

[PATCH v2 08/11] MIPS: Add CONFIG_RELOCATABLE Kconfig option

Add option to KConfig to enable the kernel to relocate itself at runtime. Relocation is supported R2 and later of the MIPS architecture, 32bit and 64bit. The platform is also required to provide support through plat_get_fdt() added in a later patch. Signed-off-by: Matt Redfearn <matt.re

Re: [PATCH v2 0/6] MIPS seccomp_bpf self test and fixups

On 30/03/16 06:06, Kees Cook wrote: On Tue, Mar 29, 2016 at 1:35 AM, Matt Redfearn <matt.redfe...@imgtec.com> wrote: These patches imporve seccomp support on MIPS. Firstly support is added for building the seccomp_bpf self test for MIPS. The initial results of these tests were: 32bit

Re: [PATCH v2 11/11] MIPS: KASLR: Print relocation Information on boot

this information during bootup using the same function as the panic notifer. Notifier. Fixed when merging. Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- Changes in v2: None arch/mips/kernel/setup.c | 9 + 1 file changed, 9 insertions(+) diff --git a/arc

[PATCH v2 6/6] secomp: Constify mode1 syscall whitelist

These values are constant and should be marked as such. Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- Changes in v2: None kernel/seccomp.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/kernel/seccomp.c b/kernel/seccomp.c index b0082c14764f..9243d6

[PATCH v2 1/6] selftests/seccomp: add MIPS self-test support

the syscall return value when skipping, since both would need to set the same register. Therefore modify that test case to just detect the skipped test. Tested on MIPS32r2 / MIPS64r2 with O32, N32 and N64 userlands. Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> Acked-by: Kee

[PATCH v2 2/6] MIPS: Support sending SIG_SYS to 32bit userspace from 64bit kernel

with O32 and N32 userlands. Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> Cc: Paul Burton <paul.bur...@imgtec.com> Cc: linux-m...@linux-mips.org --- Changes in v2: None arch/mips/kernel/signal32.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/arch/mips/kernel/signa

[PATCH v2 5/6] MIPS: seccomp: Support compat with both O32 and N32

-by: Paul Burton <paul.bur...@imgtec.com> Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- Changes in v2: None arch/mips/include/asm/seccomp.h | 47 +++-- 1 file changed, 26 insertions(+), 21 deletions(-) diff --git a/arch/mips/include/asm/secc

[PATCH v2 0/6] MIPS seccomp_bpf self test and fixups

on additional platforms - Replace __NR_syscall which isn't defined for N32 / N64 ABIs Matt Redfearn (6): selftests/seccomp: add MIPS self-test support MIPS: Support sending SIG_SYS to 32bit userspace from 64bit kernel MIPS: scall: Handle seccomp filters which redirect syscalls seccomp: Get compat

[PATCH v2 3/6] MIPS: scall: Handle seccomp filters which redirect syscalls

consistent between ABIs with scall64-64.S being the reference. With this patch in place, the seccomp_bpf self test now passes TRACE_syscall.syscall_redirected and TRACE_syscall.syscall_dropped on all MIPS ABIs. Fixes: d218af78492a ("MIPS: scall: Always run the seccomp syscall filters")

[PATCH v2 4/6] seccomp: Get compat syscalls from asm-generic header

Move retrieval of compat syscall numbers into inline function defined in asm-generic header so that arches may override it. Suggested-by: Paul Burton <paul.bur...@imgtec.com> Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- Changes in v2: None include/asm-generic/se

[PATCH 2/2] genirq: Add error code reporting to irq_{reserve,destroy}_ipi

Make these functions return appropriate error codes when something goes wrong. There are currently no users of this function that would break from the API change. Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- include/linux/irqdomain.h | 5 ++--- kernel/irq/ipi.c

[PATCH 1/2] genirq: Make irq_destroy_ipi take a cpumask of IPIs to destroy

can be re-used. The original behaviour is restored by passing the complete mask that the IPI was created with. There are currently no users of this function that would break from the API change. Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- include/linux/irqdomain.h | 2 +-

Re: [PATCH 2/2] genirq: Add error code reporting to irq_{reserve,destroy}_ipi

On Fri, Apr 22, 2016 at 05:35:46PM +0200, Thomas Gleixner wrote: > On Fri, 22 Apr 2016, Matt Redfearn wrote: > > > Make these functions return appropriate error codes when something goes > > wrong. > > And the reason for this change is? Hi Thomas, Mainly for irq_dest

[PATCH v2 2/2] genirq: Add error code reporting to irq_{reserve,destroy}_ipi

in 4.6 and the number of existing call sites are low, changing the API now has little impact on the code, while making it easier for these functions to grow over time. Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- Changes in v2: - More descriptive commit message include

[PATCH v2 1/2] genirq: Make irq_destroy_ipi take a cpumask of IPIs to destroy

can be re-used. The original behaviour is restored by passing the complete mask that the IPI was created with. There are currently no users of this function that would break from the API change. Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- Changes in v2: None include

Re: [PATCH 2/3] MIPS: smp-cps: Clear Status IPL field when using EIC

SF_IP7); } static void cps_smp_finish(void) Hi Paul Reviewed-by: Matt Redfearn <matt.redfe...@imgtec.com> Tested-by: Matt Redfearn <matt.redfe...@imgtec.com> Thanks, Matt

Re: [PATCH 3/3] irqchip: mips-gic: Setup EIC mode on each CPU if it's in use

n EIC mode */ gic_cpu_pin = 0; timer_cpu_pin = gic_cpu_pin; Hi Paul Reviewed-by: Matt Redfearn <matt.redfe...@imgtec.com> Tested-by: Matt Redfearn <matt.redfe...@imgtec.com> Thanks, Matt

Re: [PATCH 1/3] MIPS: Clear Status IPL field when using EIC

us(ST0_IM); + arch_init_irq(); } Hi Paul Reviewed-by: Matt Redfearn <matt.redfe...@imgtec.com> Tested-by: Matt Redfearn <matt.redfe...@imgtec.com>

[PATCH] genirq: Fix missing return value in irq_destroy_ipi()

i’: kernel/irq/ipi.c:128:3: warning: ‘return’ with no value, in function returning non-void [-Wreturn-type] return; ^ Fixes: 7cec18a3906b ("genirq: Add error code reporting to irq_{reserve,destroy}_ipi") Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- kernel/irq/ip

Re: [PATCH v2 2/2] MIPS: CPS: Copy EVA configuration when starting secondary VPs.

Hi Paul, On 18/05/16 23:34, Paul Burton wrote: On Wed, May 18, 2016 at 05:12:36PM +0100, Matt Redfearn wrote: When starting secondary VPEs which support EVA and the SegCtl registers, copy the memory segmentation configuration from the running VPE to ensure that all VPEs in the core have

[PATCH 2/2] MIPS: CPS: Copy EVA configuration when starting secondary VPs.

the CM. Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- arch/mips/kernel/cps-vec.S | 16 1 file changed, 16 insertions(+) diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S index ac81edd44563..07b3274c8ae1 100644 --- a/arch/mips/kernel/cps-vec.S

[PATCH 1/2] MIPS: Add definitions of SegCtl registers and use them

The SegCtl registers are standard for MIPSr3..MIPSr5. Add definitions of these registers and use them rather than constants Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- arch/mips/include/asm/mach-malta/kernel-entry-init.h | 6 +++--- arch/mips/include/asm/mips

[PATCH v2 2/2] MIPS: CPS: Copy EVA configuration when starting secondary VPs.

the CM. Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- Changes in v2: - Skip check for config3 existing - we know it must to be doing multithreading - Use a unique lable name in the function arch/mips/kernel/cps-vec.S | 15 +++ 1 file changed, 15 insertions(+) diff

[PATCH v2 1/2] MIPS: Add definitions of SegCtl registers and use them

The SegCtl registers are standard for MIPSr3..MIPSr5. Add definitions of these registers and use them rather than constants Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- Changes in v2: None arch/mips/include/asm/mach-malta/kernel-entry-init.h | 6 +++--- arch/mips/inclu

Re: [PATCH 2/2] MIPS: CPS: Copy EVA configuration when starting secondary VPs.

On 18/05/16 16:04, Paul Burton wrote: On Wed, May 18, 2016 at 03:45:22PM +0100, Matt Redfearn wrote: When starting secondary VPEs which support EVA and the SegCtl registers, copy the memory segmentation configuration from the running VPE to ensure that all VPEs in the core have a consitent

[PATCH] genirq: Dont allow affinity mask to be updated on IPIs

a new generic IPI reservation code to irq core") Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- kernel/irq/ipi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/kernel/irq/ipi.c b/kernel/irq/ipi.c index c37f34b00a11..14777af8e097 100644 --- a/kernel/irq/ipi.c +++ b/

[PATCH] MIPS: Pistachio: Enable KASLR

Allow KASLR to be selected on Pistachio based systems. Tested on a Creator Ci40. Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- arch/mips/Kconfig | 1 + arch/mips/pistachio/init.c | 8 ++-- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/arc

[PATCH v2] MIPS: Pistachio: Enable KASLR

Allow KASLR to be selected on Pistachio based systems. Tested on a Creator Ci40. Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> Reviewed-by: James Hogan <james.ho...@imgtec.com> --- Changes in v2: Add SYS_SUPPORTS_RELOCATABLE to Kconfig in alphabetical order arch/

[PATCH] MIPS: Move identification of VP(E) into proc.c from smp-mt.c

smp-mt.c. Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> Reviewed-by: Paul Burton <paul.bur...@imgtec.com> --- arch/mips/kernel/proc.c | 7 +++ arch/mips/kernel/smp-mt.c | 23 --- 2 files changed, 7 insertions(+), 23 deletions(-) diff --git a/arch

[PATCH] MIPS: OCTEON: cavium_octeon_defconfig: Enable OCTEON SATA

Commit a2127e400edd ("libata: support AHCI on OCTEON platform") added a driver for the OCTEON AHCI controller. Enable this driver in the OCTEON defconfig. Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- arch/mips/configs/cavium_octeon_defconfig | 2 ++ 1 file chang

[PATCH 3/3] MIPS: Move CPU Hotplug config option into submenu

The KConfig option HOTPLUG_CPU should appear in the "Kernel Type" submenu. Relocate it to where SMP support is configured. Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- arch/mips/Kconfig | 20 ++-- 1 file changed, 10 insertions(+), 10 deletion

[PATCH 2/3] MIPS: smp-cps: Add support for CPU hotplug of MIPSr6 processors

-off-by: Matt Redfearn <matt.redfe...@imgtec.com> Reviewed-by: Paul Burton <paul.bur...@imgtec.com> --- arch/mips/kernel/smp-cps.c | 32 +++- 1 file changed, 27 insertions(+), 5 deletions(-) diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp

[PATCH 1/3] MIPS: smp-cps: Allow booting of CPU other than VP0 within a core

other VPs within the core are stopped before bringing the core out of reset so that only the desired VP starts. Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> Reviewed-by: Paul Burton <paul.bur...@imgtec.com> --- arch/mips/kernel/smp-cps.c | 9 + 1 file changed, 5 inse

[PATCH 0/3] Support for MIPSr6 CPU hotplug.

to move the CPU hotplug config option into the Kernel type menu within menuconfig. Based atop 4.7-rc6 Matt Redfearn (3): MIPS: smp-cps: Allow booting of CPU other than VP0 within a core MIPS: smp-cps: Add support for CPU hotplug of MIPSr6 processors MIPS: Move CPU Hotplug config option

[PATCH] MIPS: sync-r4k: Fix KERN_CONT fallout

Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- arch/mips/kernel/sync-r4k.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/kernel/sync-r4k.c b/arch/mips/kernel/sync-r4k.c index 4472a7f98577..1df1160b6a47 100644 --- a/arch/mips/kernel/sync-r4k.c +++ b/

[PATCH] MIPS: Generic: Fix big endian CPUs on generic machine

Big endian CPUs require SWAP_IO_SPACE enabled to swap accesses to little endian peripherals. Without this patch, big endian kernels fail to communicate with little endian periperals, such as PCI devices, on QEMU and FPGA based platforms. Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.

[PATCH] MIPS: Fix distclean with Makefile.postlink

ux") Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- arch/mips/Makefile.postlink | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/Makefile.postlink b/arch/mips/Makefile.postlink index b0ddf0701a31..4b7f5a648c79 100644 --- a/arch/mips/Makefil

[PATCH] MIPS: IRQ Stack: Fix erroneous jal to plat_irq_dispatch

jalr to the vectored handler that has been set up. This is ok for many platforms which set the vectored handler to plat_irq_dispatch anyway, but will cause problems with platforms that use other handlers. Fixes: dda45f701c9d ("MIPS: Switch to the irq_stack in interrupts") Signed-off

Re: [PATCH v5 3/4] remoteproc/MIPS: Add a remoteproc driver for MIPS

Hi Bjorn, Please could you review this driver? Thanks, Matt On 11/01/17 15:34, Matt Redfearn wrote: This driver allows a MIPS processor offlined from Linux to be used as a remote processor. Firmware may be loaded via the sysfs interface and changed at runtime, allowing the processor

Re: [PATCH v1] irqchip: irq-mips-gic:- Handle return NULL error from ioremap_nocache

On 17/01/17 10:10, Arvind Yadav wrote: Hi Matt, Please Acknowledge this. Regards Arvind Yadav Hi Arvind, Acked-by: Matt Redfearn <matt.redfe...@imgtec.com> On Monday 09 January 2017 02:30 PM, Marc Zyngier wrote: On 09/01/17 08:08, Arvind Yadav wrote: Here, If ioremap_n

Re: [PATCH v2] irqchip: irq-mips-gic:- Avoiding Kernel panics due to Error.

On 17/01/17 08:38, Thomas Gleixner wrote: On Mon, 16 Jan 2017, Arvind Yadav wrote: Cc'ing the MIPS folks. Eliminating kernel panic due to NULL pointer dereferencing and other failure in __gic_init. Here, __gic_init can fail. This error check will avoid NULL pointer dereference and kernel

[PATCH 0/4] MIPS: Further microMIPS stack unwinding fixes

inux-next Matt Redfearn (4): MIPS: Handle non word sized instructions when examining frame MIPS: microMIPS: Fix decoding of addiusp instruction MIPS: Stacktrace: Fix __usermode() of uninitialised regs MIPS: microMIPS: Fix decoding of swsp16 instruction arch/mips/include/asm/stacktrace.h

[PATCH 4/4] MIPS: microMIPS: Fix decoding of swsp16 instruction

nding the stack") Suggested-by: Paul Burton <paul.bur...@imgtec.com> Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- arch/mips/include/uapi/asm/inst.h | 2 +- arch/mips/kernel/process.c| 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch

[PATCH 1/4] MIPS: Handle non word sized instructions when examining frame

the stack. Fix this by incrementing the instruction pointer based on the size of the previously decoded instruction. Fixes: b6c7a324df37 ("MIPS: Fix get_frame_info() handling of microMIPS function size") Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- arch

[PATCH 2/4] MIPS: microMIPS: Fix decoding of addiusp instruction

nterpreted by the existing code as having manipulated the stack pointer by +1096. Fix this by changing the order of decoding the immediate and applying the left shift. Fixes: 34c2f668d0f6 ("MIPS: microMIPS: Add unaligned access support.") Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com&

[PATCH 3/4] MIPS: Stacktrace: Fix __usermode() of uninitialised regs

es instead of correctly walking the kernel stack. Fix this by initialising the contents of the saved status register in prepare_frametrace(). Fixes: 81a76d7119f6 ("MIPS: Avoid using unwind_stack() with usermode") Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- arch/mip

Re: [PATCH 1/4] MIPS: Handle non word sized instructions when examining frame

Hi Maciej On 28/02/17 20:54, Maciej W. Rozycki wrote: On Tue, 28 Feb 2017, Matt Redfearn wrote: Since the instruction modifying the stack pointer is usually the first in the function, that one is ususally handled correctly. But the s/ususally/usually/ oops diff --git a/arch/mips

[PATCH v2 4/5] MIPS: Stacktrace: Fix __usermode() of uninitialised regs

es instead of correctly walking the kernel stack. Fix this by initialising the contents of the saved status register in prepare_frametrace(). Fixes: 81a76d7119f6 ("MIPS: Avoid using unwind_stack() with usermode") Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- Chang

[PATCH v2 2/5] MIPS: microMIPS: Fix decoding of addiusp instruction

nterpreted by the existing code as having manipulated the stack pointer by +1096. Fix this by changing the order of decoding the immediate and applying the left shift. Fixes: 34c2f668d0f6 ("MIPS: microMIPS: Add unaligned access support.") Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.c

[PATCH v2 3/5] MIPS: Refactor handling of stack pointer in get_frame_info

r is found. This reduces the amount of indentation required in get_frame_info, and more closely matches the operation of is_ra_save_ins. Suggested-by: Maciej W. Rozycki <ma...@imgtec.com> Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- Changes in v2: - Refactor is_sp_move_ins

[PATCH v2 1/5] MIPS: Handle non word sized instructions when examining frame

the stack. Fix this by incrementing the instruction pointer based on the size of the previously decoded instruction. Fixes: b6c7a324df37 ("MIPS: Fix get_frame_info() handling of microMIPS function size") Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- Changes in v2

[PATCH v2 0/5] MIPS: Further microMIPS stack unwinding fixes

inux-next Changes in v2: - Keep locals in reverse christmas tree order - Replace conditional with xor and subtract - Refactor is_sp_move_ins to interpret immediate inline. Matt Redfearn (5): MIPS: Handle non word sized instructions when examining frame MIPS: microMIPS: Fix decoding of add

Re: [PATCH 2/4] MIPS: microMIPS: Fix decoding of addiusp instruction

Hi Maciej, On 28/02/17 22:04, Maciej W. Rozycki wrote: On Tue, 28 Feb 2017, Matt Redfearn wrote: diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c index 5b1e932ae973..6ba5b775579c 100644 --- a/arch/mips/kernel/process.c +++ b/arch/mips/kernel/process.c @@ -386,8 +386,9

Re: [PATCH 1/6] irqchip: mips-gic: Add context saving for MIPS_REMOTEPROC

Hi Marc, Thanks for the review! On 02/09/16 11:54, Marc Zyngier wrote: Hi Matt, On 02/09/16 10:59, Matt Redfearn wrote: The MIPS remote processor driver allows non-Linux firmware to take control of and execute on one of the systems VPEs. If that VPE is brought back under Linux

[PATCH] MIPS: rb532: Fix undefined reference to setup_serial_port

. Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- arch/mips/rb532/serial.c | 5 + 1 file changed, 5 insertions(+) diff --git a/arch/mips/rb532/serial.c b/arch/mips/rb532/serial.c index 70482540b3db..f0ea2de38840 100644 --- a/arch/mips/rb532/serial.c +++ b/arch/mips

[PATCH] MIPS: paravirt: Fix undefined reference to smp_bootstrap

to fix the error. Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- arch/mips/include/asm/mach-paravirt/kernel-entry-init.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/mips/include/asm/mach-paravirt/kernel-entry-init.h b/arch/mips/include/asm/mach-paravirt/kernel

[PATCH 3/6] MIPS: smp.c: Introduce mechanism for freeing and allocating IPIs

-by: Matt Redfearn <matt.redfe...@imgtec.com> --- arch/mips/include/asm/smp.h | 14 +++ arch/mips/kernel/smp.c | 61 +++-- 2 files changed, 67 insertions(+), 8 deletions(-) diff --git a/arch/mips/include/asm/smp.h b/arch/mips/include/asm/smp.h

Re: [PATCH 1/6] irqchip: mips-gic: Add context saving for MIPS_REMOTEPROC

On 02/09/16 10:59, Matt Redfearn wrote: The MIPS remote processor driver allows non-Linux firmware to take control of and execute on one of the systems VPEs. If that VPE is brought back under Linux, it is necessary to ensure that all GIC interrupts are routed and masked as Linux expects them

Re: [PATCH 15/21] mips: octeon: smp: Convert to hotplug state machine

HI Sebastian, On 06/09/16 18:04, Sebastian Andrzej Siewior wrote: Install the callbacks via the state machine. Cc: Ralf Baechle Cc: linux-m...@linux-mips.org Signed-off-by: Sebastian Andrzej Siewior --- arch/mips/cavium-octeon/smp.c | 24

[PATCH v2 09/12] MIPS: pm-cps: Add MIPSr6 CPU support

yield to other VPs on the same core, so drop the MT ASE yield instruction. 3. To halt a MIPSr6 VP, the CPC VP_STOP register is used rather than the MT ASE TCHalt CP0 register. Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> Reviewed-by: Paul Burton <paul.bur...@imgtec.com>

[PATCH v2 11/12] MIPS: SMP: Wrap call to mips_cpc_lock_other in mips_cm_lock_other

All calls to mips_cpc_lock_other should be wrapped in mips_cm_lock_other. This only matters if the system has CM3 and is using cpu idle, since otherwise a) the CPC lock is sufficent for CM < 3 and b) any systems with CM > 3 have not been able to use cpu idle until now. Signed-off-by

[PATCH v2 05/12] MIPS: Barrier: Add definitions of SYNC stype values

-off-by: Matt Redfearn <matt.redfe...@imgtec.com> Reviewed-by: Paul Burton <paul.bur...@imgtec.com> --- Changes in v2: Add new patch to define standard MIPS barrier types arch/mips/include/asm/barrier.h | 96 + 1 file changed, 96 insertions(+)

[PATCH v2 10/12] MIPS: pm-cps: Support CM3 changes to Coherence Enable Register

coherence. Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> Reviewed-by: Paul Burton <paul.bur...@imgtec.com> --- Changes in v2: None arch/mips/include/asm/mips-cm.h | 1 + arch/mips/kernel/pm-cps.c | 31 ++- 2 files changed, 19 insertions(+),

[PATCH v2 08/12] MIPS: pm-cps: Remove selection of sync types

Instead of selecting an implementation or vendor specific sync type for the required sync operations, always use the architecturally mandated sync types which previous patches have put in place. The selection of special sync types is now redundant an can be removed. Signed-off-by: Matt Redfearn

[PATCH v2 01/12] MIPS: CPC: Convert bare 'unsigned' to 'unsigned int'

Checkpatch complains about use of bare unsigned type. Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> Reviewed-by: Paul Burton <paul.bur...@imgtec.com> --- Changes in v2: None arch/mips/kernel/mips-cpc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff

[PATCH v2 00/12] MIPS CPC fixup and CPU Idle for MIPSr6 CPUs

selecting CPU specific ones. Matt Redfearn (12): MIPS: CPC: Convert bare 'unsigned' to 'unsigned int' MIPS: CPC: Avoid lock when MIPS CM >= 3 is present MIPS: pm-cps: Change FSB workaround to CPU blacklist MIPS: pm-cps: Update comments on barrier instructions MIPS: Barrier: Add definiti

[PATCH v2 06/12] MIPS: pm-cps: Use MIPS standard lightweight ordering barrier

that loads / stores are gloablly completed, use the defined standard sync stype. Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> Reviewed-by: Paul Burton <paul.bur...@imgtec.com> --- Changes in v2: None arch/mips/kernel/pm-cps.c | 12 +--- 1 file changed, 5 insertions(+),

[PATCH v2 07/12] MIPS: pm-cps: Use MIPS standard completion barrier

completion sync stype. Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> Reviewed-by: Paul Burton <paul.bur...@imgtec.com> --- Changes in v2: None arch/mips/kernel/pm-cps.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/mips/kernel/pm-cps.c

[PATCH v2 04/12] MIPS: pm-cps: Update comments on barrier instructions

This code makes large use of barriers, which had quite vague descriptions. Update the comments to make the choice of barrier and reason for it more clear. Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> Reviewed-by: Paul Burton <paul.bur...@imgtec.com> --- Changes in v2: Upd

[PATCH v2 02/12] MIPS: CPC: Avoid lock when MIPS CM >= 3 is present

of a mips_cm_{lock,unlock}_other pair ensuring the correct CPC_OTHER region will be accessed. Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> Reviewed-by: Paul Burton <paul.bur...@imgtec.com> --- Changes in v2: None arch/mips/kernel/mips-cpc.c | 13 - 1 file changed, 12 inse

[PATCH v2 03/12] MIPS: pm-cps: Change FSB workaround to CPU blacklist

the workaround can then be added to the blacklist. Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> Reviewed-by: Paul Burton <paul.bur...@imgtec.com> --- Changes in v2: None arch/mips/kernel/pm-cps.c | 9 ++--- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/arch/mi

Re: [PATCH 15/21] mips: octeon: smp: Convert to hotplug state machine

Hi Sebastian On 07/09/16 15:27, Sebastian Andrzej Siewior wrote: On 2016-09-07 09:24:57 [+0100], Matt Redfearn wrote: HI Sebastian, Hi Matt, --- a/include/linux/cpuhotplug.h +++ b/include/linux/cpuhotplug.h @@ -44,6 +44,7 @@ enum cpuhp_state { CPUHP_SH_SH3X_PREPARE

[PATCH 5/6] remoteproc/MIPS: Add a remoteproc driver for MIPS

protocol. Signed-off-by: Lisa Parratt <lisa.parr...@imgtec.com> Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- Documentation/ABI/testing/sysfs-class-mips-rproc | 24 + drivers/remoteproc/Kconfig | 11 + drivers/remoteproc/Makefile

[PATCH 4/6] MIPS: CPS: Add VP(E) stealing

lisa.parr...@imgtec.com> Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- arch/mips/Kconfig | 7 ++ arch/mips/include/asm/smp-cps.h | 8 ++ arch/mips/include/asm/smp.h | 1 + arch/mips/kernel/smp-cps.c | 162 ++-- arch

[PATCH 0/6] MIPS: Remote processor driver

nux the kernel exception handlers won't be reinstated properly. [1] http://wiki.prplfoundation.org/w/images/d/df/MIPS_OS_Remote_Processor_Driver_Whitepaper_1.0.9.pdf [2] https://github.com/MIPS/mips-rproc-example Lisa Parratt (1): MIPS: CPS: Add VP(E) stealing Matt Redfearn (5): irqchip:

[PATCH 6/6] MIPS: Deprecate VPE Loader

The MIPS remote processor driver (CONFIG_MIPS_RPROC) provides a more standard mechanism for using one or more VPs as coprocessors running separate firmware. Here we deprecate this mechanism before it is removed. Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- arch/mips/Kconf

[PATCH 2/6] MIPS: tlb-r4k: If there are wired entries, don't use TLBINVF

of the Wired register. Therefore if the TLB has any wired entries, fall back to iterating over the entries rather than blasting them all using TLBINVF. Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- arch/mips/mm/tlb-r4k.c | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff

[PATCH 1/6] irqchip: mips-gic: Add context saving for MIPS_REMOTEPROC

is restored. These functions will also be useful for restoring GIC context after a suspend to RAM. Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> --- drivers/irqchip/irq-mips-gic.c | 185 +++-- 1 file changed, 178 insertions(+), 7 deletions(-)

[PATCH v2 12/12] cpuidle: cpuidle-cps: Enable use with MIPSr6 CPUs.

This patch enables the MIPS CPS driver for MIPSr6 CPUs. Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> Reviewed-by: Paul Burton <paul.bur...@imgtec.com> --- Changes in v2: None drivers/cpuidle/Kconfig.mips | 2 +- drivers/cpuidle/cpuidle-cps.c | 2 +- 2 files changed,

[PATCH 03/10] MIPS: pm-cps: Change FSB workaround to CPU blacklist

the workaround can then be added to the blacklist. Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com> Reviewed-by: Paul Burton <paul.bur...@imgtec.com> --- arch/mips/kernel/pm-cps.c | 9 ++--- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/arch/mips/kernel/pm-cps.c b/arch

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