CONFIG_MIPS_PERF_SHARED_TC_COUNTERS build
- re-use cpuc variable in mipsxx_pmu_alloc_counter,
mipsxx_pmu_free_counter rather than having sibling_ version.
Since BMIPS5000 does not implement per TC counters, we can remove the
check on cpu_has_mipsmt_pertccounters.
New patch to fix BMIPS5000 system mode perf.
Matt Redfearn (6
. A definition of this bit is
added in mipsregs.h for MIPS Technologies. No other implementations
support this feature.
Signed-off-by: Matt Redfearn
---
Changes in v2: None
arch/mips/include/asm/mipsregs.h | 5 +
arch/mips/kernel/perf_event_mipsxx.c | 29
this by replacing smp_processor_id() with
cpu_vpe_id(¤t_cpu_data), in the vpe_id() macro, and pass vpe_id()
to M_PERFCTL_VPEID() when setting up PERFCTL.VPEID. The FIXME's can also
be removed since they no longer apply.
Signed-off-by: Matt Redfearn
---
Changes in v2: None
arc
8 perf
stat -e instructions:u,branches:u ./test_prog
Performance counter stats for './test_prog':
30002 instructions:u
10000 branches:u
Signed-off-by: Matt Redfearn
---
Changes in v2:
Fix mipsxx_pmu_enable_event for !#ifdef CONFIG_MIPS_MT_SMP
ar
tions:u
branches:u
0.005179533 seconds time elapsed
Performance counter stats for './test_prog':
30002 instructions:u
1 branches:u
0.005179467 seconds time elapsed
Signed-off-by: Matt Redfearn
---
Changes in v2:
- Fix
just set the counter to count the relevant
VPE.
Signed-off-by: Matt Redfearn
---
Changes in v2:
Since BMIPS5000 does not implement per TC counters, we can remove the
check on cpu_has_mipsmt_pertccounters.
arch/mips/kernel/perf_event_mipsxx.c | 18 --
1 file changed, 4 inser
not work.
Fix this by removing this BMIPS5000 specific path and integrating it
with the generic one. Since BMIPS5000 uses specific extensions to the
perf control register, different fields must be set up to count the
relevant CPU.
Signed-off-by: Matt Redfearn
---
Changes in v2:
New patch to
bridge
arch/mips/boot/dts/img/boston.dtb: Warning (pci_bridge): /pci@1400:
missing bus-range for PCI bridge
Signed-off-by: Matt Redfearn
---
arch/mips/boot/dts/img/boston.dts | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/mips/boot/dts/img/boston.dts
b/arch/mips/boot/dts/img
Hi Neil,
On 20/03/18 08:22, NeilBrown wrote:
Further testing showed that the original version of this
patch wasn't 100% reliable. Very occasionally the read
of SYSC_REG_CHIP_NAME0 returns garbage. Repeating the
read seems to be reliable, but it hasn't happened enough
for me to be completely
uot;)
Signed-off-by: NeilBrown
Looks good to me
Reviewed-by: Matt Redfearn
---
arch/mips/ralink/mt7621.c | 42 ++
1 file changed, 22 insertions(+), 20 deletions(-)
diff --git a/arch/mips/ralink/mt7621.c b/arch/mips/ralink/mt7621.c
index 1b274742077d..
Hi Neil,
On 21/03/18 03:00, NeilBrown wrote:
On Tue, Mar 20 2018, Matt Redfearn wrote:
Hi Neil,
On 20/03/18 08:22, NeilBrown wrote:
Further testing showed that the original version of this
patch wasn't 100% reliable. Very occasionally the read
of SYSC_REG_CHIP_NAME0 returns ga
On 29/03/18 10:49, Matt Redfearn wrote:
Several messages from the MIPS GIC driver include the text "GIC", "GIC
timer", etc, but the format is not standard. Add a pr_fmt of
"mips-gic-timer: " and reword the messages now that they will be
prefixed with the dri
Hi James,
On 16/05/18 18:59, James Hogan wrote:
On Fri, Apr 20, 2018 at 11:23:06AM +0100, Matt Redfearn wrote:
diff --git a/arch/mips/kernel/perf_event_mipsxx.c
b/arch/mips/kernel/perf_event_mipsxx.c
index 7e2b7d38a774..fe50986e83c6 100644
--- a/arch/mips/kernel/perf_event_mipsxx.c
+++ b/arch
Hi James,
On 16/05/18 19:05, James Hogan wrote:
On Fri, Apr 20, 2018 at 11:23:07AM +0100, Matt Redfearn wrote:
Previously when performance counters are per-core, rather than
per-thread, the number available were divided by 2 on detection, and the
counters used by each thread in a core were
Hi James,
On 21/05/18 17:14, James Hogan wrote:
On Tue, Apr 17, 2018 at 04:40:03PM +0100, Matt Redfearn wrote:
diff --git a/arch/mips/lib/memset.S b/arch/mips/lib/memset.S
index 1cc306520a55..a06dabe99d4b 100644
--- a/arch/mips/lib/memset.S
+++ b/arch/mips/lib/memset.S
@@ -231,16 +231,25
Fixes: 8c56208aff77 ("MIPS: lib: memset: Add MIPS R6 support")
Cc: sta...@vger.kernel.org
Signed-off-by: Matt Redfearn
---
Changes in v3:
New patch to fix fault handling during MIPSr6 version of setting
unaligned bytes.
Changes in v2: None
arch/mips/lib/memset.S | 3 ++-
1 file chan
It is not immediately obvious what the expected inputs to these fault
handlers is and how they calculate the number of unset bytes. Having
stared deeply at this in order to fix some corner cases, add some
comments to assist those who follow.
Signed-off-by: Matt Redfearn
---
Changes in v3
On 03/04/18 09:53, James Hogan wrote:
On Thu, Mar 29, 2018 at 11:41:23AM +0100, Matt Redfearn wrote:
This commit removes several generic GCC library routines from
arch/mips/lib/ in favour of similar routines from lib/.
diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile
index
From: Palmer Dabbelt
As part of the MIPS conversion to use the generic GCC library routines,
Matt Redfearn discovered that I'd missed a notrace on __ucmpdi2(). This
patch rectifies the problem.
CC: Matt Redfearn
CC: Antony Pavlov
Signed-off-by: Palmer Dabbelt
Reviewed-by: Matt Red
When these are included into arch Kconfig files, maintaining
alphabetical ordering of the selects means these get split up. To allow
for keeping things tidier and alphabetical, rename the selects to
GENERIC_LIB_*
Signed-off-by: Matt Redfearn
Reviewed-by: Palmer Dabbelt
---
Changes in v5: None
tines from lib/.
Signed-off-by: Antony Pavlov
[Matt Redfearn] Use GENERIC_LIB_* named Kconfig entries
Signed-off-by: Matt Redfearn
Cc: Palmer Dabbelt
Cc: Matt Redfearn
Cc: James Hogan
Cc: Ralf Baechle
Cc: linux-m...@linux-mips.org
Cc: linux-kernel@vger.kernel.org
---
Changes in v5:
Actua
MIPS Creator CI40 (2C2T MIPS InterAptiv with per-TC
counters, though for the purposes of testing the per-TC availability was
hardcoded to allow testing both paths).
Series applies to v4.16-rc7
Matt Redfearn (5):
MIPS: perf: More robustly probe for the presence of per-tc counters
MIPS: perf:
flagging their presence. In the case of MIPS
and BMIPS5000 implementations, this bit is Config7.PTC. A definition of
this bit is added in mipsregs.h for both MIPS Technologies
implementations and BMIPS5000.
Signed-off-by: Matt Redfearn
---
The test of Config7.PTC was previously enabled when
this by replacing smp_processor_id() with
cpu_vpe_id(¤t_cpu_data), in the vpe_id() macro, and pass vpe_id()
to M_PERFCTL_VPEID() when setting up PERFCTL.VPEID. The FIXME's can also
be removed since they no longer apply.
Signed-off-by: Matt Redfearn
---
arch/mips/kernel/perf_event_
8 perf
stat -e instructions:u,branches:u ./test_prog
Performance counter stats for './test_prog':
30002 instructions:u
10000 branches:u
Signed-off-by: Matt Redfearn
---
arch/mips/kernel/perf_event_mipsxx.c | 69 +++
tions:u
branches:u
0.005179533 seconds time elapsed
Performance counter stats for './test_prog':
30002 instructions:u
1 branches:u
0.005179467 seconds time elapsed
Signed-off-by: Matt Redfearn
---
arch/mips/ker
The vpe_id() macro is now used only in mipsxx_pmu_enable_event when
CONFIG_CPU_BMIPS5000 is defined. Fold the one used definition of the
macro into it's usage and remove the now unused definitions.
Signed-off-by: Matt Redfearn
---
arch/mips/kernel/perf_event_mipsxx.c | 18
Hi Palmer,
On 29/03/18 22:59, Palmer Dabbelt wrote:
On Thu, 29 Mar 2018 03:41:21 PDT (-0700), matt.redfe...@mips.com wrote:
From: Palmer Dabbelt
As part of the MIPS conversion to use the generic GCC library routines,
Matt Redfearn discovered that I'd missed a notrace on __ucmpdi2().
s, and the extra-y rule to clean them.
Signed-off-by: Matt Redfearn
---
arch/mips/boot/compressed/.gitignore | 2 --
arch/mips/boot/compressed/Makefile | 8
2 files changed, 4 insertions(+), 6 deletions(-)
delete mode 100644 arch/mips/boot/compressed/.gitignore
diff --git a/arch
them.
Signed-off-by: Matt Redfearn
Thanks,
Matt
On 04/04/18 10:18, Matt Redfearn wrote:
Since commit "MIPS: use generic GCC library routines from lib/", MIPS
now uses the generic lib/ashldi3.c, but bswapsi.c still comes from
arch/mips/lib. The rules for including these into vmlinuz n
first iteration. Without
the second patch, j = 4..63 returns garbage.
Applies on v4.16-rc7
Tested on MIPS creator ci40 (MIPS32) and Cavium Octeon II (MIPS64).
Matt Redfearn (2):
MIPS: memset.S: EVA & fault support for small_memset
MIPS: memset.S: Fix return of __clear_user from Lpartial_fix
sets a2 to the number of
bytes that could not be cleared (as defined by __clear_user).
Reported-by: Chuanhua Lei
Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2")
Cc: sta...@vger.kernel.org
Signed-off-by: Matt Redfearn
---
arch/mips/lib/memset.S | 7 ++-
1 file changed, 6 insertions(+),
Several messages from the MIPS GIC driver include the text "GIC", "GIC
timer", etc, but the format is not standard. Add a pr_fmt of
"mips-gic-timer: " and reword the messages now that they will be
prefixed with the driver name.
Signed-off-by: Matt Redfearn
---
Chan
From: Palmer Dabbelt
As part of the MIPS conversion to use the generic GCC library routines,
Matt Redfearn discovered that I'd missed a notrace on __ucmpdi2(). This
patch rectifies the problem.
CC: Matt Redfearn
CC: Antony Pavlov
Signed-off-by: Palmer Dabbelt
Reviewed-by: Matt Red
tines from lib/.
Signed-off-by: Antony Pavlov
[Matt Redfearn] Use GENERIC_LIB_* named Kconfig entries
Signed-off-by: Matt Redfearn
Cc: Palmer Dabbelt
Cc: Matt Redfearn
Cc: James Hogan
Cc: Ralf Baechle
Cc: linux-m...@linux-mips.org
Cc: linux-kernel@vger.kernel.org
---
Changes in v4:
Rework
When these are included into arch Kconfig files, maintaining
alphabetical ordering of the selects means these get split up. To allow
for keeping things tidier and alphabetical, rename the selects to
GENERIC_LIB_*
Signed-off-by: Matt Redfearn
Reviewed-by: Palmer Dabbelt
---
Changes in v4
org
Signed-off-by: Matt Redfearn
---
arch/mips/lib/memset.S | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/arch/mips/lib/memset.S b/arch/mips/lib/memset.S
index 90bcdf1224ee..3257dca58cad 100644
--- a/arch/mips/lib/memset.S
+++ b/arch/mips/lib/memset.S
@@ -161,
not work.
Fix this by removing this BMIPS5000 specific path and integrating it
with the generic one. Since BMIPS5000 uses specific extensions to the
perf control register, different fields must be set up to count the
relevant CPU.
Signed-off-by: Matt Redfearn
Tested-by: Florian Fainelli
---
Chan
The mask cache must be initialised in the generic IRQ chip,
otherwise enabling one channel will actually enable all
channels when the empty mask cache is written.
Signed-off-by: Matt Redfearn
---
drivers/mfd/jz4740-adc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a
i’:
kernel/irq/ipi.c:128:3: warning: ‘return’ with no value, in function returning
non-void [-Wreturn-type]
return;
^
Fixes: 7cec18a3906b ("genirq: Add error code reporting to
irq_{reserve,destroy}_ipi")
Signed-off-by: Matt Redfearn
---
kernel/irq/ipi.c | 2 +-
1 file changed, 1 inse
aul
Reviewed-by: Matt Redfearn
Tested-by: Matt Redfearn
cps_smp_finish(void)
Hi Paul
Reviewed-by: Matt Redfearn
Tested-by: Matt Redfearn
Thanks,
Matt
mode */
gic_cpu_pin = 0;
timer_cpu_pin = gic_cpu_pin;
Hi Paul
Reviewed-by: Matt Redfearn
Tested-by: Matt Redfearn
Thanks,
Matt
CM.
Signed-off-by: Matt Redfearn
---
arch/mips/kernel/cps-vec.S | 16
1 file changed, 16 insertions(+)
diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S
index ac81edd44563..07b3274c8ae1 100644
--- a/arch/mips/kernel/cps-vec.S
+++ b/arch/mips/kernel/cps-vec.S
The SegCtl registers are standard for MIPSr3..MIPSr5. Add definitions of
these registers and use them rather than constants
Signed-off-by: Matt Redfearn
---
arch/mips/include/asm/mach-malta/kernel-entry-init.h | 6 +++---
arch/mips/include/asm/mipsregs.h | 3 +++
2 files
On 18/05/16 16:04, Paul Burton wrote:
On Wed, May 18, 2016 at 03:45:22PM +0100, Matt Redfearn wrote:
When starting secondary VPEs which support EVA and the SegCtl registers,
copy the memory segmentation configuration from the running VPE to ensure
that all VPEs in the core have a consitent
CM.
Signed-off-by: Matt Redfearn
---
Changes in v2:
- Skip check for config3 existing - we know it must to be doing
multithreading
- Use a unique lable name in the function
arch/mips/kernel/cps-vec.S | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/mips/kernel/cps-vec.S
The SegCtl registers are standard for MIPSr3..MIPSr5. Add definitions of
these registers and use them rather than constants
Signed-off-by: Matt Redfearn
---
Changes in v2: None
arch/mips/include/asm/mach-malta/kernel-entry-init.h | 6 +++---
arch/mips/include/asm/mipsregs.h
Hi Paul,
On 18/05/16 23:34, Paul Burton wrote:
On Wed, May 18, 2016 at 05:12:36PM +0100, Matt Redfearn wrote:
When starting secondary VPEs which support EVA and the SegCtl registers,
copy the memory segmentation configuration from the running VPE to ensure
that all VPEs in the core have a
Allow KASLR to be selected on Pistachio based systems. Tested on a
Creator Ci40.
Signed-off-by: Matt Redfearn
---
arch/mips/Kconfig | 1 +
arch/mips/pistachio/init.c | 8 ++--
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
Allow KASLR to be selected on Pistachio based systems. Tested on a
Creator Ci40.
Signed-off-by: Matt Redfearn
Reviewed-by: James Hogan
---
Changes in v2:
Add SYS_SUPPORTS_RELOCATABLE to Kconfig in alphabetical order
arch/mips/Kconfig | 1 +
arch/mips/pistachio/init.c | 8
-by: Aleksey Makarov
Signed-off-by: Leonid Rosenboim
Signed-off-by: Peter Swain
Signed-off-by: Aaron Williams
Signed-off-by: Matt Redfearn
---
v5:
Incoroprate comments from review
http://patchwork.linux-mips.org/patch/9558/
- Use standard property instead of .
- Use standard property instead
Hi Rob,
On 12/02/16 15:39, Rob Herring wrote:
On Wed, Feb 10, 2016 at 05:36:15PM +, Matt Redfearn wrote:
From: Aleksey Makarov
The OCTEON MMC controller is currently found on cn61XX and cnf71XX
devices. Device parameters are configured from device tree data.
eMMC, MMC and SD devices
a new generic IPI reservation code to
irq core")
Signed-off-by: Matt Redfearn
---
kernel/irq/ipi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/kernel/irq/ipi.c b/kernel/irq/ipi.c
index c37f34b00a11..14777af8e097 100644
--- a/kernel/irq/ipi.c
+++ b/kernel/irq/ipi.c
@@ -94,6 +94,7 @@ un
Make these functions return appropriate error codes when something goes
wrong.
There are currently no users of this function that would break from the
API change.
Signed-off-by: Matt Redfearn
---
include/linux/irqdomain.h | 5 ++---
kernel/irq/ipi.c | 31
can be re-used.
The original behaviour is restored by passing the complete mask that the
IPI was created with.
There are currently no users of this function that would break from the
API change.
Signed-off-by: Matt Redfearn
---
include/linux/irqdomain.h | 2 +-
kernel/irq/ipi.c | 18
On Fri, Apr 22, 2016 at 05:35:46PM +0200, Thomas Gleixner wrote:
> On Fri, 22 Apr 2016, Matt Redfearn wrote:
>
> > Make these functions return appropriate error codes when something goes
> > wrong.
>
> And the reason for this change is?
Hi Thomas,
Mainly for irq_dest
the syscall return value when skipping,
since both would need to set the same register. Therefore modify that
test case to just detect the skipped test.
Tested on MIPS32r2 with an O32 userland where 48/48 tests now pass.
Signed-off-by: Matt Redfearn
---
tools/testing/selftests/seccomp
4.6 and the number of existing call sites are low, changing the API now
has little impact on the code, while making it easier for these
functions to grow over time.
Signed-off-by: Matt Redfearn
---
Changes in v2:
- More descriptive commit message
include/linux/irqdomain.h | 5 ++---
kernel
can be re-used.
The original behaviour is restored by passing the complete mask that the
IPI was created with.
There are currently no users of this function that would break from the
API change.
Signed-off-by: Matt Redfearn
---
Changes in v2: None
include/linux/irqdomain.h | 2 +-
kernel/irq
On 30/03/16 06:06, Kees Cook wrote:
On Tue, Mar 29, 2016 at 1:35 AM, Matt Redfearn wrote:
These patches imporve seccomp support on MIPS.
Firstly support is added for building the seccomp_bpf self test for
MIPS. The
initial results of these tests were:
32bit kernel O32 userspace before: 48
EAD3 platforms
Matt Redfearn (11):
MIPS: tools: Add relocs tool
MIPS: tools: Build relocs tool
MIPS: Reserve space for relocation table
MIPS: Generate relocation table when CONFIG_RELOCATABLE
MIPS: Kernel: Add relocate.c
MIPS: Call relocate_kernel if CONFIG_RELOCATABLE=y
MIPS: bootmem: Wh
bunch of other stuff.
This patch adds plat_get_ftd() for IMG platforms.
Signed-off-by: Matt Redfearn
---
Changes in v2: None
arch/mips/include/asm/bootinfo.h | 18 ++
arch/mips/mti-malta/malta-setup.c | 7 ++-
arch/mips/mti-sead3/sead3-setup.c | 5 +
3 files changed, 29
remove
(mark as 0 length) the relocation sections added to vmlinux.
When vmlinux is passed to the boot makefile for conversion into a boot
image the now empty relocation sections will be removed and the
populated relocation table will be included in the binary image.
Signed-off-by: Matt Redfearn
-by: Matt Redfearn
---
Changes in v2:
- Accept the "nokaslr" command line option
- Add a kernel panic notifier to print the relocation information
- Accept entropy via the /chosen/kaslr-seed property in device tree
- Tested on MIPS Malta, Boston and SEAD3 platforms
arch/mi
When debugging a relocated kernel, the addresses of the relocated
symbols and the offset applied is essential information. If the kernel
is compiled with debugging information, then print this information
during bootup using the same function as the panic notifer.
Signed-off-by: Matt Redfearn
Build the relocs tool as part of the kbuild
Signed-off-by: Matt Redfearn
---
Changes in v2: None
arch/mips/Makefile | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index e78d60dbdffd..fa25d60bc717 100644
--- a/arch/mips/Makefile
+++ b/arch/mips
reserved within the elf by filling it with
0's, and an invalid entry is left at the start of the space such that
kernel relocation will be aborted if the table is empty.
Signed-off-by: Matt Redfearn
---
Changes in v2: None
arch/mips/Kconfig | 16
arch/mips/k
files as is done when building a
64 bit kernel.
Signed-off-by: Matt Redfearn
---
Changes in v2:
- Added support for MIPSr6
arch/mips/boot/tools/Makefile | 8 +
arch/mips/boot/tools/relocs.c | 680 +
arch/mips/boot/tools/relocs.h | 45 +++
arch
If CONFIG_RELOCATABLE is enabled, call relocate_kernel.
This function will return the entry point of the relocated kernel if
copy/relocate is sucessful or the original entry point if not. The stack
pointer must then be pointed into the new image.
Signed-off-by: Matt Redfearn
---
Changes in v2
then the entry point of the new kernel
is returned, otherwise fall back to starting the kernel in place.
Signed-off-by: Matt Redfearn
---
Changes in v2: None
arch/mips/kernel/Makefile | 2 +
arch/mips/kernel/relocate.c | 240
2 files changed, 242
(4604K kernel code, 242K rwdata,
892K rodata, 1280K init, 183K bss, 8736K reserved, 0K cma-reserved)
The 16Mb offset is removed from the reserved region and added back to
the available region.
Signed-off-by: Matt Redfearn
---
Changes in v2: None
arch/mips/kernel/setup.c | 14 ++
1 file
Add option to KConfig to enable the kernel to relocate itself at
runtime.
Relocation is supported R2 and later of the MIPS architecture, 32bit
and 64bit. The platform is also required to provide support through
plat_get_fdt() added in a later patch.
Signed-off-by: Matt Redfearn
---
Changes in
this information
during bootup using the same function as the panic notifer.
Notifier.
Fixed when merging.
Signed-off-by: Matt Redfearn
---
Changes in v2: None
arch/mips/kernel/setup.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/mips/kernel/setup.c b/arch/mips
DSI host registers it's bridge such that it is
> available for the upstream device to connect to.
>
> Signed-off-by: Matt Redfearn
>
> ---
>
> drivers/gpu/drm/bridge/adv7511/adv7511_drv.c | 9 +
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
>
know.
--
From: Matt Redfearn
commit c96eebf07692e53bf4dd5987510d8b550e793598 upstream.
The label .Llast_fixup\@ is jumped to on page fault within the final
byte set loop of memset (on < MIPSR6 architectures). For some reason, in
this fault handler, the v1 register is randomly set to a2 & ST
As long as the bootloader has
configured the uart divisor, earlycon should work as long as my patch
"serial: 8250_early: Only set divisor if valid clk & baud" is applied to
avoid a bad divisor getting calculated.
Tested-by: Matt Redfearn
Thanks,
Matt
---
drivers/tty/serial/e
Hi Michal
On 23/04/18 10:18, Michal Simek wrote:
device->baud is always non zero value because it is checked already in
early_serial8250_setup() before init_port is called.
True, currently init_port is only called from the one location and so
the test is a little redundant, though I don't see
On 20/04/18 23:51, Florian Fainelli wrote:
On 04/20/2018 03:23 AM, Matt Redfearn wrote:
This series addresses a few issues with how the MIPS performance
counters code supports the hardware multithreading MT ASE.
Firstly, implementations of the MT ASE may implement performance
counters
per
3: warning: format '%lu' expects argument of
type 'long unsigned int', but argument 4 has type 'size_t' [-Wformat=]
Change the format specifier to %zu for the size_t argument.
Fixes: 4863cc758216 ("cifs: smbd: Avoid allocating iov on the stack")
Signe
97.292878] [<805b24dc>] do_execve+0x38/0x44
[ 97.297669] [<80415a58>] syscall_common+0x34/0x58
[ 97.302924] Code: afb0003c 8e22d4e0 afa20034 <8c820008> 14400170
24030020 8f82000c 26460010 00a09825
Since it appears that MIPS oprofile support is currently broken, core
opro
On 24/04/18 14:05, James Hogan wrote:
On Tue, Apr 24, 2018 at 01:55:54PM +0100, Matt Redfearn wrote:
Since it appears that MIPS oprofile support is currently broken, core
oprofile is not getting many updates and not as many architectures
implement support for it compared to perf, remove the
Hi Robert,
On 04/05/18 10:30, Robert Richter wrote:
On 24.04.18 14:15:58, Matt Redfearn wrote:
On 24/04/18 14:05, James Hogan wrote:
On Tue, Apr 24, 2018 at 01:55:54PM +0100, Matt Redfearn wrote:
Since it appears that MIPS oprofile support is currently broken, core
oprofile is not getting
Hi Robert,
On 04/05/18 11:26, Robert Richter wrote:
On 04.05.18 10:54:32, Matt Redfearn wrote:
perf is available for MIPS and supports many more CPU types than oprofile.
oprofile userspace seemingly has been broken since 1.0.0 - removing oprofile
support from the MIPS kernel would not break it
Hi Robert,
On 04/05/18 13:27, Robert Richter wrote:
On 04.05.18 12:03:12, Matt Redfearn wrote:
As said, oprofile version 0.9.x is still available for cpus that do
not support perf. What is the breakage?
The breakage I originally set out to fix was the MT support in perf.
https://www.linux
BMIPS5000 does not implement per TC counters, we can remove the
check on cpu_has_mipsmt_pertccounters.
New patch to fix BMIPS5000 system mode perf.
Matt Redfearn (7):
MIPS: Probe for MIPS MT perf counters per TC
MIPS: perf: More robustly probe for the presence of per-tc counters
MIPS: perf
CPUs known to implement this
bit and the MT ASE, specifically, the 34K, 1004K and interAptiv.
Once the presence of the per-tc counter is indicated in cpu_data, tests
for it can be updated to use this flag.
Suggested-by: James Hogan
Signed-off-by: Matt Redfearn
---
Changes in v3:
New patch to
this by replacing smp_processor_id() with
cpu_vpe_id(¤t_cpu_data), in the vpe_id() macro, and pass vpe_id()
to M_PERFCTL_VPEID() when setting up PERFCTL.VPEID. The FIXME's can also
be removed since they no longer apply.
Signed-off-by: Matt Redfearn
---
Changes in v3: None
Changes in v2: Non
8 perf
stat -e instructions:u,branches:u ./test_prog
Performance counter stats for './test_prog':
30002 instructions:u
10000 branches:u
Signed-off-by: Matt Redfearn
---
Changes in v3: None
Changes in v2:
Fix mipsxx_pmu_enable_event for !#ifde
just set the counter to count the relevant
VPE.
Signed-off-by: Matt Redfearn
---
Changes in v3: None
Changes in v2:
Since BMIPS5000 does not implement per TC counters, we can remove the
check on cpu_has_mipsmt_pertccounters.
arch/mips/kernel/perf_event_mipsxx.c | 18 --
1
tions:u
branches:u
0.005179533 seconds time elapsed
Performance counter stats for './test_prog':
30002 instructions:u
1 branches:u
0.005179467 seconds time elapsed
Signed-off-by: Matt Redfearn
---
Chang
not work.
Fix this by removing this BMIPS5000 specific path and integrating it
with the generic one. Since BMIPS5000 uses specific extensions to the
perf control register, different fields must be set up to count the
relevant CPU.
Signed-off-by: Matt Redfearn
---
Changes in v3: None
Changes in
-by: Matt Redfearn
---
Changes in v3:
Use flag in cpu_data set by cpu_probe.c to indicate feature presence.
Changes in v2: None
arch/mips/include/asm/cpu-features.h | 7 +++
arch/mips/kernel/perf_event_mipsxx.c | 3 ---
arch/mips/oprofile/op_model_mipsxx.c | 2 --
3 files changed, 7
Hi James,
On 16/04/18 21:22, James Hogan wrote:
On Thu, Mar 29, 2018 at 10:28:23AM +0100, Matt Redfearn wrote:
@@ -260,6 +260,11 @@
jr ra
andiv1, a2, STORMASK
This patch looks good, well spotted!
But whats that v1 write about? Any ideas? Seems to go
Hi James,
On 16/04/18 23:13, James Hogan wrote:
On Thu, Mar 29, 2018 at 10:28:24AM +0100, Matt Redfearn wrote:
The __clear_user function is defined to return the number of bytes that
could not be cleared. From the underlying memset / bzero implementation
this means setting register a2 to that
Ci40 (MIPS32) and Cavium Octeon II (MIPS64).
Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2")
Cc: sta...@vger.kernel.org
Suggested-by: James Hogan
Signed-off-by: Matt Redfearn
---
Changes in v2:
- Use James Hogan's suggestion of replacing t1 with a0 to get the
correct remain
ld not be set is already contained in
a2, the andi placing a value in v1 is not necessary and actively
harmful in clobbering v1.
Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2")
Cc: sta...@vger.kernel.org
Reported-by: James Hogan
Signed-off-by: Matt Redfearn
---
arch/mips/lib/memset.S | 2 +-
ention for all instructions in a branch delay slot. This
effectively reverts the above commit, plus other locations introduced
with MIPSR6 support.
Signed-off-by: Matt Redfearn
---
arch/mips/lib/memset.S | 26 +-
1 file changed, 13 insertions(+), 13 deletions(-)
diff --
The micromips implementation of bzero additionally clobbers registers t7
& t8. Specify this in the clobbers list when invoking bzero.
Reported-by: James Hogan
Fixes: 26c5e07d1478 ("MIPS: microMIPS: Optimise 'memset' core library
function.")
Cc: sta...@vger.kernel
#x27;ve tested the above patch and it does work for MIPS
(preventing the PCICORE being built into the module).
Tested-by: Matt Redfearn
Thanks & sorry again for the breakage,
Matt
Thanks,
Larry
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