[PATCH v8 09/18] clk: tegra: Add the DFLL as a possible parent of the cclk_g clock

From: Tuomas Tynkkynen ttynkky...@nvidia.com The DFLL clocksource was missing from the list of possible parents for the fast CPU cluster. Add it to the list. Signed-off-by: Tuomas Tynkkynen ttynkky...@nvidia.com Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi --- drivers/clk/tegra/clk

[PATCH v8 17/18] ARM: tegra: Add CPU regulator to the Jetson TK1 device tree

Specify the CPU voltage regulator for the cpufreq driver. Signed-off-by: Tuomas Tynkkynen ttynkky...@nvidia.com Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi --- arch/arm/boot/dts/tegra124-jetson-tk1.dts | 6 ++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts

[PATCH v8 11/18] ARM: tegra: Add the DFLL to Tegra124 device tree

From: Tuomas Tynkkynen ttynkky...@nvidia.com The DFLL clocksource is a separate IP block from the usual clock-and-reset controller, so it gets its own device tree node. Signed-off-by: Tuomas Tynkkynen ttynkky...@nvidia.com Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi --- v8: - Changed

[PATCH v8 12/18] ARM: tegra: Enable the DFLL on the Jetson TK1

From: Tuomas Tynkkynen ttynkky...@nvidia.com Add the board-specific properties of the DFLL for the Jetson TK1 board. On this board, the DFLL will take control of the sd0 regulator on the on-board AS3722 PMIC. Signed-off-by: Tuomas Tynkkynen ttynkky...@nvidia.com Signed-off-by: Mikko Perttunen

[PATCH v8 04/18] clk: tegra: Add functions for parsing CVB tables

to be calculated on an per-chip basis. Add utility functions to parse the Tegra-specific tables and export the voltage-frequency pairs to the generic OPP framework for other drivers to use. Signed-off-by: Tuomas Tynkkynen ttynkky...@nvidia.com Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi

[PATCH v8 18/18] ARM: tegra: enable Tegra124 cpufreq driver by default

From: Tuomas Tynkkynen ttynkky...@nvidia.com The Tegra124 cpufreq driver depends on CONFIG_CPUFREQ_DT, so enable it to get the Tegra driver to build by default. Signed-off-by: Tuomas Tynkkynen ttynkky...@nvidia.com Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi --- arch/arm/configs

[PATCH v8 14/18] cpufreq: tegra: Rename tegra-cpufreq to tegra20-cpufreq

From: Tuomas Tynkkynen ttynkky...@nvidia.com The Tegra124 will use a different driver for frequency scaling, so rename the old driver (which handles only Tegra20) appropriately. Signed-off-by: Tuomas Tynkkynen ttynkky...@nvidia.com Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi

Re: [PATCH v8 15/18] cpufreq: Add cpufreq driver for Tegra124

On 03/02/2015 10:49 AM, Paul Bolle wrote: On Sun, 2015-03-01 at 14:44 +0200, Mikko Perttunen wrote: --- a/drivers/cpufreq/Kconfig.arm +++ b/drivers/cpufreq/Kconfig.arm @@ -256,6 +256,13 @@ config ARM_TEGRA20_CPUFREQ help This adds the CPUFreq driver support for Tegra20 SOCs

Re: [PATCH v3] ARM: tegra: Correct which USB controller has the UTMI pad registers

by git due to the patch context being insufficient. This broke USB after 6261b06 (regulator: Defer lookup of supply to regulator_get), because it changed the order in which the controllers were probed. The fix for this issue was suggested by Mikko Perttunen and Tuomas Tynkkynen. Signed-off

Re: [PATCH v8 10/18] clk: tegra: Initialize PLL_X before CCLK_G to ensure it has a parent

On 04/13/2015 10:31 PM, Michael Turquette wrote: Quoting Tomeu Vizoso (2015-04-13 05:17:01) On 11 April 2015 at 13:00, Mikko Perttunen mikko.perttu...@kapsi.fi wrote: On 04/11/2015 12:08 AM, Michael Turquette wrote: Quoting Mikko Perttunen (2015-03-01 04:44:33) This patch moves

Re: [PATCH v8 00/18] Tegra124 CL-DVFS / DFLL clocksource + cpufreq

. Avenues that I can see: 1) revert the above patch 2) restrict the cpu clock rate to those with 0 in the MSB 3) move to 64-bit clock rates. Cheers, Mikko. Thierry On Sun, Mar 01, 2015 at 02:44:23PM +0200, Mikko Perttunen wrote: Hi, this is v8 of the Tegra124 cpufreq series. Aside rebasing

Re: [PATCH 1/2] clk: change clk_ops' -round_rate() prototype

The series Tested-by: Mikko Perttunen mikko.perttu...@kapsi.fi on Jetson-TK1. I rebased my cpufreq series on top of this and everything's working well now. :) Thanks, Mikko. On 04/17/2015 10:29 AM, Boris Brezillon wrote: ... -- To unsubscribe from this list: send the line unsubscribe

[PATCH v9 13/17] cpufreq: tegra: Rename tegra-cpufreq to tegra20-cpufreq

From: Tuomas Tynkkynen ttynkky...@nvidia.com The Tegra124 will use a different driver for frequency scaling, so rename the old driver (which handles only Tegra20) appropriately. Signed-off-by: Tuomas Tynkkynen ttynkky...@nvidia.com Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi

[PATCH v9 08/17] clk: tegra: Save/restore CCLKG_BURST_POLICY on suspend

...@nvidia.com Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi Acked-by: Peter De Schrijver pdeschrij...@nvidia.com Acked-by: Michael Turquette mturque...@linaro.org --- drivers/clk/tegra/clk-tegra124.c | 14 ++ 1 file changed, 14 insertions(+) diff --git a/drivers/clk/tegra/clk

[PATCH v9 04/17] clk: tegra: Add functions for parsing CVB tables

to be calculated on an per-chip basis. Add utility functions to parse the Tegra-specific tables and export the voltage-frequency pairs to the generic OPP framework for other drivers to use. Signed-off-by: Tuomas Tynkkynen ttynkky...@nvidia.com Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi

[PATCH v9 11/17] ARM: tegra: Enable the DFLL on the Jetson TK1

From: Tuomas Tynkkynen ttynkky...@nvidia.com Add the board-specific properties of the DFLL for the Jetson TK1 board. On this board, the DFLL will take control of the sd0 regulator on the on-board AS3722 PMIC. Signed-off-by: Tuomas Tynkkynen ttynkky...@nvidia.com Signed-off-by: Mikko Perttunen

[PATCH v9 17/17] ARM: tegra: enable Tegra124 cpufreq driver by default

From: Tuomas Tynkkynen ttynkky...@nvidia.com The Tegra124 cpufreq driver depends on CONFIG_CPUFREQ_DT, so enable it to get the Tegra driver to build by default. Signed-off-by: Tuomas Tynkkynen ttynkky...@nvidia.com Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi --- arch/arm/configs

[PATCH v9 03/17] clk: tegra: Add closed loop support for the DFLL

-by: Tuomas Tynkkynen ttynkky...@nvidia.com Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi Acked-by: Peter De Schrijver pdeschrij...@nvidia.com Acked-by: Michael Turquette mturque...@linaro.org --- drivers/clk/tegra/clk-dfll.c | 666 ++- 1 file

[PATCH v9 01/17] clk: tegra: Add binding for the Tegra124 DFLL clocksource

in the device tree. Signed-off-by: Tuomas Tynkkynen ttynkky...@nvidia.com Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi Acked-by: Michael Turquette mturque...@linaro.org --- .../bindings/clock/nvidia,tegra124-dfll.txt| 79 ++ 1 file changed, 79 insertions(+) create mode

[PATCH v9 07/17] clk: tegra: Add Tegra124 DFLL clocksource platform driver

of the work. Signed-off-by: Tuomas Tynkkynen ttynkky...@nvidia.com Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi Acked-by: Michael Turquette mturque...@linaro.org --- drivers/clk/tegra/Makefile | 2 + drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 161

[PATCH v9 12/17] cpufreq: tegra124: Add device tree bindings

From: Tuomas Tynkkynen ttynkky...@nvidia.com The cpufreq driver for Tegra124 will be a different one than the old Tegra20 cpufreq driver (tegra-cpufreq), which does not use the device tree. Signed-off-by: Tuomas Tynkkynen ttynkky...@nvidia.com Signed-off-by: Mikko Perttunen mikko.perttu

[PATCH v9 16/17] ARM: tegra: Add CPU regulator to the Jetson TK1 device tree

Specify the CPU voltage regulator for the cpufreq driver. Signed-off-by: Tuomas Tynkkynen ttynkky...@nvidia.com Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi --- arch/arm/boot/dts/tegra124-jetson-tk1.dts | 6 ++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts

[PATCH v9 15/17] ARM: tegra: Add entries for cpufreq on Tegra124

From: Tuomas Tynkkynen ttynkky...@nvidia.com The Tegra124 cpufreq driver relies on certain clocks being present in the /cpus/cpu@0 node. Signed-off-by: Tuomas Tynkkynen ttynkky...@nvidia.com Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi --- arch/arm/boot/dts/tegra124.dtsi | 9

[PATCH v9 00/17] Tegra124 CL-DVFS / DFLL clocksource + cpufreq

just renames a driver), so hopefully we can get this merged. Mikko Perttunen (2): clk: tegra: Introduce ability for SoC-specific reset control callbacks ARM: tegra: Add CPU regulator to the Jetson TK1 device tree Paul Walmsley (1): clk: tegra: Add DFLL DVCO reset control for Tegra124 Tuomas

[PATCH v9 05/17] clk: tegra: Introduce ability for SoC-specific reset control callbacks

should not be used, as some functions interpret these as negative error codes. Each SoC with these special resets should specify the defined reset control numbers in a device tree header file. Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi Acked-by: Michael Turquette mturque...@linaro.org

Re: [PATCH v9 00/17] Tegra124 CL-DVFS / DFLL clocksource + cpufreq

On 05/15/2015 05:09 AM, Viresh Kumar wrote: On 15 May 2015 at 01:45, Rafael J. Wysocki r...@rjwysocki.net wrote: You need ACKs from Viresh for those two, then. He's officially responsible for ARM cpufreq drivers. I thought an Ack for 14th is enough :) For: 12/13/14. Acked-by: Viresh Kumar

Re: [PATCH v2 1/2] clk: change clk_ops' -round_rate() prototype

, and pass the requested rate as a pointer so that it can be adjusted depending on hardware capabilities. Signed-off-by: Boris Brezillon boris.brezil...@free-electrons.com Tested-by: Heiko Stuebner he...@sntech.de Tested-by: Mikko Perttunen mikko.perttu...@kapsi.fi Reviewed-by: Heiko Stuebner he

Re: [PATCH 11/15] thermal: thermal: Add support for hardware-tracked trip points

On 05/18/2015 09:44 PM, Brian Norris wrote: On Mon, May 18, 2015 at 02:09:44PM +0200, Sascha Hauer wrote: On Mon, May 18, 2015 at 12:06:50PM +0300, Mikko Perttunen wrote: One interesting thing I noticed was that at least the bang-bang governor only acts if the temperature is properly smaller

[PATCH v9 02/17] clk: tegra: Add library for the DFLL clock source (open-loop mode)

devices, which rely on this code. Signed-off-by: Paul Walmsley pwalms...@nvidia.com Signed-off-by: Tuomas Tynkkynen ttynkky...@nvidia.com Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi Acked-by: Peter De Schrijver pdeschrij...@nvidia.com Acked-by: Michael Turquette mturque...@linaro.org

[PATCH v9 10/17] ARM: tegra: Add the DFLL to Tegra124 device tree

From: Tuomas Tynkkynen ttynkky...@nvidia.com The DFLL clocksource is a separate IP block from the usual clock-and-reset controller, so it gets its own device tree node. Signed-off-by: Tuomas Tynkkynen ttynkky...@nvidia.com Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi Acked-by: Michael

[PATCH v9 09/17] clk: tegra: Add the DFLL as a possible parent of the cclk_g clock

From: Tuomas Tynkkynen ttynkky...@nvidia.com The DFLL clocksource was missing from the list of possible parents for the fast CPU cluster. Add it to the list. Signed-off-by: Tuomas Tynkkynen ttynkky...@nvidia.com Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi Acked-by: Michael Turquette

[PATCH v9 14/17] cpufreq: Add cpufreq driver for Tegra124

...@linaro.org Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi --- drivers/cpufreq/Kconfig.arm| 7 ++ drivers/cpufreq/Makefile | 1 + drivers/cpufreq/tegra124-cpufreq.c | 214 + 3 files changed, 222 insertions(+) create mode 100644

Re: [PATCH v9 00/17] Tegra124 CL-DVFS / DFLL clocksource + cpufreq

On 05/14/2015 01:47 AM, Rafael J. Wysocki wrote: ... If I'm supposed to apply this, I need ACKs from the appropriate people on all the patches where they are still missing. Thanks! I believe Thierry Reding will apply the series; your ACK as cpufreq maintainer for patch 13, and maybe also

[PATCH v9 06/17] clk: tegra: Add DFLL DVCO reset control for Tegra124

[mikko.perttunen: ported to special reset callback] Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi Acked-by: Michael Turquette mturque...@linaro.org --- drivers/clk/tegra/clk-tegra124.c | 68 include/dt-bindings/reset/tegra124-car.h | 11 ++ 2 files

[PATCH v10 05/17] clk: tegra: Introduce ability for SoC-specific reset control callbacks

. Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi Acked-by: Michael Turquette mturque...@linaro.org --- drivers/clk/tegra/clk.c | 39 +++ drivers/clk/tegra/clk.h | 3 +++ 2 files changed, 34 insertions(+), 8 deletions(-) diff --git a/drivers/clk/tegra

[PATCH v10 06/17] clk: tegra: Add DFLL DVCO reset control for Tegra124

[mikko.perttunen: ported to special reset callback] Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi Acked-by: Michael Turquette mturque...@linaro.org --- drivers/clk/tegra/clk-tegra124.c | 68 include/dt-bindings/reset/tegra124-car.h | 12 ++ 2 files

Re: [PATCH v10 05/17] clk: tegra: Introduce ability for SoC-specific reset control callbacks

to Thierry for the idea. Mikko On 05/19/15 14:39, Mikko Perttunen wrote: This patch allows SoC-specific CAR initialization routines to register their own reset_assert and reset_deassert callbacks with the common Tegra CAR code. If defined, the common code will call these callbacks when a reset

Re: [PATCH 11/15] thermal: thermal: Add support for hardware-tracked trip points

the trip points to be updated again. If .set_trips is not implemented, the framework behaves as before. This patch is based on an earlier version from Mikko Perttunen mikko.perttu...@kapsi.fi Signed-off-by: Sascha Hauer s.ha...@pengutronix.de --- drivers/thermal/thermal_core.c | 43

Re: [PATCH 12/15] thermal: of: implement .set_trips for device tree thermal zones

On 05/13/15 11:52, Sascha Hauer wrote: Signed-off-by: Sascha Hauer s.ha...@pengutronix.de --- drivers/thermal/of-thermal.c | 12 include/linux/thermal.h | 3 +++ 2 files changed, 15 insertions(+) diff --git a/drivers/thermal/of-thermal.c b/drivers/thermal/of-thermal.c

Re: [PATCH v8 10/18] clk: tegra: Initialize PLL_X before CCLK_G to ensure it has a parent

On 04/11/2015 12:08 AM, Michael Turquette wrote: Quoting Mikko Perttunen (2015-03-01 04:44:33) This patch moves the initialization of PLL_X to be slightly before that of CCLK_G. This ensures that at boot, CCLK_G will immediately have a parent and the common clock framework can determine its

Re: [PATCH v8 00/18] Tegra124 CL-DVFS / DFLL clocksource + cpufreq

On 04/14/2015 08:21 PM, Boris Brezillon wrote: Hi Mikko, On Tue, 14 Apr 2015 14:25:59 +0300 Mikko Perttunen mikko.perttu...@kapsi.fi wrote: On 04/11/2015 12:11 AM, Michael Turquette wrote: Quoting Thierry Reding (2015-03-11 03:07:43) Hi Mike, Have you had a chance to look at these changes

Re: [PATCH v8 00/18] Tegra124 CL-DVFS / DFLL clocksource + cpufreq

On 04/15/2015 12:06 AM, Michael Turquette wrote: Quoting Mikko Perttunen (2015-04-14 12:40:36) On 04/14/2015 08:21 PM, Boris Brezillon wrote: Hi Mikko, On Tue, 14 Apr 2015 14:25:59 +0300 Mikko Perttunen mikko.perttu...@kapsi.fi wrote: On 04/11/2015 12:11 AM, Michael Turquette wrote

Re: [PATCH v2] ARM: tegra: Correct which USB controller has the UTMI pad registers

Reviewed-by: Mikko Perttunen mikko.perttu...@kapsi.fi On 04/02/2015 06:00 PM, Tomeu Vizoso wrote: It should be the first controller, not the second. This broke USB after 6261b06 (regulator: Defer lookup of supply to regulator_get), because it changed the order in which the controllers were

Re: [PATCH v2] ARM: tegra: Correct which USB controller has the UTMI pad registers

On 04/02/2015 06:20 PM, Mikko Perttunen wrote: Reviewed-by: Mikko Perttunen mikko.perttu...@kapsi.fi Scratch that; as Tuomas noted on IRC, the reset numbers here are still wrong. phy1 should have 22 and phy2 58. On 04/02/2015 06:00 PM, Tomeu Vizoso wrote: It should be the first controller

Re: [PATCH] ARM: tegra: Correct which USB controller has the UTMI pad registers

), because it changed the order in which the controllers were probed. The fix for this issue was suggested by Mikko Perttunen. Signed-off-by: Tomeu Vizoso tomeu.viz...@collabora.com Cc: Mikko Perttunen mikko.perttu...@kapsi.fi --- arch/arm/boot/dts/tegra124.dtsi | 2 +- 1 file changed, 1 insertion

Re: [PATCH 05/15] thermal: Add comment explaining test for critical temperature

crit_temp) *temp = tz-emul_temperature; } Reviewed-by: Mikko Perttunen mperttu...@nvidia.com -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http

Re: [PATCH 06/15] thermal: inline only once used function

. But I don't know why that would matter. Reviewed-by: Mikko Perttunen mperttu...@nvidia.com -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please

Re: [PATCH 01/15] thermal: consistently use int for temperatures

On 05/13/15 11:52, Sascha Hauer wrote: The thermal code uses int, long and unsigned long for temperatures in different places. Using an unsigned type limits the thermal framework to positive temperatures without need. 'long' is 64bit on several architectures which is not needed. Consistently use

[PATCH v11 05/17] clk: tegra: Introduce ability for SoC-specific reset control callbacks

. Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi Acked-by: Michael Turquette mturque...@linaro.org --- drivers/clk/tegra/clk.c | 39 +++ drivers/clk/tegra/clk.h | 3 +++ 2 files changed, 34 insertions(+), 8 deletions(-) diff --git a/drivers/clk/tegra/clk.c

Re: [PATCH 11/15] thermal: thermal: Add support for hardware-tracked trip points

On 05/18/15 23:28, Brian Norris wrote: On Mon, May 18, 2015 at 10:13:46PM +0300, Mikko Perttunen wrote: On 05/18/2015 09:44 PM, Brian Norris wrote: On Mon, May 18, 2015 at 02:09:44PM +0200, Sascha Hauer wrote: On Mon, May 18, 2015 at 12:06:50PM +0300, Mikko Perttunen wrote: One interesting

Re: [PATCH v10 05/17] clk: tegra: Introduce ability for SoC-specific reset control callbacks

On 05/19/2015 05:59 PM, Thierry Reding wrote: On Tue, May 19, 2015 at 02:39:27PM +0300, Mikko Perttunen wrote: This patch allows SoC-specific CAR initialization routines to register their own reset_assert and reset_deassert callbacks with the common Tegra CAR code. If defined, the common code

Re: [PATCH 01/15] thermal: consistently use int for temperatures

On 05/20/15 11:34, Sascha Hauer wrote: On Wed, May 20, 2015 at 10:12:44AM +0300, Mikko Perttunen wrote: On 05/13/15 11:52, Sascha Hauer wrote: The thermal code uses int, long and unsigned long for temperatures in different places. Using an unsigned type limits the thermal framework to positive

Re: [PATCH 11/15] thermal: thermal: Add support for hardware-tracked trip points

On 05/19/15 16:58, Sascha Hauer wrote: On Mon, May 18, 2015 at 02:09:44PM +0200, Sascha Hauer wrote: Hi Mikko, On Mon, May 18, 2015 at 12:06:50PM +0300, Mikko Perttunen wrote: + for (i = 0; i tz-trips; i++) { + int trip_low; + + tz-ops-get_trip_temp(tz, i

Re: [PATCH 3/4] drm/tegra: Add VIC support

Hi, very good patch! Here are a few small comments. Aside those, you should also add a section to Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt in a separate patch. Thanks, Mikko. On 05/21/2015 04:20 PM, Arto Merilainen wrote: This patch adds support for Video Image

Re: [PATCH 3/4] drm/tegra: Add VIC support

On 05/21/2015 06:10 PM, Arto Merilainen wrote: ... + +vic-rst = devm_reset_control_get(dev, vic03); I might prefer just vic as the clock/reset name. The name is often used as a sort of role for the clock/reset for the device, not necessarily the raw name of the correct clock/reset. I

[PATCH] regulator: max8973: Set VSEL regmap ops if DVS GPIO is not set

of the *hardware_vsel* regulator APIs. Signed-off-by: Mikko Perttunen mperttu...@nvidia.com --- This was just compile-tested as I don't have a board with this regulator. drivers/regulator/max8973-regulator.c | 9 + 1 file changed, 9 insertions(+) diff --git a/drivers/regulator/max8973-regulator.c b

Re: [RFC PATCH] dt: Tegra XUSB padctl: per-lane PHYs and USB lane map

On 10/20/2015 06:56 PM, Stephen Warren wrote: ... In drivers/pci/host/pci-tegra.c tegra_pcie_get_resources() I see a call to devm_phy_optional_get(). The SATA driver doesn't seem to do anything with phys at the moment, although tegra124.dtsi does put phy-related properties into the SATA DT

[PATCH] clk: tegra: Unlock top rates for Tegra124 DFLL clock

The new determine_rate prototype allows for clock rates exceeding 2^31-1 Hz to be used. Switch the DFLL clock to use determine_rate instead of round_rate and unlock the top rates supported by the Tegra124. Signed-off-by: Mikko Perttunen <mikko.perttu...@kapsi.fi> --- drivers/clk/tegra/clk-

Re: [PATCH] HID: sony: disable descriptor fixup for FutureMax Dance Mat

On 07/25/16 14:05, Antonio Ospite wrote: On Mon, 25 Jul 2016 11:14:04 +0200 Benjamin Tissoires wrote: On Jul 21 2016 or thereabouts, Antonio Ospite wrote: [...] It would be interesting to understand why some (supposedly) compatible devices break, maybe they

Re: [PATCH] HID: sony: disable descriptor fixup for FutureMax Dance Mat

On 07/25/16 18:23, Mikko Perttunen wrote: On 07/25/16 14:05, Antonio Ospite wrote: You can also find out the length of the raw output report with trial and error, start with a line like this: $ sudo hexdump -v -e '49/1 "%02x " "\n"' /dev/hidraw0 and increase/decrease

Re: [PATCH v2] HID: sony: disable descriptor fixup for FutureMax Dance Mat

Reviewed-by: Benjamin Tissoires Acked-by: Antonio Ospite Thanks! Mikko

[PATCH v2] HID: sony: disable descriptor fixup for FutureMax Dance Mat

From: Mikko Perttunen <mperttu...@nvidia.com> The FutureMax Dance Mat claims to be a SixAxis controller but breaks if descriptor fixups are applied. Detect the device using its USB product string and disable fixups when it is detected. Signed-off-by: Mikko Perttunen <mperttu...@n

[PATCH] HID: sony: disable descriptor fixup for FutureMax Dance Mat

From: Mikko Perttunen <mperttu...@nvidia.com> The FutureMax Dance Mat claims to be a SixAxis controller but breaks if descriptor fixups are applied. Detect the device using its USB product string and disable fixups when it is detected. Signed-off-by: Mikko Perttunen <mperttu...@n

Re: [PATCH] HID: sony: disable descriptor fixup for FutureMax Dance Mat

On 07/18/16 17:28, Benjamin Tissoires wrote: On Jul 17 2016 or thereabouts, Mikko Perttunen wrote: From: Mikko Perttunen <mperttu...@nvidia.com> ... #include #include #include +#include + +#include "usbhid/usbhid.h" I spent a lot of effort 2 years ago to remove the usb

Re: [PATCH 4/7] clk: tegra: remove non-existing pll_m_out1 clock

Missing commit message Cheers, Mikko. On 02/22/2017 05:13 PM, Peter De Schrijver wrote: Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk-tegra210.c | 5 - 1 file changed, 5 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra210.c

Re: [PATCH 1/7] clk: tegra: fix pll_a1 iddq register, add pll_a1

Reviewed-by: Mikko Perttunen <mperttu...@nvidia.com> On 02/22/2017 05:13 PM, Peter De Schrijver wrote: pll_a1 was using CLK_RST_CONTROLLER_PLLA1_MISC_0 for IDDQ control rather than the correct register CLK_RST_CONTROLLER_PLLA1_MISC_1. Also add pll_a1 to the set of clocks defined for Te

Re: [PATCH 6/7] clk: tegra: correct tegra210_pll_fixed_mdiv_cfg rate calculation

Reviewed-by: Mikko Perttunen <mperttu...@nvidia.com> On 22.02.2017 17:14, Peter De Schrijver wrote: Return the actually achieved rate in cfg->output_rate rather than just the requested rate. This is important to make clk_round_rate return the correct result. Signed-off-by: Peter De

Re: [PATCH 7/7] clk: tegra: fix type for m field

Reviewed-by: Mikko Perttunen <mperttu...@nvidia.com> On 22.02.2017 17:14, Peter De Schrijver wrote: When used as part of fractional ndiv calculations, the current range is not enough because the denominator of the fraction is multiplied with m. Signed-off-by: Peter De Schrijver <

Re: [PATCH 2/7] clk: tegra: fix isp clock modelling

The TRM shows a CLK_SOURCE_ISPB register, but after some discussion, it seems like that is a documentation generation bug, so this should be correct. Reviewed-by: Mikko Perttunen <mperttu...@nvidia.com> On 22.02.2017 17:13, Peter De Schrijver wrote: The 2 isp clocks (ispa and ispb)

Re: [PATCH 4/7] clk: tegra: remove non-existing pll_m_out1 clock

Whoops, that is, after a commit message is added. On 23.02.2017 10:17, Mikko Perttunen wrote: Reviewed-by: Mikko Perttunen <mperttu...@nvidia.com> On 22.02.2017 17:13, Peter De Schrijver wrote: Signed-off-by: Peter De Schrijver <pdeschrij...@nvidia.com> --- drivers/clk/tegra/cl

Re: [PATCH 4/7] clk: tegra: remove non-existing pll_m_out1 clock

Reviewed-by: Mikko Perttunen <mperttu...@nvidia.com> On 22.02.2017 17:13, Peter De Schrijver wrote: Signed-off-by: Peter De Schrijver <pdeschrij...@nvidia.com> --- drivers/clk/tegra/clk-tegra210.c | 5 - 1 file changed, 5 deletions(-) diff --git a/drivers/clk/tegra/clk-

Re: [PATCH 3/7] clk: tegra: correct afi parent

Reviewed-by: Mikko Perttunen <mperttu...@nvidia.com> On 22.02.2017 17:13, Peter De Schrijver wrote: The parent for afi is actually mselect, not clk_m. Signed-off-by: Peter De Schrijver <pdeschrij...@nvidia.com> --- drivers/clk/tegra/clk-tegra-periph.c | 2 +- 1 file changed, 1 ins

Re: [PATCH 5/7] clk: tegra: don't warn for PLL defaults unnecessarily

Reviewed-by: Mikko Perttunen <mperttu...@nvidia.com> On 22.02.2017 17:14, Peter De Schrijver wrote: If the PLL is on, only warn if the defaults are not yet set. Otherwise be silent. Signed-off-by: Peter De Schrijver <pdeschrij...@nvidia.com> --- drivers/clk/tegra/clk-teg

Re: [PATCH 6/7] net: stmmac: dwc-qos: Split out ->probe() and ->remove()

dev_err(>dev, "failed to remove subdriver: %d\n", err); + + stmmac_remove_config_dt(pdev, priv->plat); + + return err; } static const struct of_device_id dwc_eth_dwmac_match[] = { - { .compatible = "snps,dwc-qos-ethernet-4.10", }, + { .compatible = "snps,dwc-qos-ethernet-4.10", .data = _qos_data }, { } }; MODULE_DEVICE_TABLE(of, dwc_eth_dwmac_match); Reviewed-by: Mikko Perttunen <mperttu...@nvidia.com>

Re: [PATCH 2/7] net: stmmac: Balance PTP reference clock enable/disable

On 23.02.2017 19:24, Thierry Reding wrote: From: Thierry Reding clk_prepare_enable() and clk_disable_unprepare() for this clock aren't properly balanced, which can trigger a WARN_ON() in the common clock framework. Signed-off-by: Thierry Reding ---

Re: [PATCH 5/7] net: stmmac: Program RX queue size and flow control

On 23.02.2017 19:24, Thierry Reding wrote: From: Thierry Reding Program the receive queue size based on the RX FIFO size and enable hardware flow control for large FIFOs. Signed-off-by: Thierry Reding --- drivers/net/ethernet/stmicro/stmmac/dwmac4.h

Re: [PATCH 7/7] net: stmmac: dwc-qos: Add Tegra186 support

On 23.02.2017 19:24, Thierry Reding wrote: From: Thierry Reding The NVIDIA Tegra186 SoC contains an instance of the Synopsys DWC ethernet QOS IP core. The binding that it uses is slightly different from existing ones because of the integration (clocks, resets, ...).

Re: [PATCH v2 0/7] Tegra210 clock bug fixes

Series, Reviewed-by: Mikko Perttunen <mperttu...@nvidia.com> Tested-by: Mikko Perttunen <mperttu...@nvidia.com> On 02/23/2017 12:44 PM, Peter De Schrijver wrote: A number of bug fixes for the Tegra210 clock implementation. Changelog: v2: add better description for 'remove

Re: [PATCH 2/5] clk: tegra: define Tegra210 DMIC sync clocks

ync_clk_init which takes "const char **". Similarly for mux_dmic[123] which end up in a struct tegra_periph_init_data which also has a "const char **" field; and finally aclk_parents has the same issue. Apart from that, the series: Reviewed-by: Mikko Perttunen &

Re: [PATCH 4/7] net: stmmac: Parse FIFO sizes from feature registers

fosz = priv->dma_cap.rx_fifo_size; + if (priv->plat->force_thresh_dma_mode) priv->hw->dma->dma_mode(priv->ioaddr, tc, tc, rxfifosz); else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) { Reviewed-by: Mikko Perttunen <mperttu...@nvidia.com>

Re: [PATCH 3/7] net: stmmac: Check for DMA mapping errors

On 23.02.2017 19:24, Thierry Reding wrote: From: Thierry Reding When DMA mapping an SKB fragment, the mapping must be checked for errors, otherwise the DMA debug code will complain upon unmap. Signed-off-by: Thierry Reding ---

Re: linux-next: build failure after merge of the tip tree

On 05.04.2017 06:36, Stephen Rothwell wrote: Hi all, After merging the tip tree, today's linux-next build (arm multi_v7_defconfig) failed like this: drivers/gpu/built-in.o:(__tracepoints+0x64): multiple definition of `__tracepoint_remove_device_from_group'

[PATCH] fixup! gpu: host1x: Add IOMMU support

Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- drivers/gpu/host1x/dev.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/host1x/dev.c b/drivers/gpu/host1x/dev.c index f8fda446a6a6..f05ebb14fa63 100644 --- a/drivers/gpu/host1x/dev.c +++ b/drivers/gpu/host1x

[PATCH 1/3] cpufreq: Add Tegra186 cpufreq driver

can be set individually; however, this is just a hint as all CPUs in a cluster will run at the maximum rate of non-idle CPUs in the cluster. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- drivers/cpufreq/Kconfig.arm| 7 + drivers/cpufreq/Makefile | 1 + d

[PATCH 2/3] dt-bindings: Add bindings for nvidia,tegra186-ccplex-cluster

The Tegra186 CCPLEX_CLUSTER area contains memory-mapped registers that initiate CPU frequency/voltage transitions. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- .../arm/tegra/nvidia,tegra186-ccplex-cluster.txt | 22 ++ 1 file changed, 22 insertions(+)

[PATCH 3/3] arm64: tegra: Add CCPLEX_CLUSTER area in Tegra186

The Tegra186 CCPLEX_CLUSTER area contains memory-mapped registers that initiate CPU frequency/voltage transitions. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 9 + 1 file changed, 9 insertions(+) diff --git a/arch/arm64/bo

Re: [PATCH 2/3] dt-bindings: Add bindings for nvidia,tegra186-ccplex-cluster

On 04/03/2017 05:24 PM, Jon Hunter wrote: On 03/04/17 13:42, Mikko Perttunen wrote: The Tegra186 CCPLEX_CLUSTER area contains memory-mapped registers that initiate CPU frequency/voltage transitions. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- .../arm/tegra/nvidia,te

Re: [PATCH 2/3] dt-bindings: Add bindings for nvidia,tegra186-ccplex-cluster

On 04/03/2017 05:06 PM, Thierry Reding wrote: On Mon, Apr 03, 2017 at 03:42:24PM +0300, Mikko Perttunen wrote: The Tegra186 CCPLEX_CLUSTER area contains memory-mapped registers that initiate CPU frequency/voltage transitions. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- .

Re: [PATCH 1/3] cpufreq: Add Tegra186 cpufreq driver

On 04/03/2017 05:47 PM, Thierry Reding wrote: On Mon, Apr 03, 2017 at 03:42:23PM +0300, Mikko Perttunen wrote: Add a new cpufreq driver for Tegra186 (and likely later). The CPUs are organized into two clusters, Denver and A57, with two and four cores respectively. CPU frequency can be adjusted

[PATCH v2 2/3] dt-bindings: Add bindings for nvidia,tegra186-ccplex-cluster

The Tegra186 CCPLEX_CLUSTER area contains memory-mapped registers that initiate CPU frequency/voltage transitions. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- v2: - Only one regs entry. - s/Phandle/phandle/ .../arm/tegra/nvidia,tegra186-ccplex-cluster.txt

[PATCH v2 3/3] arm64: tegra: Add CCPLEX_CLUSTER area in Tegra186

The Tegra186 CCPLEX_CLUSTER area contains memory-mapped registers that initiate CPU frequency/voltage transitions. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- v2: - Only one regs entry arch/arm64/boot/dts/nvidia/tegra186.dtsi | 7 +++ 1 file changed, 7 insertions(+)

[PATCH v2 1/3] cpufreq: Add Tegra186 cpufreq driver

can be set individually; however, this is just a hint as all CPUs in a cluster will run at the maximum rate of non-idle CPUs in the cluster. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- v2: - Many cosmetic / restructuring changes - Only one aperture read from DT now, with

[PATCH] irqchip/gic: Don't write to GICD_ICFGR0

] Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- drivers/irqchip/irq-gic.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index 1b1df4f770bd..d9c050e0 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers

Re: [PATCH] irqchip/gic: Don't write to GICD_ICFGR0

On 07.04.2017 10:32, Marc Zyngier wrote: On 07/04/17 07:49, Mikko Perttunen wrote: On 06.04.2017 12:26, Marc Zyngier wrote: On 06/04/17 09:17, Mikko Perttunen wrote: From: Matt Craighead <mcraigh...@nvidia.com> According to the GICv2 specification, the GICD_ICFGR0, or GIC_DIST_CO

[PATCH v3 1/3] cpufreq: Add Tegra186 cpufreq driver

can be set individually; however, this is just a hint as all CPUs in a cluster will run at the maximum rate of non-idle CPUs in the cluster. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> Acked-by: Viresh Kumar <viresh.ku...@linaro.org> --- v3: - Fixed size parameter of dma_f

Re: [PATCH v2 1/3] cpufreq: Add Tegra186 cpufreq driver

On 04/11/2017 09:35 AM, Viresh Kumar wrote: On 04-04-17, 16:43, Mikko Perttunen wrote: Add a new cpufreq driver for Tegra186 (and likely later). The CPUs are organized into two clusters, Denver and A57, with two and four cores respectively. CPU frequency can be adjusted by writing the desired

Re: [PATCH] gpu: host1x: Fix error handling

dev_err(>dev, "failed to get reset: %d\n", err); return err; } Reviewed-by: Mikko Perttunen <mperttu...@nvidia.com>

Re: [PATCH] [RFC] gpu: host1x: shut up warning about DMA API misuse

On 20.04.2017 11:25, Arnd Bergmann wrote: On Thu, Apr 20, 2017 at 9:02 AM, Mikko Perttunen <cyn...@kapsi.fi> wrote: On 19.04.2017 21:24, Arnd Bergmann wrote: When dma_addr_t and phys_addr_t are not the same size, we get a warning from the dma_alloc_wc function: drivers/gpu/host1x/

Re: [PATCH] [RFC] gpu: host1x: shut up warning about DMA API misuse

On 20.04.2017 13:02, Arnd Bergmann wrote: On Thu, Apr 20, 2017 at 11:44 AM, Mikko Perttunen <cyn...@kapsi.fi> wrote: On 20.04.2017 11:25, Arnd Bergmann wrote: On Thu, Apr 20, 2017 at 9:02 AM, Mikko Perttunen <cyn...@kapsi.fi> wrote: On 19.04.2017 21:24, Arnd Bergmann wrote: I

Re: [PATCH v2 2/3] dt-bindings: Add bindings for nvidia,tegra186-ccplex-cluster

Rob, Mark, could you review this and the 3/3 in the series (which I'm sending to you momentarily)? Thanks, Mikko. On 04.04.2017 16:43, Mikko Perttunen wrote: The Tegra186 CCPLEX_CLUSTER area contains memory-mapped registers that initiate CPU frequency/voltage transitions. Signed-off

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