On 7/4/2018 10:43 PM, Jarkko Sakkinen wrote:
On Wed, Jul 04, 2018 at 02:33:40PM +0530, Shirish S wrote:
During system shutdown,
tpm_class_shutdown() when called with TPM_CHIP_FLAG_TPM2
flag set, makes chip->ops NULL.
However tpm_chip_unregister() called later in shutdown
sequence tries to
Hi Stephen,
On 10/3/2019 3:41 AM, Stephen Rothwell wrote:
> Hi all,
>
> In commit
>
>8c9f69bc5cc4 ("drm/amdgpu: fix build error without CONFIG_HSA_AMD")
>
> Fixes tag
>
>Fixes: 1abb680ad371 ("drm/amdgpu: disable gfxoff while use no H/W
> scheduling policy")
>
> has these problem(s):
>
>
Hi All,
Can we land this patch upstream?
Feel free to add my tested-by.
Thanks.
Regards,
Shirish S
-Original Message-
From: S, Shirish
Sent: Wednesday, July 1, 2020 12:15 PM
To: Tony Lindgren ; Sergey Senozhatsky
Cc: Petr Mladek ; Andy Shevchenko
; Raul Rangel ; Sergey
This one:
https://lkml.org/lkml/2020/6/30/394
I did reply to all, not sure what I am missing while replying.
Regards,
Shirish S
-Original Message-
From: Greg Kroah-Hartman
Sent: Thursday, July 2, 2020 11:42 AM
To: S, Shirish
Cc: Tony Lindgren ; Sergey Senozhatsky
; Petr Mladek
On 6/30/2020 11:32 PM, Tony Lindgren wrote:
* Sergey Senozhatsky [200630 13:06]:
On (20/06/30 14:22), Petr Mladek wrote:
...
@@ -2284,8 +2289,6 @@ int serial8250_do_startup(struct uart_port *port)
* allow register changes to become visible.
*/
Its evident from various forums and logs that MC4_MISC thresholding is not
supported for the family 15 processors, hence skip the x86_model check
while applying quirk.
Changelog[v2]:
- reword commit message to adhere to coding standards
- remove check of model range
Signed-off-by: Shirish S
Below patch series applies to family 15 CPU's of AMD platform, to address a
consistent warning of:
"[Firmware Bug]: cpu 0, invalid threshold interrupt offset ..."
at every boot and every resume, which is misguiding as the reason is not a
Firmware Bug but "MC4_MISC thresholding quirk" not being
MC4_MISC thresholding quirk needs to be applied during S5 -> S0 and
S3 -> S0 state transitions, which follow different code paths, hence
carve it out and move it mce_amd_feature_init(), which is the converging
point of both code paths.
Changelog[v2]:
- move the quirk to mce/amd.c
Nope thats not my email id, am not sure how(s...@vger.kernel.org) its getting
added.
Do you find the same for the new patchset I have sent?
Regards,
Shirish S
-Original Message-
From: Borislav Petkov
Sent: Wednesday, January 16, 2019 8:57 PM
To: S, Shirish
Cc: Thomas Gleixner
I believe its fixed now in :
https://lkml.org/lkml/2019/1/16/507
https://lkml.org/lkml/2019/1/16/508
I don’t see S@vger ... in the From field in the above links instead I see "S,
Shirish" <>
Regards,
Shirish S
-Original Message-
From: S, Shirish
Sent: Wednesday, Ja
This patch series applies to family 15 CPU's of AMD platforms,
so as to address a consistent warning of
"[Firmware Bug]: cpu 0, invalid threshold interrupt offset"
at every boot and upon completiong of successful S3 cycle,
due to a missing quirk, which was not extended to newer models
and also
The below patch added this quirk only for the first generation of family
15 processors, over time its noticed that its required for later
generations too.
"575203b4747c x86, MCE, AMD: Disable error thresholding bank 4 on some
models"
This patch extends the quirk to make it applicable till 7th
This patch adds threshold quirk applicable for family 15
in resume path as well, since mce_amd_feature_init()
does not have quirks applied when originating from mce_syscore_resume(),
resulting in the below message at every successful resume:
"[Firmware Bug]: cpu 0, invalid threshold interrupt
The below patch added this quirk only for the first generation of family
15 processors, over time its noticed that its required for later
generations too.
"575203b4747c x86, MCE, AMD: Disable error thresholding bank 4 on some
models"
This patch extends the quirk to make it applicable till 7th
This patch adds threshold quirk applicable for family 15
in resume path as well, since mce_amd_feature_init()
does not have quirks applied when originating from mce_syscore_resume(),
resulting in the below message at every successful resume:
"[Firmware Bug]: cpu 0, invalid threshold interrupt
Its evident from various forums and logs that MC4_MISC thresholding is not
supported for the family 15 processors, hence skip the x86_model check
while applying quirk.
Changelog[v2]:
- reword commit message to adhere to coding standards
- remove check of model range
Signed-off-by: Shirish S
MC4_MISC thresholding quirk needs to be applied during S5 -> S0 and
S3 -> S0 state transitions, which follow different code paths, hence
carve it out so as to facilitate its application in both scenarios.
Signed-off-by: Shirish S
---
arch/x86/include/asm/mce.h | 1 +
There are 2 code paths leading to mce_amd_feature_init() as below.
1) S5 -> S0: (boot)
secondary_startup_64 -> start_kernel -> identify_boot_cpu ->
identify_cpu ->
mcheck_cpu_init (calls __mcheck_cpu_apply_quirks before) ->
mce_amd_feature_init
2) S3 -> S0: (resume)
syscore_resume ->
Below patch series applies to family 15 CPU's of AMD platform, to address a
consistent warning of:
"[Firmware Bug]: cpu 0, invalid threshold interrupt offset ..."
at every boot and every resume, which is misguiding as the reason is not a
Firmware Bug but "MC4_MISC thresholding quirk" not being
On 7/4/2018 10:43 PM, Jarkko Sakkinen wrote:
On Wed, Jul 04, 2018 at 02:33:40PM +0530, Shirish S wrote:
During system shutdown,
tpm_class_shutdown() when called with TPM_CHIP_FLAG_TPM2
flag set, makes chip->ops NULL.
However tpm_chip_unregister() called later in shutdown
sequence tries to
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