APB SSI controller and the SPI
peripheral device private data.
Note we'll preserve the explicit SSI_MOTO_SPI interface type setting up to
signify the only currently supported interface protocol.
Signed-off-by: Serge Semin
---
drivers/spi/spi-dw-core.c | 6 ++
drivers/spi/spi-dw.h | 1
-off-by: Serge Semin
---
.../bindings/spi/snps,dw-apb-ssi.yaml | 33 +--
1 file changed, 31 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
index c62cbe79f00d
that. We'll also need a way to explicitly set and clear the
corresponding CS bit at a certain moment of the operation. Let's alter
the set_cs function then to also de-activate the CS, when it's required.
Signed-off-by: Serge Semin
---
drivers/spi/spi-dw-core.c | 2 +-
1 file changed, 1 insertion
, which would be activated by means of the dedicated
DW_SPI_CAP_KEEMBAY_MST capability setup.
Note this will be also useful if the driver will be ever altered to
support the DW SPI slave interface.
Signed-off-by: Serge Semin
---
drivers/spi/spi-dw-core.c | 4
drivers/spi/spi-dw-mmio.c | 20
Since n_bytes field of the DW SPI private data is also utilized by the
IRQ handler, we need to make sure it' initialization is done before the
memory barrier.
Signed-off-by: Serge Semin
---
drivers/spi/spi-dw-core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi
the generic DW SPI controller driver up in accordance with the
particular controller specifics. It's done by converting a simple
Alpine-specific CS-override capability into the DW SPI controller
capability activated by setting the DW_SPI_CAP_CS_OVERRIDE flag.
Signed-off-by: Serge Semin
---
drivers
responding patch for
details.
Link:
https://lore.kernel.org/linux-spi/20200508093621.31619-1-sergey.se...@baikalelectronics.ru/
[1] "LINUX KERNEL MEMORY BARRIERS", Documentation/memory-barriers.txt,
Section "KERNEL I/O BARRIER EFFECTS"
Signed-off-by: Serge Semin
Cc: Alexey
Simplify the dw_spi_add_host() method a bit by replacing the set_cs
callback overwrite procedure with direct setting the callback if a custom
version of one is specified.
Signed-off-by: Serge Semin
---
drivers/spi/spi-dw-core.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff
The macro has been unused since a half of FIFO length was defined to be a
marker of the IRQ. Let's remove it definition.
Signed-off-by: Serge Semin
---
drivers/spi/spi-dw.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h
index 90dfd21622d6
of setting it up.
By doing so we'll finally make the SPI device chip_data serving as it's
supposed to - to preserve the SPI device specific DW SPI configuration.
See spi-fsl-dspi.c, spi-pl022.c, spi-pxa2xx.c drivers for example of the
way the chip data is utilized.
Signed-off-by: Serge Semin
RIERS", Documentation/memory-barriers.txt,
Section "KERNEL I/O BARRIER EFFECTS"
Signed-off-by: Serge Semin
---
drivers/spi/spi-dw.h | 18 --
1 file changed, 4 insertions(+), 14 deletions(-)
diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h
index ff77f3
), third we make the generic transfer method more readable,
where now the functionality of submission, execution and wait procedures
is transparently split up instead of having a preparation, intermixed
submission/execution and wait procedures.
Signed-off-by: Serge Semin
---
drivers/spi/spi-dw-dma.c
initialization up a bit, particularly if the APB bus is
relatively slow.
Signed-off-by: Serge Semin
---
drivers/spi/spi-dw-dma.c | 28 +---
1 file changed, 13 insertions(+), 15 deletions(-)
diff --git a/drivers/spi/spi-dw-dma.c b/drivers/spi/spi-dw-dma.c
index bb390ff67d1d
It's pointless to pass the Rx and Tx transfers DMA Tx-descriptors, since
they are used in the Tx/Rx submit method only. Instead just return the
submission status from these methods. This alteration will make the code
less complex.
Signed-off-by: Serge Semin
---
drivers/spi/spi-dw-dma.c | 31
and get into an unpredictable driver behaviour.
Signed-off-by: Serge Semin
---
Changelog v2:
- Replace negative conditional statements with the positive ones.
- Terminate the prepared descriptors on submission errors.
---
drivers/spi/spi-dw-dma.c | 20 ++--
1 file changed, 18
an unlimited number SG entries or Tx-only SPI transfer is requested. But
currently just use it for any SPI transfer.
Signed-off-by: Serge Semin
---
drivers/spi/spi-dw-dma.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-dw-dma.c b/drivers/spi/spi-dw-dma.c
er cleanup to a single place in the
dw_spi_dma_transfer_all() method.
Signed-off-by: Serge Semin
---
drivers/spi/spi-dw-dma.c | 17 -
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/drivers/spi/spi-dw-dma.c b/drivers/spi/spi-dw-dma.c
index f2baefcae9ae..935f073a3
on submission errors.
- Split the patch "spi: dw-dma: Move DMA transfers submission to the
channels prep methods" up into a series of more simple commits.
Signed-off-by: Serge Semin
Cc: Alexey Malahov
Cc: Georgy Vlasov
Cc: Ramil Zaripov
Cc: Pavel Parkhomenko
Cc: Peter Ujfalusi
DW APB SSI DMA driver code is still left in state as if Tx-buffer
might be optional, which is no longer true. Let's fix it so an error would
be returned if no Tx-buffer detected and DMA Tx would be always
enabled.
Signed-off-by: Serge Semin
---
drivers/spi/spi-dw-dma.c | 27 +
, since its device_config() callback
always returns zero (though it might change in future). But since DW APB
SSI driver now supports any DMA back-end we must make sure the DMA device
configuration has been successful before proceeding with further setups.
Signed-off-by: Serge Semin
---
drivers/spi
-by: Serge Semin
---
drivers/spi/spi-dw-dma.c | 35 +--
1 file changed, 17 insertions(+), 18 deletions(-)
diff --git a/drivers/spi/spi-dw-dma.c b/drivers/spi/spi-dw-dma.c
index 935f073a3523..f333c2e23bf6 100644
--- a/drivers/spi/spi-dw-dma.c
+++ b/drivers/spi/spi-dw-dma.c
described above is only executed if a full-duplex SPI
transfer is requested and the DMA engine hasn't provided channels with
hardware accelerated SG list traverse capability to handle both SG
lists at once.
Signed-off-by: Serge Semin
Suggested-by: Andy Shevchenko
---
drivers/spi/spi-dw-dma.c | 137
calling the Rx preparation method.
Signed-off-by: Serge Semin
---
drivers/spi/spi-dw-dma.c | 13 ++---
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/drivers/spi/spi-dw-dma.c b/drivers/spi/spi-dw-dma.c
index da17897b8acb..d2a67dee1a66 100644
--- a/drivers/spi/spi-dw-dma.c
+++ b
memory regions must be done via the dword-aligned addresses.
Signed-off-by: Serge Semin
Cc: Alexey Malahov
Cc: Pavel Parkhomenko
Cc: Lee Jones
Cc: linux-m...@vger.kernel.org
---
Link:
https://lore.kernel.org/linux-mtd/20200508100905.5854-1-sergey.se...@baikalelectronics.ru/
Changelog v2
resets. So for now just mark the PLL clock provider as critical.
Signed-off-by: Serge Semin
Cc: Alexey Malahov
Cc: linux-m...@vger.kernel.org
---
drivers/clk/baikal-t1/clk-ccu-pll.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/baikal-t1/clk-ccu
the caller task hanging up in case if the PVT sensor is suddenly powered
down.
Fixes: 87976ce2825d ("hwmon: Add Baikal-T1 PVT sensor driver")
Signed-off-by: Serge Semin
---
drivers/hwmon/bt1-pvt.c | 85 ++---
drivers/hwmon/bt1-pvt.h | 3 ++
2 files c
hwmon: Add Baikal-T1 PVT sensor driver")
Signed-off-by: Serge Semin
---
drivers/hwmon/bt1-pvt.c | 40
1 file changed, 40 insertions(+)
diff --git a/drivers/hwmon/bt1-pvt.c b/drivers/hwmon/bt1-pvt.c
index 94698cae0497..f4b7353c078a 100644
--- a/drivers
and using it to set the wait-completion timeout.
Fixes: 87976ce2825d ("hwmon: Add Baikal-T1 PVT sensor driver")
Signed-off-by: Serge Semin
Cc: Maxim Kaurkin
Cc: Alexey Malahov
Cc: Pavel Parkhomenko
Cc: linux-m...@vger.kernel.org
Cc: linux-hw...@vger.kernel.org
Cc: linux-kernel@vger.kernel.
timeout is exactly what we need to predict for how long conversion could
normally last.
Fixes: 87976ce2825d ("hwmon: Add Baikal-T1 PVT sensor driver")
Signed-off-by: Serge Semin
---
drivers/hwmon/bt1-pvt.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git
4.2 Execution Order Behavior,
p. 33
[2] MIPS Coherence Protocol Specification, Document Number: MD00605,
Revision 01.01. September 14, 2015, 4.8.1 IO Device Access, p. 58
[3] "LINUX KERNEL MEMORY BARRIERS", Documentation/memory-barriers.txt,
Section "KERNEL I/O BA
for the various MIPS platforms.
[1] MIPS32 P5600 Multiprocessing System Software User's Manual,
Document Number: MD01025, Revision 01.60, April 19, 2016, p. 400
Signed-off-by: Serge Semin
---
Folks, do you think it would be better to implement a dedicated config for
arch/mips/kernel/mips-cm.c code
,
Revision 01.01. September 14, 2015, 4.8.1 IO Device Access, p. 58
[3] "LINUX KERNEL MEMORY BARRIERS", Documentation/memory-barriers.txt,
Section "KERNEL I/O BARRIER EFFECTS"
Signed-off-by: Serge Semin
Cc: Alexey Malahov
Cc: Pavel Parkhomenko
Cc: Vadim Vlasov
Cc: M
Hello Andrew.
On Fri, Sep 18, 2020 at 03:54:03PM +0200, Andrew Lunn wrote:
> On Fri, Sep 18, 2020 at 06:55:16AM +, 劉偉權 wrote:
> > Hi Serge,
>
> > Thanks for your reply. There is a confidential issue that realtek
> > doesn't offer the detail of a full register layout for configuration
> >
Hello Willy,
Thanks for the patch. My comments are below.
I've Cc'ed the U-boot/FreeBSD, who might be also interested in the solution
you've provided.
On Thu, Sep 17, 2020 at 09:47:33AM +0800, Willy Liu wrote:
> RGMII RX Delay and TX Delay settings will not applied if Force TX RX Delay
> Control
On Sun, Sep 06, 2020 at 06:18:07AM +, Dingtianhong wrote:
[...]
> > On Sat, Aug 22, 2020 at 12:27:53PM +0800, Ding Tianhong wrote:
> >> The hisilicon ascend soc's gpio is based on the synopsys DW gpio,
> >> and expand the register to support for INTCOMB_MASK, the new
> >> register is used to
Hello Ding,
Thanks for the patch. My comments are below.
On Sat, Aug 22, 2020 at 12:27:53PM +0800, Ding Tianhong wrote:
> The hisilicon ascend soc's gpio is based on the synopsys DW gpio,
> and expand the register to support for INTCOMB_MASK, the new
> register is used to enable/disable the
On Wed, Aug 19, 2020 at 10:43:51AM +0800, Wang Hai wrote:
> Remove linux/clk.h which is included more than once
>
> Reported-by: Hulk Robot
> Signed-off-by: Wang Hai
Thanks!
Acked-by: Serge Semin
> ---
> drivers/bus/bt1-apb.c | 1 -
> 1 file changed, 1 deletion(-)
>
nnel
before each transfer") we can freely do that in the generic
dw_dma_initialize_chan() method.
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
---
drivers/dma/dw/dw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/dma/dw/dw.c b/drivers/dma/dw/dw.c
in
in a single line even though it
gets out of 80 columns limit.
Signed-off-by: Serge Semin
Cc: Alexey Malahov
Cc: Pavel Parkhomenko
Cc: Peter Ujfalusi
Cc: Andy Shevchenko
Cc: Rob Herring
Cc: dmaeng...@vger.kernel.org
Cc: devicet...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Serge Se
and speed up the DMA-channel performance for
DMA_DEV_TO_MEM DMA-transfers.
Signed-off-by: Serge Semin
Acked-by: Andy Shevchenko
---
Changelog v2:
- Add Databook version to the commit log.
---
drivers/dma/dw/core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/dma
a channel FIFO or
data items required to complete the block transfer, whichever is smaller;
length of burst transfers from memory is always equal to the space
available in a channel FIFO or number of data items required to complete
the block transfer, whichever is smaller.
Signed-off-by: S
been noticed for the channels synthesized with
max-burst-len=4.
Signed-off-by: Serge Semin
---
Changelog v2:
- Use the statement "slave.channels >= BIT(dw->pdata->nr_channels)" to
make sure the permitted DMA-channels pool is valid.
- Describe new DW DMAC "channels&quo
the
phandle arguments or the mask is zero, then the allocation will be
performed from a set of all channels provided by the DMA controller.
Signed-off-by: Serge Semin
---
.../devicetree/bindings/dma/snps,dma-spear1340.yaml| 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff
On Fri, Jul 31, 2020 at 10:22:54PM +0530, Vinod Koul wrote:
> On 30-07-20, 20:13, Serge Semin wrote:
> > On Thu, Jul 30, 2020 at 07:47:03PM +0300, Andy Shevchenko wrote:
> > > On Thu, Jul 30, 2020 at 07:31:54PM +0300, Serge Semin wrote:
> > > > On Thu, Jul 30,
On Fri, Jul 31, 2020 at 10:56:37AM -0500, Dinh Nguyen wrote:
> Hi Serge,
>
> On 7/31/20 1:48 AM, Serge Semin wrote:
> > Hello Dinh,
> > It must be something wrong with your timer2 and timer3 declared in the
> > Arria10
> > dts because the patch didn't change
On Fri, Jul 31, 2020 at 12:26:12PM +0300, Andy Shevchenko wrote:
> On Fri, Jul 31, 2020 at 10:59:45AM +0300, Serge Semin wrote:
>
> ...
>
> > Note since the DMA-engine subsystem in kernel 5.8-rcX doesn't have the
> > max_sg_burst capability supported, this series i
On Fri, Jul 31, 2020 at 12:15:28PM +0300, Andy Shevchenko wrote:
> On Fri, Jul 31, 2020 at 10:59:49AM +0300, Serge Semin wrote:
> > Indeed we can freely move the dmaengine_submit() method invocation and the
> > Tx and Rx busy flag setting into the DMA Tx/Rx prepare methods. By doi
On Fri, Jul 31, 2020 at 12:16:38PM +0300, Andy Shevchenko wrote:
> On Fri, Jul 31, 2020 at 10:59:48AM +0300, Serge Semin wrote:
> > Mainly this is a preparation patch before adding one-by-one DMA SG entries
> > transmission. But logically the Tx and Rx DMA channels setup should b
DW APB SSI DMA driver code is still left in state as if Tx-buffer
might be optional, which is no longer true. Let's fix it so an error would
be returned if no Tx-buffer detected and DMA Tx would be always
enabled.
Signed-off-by: Serge Semin
---
drivers/spi/spi-dw-dma.c | 27 +
methods are now responsible for
the DMA transactions submission, we also rename them to
dw_spi_dma_submit_{tx,rx}().
Signed-off-by: Serge Semin
---
drivers/spi/spi-dw-dma.c | 56 ++--
1 file changed, 31 insertions(+), 25 deletions(-)
diff --git a/drivers/spi/spi
-by: Serge Semin
---
drivers/spi/spi-dw-dma.c | 35 +--
1 file changed, 17 insertions(+), 18 deletions(-)
diff --git a/drivers/spi/spi-dw-dma.c b/drivers/spi/spi-dw-dma.c
index f8508c0c7978..2b42b42b6cf2 100644
--- a/drivers/spi/spi-dw-dma.c
+++ b/drivers/spi/spi-dw-dma.c
er cleanup to a single place in the
dw_spi_dma_transfer_all() method.
Signed-off-by: Serge Semin
---
drivers/spi/spi-dw-dma.c | 17 -
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/drivers/spi/spi-dw-dma.c b/drivers/spi/spi-dw-dma.c
index 32ef7913a73d..f8508c0c7
described above is only executed if a full-duplex SPI
transfer is requested and the DMA engine hasn't provided channels with
hardware accelerated SG list traverse capability to handle both SG
lists at once.
Signed-off-by: Serge Semin
Suggested-by: Andy Shevchenko
---
drivers/spi/spi-dw-dma.c | 137
an unlimited number SG entries or Tx-only SPI transfer is requested. But
currently just use it for any SPI transfer.
Signed-off-by: Serge Semin
---
drivers/spi/spi-dw-dma.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-dw-dma.c b/drivers/spi/spi-dw-dma.c
initialization up a bit, particularly if the APB bus is
relatively slow.
Signed-off-by: Serge Semin
---
drivers/spi/spi-dw-dma.c | 29 ++---
1 file changed, 14 insertions(+), 15 deletions(-)
diff --git a/drivers/spi/spi-dw-dma.c b/drivers/spi/spi-dw-dma.c
index bb390ff67d1d
now supports any DMA back-end we must make sure the
DMA device configuration has been successful before proceeding with
further setups.
Signed-off-by: Serge Semin
---
drivers/spi/spi-dw-dma.c | 42 +---
1 file changed, 31 insertions(+), 11 deletions(-)
diff
be merged in through the
DMA-engine repo.
Signed-off-by: Serge Semin
Cc: Alexey Malahov
Cc: Georgy Vlasov
Cc: Ramil Zaripov
Cc: Pavel Parkhomenko
Cc: Peter Ujfalusi
Cc: Andy Shevchenko
Cc: Andy Shevchenko
Cc: Feng Tang
Cc: Vinod Koul
Cc: linux-...@vger.kernel.org
Cc: linux-kernel@vger.
Hello Dinh,
It must be something wrong with your timer2 and timer3 declared in the Arria10
dts because the patch didn't change anything for the first two timers (timer0
and
timer1). It just permits to register all DW APB Timers found in dts.
If those timers are broken, then you should have
On Fri, Jul 31, 2020 at 12:10:16PM +0800, Jiaxun Yang wrote:
> Requested by downstream distros, a Kconfig option for default
> IEEE754 conformance mode allows them to set their mode to
> relaxed by default.
That's what should have been here in the first place. Thanks!
Reviewed-by: Se
On Thu, Jul 30, 2020 at 07:47:03PM +0300, Andy Shevchenko wrote:
> On Thu, Jul 30, 2020 at 07:31:54PM +0300, Serge Semin wrote:
> > On Thu, Jul 30, 2020 at 07:24:28PM +0300, Andy Shevchenko wrote:
> > > On Thu, Jul 30, 2020 at 06:45:42PM +0300, Serge Semin wrote:
>
&g
On Thu, Jul 30, 2020 at 07:41:46PM +0300, Andy Shevchenko wrote:
> On Thu, Jul 30, 2020 at 06:45:45PM +0300, Serge Semin wrote:
> > DW DMA IP-core provides a way to synthesize the DMA controller with
> > channels having different parameters like maximum burst-length,
> >
On Thu, Jul 30, 2020 at 07:31:22PM +0300, Andy Shevchenko wrote:
> On Thu, Jul 30, 2020 at 06:45:44PM +0300, Serge Semin wrote:
> > According to the DW DMA controller Databook (page 40 "3.5 Memory
>
> Which version of it?
2.18b
>
> > Peripherals") memory
On Thu, Jul 30, 2020 at 07:24:28PM +0300, Andy Shevchenko wrote:
> On Thu, Jul 30, 2020 at 06:45:42PM +0300, Serge Semin wrote:
> > CFGx.FIFO_MODE field controls a DMA-controller "FIFO readiness" criterion.
> > In other words it determines when to start pushing data out
d speed up the DMA-channel performance for
DMA_DEV_TO_MEM DMA-transfers.
Signed-off-by: Serge Semin
---
drivers/dma/dw/core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c
index 4700f2e87a62..3da0aea9fe25 100644
--- a/drivers/dma
nnel
before each transfer") we can freely do that in the generic
dw_dma_initialize_chan() method.
Signed-off-by: Serge Semin
---
Note the DMA-engine repository git.infradead.org/users/vkoul/slave-dma.git
isn't accessible. So I couldn't find out the Andy' commit hash to use it in
the log
annel FIFO or
data items required to complete the block transfer, whichever is smaller;
length of burst transfers from memory is always equal to the space
available in a channel FIFO or number of data items required to complete
the block transfer, whichever is smaller.
Signed-off-by: Serge Semin
--
been noticed for the channels synthesized with
max-burst-len=4.
Signed-off-by: Serge Semin
---
drivers/dma/dw/core.c| 4
drivers/dma/dw/of.c | 7 +--
include/linux/platform_data/dma-dw.h | 3 +++
3 files changed, 12 insertions(+), 2 deletions(-)
diff --git
of the series:
Link:
https://lore.kernel.org/dmaengine/20200723005848.31907-1-sergey.se...@baikalelectronics.ru
Signed-off-by: Serge Semin
Cc: Alexey Malahov
Cc: Pavel Parkhomenko
Cc: Peter Ujfalusi
Cc: Andy Shevchenko
Cc: Rob Herring
Cc: dmaeng...@vger.kernel.org
Cc: devicet...@vger.kernel.
the
phandle arguments or the mask is zero, then the allocation will be
performed from a set of all channels provided by the DMA controller.
Signed-off-by: Serge Semin
---
.../devicetree/bindings/dma/snps,dma-spear1340.yaml| 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff
d Andy' Suggested-by to the patch: "gpio: dwapb: Add max GPIOs macro"
- Add blank lines to the IRQ-chip conversion commit message to make it
more readable.
- Dynamically allocate memory for the IRQ-chip-related data.
Signed-off-by: Serge Semin
Cc: Andy Shevchenko
Cc: Andy Shevchenko
will be purely managed by the device resources interface.
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
---
drivers/gpio/gpio-dwapb.c | 35 +--
1 file changed, 29 insertions(+), 6 deletions(-)
diff --git a/drivers/gpio/gpio-dwapb.c b/drivers/gpio/gpio
Add a new macro DWAPB_MAX_GPIOS which defines the maximum possible number
of GPIO lines corresponding to the maximum DW APB GPIO controller port
width. Use the new macro instead of number literal 32 where it's
applicable.
Suggested-by: Andy Shevchenko
Signed-off-by: Serge Semin
---
drivers
-by: Serge Semin
Reviewed-by: Andy Shevchenko
---
Changelog v2:
- This is a new patch detached from commit
"gpio: dwapb: Convert driver to using the GPIO-lib-based IRQ-chip".
---
drivers/gpio/gpio-dwapb.c | 10 --
1 file changed, 10 deletions(-)
diff --git a/drivers/gpio/gpio
It's redundant to have a vendor-specific property describing a number of
GPIOS while there is a generic one. Let's mark the former one as
deprecated and define the "ngpios" property supported with constraints
of being within [1; 32] range.
Signed-off-by: Serge Semin
Reviewed-by: R
that
the clocks acquisition and release will be purely managed by the device
resources interface.
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
---
drivers/gpio/gpio-dwapb.c | 48 ++-
1 file changed, 32 insertions(+), 16 deletions(-)
diff --git a/drivers/gpio
Since GPIOlib-based IRQ-chip interface is now utilized there is no need
in calling the methods acpi_gpiochip_{request,free}_interrupts() here.
They will be called from gpiochip_add_irqchip()/gpiochip_irqchip_remove()
anyway.
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
all
motivate the platform developer to convert the DW APB GPIO DT-nodes to
using the standard number of GPIOs property.
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
---
drivers/gpio/gpio-dwapb.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpio/gpio
to be done for it. All the cleanups are now performed by means of the
device managed framework.
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
---
drivers/gpio/gpio-dwapb.c | 37 ++---
1 file changed, 2 insertions(+), 35 deletions(-)
diff --git a/drivers/gpio
For better readability let's group all the IRQ handlers in a single place
of the driver instead of having them scatter around all over the file.
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
---
drivers/gpio/gpio-dwapb.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions
a regression of commit 6a2f4b7dadd5
("gpio: dwapb: use a second irq chip"), since the later isn't properly
used here anyway.
Signed-off-by: Serge Semin
---
Note in this patch we omit the next GPIO-lib IRQ-chip settings
initialization:
gc->irq.map
gc->irq.init_valid_mask
That's in
On Thu, Jul 30, 2020 at 05:26:18PM +0300, Andy Shevchenko wrote:
> On Thu, Jul 30, 2020 at 04:55:31PM +0300, Serge Semin wrote:
> > GPIO-lib provides a ready-to-use interface to initialize an IRQ-chip on
> > top of a GPIO chip. It's better from maintainability and readability
&g
On Thu, Jul 30, 2020 at 05:05:26PM +0300, Andy Shevchenko wrote:
> On Thu, Jul 30, 2020 at 04:55:30PM +0300, Serge Semin wrote:
> > Add a new macro DWAPB_MAX_GPIOS which defines the maximum possible number
> > of GPIO lines corresponding to the maximum DW APB GPIO controller port
Wou, I've confused my SOB tag here.
Linus, if no additional patchset revision is required, could you please
replace it with:
Signed-off-by: Serge Semin
?
Alternatively I could resend the series with correct version of the tag.
-Sergey
On Thu, Jul 30, 2020 at 04:55:26PM +0300, Serge Semin
On Thu, Jul 30, 2020 at 05:05:26PM +0300, Andy Shevchenko wrote:
> On Thu, Jul 30, 2020 at 04:55:30PM +0300, Serge Semin wrote:
> > Add a new macro DWAPB_MAX_GPIOS which defines the maximum possible number
> > of GPIO lines corresponding to the maximum DW APB GPIO controller port
For better readability let's group all the IRQ handlers in a single place
of the driver instead of having them scatter around all over the file.
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
---
drivers/gpio/gpio-dwapb.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions
Since GPIOlib-based IRQ-chip interface is now utilized there is no need
in calling the methods acpi_gpiochip_{request,free}_interrupts() here.
They will be called from gpiochip_add_irqchip()/gpiochip_irqchip_remove()
anyway.
Signed-off-by: Serge Semin
---
Changelog v2:
- This is a new patch
-by: Serge Semin
---
Changelog v2:
- This is a new patch detached from commit
"gpio: dwapb: Convert driver to using the GPIO-lib-based IRQ-chip".
---
drivers/gpio/gpio-dwapb.c | 10 --
1 file changed, 10 deletions(-)
diff --git a/drivers/gpio/gpio-dwapb.c b/drivers/gpio/gpio-dwa
Add a new macro DWAPB_MAX_GPIOS which defines the maximum possible number
of GPIO lines corresponding to the maximum DW APB GPIO controller port
width. Use the new macro instead of number literal 32 where it's
applicable.
Signed-off-by: Serge Semin
---
drivers/gpio/gpio-dwapb.c
It's redundant to have a vendor-specific property describing a number of
GPIOS while there is a generic one. Let's mark the former one as
deprecated and define the "ngpios" property supported with constraints
of being within [1; 32] range.
Signed-off-by: Serge Semin
Reviewed-by: R
to be done for it. All the cleanups are now performed by means of the
device managed framework.
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
---
drivers/gpio/gpio-dwapb.c | 37 ++---
1 file changed, 2 insertions(+), 35 deletions(-)
diff --git a/drivers/gpio
that
the clocks acquisition and release will be purely managed by the device
resources interface.
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
---
drivers/gpio/gpio-dwapb.c | 48 ++-
1 file changed, 32 insertions(+), 16 deletions(-)
diff --git a/drivers/gpio
of commit 6a2f4b7dadd5
("gpio: dwapb: use a second irq chip"), since the later isn't properly
used here anyway.
Signed-off-by: Serge Semin
---
Note in this patch we omit the next GPIO-lib IRQ-chip settings
initialization:
gc->irq.map
gc->irq.init_valid_mask
That's intentional
will be purely managed by the device resources interface.
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
---
drivers/gpio/gpio-dwapb.c | 35 +--
1 file changed, 29 insertions(+), 6 deletions(-)
diff --git a/drivers/gpio/gpio-dwapb.c b/drivers/gpio/gpio
o.
- Introduce dwapb_convert_irqs() method to convert the sparse parental
IRQs array into an array of linearly distributed IRQs correctly
perceived by GPIO-lib.
Signed-off-by: Serge Semin
Cc: Andy Shevchenko
Cc: Andy Shevchenko
Cc: Alexey Malahov
Cc: Pavel Parkhomenko
Cc: Rob Herring
Cc: linux
all
motivate the platform developer to convert the DW APB GPIO DT-nodes to
using the standard number of GPIOs property.
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
---
drivers/gpio/gpio-dwapb.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpio/gpio
On Wed, Jul 29, 2020 at 06:10:24PM +0300, Andy Shevchenko wrote:
> On Wed, Jul 29, 2020 at 3:58 PM Serge Semin
> wrote:
> > On Mon, Jul 27, 2020 at 12:22:28AM +0200, Linus Walleij wrote:
>
> ...
>
> > Sorry for a delay with a response to this issue. I had to g
On Mon, Jul 27, 2020 at 12:22:28AM +0200, Linus Walleij wrote:
> On Sat, Jul 25, 2020 at 1:03 AM Serge Semin
> wrote:
>
> > According to the DW APB GPIO databook it can be configured to provide
> > either a
> > combined IRQ line or multiple interrupt sig
On Sat, Jul 25, 2020 at 03:12:49PM +0300, Andy Shevchenko wrote:
> On Sat, Jul 25, 2020 at 2:03 AM Serge Semin
> wrote:
> > On Thu, Jul 23, 2020 at 01:03:17PM +0300, Andy Shevchenko wrote:
> > > On Thu, Jul 23, 2020 at 04:38:55AM +03
On Mon, Jul 27, 2020 at 02:31:14PM +0530, Vinod Koul wrote:
> On 23-07-20, 03:58, Serge Semin wrote:
> > In the previous patchset I've written the next message:
> >
> > > Folks, note I've removed the next patches from the series:
> > > [PATCH v7 04/11] dmaengi
On Thu, Jul 23, 2020 at 05:08:15PM +0300, Andy Shevchenko wrote:
> On Thu, Jul 23, 2020 at 04:38:55AM +0300, Serge Semin wrote:
> > GPIO-lib provides a ready-to-use interface to initialize an IRQ-chip on
> > top of a GPIO chip. It's better from maintainability and readability
&g
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