On Wed, Mar 06, 2019 at 04:22:33PM -0700, Logan Gunthorpe wrote:
>
> On 2019-03-06 3:45 p.m., Serge Semin wrote:
> [Snip]
>
> Pretty sure everything above is just agreement...
>
> > So your current approach is inbound MW-centralized, while mine is developed
> > a
/spi-dw-bt1.c: In function 'dw_spi_bt1_dirmap_copy_from_map':
> drivers/spi/spi-dw-bt1.c:77:6: note: 'data' declared here
>77 | u32 data;
> | ^~~~
Can't believe I missed that. Thanks!
Acked-by: Serge Semin
>
> Addresses-Coverity: CID 149777
e of code
> is actually intended to be a byte offset.
Thanks, one more time.)
Acked-by: Serge Semin
>
> Fixes: b3e79e7682e0 ("mtd: physmap: Add Baikal-T1 physically mapped ROM
> support")
> Addresses-Coverity-ID: 1497765 ("Out-of-bounds access")
> Cc
On Wed, Feb 10, 2021 at 10:33:26PM +0300, Serge Semin wrote:
> On Wed, Feb 10, 2021 at 12:56:59PM -0600, Bjorn Andersson wrote:
> > On Wed 10 Feb 12:40 CST 2021, Serge Semin wrote:
> >
> > > On Wed, Feb 10, 2021 at 12:17:27PM -0600, Rob Herring wrote:
> > > &
On Fri, Feb 12, 2021 at 11:49:15AM -0600, Bjorn Andersson wrote:
> On Wed 10 Feb 13:33 CST 2021, Serge Semin wrote:
>
> > On Wed, Feb 10, 2021 at 12:56:59PM -0600, Bjorn Andersson wrote:
> > > On Wed 10 Feb 12:40 CST 2021, Serge Semin wrote:
> > >
> > > >
mpatible string to match the "snps,dwc3". The semantic of the code
won't change seeing all the DWC USB3 nodes are supposed to have the
compatible property with any of those strings set.
Signed-off-by: Serge Semin
---
Changelog v7:
- Replace "of_get_child_by_name(np, "
In accordance with the DWC USB3 bindings the corresponding node
name is suppose to comply with the Generic USB HCD DT schema, which
requires the USB nodes to have the name acceptable by the regexp:
"^usb(@.*)?" . Make sure the "snps,dwc3"-compatible nodes are correctly
named.
there.
Fixes: a4333c3a6ba9 ("usb: dwc3: Add Qualcomm DWC3 glue driver")
Signed-off-by: Serge Semin
---
Note the patch will get cleanly applied on the commit 2bc02355f8ba ("usb:
dwc3: qcom: Add support for booting with ACPI"), while the bug has been
there since the Qualcomm
On Wed, Feb 03, 2021 at 10:06:46AM +0100, Greg Kroah-Hartman wrote:
> On Tue, Feb 02, 2021 at 05:02:08PM -0600, Bjorn Andersson wrote:
> > On Sat 05 Dec 09:56 CST 2020, Serge Semin wrote:
> >
> > > In accordance with the USB HCD/DRD schema all the USB controllers are
&
On Tue, Feb 09, 2021 at 10:56:46AM +, Russell King - ARM Linux admin wrote:
> On Tue, Feb 09, 2021 at 11:37:29AM +0100, Heiner Kallweit wrote:
> > Right, adding something like a genphy_{read,write}_mmd() doesn't make
> > too much sense for now. What I meant is just exporting mmd_phy_indirect().
hci"-compatible
nodes are correctly named.
Signed-off-by: Serge Semin
Acked-by: Vladimir Zapolskiy
Acked-by: Krzysztof Kozlowski
---
arch/arm/boot/dts/lpc18xx.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/lpc18xx.dtsi b/arch/arm/boot/dts/l
hci"-compatible
nodes are correctly named.
Signed-off-by: Serge Semin
Acked-by: Alexey Brodkin
Acked-by: Krzysztof Kozlowski
---
arch/arc/boot/dts/axc003.dtsi| 4 ++--
arch/arc/boot/dts/axc003_idu.dtsi| 4 ++--
arch/arc/boot/dts/axs10x_mb.dtsi | 4 ++--
arch/arc/boot/dts/hsdk.dt
Syonpsys IP cores are supposed to be defined with "snps" vendor-prefix.
Use it instead of the deprecated "synopsys" one.
Signed-off-by: Serge Semin
Reviewed-by: Krzysztof Kozlowski
---
arch/arm/boot/dts/keystone-k2e.dtsi | 2 +-
arch/arm/boot/dts/keystone.dtsi | 2 +-
org
Cc: linux-arm-...@vger.kernel.org
Cc: devicet...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Serge Semin (10):
arm: dts: ls1021a: Harmonize DWC USB3 DT nodes name
arm: dts: keystone: Correct DWC USB3 compatible string
arc: dts: Harmonize EHCI/OHCI DT nodes name
arm: dts: lpc18xx: Harmoni
In accordance with the DWC USB3 bindings the corresponding node
name is suppose to comply with the Generic USB HCD DT schema, which
requires the USB nodes to have the name acceptable by the regexp:
"^usb(@.*)?" . Make sure the "snps,dwc3"-compatible nodes are correctly
named.
In accordance with the DWC USB3 bindings the corresponding node
name is suppose to comply with the Generic USB HCD DT schema, which
requires the USB nodes to have the name acceptable by the regexp:
"^usb(@.*)?" . Make sure the "snps,dwc3"-compatible nodes are correctly
named.
In accordance with the DWC USB3 bindings the corresponding node
name is suppose to comply with the Generic USB HCD DT schema, which
requires the USB nodes to have the name acceptable by the regexp:
"^usb(@.*)?" . Make sure the "snps,dwc3"-compatible nodes are correctly
named.
the
deprecated naming so not to fail on the legacy DTS-files passed to the
newer kernels.
Signed-off-by: Serge Semin
Reviewed-by: Bjorn Andersson
---
drivers/usb/dwc3/dwc3-qcom.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/d
spite of the warning comment about possible backward
compatibility issues.
Signed-off-by: Serge Semin
Acked-by: Krzysztof Kozlowski
---
arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 4 ++--
arch/arm64/boot/dts/apm/apm-storm.dtsi | 6 +++---
2 files changed, 5 insertions(+), 5 deletions(-
hci"-compatible
nodes are correctly named.
Signed-off-by: Serge Semin
Acked-by: Krzysztof Kozlowski
---
arch/powerpc/boot/dts/akebono.dts | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/boot/dts/akebono.dts
b/arch/powerpc/boot/dts/akebono.dts
index df18f8dc4
In accordance with the DWC USB3 bindings the corresponding node
name is suppose to comply with the Generic USB HCD DT schema, which
requires the USB nodes to have the name acceptable by the regexp:
"^usb(@.*)?" . Make sure the "snps,dwc3"-compatible nodes are correctly
named.
On Tue, Feb 09, 2021 at 03:11:41PM +0100, Andrew Lunn wrote:
> > Regarding splitting the series up. I don't see a problem in just
> > sending the cover-letter patch and actual GPIO-related patches to
> > the GPIO-maintainers with no need to have them added to Cc in the rest
> > of the series.
>
>
On Wed, Feb 10, 2021 at 12:17:27PM -0600, Rob Herring wrote:
> On Wed, Feb 10, 2021 at 11:29 AM Serge Semin
> wrote:
> >
> > In accordance with the USB HCD/DRD schema all the USB controllers are
> > supposed to have DT-nodes named with prefix "^usb(@.*)?". Since
On Wed, Feb 10, 2021 at 10:21:47AM -0800, Florian Fainelli wrote:
> On 2/10/21 9:28 AM, Serge Semin wrote:
> > As the subject states this series is an attempt to harmonize the xHCI,
> > EHCI, OHCI and DWC USB3 DT nodes with the DT schema introduced in the
> > framewo
On Wed, Feb 10, 2021 at 12:56:59PM -0600, Bjorn Andersson wrote:
> On Wed 10 Feb 12:40 CST 2021, Serge Semin wrote:
>
> > On Wed, Feb 10, 2021 at 12:17:27PM -0600, Rob Herring wrote:
> > > On Wed, Feb 10, 2021 at 11:29 AM Serge Semin
> > > wrote:
> > > &
On Tue, Feb 09, 2021 at 04:26:08PM -0600, Rob Herring wrote:
> On Mon, Feb 08, 2021 at 04:55:48PM +0300, Serge Semin wrote:
> > Currently the "snps,axi-config", "snps,mtl-rx-config" and
> > "snps,mtl-tx-config" properties are declared as a single phand
On Tue, Feb 09, 2021 at 04:32:58PM -0600, Rob Herring wrote:
> On Mon, Feb 08, 2021 at 04:55:51PM +0300, Serge Semin wrote:
> > Currently the snps,dwmac.yaml DT bindings file is used for both DT nodes
> > describing generic DW MAC devices and as DT schema with common properties
>
On Wed, Feb 10, 2021 at 02:49:24PM +0800, Jisheng Zhang wrote:
> Hi,
>
> On Mon, 8 Feb 2021 16:56:00 +0300 Serge Semin wrote:
>
>
> >
> > Since commit bb3222f71b57 ("net: stmmac: platform: use optional clk/reset
> > get APIs") a manual implemen
On Tue, Feb 09, 2021 at 05:13:52PM -0600, Rob Herring wrote:
> On Mon, Feb 08, 2021 at 05:08:05PM +0300, Serge Semin wrote:
> > Synopsys DesignWare Ethernet controllers can be synthesized with
> > General-Purpose IOs support. GPIOs can work either as inputs or as outputs
> &g
On Thu, Feb 11, 2021 at 10:39:41AM +, Russell King - ARM Linux admin wrote:
> On Wed, Feb 10, 2021 at 07:47:20PM +0300, Serge Semin wrote:
> > On Tue, Feb 09, 2021 at 10:56:46AM +, Russell King - ARM Linux admin
> > wrote:
> > > On Tue, Feb 09, 2021 at 11:37:29A
eb 12, 2021 at 11:55:19PM +0300, Serge Semin wrote:
> of_get_child_by_name() increments the reference counter of the OF node it
> managed to find. So after the code is done using the device node, the
> refcount must be decremented. Add missing of_node_put() invocation then
> to the dwc3_qcom
On Thu, Feb 18, 2021 at 04:32:29PM +0100, Greg Kroah-Hartman wrote:
> On Thu, Feb 18, 2021 at 06:29:04PM +0300, Serge Semin wrote:
> > Bjorn, Greg, Felippe, Andy,
> > Any comments on this series? Bjorn, Greg you asked me to resend the
> > patches related with the DW USB3 node
On Thu, Feb 11, 2021 at 01:28:06AM +0300, Serge Semin wrote:
> On Tue, Feb 09, 2021 at 05:13:52PM -0600, Rob Herring wrote:
> > On Mon, Feb 08, 2021 at 05:08:05PM +0300, Serge Semin wrote:
> > > Synopsys DesignWare Ethernet controllers can be synthesized with
> > >
On Thu, Feb 11, 2021 at 12:58:00AM +0300, Serge Semin wrote:
> On Tue, Feb 09, 2021 at 04:26:08PM -0600, Rob Herring wrote:
> > On Mon, Feb 08, 2021 at 04:55:48PM +0300, Serge Semin wrote:
> > > Currently the "snps,axi-config", "snps,mtl-rx-config" and
>
On Wed, Feb 03, 2021 at 10:06:46AM +0100, Greg Kroah-Hartman wrote:
> On Tue, Feb 02, 2021 at 05:02:08PM -0600, Bjorn Andersson wrote:
> > On Sat 05 Dec 09:56 CST 2020, Serge Semin wrote:
> >
> > > In accordance with the USB HCD/DRD schema all the USB controllers are
&
le the DMA IRQs
anymore. Such modification won't break the DMA-related code because the
default macro has both Tx and Rx DMA IRQs flags set anyway. So in order to
make things working as usual we just need to call the
stmmac_enable_dma_irq() method aside with the generic IRQs activating
function.
onous flag
switching together with the IRQs unmasking and masking. Luckily the IRQs
are normally enabled/disable in the late/early network initialization
stages respectively.
Signed-off-by: Serge Semin
---
drivers/net/ethernet/stmicro/stmmac/stmmac.h | 2 +-
drivers/net/ethernet/stmi
uired for some early versions of DW GMAC (in our case it's DW GMAC
v3.73a).
Signed-off-by: Serge Semin
---
.../net/ethernet/stmicro/stmmac/stmmac_main.c | 32 +--
1 file changed, 30 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
them have been
enabled by default.
Signed-off-by: Serge Semin
---
Folks, the zero initialization of the DW xGMAC XGMAC_MTL_ECC_CONTROL
register looks suspicious. Are you sure it is supposed to be cleared out
in order to enable the safety IRQs?
---
.../net/ethernet/stmicro/stmmac/dwmac4_core.c
if there were no more specific glue-driver for them.
Signed-off-by: Serge Semin
---
drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c
.
Signed-off-by: Serge Semin
---
Folks, I don't know whether the same GPIO CSR layout is defined for some
other DW MAC IP-core. So for now the accessors have been created for
GMACs only. But if you are sure the callbacks can be used for some other
IP, I can move them to dwmac_lib.c. Though in
to the initial state too. Instead we
suggest to at least restore the DMA/MAC registers to the initial state,
when the software reset were supposed to happen.
Signed-off-by: Serge Semin
---
.../ethernet/stmicro/stmmac.rst | 4 +
drivers/net/ethernet/stmicro/stmmac/Kconfig |
On Mon, Feb 08, 2021 at 04:27:36PM +0100, Andrew Lunn wrote:
> On Mon, Feb 08, 2021 at 05:03:22PM +0300, Serge Semin wrote:
> > It has been noticed that RTL8211E PHY stops detecting and reporting events
> > when EEE is successfully advertised and RXC stopping in LPI is enabled.
On Mon, Feb 08, 2021 at 09:14:02PM +0100, Heiner Kallweit wrote:
> On 08.02.2021 15:03, Serge Semin wrote:
> > It has been noticed that RTL8211E PHY stops detecting and reporting events
> > when EEE is successfully advertised and RXC stopping in LPI is enabled.
> > The freez
On Mon, Feb 08, 2021 at 11:05:21AM -0800, Jakub Kicinski wrote:
> On Mon, 8 Feb 2021 16:55:44 +0300 Serge Semin wrote:
> > Baikal-T1 SoC is equipped with two Synopsys DesignWare GMAC v3.73a-based
> > ethernet interfaces with no internal Ethernet PHY attached. The IP-cores
> &
On Mon, Feb 08, 2021 at 08:36:33PM +0100, Andrew Lunn wrote:
> On Mon, Feb 08, 2021 at 05:08:04PM +0300, Serge Semin wrote:
>
> Hi Serge
>
> I suggest you split this patchset up. This uses the generic GPIO
> framework, which is great. But that also means you should be Cc: th
ynchronous configuration.
Signed-off-by: Serge Semin
Reviewed-by: Guenter Roeck
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Arnd Bergmann
Cc: Rob Herring
Cc: linux-m...@vger.kernel.org
Cc: devicet...@vger.kernel.org
---
Changelog v2:
- Rearrange SoBs.
---
drivers/watchdog/dw_
pport the optional APB3 bus clock specified along
with the mandatory watchdog timer reference clock.
Signed-off-by: Serge Semin
Reviewed-by: Rob Herring
Reviewed-by: Guenter Roeck
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Arnd Bergmann
Cc: linux-m...@vger.kernel.org
---
Changelog v2:
- I
support the new timeouts data
structure.
Signed-off-by: Serge Semin
Reviewed-by: Guenter Roeck
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Arnd Bergmann
Cc: Rob Herring
Cc: linux-m...@vger.kernel.org
Cc: devicet...@vger.kernel.org
---
Changelog v2:
- Rearrange SoBs.
- Add "ms" suffix
happens, the IRQ lane will be left pending until
it's cleared by the timer restart.
Signed-off-by: Serge Semin
Reviewed-by: Guenter Roeck
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Arnd Bergmann
Cc: Rob Herring
Cc: linux-m...@vger.kernel.org
Cc: devicet...@vger.kernel.org
---
Changel
references clock source, optional reset line and
pre-timeout interrupt.
Signed-off-by: Serge Semin
Reviewed-by: Rob Herring
Reviewed-by: Guenter Roeck
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Arnd Bergmann
Cc: linux-m...@vger.kernel.org
---
Changelog v2:
- Rearrange SoBs.
- Discard BE
dog/20200526154123.24402-1-sergey.se...@baikalelectronics.ru
Changelog v4:
- Add Guenter's Reviewed-by tags.
- IRQ > 0 is only valid in Linux so make sure we request IRQ only if valid
number is returned from platform_get_irq_optional().
Signed-off-by: Serge Semin
Cc: Alexey Malahov
Cc: Ma
In case if DW Watchdog IP core is built with WDT_USE_FIX_TOP == false,
a custom timeout periods are used to preset the timer counter. In
this case that periods should be specified in a new "snps,watchdog-tops"
property of the DW watchdog dts node.
Signed-off-by: Serge Semin
Review
For the sake of the easier device-driver debug procedure, we added a
DebugFS file with the controller registers state. It's available only if
kernel is configured with DebugFS support.
Signed-off-by: Serge Semin
Reviewed-by: Guenter Roeck
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc:
Hello Wolfram
On Sat, May 30, 2020 at 11:39:42AM +0200, Wolfram Sang wrote:
>
> Just double checking:
>
> > Signed-off-by: Serge Semin
> > Reviewed-by: Rob Herring
>
> Rob, what about this checkpatch warning?
>
> WARNING: DT binding documents should be l
On Sat, May 30, 2020 at 11:05:54PM +0200, Wolfram Sang wrote:
> On Sat, May 30, 2020 at 01:09:30PM +0200, Wolfram Sang wrote:
> > On Thu, May 28, 2020 at 12:33:18PM +0300, Serge Semin wrote:
> > > Seeing the DW I2C driver is using flags-based accessors with two
> > > c
On Sat, May 30, 2020 at 11:31:52AM +0200, Wolfram Sang wrote:
>
> > + addr = reg & 0x3FFFU;
> > + snprintf(unit_addr, sizeof(unit_addr), "%x", addr);
>
> Hmm, this hardcoded value will not work if we ever need to add another
> bit. I hope this will never happen, though.
>
> > +
It's a Cluster Power Controller embedded into the MIPS IP cores.
Currently the corresponding dts node is supposed to have compatible
and reg properties.
Signed-off-by: Serge Semin
Reviewed-by: Rob Herring
---
Changelog prev:
- Reword the changelog summary - use shorter version.
- Lowe
platforms by default.
Signed-off-by: Serge Semin
---
Changelog prev:
- Use alphabetical order for the include pre-processor operator.
---
drivers/bus/mips_cdmm.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/bus/mips_cdmm.c b/drivers/bus/mips_cdmm.c
index
Add myself as a maintainer of MIPS CPU and GIC IRQchip, MIPS GIC timer
and MIPS CPS CPUidle drivers.
Signed-off-by: Serge Semin
---
MAINTAINERS | 10 ++
1 file changed, 10 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 2926327e4976..f21e51c4a0d5 100644
--- a/MAINTAINERS
.
MIPS GIC also includes a free-running global timer, per-CPU count/compare
timers, and a watchdog. Since currently the GIC Timer is only supported the
DT schema expects an IRQ and clock-phandler charged timer sub-node with
"mti,mips-gic-timer" compatible string.
Signed-off-by: Serge Sem
s file for MIPS CDMM dt-node.
- Convert mti,mips-cpc to DT schema.
- Use a shorter summary describing the bindings modification patches.
- Rearrange the SoBs with adding Alexey' co-development tag.
- Lowercase the hex numbers in the dt-bindings.
Changelog v2:
- Resend.
Signed-off-by: Serge
It's a Common Device Memory Map controller embedded into the MIPS IP
cores, which dts node is supposed to have compatible and reg properties.
Signed-off-by: Serge Semin
Reviewed-by: Rob Herring
---
Changelog prev:
- Lowercase the example hex'es.
---
.../bindings/bus/mti,mips
CDMM may be available not only on MIPS R2 architectures, but also on
newer MIPS R5 chips. For instance our P5600 chip has one. Let's mark
the CDMM bus being supported for that MIPS arch too.
Signed-off-by: Serge Semin
Reviewed-by: Thomas Bogendoerfer
---
drivers/bus/Kconfig | 2 +-
1
On Mon, Jun 01, 2020 at 04:56:21PM +0300, Andy Shevchenko wrote:
> On Mon, Jun 1, 2020 at 3:26 PM Serge Semin
> wrote:
> >
> > Add myself as a maintainer of MIPS CPU and GIC IRQchip, MIPS GIC timer
> > and MIPS CPS CPUidle drivers.
> ...
> > +MIPS CORE DRIVER
Hello Marc,
On Mon, Jun 01, 2020 at 01:31:27PM +0100, Marc Zyngier wrote:
> On 2020-06-01 13:21, Serge Semin wrote:
>
> [...]
>
> > Since Paul isn't looking after the MIPS arch code anymore, Ralf hasn't
> > been seen maintaining MIPS for a long time, Thomas is
On Mon, Jun 01, 2020 at 06:30:22PM +0300, Andy Shevchenko wrote:
> On Mon, Jun 1, 2020 at 6:19 PM Serge Semin
> wrote:
> > On Mon, Jun 01, 2020 at 04:56:21PM +0300, Andy Shevchenko wrote:
> > > On Mon, Jun 1, 2020 at 3:26 PM Serge Semin
> > > wrote:
> > >
On Mon, Jun 01, 2020 at 06:56:46PM +0200, Thomas Bogendoerfer wrote:
> On Mon, Jun 01, 2020 at 06:24:49PM +0300, Serge Semin wrote:
> > Hello Marc,
> >
> > On Mon, Jun 01, 2020 at 01:31:27PM +0100, Marc Zyngier wrote:
> > > On 2020-
On Mon, May 18, 2020 at 11:30:03AM -0600, Rob Herring wrote:
> On Sun, May 17, 2020 at 08:47:39PM +0300, Serge Semin wrote:
> > On Fri, May 15, 2020 at 02:11:13PM +0300, Serge Semin wrote:
> > > On Fri, May 15, 2020 at 04:26:58PM +0530, Vinod Koul wrote:
> > > > On 15
On Mon, May 18, 2020 at 06:32:06PM +0200, Thomas Bogendoerfer wrote:
> On Mon, May 18, 2020 at 04:48:20PM +0300, Serge Semin wrote:
> > On Fri, May 15, 2020 at 11:06:47PM +0200, Thomas Bogendoerfer wrote:
> > > On Fri, May 15, 2020 at 10:48:27AM +0300, Serge Semin wro
On Mon, May 18, 2020 at 04:19:47PM +0100, Mark Brown wrote:
> On Mon, May 18, 2020 at 03:05:42AM +0300, Serge Semin wrote:
> > On Mon, May 11, 2020 at 10:25:06PM +0100, Mark Brown wrote:
>
> > > Yes, some flags should work here - the issue was that at least some
> &g
On Mon, May 18, 2020 at 09:26:59AM -0600, Rob Herring wrote:
> On Fri, May 08, 2020 at 12:36:20PM +0300, Serge Semin wrote:
> > Baikal-T1 Boot SPI is a part of the SoC System Controller and is
> > responsible for the system bootup from an external SPI flash. It's a DW
&
On Mon, May 18, 2020 at 02:33:19PM -0600, Rob Herring wrote:
> On Sun, May 10, 2020 at 12:50:09PM +0300, Serge Semin wrote:
> > Add the "baikal,bt1-sys-i2c" compatible string to the DW I2C binding and
> > make sure the reg property isn't required in this case because
On Mon, May 18, 2020 at 02:40:37PM -0600, Rob Herring wrote:
> On Sun, May 10, 2020 at 01:58:03PM +0300, Serge Semin wrote:
> > In case if DW Watchdog IP core is built with WDT_USE_FIX_TOP == false,
> > a custom timeout periods are used to preset the timer counter. In
> > t
On Mon, May 18, 2020 at 09:26:59AM -0600, Rob Herring wrote:
> On Fri, May 08, 2020 at 12:36:20PM +0300, Serge Semin wrote:
> > Baikal-T1 Boot SPI is a part of the SoC System Controller and is
> > responsible for the system bootup from an external SPI flash. It's a DW
&
03AM +0300, Serge Semin wrote:
> There is a single register provided by the SoC system controller,
> which can be used to tune the L2-cache RAM up. It only provides a way
> to change the L2-RAM access latencies. So aside from "be,bt1-l2-ctl"
> compatible string the device node
On Thu, May 14, 2020 at 02:13:18PM -0500, Rob Herring wrote:
> On Thu, May 07, 2020 at 01:22:57AM +0300, Serge Semin wrote:
> > Baikal-T1 Clocks Control Unit is responsible for transformation of a
> > signal coming from an external oscillator into clocks of various
> > fre
On Mon, Jul 27, 2020 at 12:22:28AM +0200, Linus Walleij wrote:
> On Sat, Jul 25, 2020 at 1:03 AM Serge Semin
> wrote:
>
> > According to the DW APB GPIO databook it can be configured to provide
> > either a
> > combined IRQ line or multiple interrupt signals for ea
On Wed, Jul 29, 2020 at 06:10:24PM +0300, Andy Shevchenko wrote:
> On Wed, Jul 29, 2020 at 3:58 PM Serge Semin
> wrote:
> > On Mon, Jul 27, 2020 at 12:22:28AM +0200, Linus Walleij wrote:
>
> ...
>
> > Sorry for a delay with a response to this issue. I had to g
macro.
- Introduce dwapb_convert_irqs() method to convert the sparse parental
IRQs array into an array of linearly distributed IRQs correctly
perceived by GPIO-lib.
Signed-off-by: Serge Semin
Cc: Andy Shevchenko
Cc: Andy Shevchenko
Cc: Alexey Malahov
Cc: Pavel Parkhomenko
Cc: Rob Herring
Cc:
rors log above shall
motivate the platform developer to convert the DW APB GPIO DT-nodes to
using the standard number of GPIOs property.
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
---
drivers/gpio/gpio-dwapb.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
4) nor 5) shall cause a regression of commit 6a2f4b7dadd5
("gpio: dwapb: use a second irq chip"), since the later isn't properly
used here anyway.
Signed-off-by: Serge Semin
---
Note in this patch we omit the next GPIO-lib IRQ-chip settings
initialization:
gc->irq.map
gc->ir
be purely managed by the device resources interface.
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
---
drivers/gpio/gpio-dwapb.c | 35 +--
1 file changed, 29 insertions(+), 6 deletions(-)
diff --git a/drivers/gpio/gpio-dwapb.c b/drivers/gpio/gpio
done for it. All the cleanups are now performed by means of the
device managed framework.
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
---
drivers/gpio/gpio-dwapb.c | 37 ++---
1 file changed, 2 insertions(+), 35 deletions(-)
diff --git a/drivers/gpio
clocks acquisition and release will be purely managed by the device
resources interface.
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
---
drivers/gpio/gpio-dwapb.c | 48 ++-
1 file changed, 32 insertions(+), 16 deletions(-)
diff --git a/drivers/gpio
Add a new macro DWAPB_MAX_GPIOS which defines the maximum possible number
of GPIO lines corresponding to the maximum DW APB GPIO controller port
width. Use the new macro instead of number literal 32 where it's
applicable.
Signed-off-by: Serge Semin
---
drivers/gpio/gpio-dw
It's redundant to have a vendor-specific property describing a number of
GPIOS while there is a generic one. Let's mark the former one as
deprecated and define the "ngpios" property supported with constraints
of being within [1; 32] range.
Signed-off-by: Serge Semin
Revi
: Serge Semin
---
Changelog v2:
- This is a new patch detached from commit
"gpio: dwapb: Convert driver to using the GPIO-lib-based IRQ-chip".
---
drivers/gpio/gpio-dwapb.c | 10 --
1 file changed, 10 deletions(-)
diff --git a/drivers/gpio/gpio-dwapb.c b/drivers/gpio/gpio-dwa
Since GPIOlib-based IRQ-chip interface is now utilized there is no need
in calling the methods acpi_gpiochip_{request,free}_interrupts() here.
They will be called from gpiochip_add_irqchip()/gpiochip_irqchip_remove()
anyway.
Signed-off-by: Serge Semin
---
Changelog v2:
- This is a new patch
For better readability let's group all the IRQ handlers in a single place
of the driver instead of having them scatter around all over the file.
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
---
drivers/gpio/gpio-dwapb.c | 10 +-
1 file changed, 5 insertions(+), 5 dele
On Thu, Jul 30, 2020 at 05:05:26PM +0300, Andy Shevchenko wrote:
> On Thu, Jul 30, 2020 at 04:55:30PM +0300, Serge Semin wrote:
> > Add a new macro DWAPB_MAX_GPIOS which defines the maximum possible number
> > of GPIO lines corresponding to the maximum DW APB GPIO controller port
Wou, I've confused my SOB tag here.
Linus, if no additional patchset revision is required, could you please
replace it with:
Signed-off-by: Serge Semin
?
Alternatively I could resend the series with correct version of the tag.
-Sergey
On Thu, Jul 30, 2020 at 04:55:26PM +0300, Serge
On Thu, Jul 30, 2020 at 05:05:26PM +0300, Andy Shevchenko wrote:
> On Thu, Jul 30, 2020 at 04:55:30PM +0300, Serge Semin wrote:
> > Add a new macro DWAPB_MAX_GPIOS which defines the maximum possible number
> > of GPIO lines corresponding to the maximum DW APB GPIO controller port
On Thu, Jul 30, 2020 at 05:26:18PM +0300, Andy Shevchenko wrote:
> On Thu, Jul 30, 2020 at 04:55:31PM +0300, Serge Semin wrote:
> > GPIO-lib provides a ready-to-use interface to initialize an IRQ-chip on
> > top of a GPIO chip. It's better from maintainability and readability
ote neither 4) nor 5) shall cause a regression of commit 6a2f4b7dadd5
("gpio: dwapb: use a second irq chip"), since the later isn't properly
used here anyway.
Signed-off-by: Serge Semin
---
Note in this patch we omit the next GPIO-lib IRQ-chip settings
initialization:
gc->irq.map
For better readability let's group all the IRQ handlers in a single place
of the driver instead of having them scatter around all over the file.
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
---
drivers/gpio/gpio-dwapb.c | 10 +-
1 file changed, 5 insertions(+), 5 dele
clocks acquisition and release will be purely managed by the device
resources interface.
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
---
drivers/gpio/gpio-dwapb.c | 48 ++-
1 file changed, 32 insertions(+), 16 deletions(-)
diff --git a/drivers/gpio
Since GPIOlib-based IRQ-chip interface is now utilized there is no need
in calling the methods acpi_gpiochip_{request,free}_interrupts() here.
They will be called from gpiochip_add_irqchip()/gpiochip_irqchip_remove()
anyway.
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
rors log above shall
motivate the platform developer to convert the DW APB GPIO DT-nodes to
using the standard number of GPIOs property.
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
---
drivers/gpio/gpio-dwapb.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
done for it. All the cleanups are now performed by means of the
device managed framework.
Signed-off-by: Serge Semin
Reviewed-by: Andy Shevchenko
---
drivers/gpio/gpio-dwapb.c | 37 ++---
1 file changed, 2 insertions(+), 35 deletions(-)
diff --git a/drivers/gpio
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