On 12.07.2018 10:06, Stefan Agner wrote:
> In the uSDHC case (e.g. i.MX 6) clocks only get disabled if frequency
> is set to 0. However, it could be that the stack asks for a frequency
> change while clocks are on. In that case the function clears the
> divider registers
: Stefan Agner
---
drivers/mmc/host/sdhci-esdhc-imx.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
b/drivers/mmc/host/sdhci-esdhc-imx.c
index 85fd5a8b0b6d..acacd8481473 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b
Fix indent. This also makes disable/enable clock blocks look
alike.
Signed-off-by: Stefan Agner
---
drivers/mmc/host/sdhci-esdhc-imx.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
b/drivers/mmc/host/sdhci-esdhc-imx.c
index acacd8481473
: Stefan Agner
---
drivers/mmc/host/sdhci-esdhc-imx.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
b/drivers/mmc/host/sdhci-esdhc-imx.c
index 85fd5a8b0b6d..acacd8481473 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b
-CMD23 being
used for now. With this the eMMC works stable on high-speed mode
while still announcing SD3.0.
This allows to use mmc-ddr-1_8v to enables DDR52 mode. In DDR52
mode read speed improves from about 42MiB/s to 72MiB/s on an
Apalis T30.
Signed-off-by: Stefan Agner
---
drivers/mmc/host/sdhci
Make sure the clock is doubled when using eMMC DDR52 mode.
Signed-off-by: Stefan Agner
---
drivers/mmc/host/sdhci-tegra.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index 137df06b9b6e..888a1ad511db 100644
The controller simply does not support HS200.
Fixes: 7ad2ed1dfcbe ("mmc: tegra: enable UHS-I modes")
Signed-off-by: Stefan Agner
---
drivers/mmc/host/sdhci-tegra.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc
>>
>> is missing a Signed-off-by from its author.
>
> Thanks for spotting, but it's worse than that. It does have a sign-off
> from its author, but the authorship wasn't preserved by Stefan Agner
> (no From: line in the email body, as there was in Steven's original
On 04.07.2018 13:30, Stefan Agner wrote:
> On 21.06.2018 18:47, Steven Rostedt wrote:
>> From: Steven Rostedt (VMware)
>>
>> Dynamic ftrace requires modifying the code segments that are usually
>> set to read-only. To do this, a per arch function is called both bef
Use the disable-wp to indicate that Apalis and Colibri iMX6 do not
make use of the native write-protect signal available on the i.MX 6
SoCs. This prevents warnings:
mmc0: host does not support reading read-only switch, assuming write-enable
Signed-off-by: Stefan Agner
---
arch/arm/boot/dts
The fixed 1.8V regulator is not used, and there is in fact no
fixed 1.8V regulator on the module. Remove it.
Signed-off-by: Stefan Agner
---
arch/arm/boot/dts/imx6qdl-apalis.dtsi | 8
arch/arm/boot/dts/imx6qdl-colibri.dtsi | 8
2 files changed, 16 deletions(-)
diff --git a
voltage (VAG) from this
supply. The new value should allow higher output swings before
clipping occurs. Refer to the SGTL5000 datasheet for details.
Signed-off-by: Stefan Agner
---
arch/arm/boot/dts/imx6qdl-apalis.dtsi | 22 +++---
arch/arm/boot/dts/imx6qdl-colibri.dtsi | 20
100/200MHz states for USDHC3 are not required since the SoC
does not support modes faster than DDR52 for the on board eMMC.
Signed-off-by: Stefan Agner
---
arch/arm/boot/dts/imx6qdl-apalis.dtsi | 34 --
arch/arm/boot/dts/imx6qdl-colibri.dtsi | 34
VDDD is connected to VGEN4 of the PF0100. This rail should only
run at 1.8V since there are multiple consumer and they all
expect the rail to be at 1.8V.
Signed-off-by: Stefan Agner
---
arch/arm/boot/dts/imx6qdl-apalis.dtsi | 3 ++-
arch/arm/boot/dts/imx6qdl-colibri.dtsi | 3 ++-
2 files
Add Apalis UART1 as default serial console.
Signed-off-by: Stefan Agner
---
arch/arm/boot/dts/imx6q-apalis-eval.dts | 4
arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts | 4
arch/arm/boot/dts/imx6q-apalis-ixora.dts | 4
3 files changed, 12 insertions(+)
diff --git a
Add the 3.3V main supply on the carrier board. Currently as a fixed
supply since not all consumer are modeled yet. This gets also rid of
some missing supply warnings.
Signed-off-by: Stefan Agner
---
arch/arm/boot/dts/imx6q-apalis-eval.dts | 12
1 file changed, 12 insertions
Use no-1-8-v device tree property to indicate that the board does
not support 1.8V signaling. The property voltage-ranges seems not
appropriate in our case since we do not have level shifters in
place.
Signed-off-by: Stefan Agner
---
arch/arm/boot/dts/imx6qdl-apalis.dtsi | 6 +++---
arch/arm
IRQ19 for ARM PMU counters
hw perfevents: /pmu: failed to register PMU devices!
armv7-pmu: probe of pmu failed with error -16
The driver is clearly not designed to be removed. Disable bind/
unbind for this driver.
Signed-off-by: Stefan Agner
---
arch/arm/kernel/perf_event_v7.c | 1 +
1 file
Hi Vinod, Hi Angelo,
On 05.07.2018 14:45, Angelo Dureghello wrote:
> Hi Vinod,
>
> On Thu, Jul 05, 2018 at 10:12:53AM +0200, Angelo Dureghello wrote:
>> Hi Vinod,
>>
>> On Thu, Jul 05, 2018 at 01:05:52PM +0530, Vinod wrote:
>> > On 04-07-18, 10:54, Krzysztof Kozlowski wrote:
>> > > Hi,
>> > >
>>
On 05.07.2018 14:45, Angelo Dureghello wrote:
> Hi Vinod,
>
> On Thu, Jul 05, 2018 at 10:12:53AM +0200, Angelo Dureghello wrote:
>> Hi Vinod,
>>
>> On Thu, Jul 05, 2018 at 01:05:52PM +0530, Vinod wrote:
>> > On 04-07-18, 10:54, Krzysztof Kozlowski wrote:
>> > > Hi,
>> > >
>> > > The commit 6ad0691
On 05.07.2018 15:09, Ulf Hansson wrote:
> On 5 July 2018 at 14:15, Stefan Agner wrote:
>> In the uSDHC case (e.g. i.MX 6) clocks only get disabled if frequency
>> is set to 0. However, it could be that the stack asks for a frequency
>> change while clocks are on. In that cas
On 05.07.2018 15:10, Ulf Hansson wrote:
> On 4 July 2018 at 17:07, Stefan Agner wrote:
>> If pinctrl nodes for 100/200MHz are missing, the controller should
>> not select any mode which need signal frequencies 100MHz or higher.
>> To prevent such speed modes the driver cur
not available. This prevents the stack from even trying to use
3.3V signaling and avoids the above warning.
Signed-off-by: Stefan Agner
---
drivers/mmc/host/sdhci.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
to make disable/enable clock look
alike.
Signed-off-by: Stefan Agner
---
drivers/mmc/host/sdhci-esdhc-imx.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
b/drivers/mmc/host/sdhci-esdhc-imx.c
index 85fd5a8b0b6d..aa48f4b2541a
On 05.07.2018 13:23, Ulf Hansson wrote:
> On 4 July 2018 at 17:07, Stefan Agner wrote:
>> If pinctrl nodes for 100/200MHz are missing, the controller should
>> not select any mode which need signal frequencies 100MHz or higher.
>> To prevent such speed modes the driver cur
to make disable/enable clock look
alike.
Signed-off-by: Stefan Agner
---
drivers/mmc/host/sdhci-esdhc-imx.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
b/drivers/mmc/host/sdhci-esdhc-imx.c
index 85fd5a8b0b6d..aa48f4b2541a
On 05.07.2018 11:48, Ulf Hansson wrote:
> On 4 July 2018 at 17:18, Stefan Agner wrote:
>> On 04.07.2018 17:07, Stefan Agner wrote:
>>> If pinctrl nodes for 100/200MHz are missing, the controller should
>>> not select any mode which need signal frequencies 100MHz or
On 05.07.2018 04:52, A.s. Dong wrote:
>> -Original Message-
>> From: Stefan Agner [mailto:ste...@agner.ch]
>> Sent: Thursday, June 28, 2018 4:13 PM
>> To: adrian.hun...@intel.com; ulf.hans...@linaro.org
>> Cc: Fabio Estevam ; Bough Chen
>> ; A.s. Dong ;
On 05.07.2018 04:40, A.s. Dong wrote:
>> -Original Message-
>> From: Stefan Agner [mailto:ste...@agner.ch]
>> Sent: Wednesday, July 4, 2018 11:08 PM
>> To: adrian.hun...@intel.com; ulf.hans...@linaro.org
>> Cc: Fabio Estevam ; Bough Chen
>> ; A.s. Do
On 04.07.2018 17:07, Stefan Agner wrote:
> If pinctrl nodes for 100/200MHz are missing, the controller should
> not select any mode which need signal frequencies 100MHz or higher.
> To prevent such speed modes the driver currently uses the quirk flag
> SDHCI_QUIRK2_NO_1_8_V. This work
faster pinctrl states are available:
# cat /sys/kernel/debug/mmc1/ios
...
timing spec:8 (mmc DDR52)
signal voltage: 1 (1.80 V)
...
Link: http://lkml.kernel.org/r/20180628081331.13051-1-ste...@agner.ch
Signed-off-by: Stefan Agner
---
drivers/mmc/host/sdhci-esdhc-imx.c | 21
On 04.07.2018 13:16, Ulf Hansson wrote:
> On 4 July 2018 at 12:55, Stefan Agner wrote:
>> On 04.07.2018 12:07, Ulf Hansson wrote:
>>> On 3 July 2018 at 10:48, Stefan Agner wrote:
>>>> On 02.07.2018 16:36, Ulf Hansson wrote:
>>>>> On 28 June 2018 at
et set. This is
> similar to the x86 solution from commit 162396309745 ("ftrace, x86:
> make kernel text writable only for conversions").
>
> Reported-by: Stefan Agner
> Tested-by: Stefan Agner
> Link: http://lkml.kernel.org/r/20180620212906.24b7b...@vmware.local.home
&g
On 04.07.2018 12:07, Ulf Hansson wrote:
> On 3 July 2018 at 10:48, Stefan Agner wrote:
>> On 02.07.2018 16:36, Ulf Hansson wrote:
>>> On 28 June 2018 at 10:13, Stefan Agner wrote:
>>>> Some hosts are capable of running higher speed modes but do not
>>>>
he stack asks for a chip select we currently do
not support.
Reported-by: Dan Carpenter
Signed-off-by: Stefan Agner
---
drivers/mtd/nand/raw/tegra_nand.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/raw/tegra_nand.c
b/drivers/mtd/nand/raw/tegra
Hi Thierry, Hi Miquel,
On 25.06.2018 14:34, Miquel Raynal wrote:
> Hi Stefan,
>
> On Sun, 24 Jun 2018 23:27:21 +0200, Stefan Agner
> wrote:
>
>> Eigth and hopefully final revision gets rid of nand_release() as
>> suggested by Boris.
>>
>> --
>&
On 02.07.2018 16:36, Ulf Hansson wrote:
> On 28 June 2018 at 10:13, Stefan Agner wrote:
>> Some hosts are capable of running higher speed modes but do not
>> have the board support for it. Introduce a quirk which prevents
>> the stack from using modes running at 100MHz or fa
x144/0x1d8)
> [<80900d48>] (kernel_init_freeable) from [<805ff6a8>]
> (kernel_init+0x10/0x114)
> [<805ff698>] (kernel_init) from [<80107be8>] (ret_from_fork+0x14/0x2c)
>
> Cc:
> Fixes: 5ee67b587a2b ("spi: dspi: clear SPI_SR before enable inter
DDR52)
signal voltage: 1 (1.80 V)
...
Signed-off-by: Stefan Agner
---
drivers/mmc/host/sdhci-esdhc-imx.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
b/drivers/mmc/host/sdhci-esdhc-imx.c
index 20a420b765b3..4a1c33018072 100644
--- a
Some hosts are capable of running higher speed modes but do not
have the board support for it. Introduce a quirk which prevents
the stack from using modes running at 100MHz or faster.
Signed-off-by: Stefan Agner
---
drivers/mmc/host/sdhci.c | 8
drivers/mmc/host/sdhci.h | 2 ++
2 files
The field support_vsel is currently only used in the device tree
case. Get rid of it. No change in behavior.
Signed-off-by: Stefan Agner
---
drivers/mmc/host/sdhci-esdhc-imx.c | 8 ++--
include/linux/platform_data/mmc-esdhc-imx.h | 2 --
2 files changed, 2 insertions(+), 8
board device trees which work around this by
not setting vqmmc-supply, e.g.
arch/arm/boot/dts/imx6qdl-sr-som-ti.dtsi.
Introducing a new quirk was the only way which I came up with,
but maybe there is a better way to prevent higher speed modes
while allowing 1.8V eMMC?
Stefan Agner (3):
mmc
care)
power mode: 2 (on)
bus width: 3 (8 bits)
timing spec:8 (mmc DDR52)
signal voltage: 0 (3.30 V)
driver type:0 (driver type B)
Signed-off-by: Stefan Agner
---
drivers/mmc/host/sdhci-esdhc-imx.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/driver
On 26.06.2018 12:26, Colin King wrote:
> From: Colin Ian King
>
> Trival fix of two spelling mistakes in dev_err error messages:
> "supportes" -> "supports" and "strenght" -> "strength"
Acked-by: Stefan Agner
>
> Signed-off-by
On 17.04.2018 10:11, Thierry Reding wrote:
> On Mon, Apr 16, 2018 at 08:21:09PM +0200, Stefan Agner wrote:
>> On 16.04.2018 18:08, Stephen Warren wrote:
>> > On 04/16/2018 09:56 AM, Stefan Agner wrote:
>> >> On 27.03.2018 14:16, Dmitry Osipenko wrote:
>> >>
On 25.06.2018 10:00, Marcel Ziswiler wrote:
> From: Marcel Ziswiler
>
> On ams AS3722, power on when AC OK is enabled by default.
> Making this option as disable by default and enable only
> when platform need this explicitly.
>
> Signed-off-by: Laxman Dewangan
> Reviewed-by: Bibek Basu
> Test
This enables the on-module ONFI conformant NAND flash.
Signed-off-by: Lucas Stach
Signed-off-by: Stefan Agner
---
arch/arm/boot/dts/tegra20-colibri-512.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
b/arch/arm/boot/dts
From: Lucas Stach
Add basic controller device tree node to be extended by
individual boards. Use the assigned-clocks mechanism to set
NDFLASH clock to a sensible default rate of 150MHz.
Signed-off-by: Lucas Stach
Signed-off-by: Stefan Agner
---
arch/arm/boot/dts/tegra20.dtsi | 15
Add Reed-Solomon (RS) to the enumeration of ECC algorithms.
Signed-off-by: Stefan Agner
Reviewed-by: Boris Brezillon
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/mtd/nand.txt | 2 +-
drivers/mtd/nand/raw/nand_base.c | 1 +
include/linux/mtd/rawnand.h
Allow to define a NAND chip as a boot device. This can be helpful
for the selection of the ECC algorithm and strength in case the boot
ROM supports only a subset of controller provided options.
Signed-off-by: Stefan Agner
Reviewed-by: Boris Brezillon
---
Documentation/devicetree/bindings/mtd
es support
Changes since v6:
- checkpatch.pl fixes
Changes since v7:
- Replace nand_release() with mtd_device_unregister() + nand_cleanup()
Lucas Stach (1):
ARM: dts: tegra: add Tegra20 NAND flash controller node
Stefan Agner (5):
mtd: rawnand: add Reed-Solomon error correction algorithm
mt
-by: Lucas Stach
Signed-off-by: Stefan Agner
Reviewed-by: Dmitry Osipenko
Reviewed-by: Boris Brezillon
---
MAINTAINERS |7 +
drivers/mtd/nand/raw/Kconfig | 10 +
drivers/mtd/nand/raw/Makefile |1 +
drivers/mtd/nand/raw/tegra_nand.c | 1
This adds the devicetree binding for the Tegra 2 NAND flash
controller.
Signed-off-by: Lucas Stach
Signed-off-by: Stefan Agner
Reviewed-by: Boris Brezillon
Reviewed-by: Rob Herring
---
.../bindings/mtd/nvidia-tegra20-nand.txt | 64 +++
1 file changed, 64 insertions
On 24.06.2018 21:50, Boris Brezillon wrote:
> On Sun, 24 Jun 2018 21:22:28 +0200
> Stefan Agner wrote:
>
>> +
>> +static int tegra_nand_remove(struct platform_device *pdev)
>> +{
>> +struct tegra_nand_controller *ctrl = platform_get_drvdata(pdev);
>>
This enables the on-module ONFI conformant NAND flash.
Signed-off-by: Lucas Stach
Signed-off-by: Stefan Agner
---
arch/arm/boot/dts/tegra20-colibri-512.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
b/arch/arm/boot/dts
Add Reed-Solomon (RS) to the enumeration of ECC algorithms.
Signed-off-by: Stefan Agner
Reviewed-by: Boris Brezillon
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/mtd/nand.txt | 2 +-
drivers/mtd/nand/raw/nand_base.c | 1 +
include/linux/mtd/rawnand.h
From: Lucas Stach
Add basic controller device tree node to be extended by
individual boards. Use the assigned-clocks mechanism to set
NDFLASH clock to a sensible default rate of 150MHz.
Signed-off-by: Lucas Stach
Signed-off-by: Stefan Agner
---
arch/arm/boot/dts/tegra20.dtsi | 15
This adds the devicetree binding for the Tegra 2 NAND flash
controller.
Signed-off-by: Lucas Stach
Signed-off-by: Stefan Agner
Reviewed-by: Boris Brezillon
Reviewed-by: Rob Herring
---
.../bindings/mtd/nvidia-tegra20-nand.txt | 64 +++
1 file changed, 64 insertions
-by: Lucas Stach
Signed-off-by: Stefan Agner
Reviewed-by: Dmitry Osipenko
---
MAINTAINERS |7 +
drivers/mtd/nand/raw/Kconfig | 10 +
drivers/mtd/nand/raw/Makefile |1 +
drivers/mtd/nand/raw/tegra_nand.c | 1223 +
4 files chan
Allow to define a NAND chip as a boot device. This can be helpful
for the selection of the ECC algorithm and strength in case the boot
ROM supports only a subset of controller provided options.
Signed-off-by: Stefan Agner
Reviewed-by: Boris Brezillon
---
Documentation/devicetree/bindings/mtd
variant of wait_for_completion_timeout
Changes since v5:
- Drop extra OOB bytes support
Changes since v6:
- checkpatch.pl fixes
Lucas Stach (1):
ARM: dts: tegra: add Tegra20 NAND flash controller node
Stefan Agner (5):
mtd: rawnand: add Reed-Solomon error correction algorithm
mtd: rawnand: add
This adds the devicetree binding for the Tegra 2 NAND flash
controller.
Signed-off-by: Lucas Stach
Signed-off-by: Stefan Agner
Reviewed-by: Boris Brezillon
Reviewed-by: Rob Herring
---
.../bindings/mtd/nvidia-tegra20-nand.txt | 64 +++
1 file changed, 64 insertions
ARM: dts: tegra: add Tegra20 NAND flash controller node
Stefan Agner (5):
mtd: rawnand: add Reed-Solomon error correction algorithm
mtd: rawnand: add an option to specify NAND chip as a boot device
mtd: rawnand: tegra: add devicetree binding
mtd: rawnand: add NVIDIA Tegra NAND Flash control
From: Lucas Stach
Add basic controller device tree node to be extended by
individual boards. Use the assigned-clocks mechanism to set
NDFLASH clock to a sensible default rate of 150MHz.
Signed-off-by: Lucas Stach
Signed-off-by: Stefan Agner
---
arch/arm/boot/dts/tegra20.dtsi | 15
-by: Lucas Stach
Signed-off-by: Stefan Agner
Reviewed-by: Dmitry Osipenko
---
MAINTAINERS |7 +
drivers/mtd/nand/raw/Kconfig |6 +
drivers/mtd/nand/raw/Makefile |1 +
drivers/mtd/nand/raw/tegra_nand.c | 1225 +
4 files chan
Add Reed-Solomon (RS) to the enumeration of ECC algorithms.
Signed-off-by: Stefan Agner
Reviewed-by: Boris Brezillon
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/mtd/nand.txt | 2 +-
drivers/mtd/nand/raw/nand_base.c | 1 +
include/linux/mtd/rawnand.h
This enables the on-module ONFI conformant NAND flash.
Signed-off-by: Lucas Stach
Signed-off-by: Stefan Agner
---
arch/arm/boot/dts/tegra20-colibri-512.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
b/arch/arm/boot/dts
Allow to define a NAND chip as a boot device. This can be helpful
for the selection of the ECC algorithm and strength in case the boot
ROM supports only a subset of controller provided options.
Signed-off-by: Stefan Agner
Reviewed-by: Boris Brezillon
---
Documentation/devicetree/bindings/mtd
be converted to read-only, and make the ftrace "before"
>> and "after" calls do nothing if that variable is not yet set. This is
>> similar to the x86 solution from commit 162396309745 ("ftrace, x86:
>> make kernel text writable only for conversions").
On 19.06.2018 04:12, Shawn Guo wrote:
> Hi Stefan,
>
> Can you take a look at the patch? Thanks.
>
> Shawn
>
> On Tue, Jun 05, 2018 at 10:43:26PM +0100, Suzuki K Poulose wrote:
>> Switch to the updated coresight bindings.
Looks good to me.
Reviewed-by: Stefan
Hi Boris,
On 18.06.2018 13:59, Boris Brezillon wrote:
> Hi Stefan,
>
> On Mon, 18 Jun 2018 12:51:52 +0200
> Stefan Agner wrote:
>
>> On 18.06.2018 11:58, Boris Brezillon wrote:
>> > On Sun, 17 Jun 2018 22:45:59 +0200
>> > Stefan Agner wrote:
>&
On 18.06.2018 11:58, Boris Brezillon wrote:
> On Sun, 17 Jun 2018 22:45:59 +0200
> Stefan Agner wrote:
>
>> Changes definitly calm down, most noteably probably the changes
>> around checking whether a page is empty if the stack reports ECC
>> errors.. I verified th
This enables the on-module ONFI conformant NAND flash.
Signed-off-by: Lucas Stach
Signed-off-by: Stefan Agner
---
arch/arm/boot/dts/tegra20-colibri-512.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
b/arch/arm/boot/dts
-by: Lucas Stach
Signed-off-by: Stefan Agner
Reviewed-by: Dmitry Osipenko
---
MAINTAINERS |7 +
drivers/mtd/nand/raw/Kconfig |6 +
drivers/mtd/nand/raw/Makefile |1 +
drivers/mtd/nand/raw/tegra_nand.c | 1268 +
4 files chan
From: Lucas Stach
Add basic controller device tree node to be extended by
individual boards. Use the assigned-clocks mechanism to set
NDFLASH clock to a sensible default rate of 150MHz.
Signed-off-by: Lucas Stach
Signed-off-by: Stefan Agner
---
arch/arm/boot/dts/tegra20.dtsi | 15
ARM: dts: tegra: add Tegra20 NAND flash controller node
Stefan Agner (5):
mtd: rawnand: add Reed-Solomon error correction algorithm
mtd: rawnand: add an option to specify NAND chip as a boot device
mtd: rawnand: tegra: add devicetree binding
mtd: rawnand: add NVIDIA Tegra NAND Flash
Allow to define a NAND chip as a boot device. This can be helpful
for the selection of the ECC algorithm and strength in case the boot
ROM supports only a subset of controller provided options.
Signed-off-by: Stefan Agner
Reviewed-by: Boris Brezillon
---
Documentation/devicetree/bindings/mtd
This adds the devicetree binding for the Tegra 2 NAND flash
controller.
Signed-off-by: Lucas Stach
Signed-off-by: Stefan Agner
Reviewed-by: Boris Brezillon
Reviewed-by: Rob Herring
---
.../bindings/mtd/nvidia-tegra20-nand.txt | 64 +++
1 file changed, 64 insertions
Add Reed-Solomon (RS) to the enumeration of ECC algorithms.
Signed-off-by: Stefan Agner
Reviewed-by: Boris Brezillon
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/mtd/nand.txt | 2 +-
drivers/mtd/nand/raw/nand_base.c | 1 +
include/linux/mtd/rawnand.h
On 12.06.2018 10:13, Boris Brezillon wrote:
> On Tue, 12 Jun 2018 10:02:12 +0200
> Stefan Agner wrote:
>
>> >> +static int tegra_nand_read_page_hwecc(struct mtd_info *mtd,
>> >> + struct nand_chip *chip,
>> >> +
MIXER_CTL'
[-Wenum-conversion]
for (i = AMIXER_PCM_F, j = SUM_IN_F; i <= AMIXER_PCM_S; i++, j++) {
~ ^~~~
Introduce enum CT_SUM_CTL k and it instead.
Signed-off-by: Stefan Agner
---
sound/pci/ctxfi/ctmixer.c | 15 ---
1 file cha
This fixes a warning seen with clang:
sound/pci/ice1712/prodigy_hifi.c:321:28: warning: variable 'wm_vol' is not
needed and will not be emitted [-Wunneeded-internal-declaration]
static const unsigned char wm_vol[256] = {
^
Signed-off-by: Stefan Agner
sion]
if (&priv->work)
~~ ~~~~~~^~~~
Signed-off-by: Stefan Agner
---
sound/soc/codecs/pcm1789.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/sound/soc/codecs/pcm1789.c b/sound/soc/codecs/pcm1789.c
index 21f15219b3ad..8df6447c76a6 100644
--- a/so
On 12.06.2018 17:24, Jens Axboe wrote:
> On 6/12/18 3:17 AM, Stefan Agner wrote:
>> [also added Jens Axboe]
>>
>> On 12.06.2018 10:27, Boris Brezillon wrote:
>>> On Tue, 12 Jun 2018 10:06:42 +0200
>>> Stefan Agner wrote:
>>>
>>>> On
On 12.06.2018 19:19, Guenter Roeck wrote:
> On Sun, Mar 25, 2018 at 08:09:57PM +0200, Stefan Agner wrote:
>> According to GCC documentation -m(no-)thumb-interwork is
>> meaningless in AAPCS configurations. Also clang does not
>
> It appears that this is only correct for r
On 07.06.2018 09:56, Uwe Kleine-König wrote:
> On Fri, Apr 20, 2018 at 02:44:07PM +0200, Stefan Agner wrote:
>> To reset the UART the SRST needs be cleared (low active). According
>> to the documentation the bit will remain active for 4 module clocks
>> until it is cleared (s
[also added Jens Axboe]
On 12.06.2018 10:27, Boris Brezillon wrote:
> On Tue, 12 Jun 2018 10:06:42 +0200
> Stefan Agner wrote:
>
>> On 12.06.2018 02:03, Dmitry Osipenko wrote:
>> > On Monday, 11 June 2018 23:52:22 MSK Stefan Agner wrote:
>> >> Add support fo
On 12.06.2018 02:03, Dmitry Osipenko wrote:
> On Monday, 11 June 2018 23:52:22 MSK Stefan Agner wrote:
>> Add support for the NAND flash controller found on NVIDIA
>> Tegra 2 SoCs. This implementation does not make use of the
>> command queue feature. Regular operations/data
On 12.06.2018 01:32, Dmitry Osipenko wrote:
> On Monday, 11 June 2018 23:52:22 MSK Stefan Agner wrote:
>> Add support for the NAND flash controller found on NVIDIA
>> Tegra 2 SoCs. This implementation does not make use of the
>> command queue feature. Regular operations/data
Allow to define a NAND chip as a boot device. This can be helpful
for the selection of the ECC algorithm and strength in case the boot
ROM supports only a subset of controller provided options.
Signed-off-by: Stefan Agner
Reviewed-by: Boris Brezillon
---
Documentation/devicetree/bindings/mtd
This adds the devicetree binding for the Tegra 2 NAND flash
controller.
Signed-off-by: Lucas Stach
Signed-off-by: Stefan Agner
Reviewed-by: Boris Brezillon
Reviewed-by: Rob Herring
---
.../bindings/mtd/nvidia-tegra20-nand.txt | 64 +++
1 file changed, 64 insertions
Signed-off-by: Stefan Agner
---
MAINTAINERS |7 +
drivers/mtd/nand/raw/Kconfig |6 +
drivers/mtd/nand/raw/Makefile |1 +
drivers/mtd/nand/raw/tegra_nand.c | 1248 +
4 files changed, 1262 insertions(+)
create mode 100644
This enables the on-module ONFI conformant NAND flash.
Signed-off-by: Lucas Stach
Signed-off-by: Stefan Agner
---
arch/arm/boot/dts/tegra20-colibri-512.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
b/arch/arm/boot/dts
Add Reed-Solomon (RS) to the enumeration of ECC algorithms.
Signed-off-by: Stefan Agner
Reviewed-by: Boris Brezillon
---
Documentation/devicetree/bindings/mtd/nand.txt | 2 +-
drivers/mtd/nand/raw/nand_base.c | 1 +
include/linux/mtd/rawnand.h| 1 +
3 files
From: Lucas Stach
Add basic controller device tree node to be extended by
individual boards. Use the assigned-clocks mechanism to set
NDFLASH clock to a sensible default rate of 150MHz.
Signed-off-by: Lucas Stach
Signed-off-by: Stefan Agner
---
arch/arm/boot/dts/tegra20.dtsi | 15
ty
- Clear interrupts and reinit wait queues in case command/DMA times out
- Set default MTD name after nand_set_flash_node
- Move MODULE_DEVICE_TABLE after declaration of tegra_nand_of_match
- Make (rs|bch)_strength static
Lucas Stach (1):
ARM: dts: tegra: add Tegra20 NAND flash controller node
Stefa
On 11.06.2018 14:42, Clément Péron wrote:
> Hi Stefan,
>
>
>> > +
>> > +#define EPITCR 0x00
>> > +#define EPITSR 0x04
>> > +#define EPITLR 0x08
>> > +#define EPITCMPR 0x0c
>> > +#define E
On 07.06.2018 16:05, Clément Péron wrote:
> From: Colin Didier
>
> Add driver for NXP's EPIT timer used in i.MX SoC.
>
> Signed-off-by: Colin Didier
> Signed-off-by: Clément Peron
> ---
> drivers/clocksource/Kconfig | 11 ++
> drivers/clocksource/Makefile | 1 +
> drivers/
On 09.06.2018 14:21, Dmitry Osipenko wrote:
> On Saturday, 9 June 2018 00:51:01 MSK Stefan Agner wrote:
>> On 01.06.2018 11:20, Dmitry Osipenko wrote:
>> > On 01.06.2018 01:16, Stefan Agner wrote:
>> >> Add support for the NAND flash controller found on N
On 09.06.2018 08:41, Boris Brezillon wrote:
> On Sat, 09 Jun 2018 08:23:51 +0200
> Stefan Agner wrote:
>
>> On 09.06.2018 07:52, Boris Brezillon wrote:
>> > On Fri, 08 Jun 2018 23:51:01 +0200
>> > Stefan Agner wrote:
>> >
>> >
>
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