On 09.06.2018 07:52, Boris Brezillon wrote:
> On Fri, 08 Jun 2018 23:51:01 +0200
> Stefan Agner wrote:
>
>
>> >
>> > void tegra_nand_controller_reset(struct tegra_nand_controller *ctrl)
>> > {
>> >int err;
>> >
>> >disabl
On 01.06.2018 11:20, Dmitry Osipenko wrote:
> On 01.06.2018 01:16, Stefan Agner wrote:
>> Add support for the NAND flash controller found on NVIDIA
>> Tegra 2 SoCs. This implementation does not make use of the
>> command queue feature. Regular operations/data transfers ar
o wrote:
>> > > On 01.06.2018 10:30, Boris Brezillon wrote:
>> > > > On Fri, 1 Jun 2018 00:16:34 +0200
>> > > > Stefan Agner wrote:
>> > > >
>> > > >> This adds the devicetree binding for the Tegra 2 N
On 05.06.2018 08:27, Masahiro Yamada wrote:
> 2018-06-05 14:50 GMT+09:00 Stefan Agner :
>> On 05.06.2018 02:07, Masahiro Yamada wrote:
>>> Hi Stefan
>>>
>>> 2018-06-05 6:49 GMT+09:00 Stefan Agner :
>>>> Hi Masahiro,
>>>>
>>>>
On 05.06.2018 02:07, Masahiro Yamada wrote:
> Hi Stefan
>
> 2018-06-05 6:49 GMT+09:00 Stefan Agner :
>> Hi Masahiro,
>>
>> On 28.05.2018 11:22, Masahiro Yamada wrote:
>>> This will be useful to specify the required compiler version,
>>> like this:
Hi Masahiro,
On 28.05.2018 11:22, Masahiro Yamada wrote:
> This will be useful to specify the required compiler version,
> like this:
>
> config FOO
> bool "Use Foo"
> depends on GCC_VERSION >= 40800
> help
> This feature requires GCC 4.8 or newer.
>
I tried us
Hi Randolph,
On 04.06.2018 19:16, Randolph Maaßen wrote:
> Am Freitag, den 01.06.2018, 00:16 +0200 schrieb Stefan Agner:
>> Add support for the NAND flash controller found on NVIDIA
>> Tegra 2 SoCs. This implementation does not make use of the
>> command queue feature. Re
On 01.06.2018 11:25, Boris Brezillon wrote:
> On Fri, 1 Jun 2018 09:26:00 +0200
> Boris Brezillon wrote:
>
>> On Fri, 1 Jun 2018 00:16:32 +0200
>> Stefan Agner wrote:
>>
>> > Add Reed-Solomon (RS) to the enumeration of ECC algorithms.
>> >
>&g
This adds the devicetree binding for the Tegra 2 NAND flash
controller.
Signed-off-by: Lucas Stach
Signed-off-by: Stefan Agner
---
.../bindings/mtd/nvidia-tegra20-nand.txt | 64 +++
1 file changed, 64 insertions(+)
create mode 100644
Documentation/devicetree/bindings/mtd
Allow to define a NAND chip as a boot device. This can be helpful
for the selection of the ECC algorithm and strength in case the boot
ROM supports only a subset of controller provided options.
Signed-off-by: Stefan Agner
---
Documentation/devicetree/bindings/mtd/nand.txt | 4
drivers/mtd
From: Lucas Stach
This enables the on-module ONFI conformant NAND flash.
Signed-off-by: Lucas Stach
Signed-off-by: Stefan Agner
---
arch/arm/boot/dts/tegra20-colibri-512.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
b
Add Reed-Solomon (RS) to the enumeration of ECC algorithms.
Signed-off-by: Stefan Agner
---
drivers/mtd/nand/raw/nand_base.c | 1 +
include/linux/mtd/rawnand.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index
ut
- Unify tegra_nand_(read|write)_page in tegra_nand_page_xfer
Lucas Stach (2):
ARM: dts: tegra: add Tegra20 NAND flash controller node
ARM: dts: tegra: enable NAND flash on Colibri T20
Stefan Agner (4):
mtd: rawnand: add Reed-Solomon error correction algorithm
mtd: rawnand: add an option to sp
From: Lucas Stach
Add basic controller device tree node to be extended by
individual boards. Use the assigned-clocks mechanism to set
NDFLASH clock to a sensible default rate of 150MHz.
Signed-off-by: Lucas Stach
Signed-off-by: Stefan Agner
---
arch/arm/boot/dts/tegra20.dtsi | 15
Signed-off-by: Stefan Agner
---
MAINTAINERS |7 +
drivers/mtd/nand/raw/Kconfig |6 +
drivers/mtd/nand/raw/Makefile |1 +
drivers/mtd/nand/raw/tegra_nand.c | 1143 +
4 files changed, 1157 insertions(+)
create mode 100644
On 31.05.2018 22:30, Boris Brezillon wrote:
> On Thu, 31 May 2018 19:54:08 +0200
> Stefan Agner wrote:
>
>> >> +
>> >> + mtd->dev.parent = &pdev->dev;
>> >> + mtd->name = "tegra_nand";
>> >
>> > I just figured
gt; On Tue, 22 May 2018 14:07:06 +0200, Stefan Agner
> wrote:
>
>> Add support for the NAND flash controller found on NVIDIA
>> Tegra 2 SoCs. This implementation does not make use of the
>> command queue feature. Regular operations/data transfers are
>> done in PIO m
On 31.05.2018 11:37, Stefan Agner wrote:
> On 27.05.2018 23:54, Stefan Agner wrote:
>> Add support for the NAND flash controller found on NVIDIA
>> Tegra 2 SoCs. This implementation does not make use of the
>> command queue feature. Regular operations/data transfers are
>
On 27.05.2018 23:54, Stefan Agner wrote:
> Add support for the NAND flash controller found on NVIDIA
> Tegra 2 SoCs. This implementation does not make use of the
> command queue feature. Regular operations/data transfers are
> done in PIO mode. Page read/writes with hardware ECC make
On 29.05.2018 09:48, Peter De Schrijver wrote:
> On Mon, May 28, 2018 at 05:53:08PM +0200, Stefan Agner wrote:
>> On 28.05.2018 09:55, Peter De Schrijver wrote:
>> > On Sun, May 27, 2018 at 11:54:40PM +0200, Stefan Agner wrote:
>> >> From: Lucas Stach
>> >&
On 28.05.2018 09:55, Peter De Schrijver wrote:
> On Sun, May 27, 2018 at 11:54:40PM +0200, Stefan Agner wrote:
>> From: Lucas Stach
>>
>> Set up the NAND Flash controller clock to run at 150MHz
>> instead of the rate set by the bootloader. This is a
>> conserv
On 28.05.2018 13:57, Dmitry Osipenko wrote:
> On 28.05.2018 00:54, Stefan Agner wrote:
>> Add support for the NAND flash controller found on NVIDIA
>> Tegra 2 SoCs. This implementation does not make use of the
>> command queue feature. Regular operations/data transfers ar
On 28.05.2018 00:19, Miquel Raynal wrote:
> Hi Stefan,
>
> A few more comments here.
>
> On Sun, 27 May 2018 23:54:39 +0200, Stefan Agner
> wrote:
>
>> Add support for the NAND flash controller found on NVIDIA
>> Tegra 2 SoCs. This implementation does not
nks for the work though!
> Miquèl
>
> On Tue, 22 May 2018 14:07:06 +0200, Stefan Agner
> wrote:
>
>> Add support for the NAND flash controller found on NVIDIA
>> Tegra 2 SoCs. This implementation does not make use of the
>> command queue feature. Regular oper
From: Lucas Stach
Set up the NAND Flash controller clock to run at 150MHz
instead of the rate set by the bootloader. This is a
conservative rate which also yields good performance.
Signed-off-by: Lucas Stach
Signed-off-by: Stefan Agner
---
drivers/clk/tegra/clk-tegra20.c | 1 +
1 file
From: Lucas Stach
Add basic controller description to be extended
by individual boards.
Signed-off-by: Lucas Stach
Signed-off-by: Stefan Agner
---
arch/arm/boot/dts/tegra20.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot
Signed-off-by: Stefan Agner
---
MAINTAINERS | 7 +
drivers/mtd/nand/raw/Kconfig | 6 +
drivers/mtd/nand/raw/Makefile | 1 +
drivers/mtd/nand/raw/tegra_nand.c | 999 ++
4 files changed, 1013 insertions(+)
create mode 100644 drivers
gra: add Tegra20 NAND flash controller node
ARM: tegra: enable NAND flash on Colibri T20
Stefan Agner (2):
mtd: rawnand: add Reed-Solomon error correction algorithm
mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver
.../bindings/mtd/nvidia,tegra20-nand.txt | 62 ++
MAINTAIN
From: Lucas Stach
This enables the on-module ONFI conformant NAND flash.
Signed-off-by: Lucas Stach
Signed-off-by: Stefan Agner
---
arch/arm/boot/dts/tegra20-colibri-512.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
b
From: Lucas Stach
This adds the devicetree binding for the Tegra 2 NAND flash
controller.
Signed-off-by: Lucas Stach
Signed-off-by: Stefan Agner
---
.../bindings/mtd/nvidia,tegra20-nand.txt | 62 +++
1 file changed, 62 insertions(+)
create mode 100644
Documentation
Add Reed-Solomon (RS) to the enumeration of ECC algorithms.
Signed-off-by: Stefan Agner
---
drivers/mtd/nand/raw/nand_base.c | 1 +
include/linux/mtd/rawnand.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index
>> > Miquel Raynal wrote:
>> >
>> > > Hi Stefan,
>> > >
>> > > On Thu, 24 May 2018 14:19:18 +0200, Stefan Agner
>> > > wrote:
>> > >
>> > > > On 24.05.2018 13:53, Boris Brezillon wrote:
>> &
On 24.05.2018 14:41, Boris Brezillon wrote:
> On Thu, 24 May 2018 14:23:56 +0200
> Boris Brezillon wrote:
>
>> On Thu, 24 May 2018 13:09:53 +0200
>> Stefan Agner wrote:
>>
>> > On 24.05.2018 10:56, Boris Brezillon wrote:
>> > > On Thu, 24 Ma
On 24.05.2018 13:53, Boris Brezillon wrote:
> Hi Benjamin,
>
> On Thu, 24 May 2018 13:30:14 +0200
> Benjamin Lindqvist wrote:
>
>> Hi Stefan,
>>
>> It seems to me that a probe similar to what the BootROM does shouldn't
>> be awfully complicated to implement - just cycle through the switch
>> cas
On 24.05.2018 10:56, Boris Brezillon wrote:
> On Thu, 24 May 2018 10:46:27 +0200
> Stefan Agner wrote:
>
>> Hi Boris,
>>
>> Thanks for the initial review! One small question below:
>>
>> On 23.05.2018 16:18, Boris Brezillon wrote:
>> > Hi Stef
On 24.05.2018 09:45, Benjamin Lindqvist wrote:
> Hi Stefan (and all),
>
> First off, I apoloigize in advance if I'm deviating from common
> kernel mailing list courtesy -- this is my first time responding.
> I just have a comment on the NAND driver that I'd like to bring
> to the public.
>
Welco
ny.dtb: Warning (unit_address_vs_reg):
> /memory: node has a reg or ranges property, but no unit name
>
> The DTB after the change is the same as before except adding
> unit-address to /memory node.
>
> Signed-off-by: Krzysztof Kozlowski
>
Looks good to me! Thanks!
R
ned-off-by: Krzysztof Kozlowski
That looks good!
Reviewed-by: Stefan Agner
Also works fine with full memory available on a 512MiB Colibri T20 using
downstream U-Boot 2016.11.
Tested-by: Stefan Agner
--
Stefan
>
> ---
>
> RFT:
> Not tested on 512 MB module as I have only th
Hi Boris,
Thanks for the initial review! One small question below:
On 23.05.2018 16:18, Boris Brezillon wrote:
> Hi Stefan,
>
> On Tue, 22 May 2018 14:07:06 +0200
> Stefan Agner wrote:
>> +
>> +struct tegra_nand {
>> +void __iomem *regs;
>> +struc
On 23.05.2018 11:56, Krzysztof Kozlowski wrote:
> Colibri-T20 can come in 256 MB RAM (with 512 MB NAND) or 512 MB RAM
> (with 1024 MB NAND) flavors. Both of them will use the same DTSI
> expecting the bootloader to do the fixup of /memory node. However in
> case it does not happen, let's stay on
On 23.05.2018 11:56, Krzysztof Kozlowski wrote:
> Add a generic /memory node in each Tegra DTSI (with empty reg property,
> to be overidden by each DTS) and set proper unit address for /memory
> nodes to fix the DTC warnings:
>
> arch/arm/boot/dts/tegra20-harmony.dtb: Warning (unit_address_vs_
yet... That makes the split indeed a bit less
appealing.
Anyway, now we have it, and I think it is still nice to have a separate
change.
Reviewed-by: Stefan Agner
--
Stefan
>
> ---
>
> Changes since v5:
> 1. New patch, split with skeleton.dtsi removal (suggested by Stefan).
that frequencies moved to the base device tree.
Also, add a comment that frequency selection is now handled in code,
e.g.:
"The valid frequencies for a particular SKU are now selected by the
cpufreq driver according to ratings stored in OTP fuses."
But the two device tree changes with the driver do what they should do
here, so:
Tested-by: Stefan Agner
Reviewed-by: Stefan Agner
--
Stefan
On 22.05.2018 08:28, Sébastien Szymanski wrote:
> Check the max speed supported from the fuses for i.MX6ULL and update the
> operating points table accordingly.
>
> Signed-off-by: Sébastien Szymanski
Tested with a 528MHz and 792MHz rated i.MX 6ULL, looks good!
Tested-by: Stefan Agn
On 23.05.2018 10:34, Krzysztof Kozlowski wrote:
> On Wed, May 23, 2018 at 10:22 AM, Stefan Agner wrote:
>> On 23.05.2018 09:05, Krzysztof Kozlowski wrote:
>>> On Thu, May 17, 2018 at 1:39 PM, Stefan Agner wrote:
>>>> On 17.05.2018 09:45, Krzysztof Kozlowsk
On 23.05.2018 09:05, Krzysztof Kozlowski wrote:
> On Thu, May 17, 2018 at 1:39 PM, Stefan Agner wrote:
>> On 17.05.2018 09:45, Krzysztof Kozlowski wrote:
>>> Remove the usage of skeleton.dtsi and add necessary properties to /memory
>>> node to fix the DTC warnings:
&g
On 18.05.2018 03:01, Anson Huang wrote:
> ENET "ipg" clock should be IMX7D_ENETx_IPG_ROOT_CLK
> rather than IMX7D_ENET_AXI_ROOT_CLK which is for ENET bus
> clock.
>
> Based on Andy Duan's patch from the NXP kernel tree.
>
> Signed-off-by: Anson Huang
R
Hi,
I do have some questions for some areas I wanted to improve in the next
revision. But I would like to make sure that the way I would like to
implement aligns with the MTD subsystem.
On 22.05.2018 14:07, Stefan Agner wrote:
> Add support for the NAND flash controller found on NVIDIA
> T
On 22.05.2018 15:34, Dmitry Osipenko wrote:
> On 22.05.2018 15:19, Stefan Agner wrote:
>> [review sent to my first patch sent off-ml, moving to ml thread]
>>
>> On 21.05.2018 16:05, Dmitry Osipenko wrote:
>>> Hello Stefan,
>>>
>>> I don't ha
, though I've couple
> minor
> comments.
>
> On 21.05.2018 03:16, Stefan Agner wrote:
>> Add support for the NAND flash controller found on NVIDIA
>> Tegra 2 SoCs. This implementation does not make use of the
>> command queue feature. Regular operations/data transfers
From: Lucas Stach
This enables the on-module ONFI conformant NAND flash.
Signed-off-by: Lucas Stach
Signed-off-by: Stefan Agner
---
arch/arm/boot/dts/tegra20-colibri-512.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
b/arch/arm
a20: init NDFLASH clock to sensible rate
ARM: tegra: add Tegra20 NAND flash controller node
ARM: tegra: enable NAND flash on Colibri T20
Stefan Agner (1):
mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver
.../bindings/mtd/nvidia,tegra20-nand.txt | 29 +
MAINTAIN
From: Lucas Stach
Add basic controller description to be extended
by individual boards.
Signed-off-by: Lucas Stach
Signed-off-by: Stefan Agner
---
arch/arm/boot/dts/tegra20.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot
From: Lucas Stach
This adds the devicetree binding for the Tegra 2 NAND flash
controller.
Signed-off-by: Lucas Stach
Signed-off-by: Stefan Agner
---
.../bindings/mtd/nvidia,tegra20-nand.txt | 29 +++
1 file changed, 29 insertions(+)
create mode 100644
Documentation
Signed-off-by: Stefan Agner
---
MAINTAINERS | 7 +
drivers/mtd/nand/raw/Kconfig | 6 +
drivers/mtd/nand/raw/Makefile | 1 +
drivers/mtd/nand/raw/tegra_nand.c | 915 ++
4 files changed, 929 insertions(+)
create mode 100644 drivers
From: Lucas Stach
Set up the NAND Flash controller clock to run at 150MHz
instead of the rate set by the bootloader. This is a
conservative rate which also yields good performance.
Signed-off-by: Lucas Stach
Signed-off-by: Stefan Agner
---
drivers/clk/tegra/clk-tegra20.c | 1 +
1 file
On 21.05.2018 04:35, Anson Huang wrote:
> Hi, Stefan
>
> Anson Huang
> Best Regards!
>
>
>> -Original Message-----
>> From: Stefan Agner [mailto:ste...@agner.ch]
>> Sent: Friday, May 18, 2018 9:02 PM
>> To: Anson Huang
>> Cc: shawn...@
On 18.05.2018 03:01, Anson Huang wrote:
> IMX7D_ENET_PHY_REF_ROOT_DIV supplies clock for PHY directly,
> there is no clock gate after it, rename it to
> IMX7D_ENET_PHY_REF_ROOT_CLK to avoid device tree change.
>
> Signed-off-by: Anson Huang
Reviewed-by: Stefan Ag
On 18.05.2018 03:01, Anson Huang wrote:
> Correct enet clock gates as below:
>
> CCGR6: IMX7D_ENET_AXI_ROOT_CLK (enet1 and enet2 bus clocks)
> CCGR112: IMX7D_ENET1_TIME_ROOT_CLK, IMX7D_ENET1_IPG_ROOT_CLK
> CCGR113: IMX7D_ENET2_TIME_ROOT_CLK, IMX7D_ENET2_IPG_ROOT_CLK
>
> Just rename unused IMX7D_E
On 17.05.2018 09:45, Krzysztof Kozlowski wrote:
> Colibri-T20 can come in 256 MB RAM (with 512 MB NAND) or 512 MB RAM
> (with 1024 MB NAND) flavors. Both of them will use the same DTSI
> expecting the bootloader to do the fixup of /memory node. However in
> case it does not happen, let's stay on
On 17.05.2018 09:45, Krzysztof Kozlowski wrote:
> Remove the usage of skeleton.dtsi and add necessary properties to /memory
> node to fix the DTC warnings:
>
> arch/arm/boot/dts/tegra20-harmony.dtb: Warning (unit_address_vs_reg):
> /memory: node has a reg or ranges property, but no uni
t;
> Signed-off-by: Krzysztof Kozlowski
Looks good!
Reviewed-by: Stefan Agner
>
> ---
>
> Changes since v4:
> 1. None
> ---
> arch/arm/boot/dts/tegra30-apalis.dtsi | 4 +---
> arch/arm/boot/dts/tegra30-beaver.dts | 3 ---
> arch/arm/boot/dts/tegra30-colibri.dtsi |
On 17.05.2018 10:40, Anson Huang wrote:
> Correct enet clock CCGR register offset.
>
> CCGR6: IMX7D_ENET_AXI_ROOT_CLK (enet1 and enet2 bus clocks)
> CCGR112: IMX7D_ENET1_TIME_ROOT_CLK, IMX7D_ENET1_IPG_ROOT_CLK
> CCGR113: IMX7D_ENET2_TIME_ROOT_CLK, IMX7D_ENET2_IPG_ROOT_CLK
>
> IMX7D_ENET_PHY_REF_R
use
> that ADC.
That seems sensible.
Acked-by: Stefan Agner
>
> Signed-off-by: Nikita Yushchenko
> ---
> arch/arm/boot/dts/vf610-zii-dev.dtsi | 4
> arch/arm/boot/dts/vfxxx.dtsi | 2 +-
> 2 files changed, 5 insertions(+), 1 deletion(-)
>
> diff --git
On 15.05.2018 16:41, Krzysztof Kozlowski wrote:
> Colibri-T20 can come in 256 MB RAM (with 512 MB NAND) or 512 MB RAM
> (with 1024 MB NAND) flavors. Both of them will use the same DTSI
> expecting the bootloader to do the fixup of /memory node. However in
> case it does not happen, let's stay on
On 09.05.2018 03:26, Jacky Bai wrote:
>> Subject: Re: [PATCH] clk: imx6ull: use OSC clock during AXI rate change
>>
>> Quoting Stefan Agner (2018-05-08 06:20:03)
>> > On 08.05.2018 09:32, Jacky Bai wrote:
>> > >
>> > > I have tried two 6ULL board,
return
in asm. There is no need for the unreachable() call.
GCC 7.2 generates identical object files before and after, other
than (for obvious reasons) the line numbers generated by
WANT_WARN_ON_SLOWPATH for all the WARN()s appearing later in the
file.
Suggested-by: Russell King
Signed-off-by: Stefan
t to IMX6UL_CLK_PLL3_USB_OTG. This only seems to appear since
>> >> commit 6f9575e55632 ("clk: imx: Add CLK_IS_CRITICAL flag for busy
>> >> divider and busy mux"), probably because the clock is now forced to
>> >> be on.
>> >>
&
On 08.05.2018 14:19, Robin Murphy wrote:
> On 08/05/18 12:32, Stefan Agner wrote:
>> Mixing asm and C code is not recommended in a naked function by
>> gcc and leads to an error when using clang:
>>drivers/bus/arm-cci.c:2107:2: error: non-ASM statement in naked
>>
return
in asm. There is no need for the unreachable() call.
Suggested-by: Russell King
Signed-off-by: Stefan Agner
Acked-by: Nicolas Pitre
---
drivers/bus/arm-cci.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/bus/arm-cci.c b/drivers/bus/arm-cci.c
index 443e4c3fd357..b8184a903583
On 03.05.2018 10:44, Satendra Singh Thakur wrote:
> To avoid duplicate logic for the same
How about:
Use drm_display_mode_to_videomode to avoid duplicate logic.
>
> Signed-off-by: Satendra Singh Thakur
> Cc: Madhur Verma
> Cc: Hemanshu Srivastava
> ---
> drivers/gpu/drm/fsl-dcu/fsl_dcu_drm
On 25.03.2018 20:09, Stefan Agner wrote:
> This patchset fixes some remaining issues when building the ARM
> architecture using LLVM/clang. The patchset requires the following
> kbuild change:
> https://lkml.org/lkml/2018/3/19/1756
>
> With that patch and this patchset
mux"), probably because the clock is
>> now forced to be on.
>>
>> Fixes: 6f9575e55632("clk: imx: Add CLK_IS_CRITICAL flag for busy divider and
>> busy mux")
>> Signed-off-by: Stefan Agner
>> ---
>> This addresses a regression ssen on v4.1
On 03.05.2018 17:08, Krzysztof Kozlowski wrote:
> Colibri-T20 can come in 256 MB RAM (with 512 MB NAND) or 512 MB RAM
> (with 1024 MB NAND) flavors. Add support for the 256 MB version on Iris
> evaluation board.
To we really need to specify memory size these days? I think all common
boot loaders
baudrate because the baud rate register got
restored before reset completed in imx_flush_buffer.
Fixes: 3a0ab62f43de ("serial: imx: implement shadow registers for UCRx and
UFCR")
Signed-off-by: Stefan Agner
Reviewed-by: Fabio Estevam
Reviewed-by: Uwe Kleine-König
---
Hi Greg,
Since
On 20.04.2018 13:15, Matthew Wilcox wrote:
> On Thu, Apr 19, 2018 at 11:42:04PM +0200, Stefan Agner wrote:
>> With PHYS_ADDR_MAX there is now a type safe variant for all
>> bits set. Make use of it.
>
> There is? I don't see it in linux-next.
The patch "mm/membloc
On 20.04.2018 08:03, Uwe Kleine-König wrote:
> Hello Stefan,
>
> On Thu, Apr 19, 2018 at 11:37:23PM +0200, Stefan Agner wrote:
>> On 16.04.2018 17:35, Stefan Agner wrote:
>> > To reset the UART the SRST needs be cleared (low active). According
>> > to the documen
With PHYS_ADDR_MAX there is now a type safe variant for all
bits set. Make use of it.
Patch created using a sematic patch as follows:
//
@@
typedef phys_addr_t;
@@
-(phys_addr_t)ULLONG_MAX
+PHYS_ADDR_MAX
//
Signed-off-by: Stefan Agner
---
arch/arm64/mm/init.c | 6 +++---
arch
Hi Uwe,
On 16.04.2018 17:35, Stefan Agner wrote:
> To reset the UART the SRST needs be cleared (low active). According
> to the documentation the bit will remain active for 4 module clocks
> until it is cleared (set to 1).
>
> Hence the real register need to be read in case the
SER_RS485_RX_DURING_TX flag).
Signed-off-by: Stefan Agner
---
drivers/tty/serial/imx.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
index 91f3a1a5cb7f..65d7a2bfb6d2 100644
--- a/drivers/tty/serial/imx.c
+++ b/drivers/tty/serial
On 18.04.2018 16:53, Uwe Kleine-König wrote:
> On Wed, Apr 18, 2018 at 04:06:38PM +0200, Stefan Agner wrote:
>> When using half-duplex mode (which disables receiver during txing)
>> the RTS signal cannot be driven low during transmission. This seems
>> to be a limitation of
: Stefan Agner
---
Changes since v1:
- Consistently check for sport->have_rtscts && !(rs485conf->flags &
SER_RS485_RTS_ON_SEND)
- Don't break printed message
drivers/tty/serial/imx.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/tty/serial/imx
: Stefan Agner
---
drivers/tty/serial/imx.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
index 91f3a1a5cb7f..1ba7e98ddc76 100644
--- a/drivers/tty/serial/imx.c
+++ b/drivers/tty/serial/imx.c
@@ -1833,6 +1833,10 @@ static int
According to the data sheet the 3rd choice is the bypass clock
of pll2. This should not have any effect in practice as this
selection is not used currently.
Signed-off-by: Stefan Agner
---
drivers/clk/imx/clk-imx6ul.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers
55632("clk: imx: Add CLK_IS_CRITICAL flag for busy divider and
busy mux")
Signed-off-by: Stefan Agner
---
This addresses a regression ssen on v4.17-rc1 where the kernel
boots during clock initialization, see also:
https://patchwork.kernel.org/patch/10295927/
drivers/clk/imx/clk-imx
On 16.04.2018 18:08, Stephen Warren wrote:
> On 04/16/2018 09:56 AM, Stefan Agner wrote:
>> On 27.03.2018 14:16, Dmitry Osipenko wrote:
>>> On 27.03.2018 14:54, Robin Murphy wrote:
>>>> On 26/03/18 22:20, Dmitry Osipenko wrote:
>>>>> On 25.03.2018 21:09
On 25.03.2018 20:09, Stefan Agner wrote:
> Mixing asm and C code is not recommended in a naked function by
> gcc and leads to an error when using clang:
> drivers/bus/arm-cci.c:2107:2: error: non-ASM statement in naked
> function is not supported
> unreachable();
>
On 27.03.2018 14:16, Dmitry Osipenko wrote:
> On 27.03.2018 14:54, Robin Murphy wrote:
>> On 26/03/18 22:20, Dmitry Osipenko wrote:
>>> On 25.03.2018 21:09, Stefan Agner wrote:
>>>> As documented in GCC naked functions should only use Basic asm
>>>> syntax
baudrate because the baud rate register got
restored before reset completed in imx_flush_buffer.
Fixes: 3a0ab62f43de ("serial: imx: implement shadow registers for UCRx and
UFCR")
Signed-off-by: Stefan Agner
---
drivers/tty/serial/imx.c | 2 +-
1 file changed, 1 insertion(+), 1 deletio
Han,
On 15.03.2018 16:39, Stefan Agner wrote:
> On March 15, 2018 4:36:20 PM GMT+01:00, Boris Brezillon
> wrote:
>>Hi,
>>
>>On Sun, 4 Mar 2018 21:06:01 +0100
>>Stefan Agner wrote:
>>
>>> Add support for specified ECC strength/size using device t
ggested-by: Linus Torvalds
Signed-off-by: Stefan Agner
---
Hi,
There are about a dozen other instances of (phys_addr_t)ULLONG_MAX
accross the tree. Should I address them too?
--
Stefan
include/linux/kernel.h | 1 +
mm/memblock.c | 22 +++---
2 files changed, 12 inserti
a agrees to the change, do you want me to
send a non-RFC version or can you merge the patch as is?
--
Stefan
>
> -Raveendra
>
> On Sat, Mar 24, 2018 at 4:32 PM, Stefan Agner wrote:
>> In the AES cases enum spu_cipher_type and enum hash_type have
>> the same values, so
On 25.03.2018 20:14, Nicolas Pitre wrote:
> On Sun, 25 Mar 2018, Stefan Agner wrote:
>
>> Mixing asm and C code is not recommended in a naked function by
>> gcc and leads to an error when using clang:
>> drivers/bus/arm-cci.c:2107:2: error: non-ASM statement in na
4.16-rc5 using clang
5.0.1 and 6.0.0.
This version also adds a patch to mitigate a often printed warning
about duplicate 'const' declaration specifier when using get_user().
Stefan Agner (6):
bus: arm-cci: use asm unreachable
efi/libstub/arm: add support for building with c
According to GCC documentation -m(no-)thumb-interwork is
meaningless in AAPCS configurations. Also clang does not
support the flag:
clang-5.0: error: unknown argument: '-mno-thumb-interwork'
Just drop -mno-thumb-interwork in AEABI configuration.
Signed-off-by: Stefan Agner
---
e a regular function to be more portable. This aligns also with
the other smc call implementations e.g. in qcom_scm-32.c and
bcm_kona_smc.c.
Cc: Dmitry Osipenko
Cc: Stephen Warren
Cc: Thierry Reding
Signed-off-by: Stefan Agner
---
Changes in v2:
- Keep stmfd/ldmfd to avoid potential ABI issues
Use cc-options call for -mno-single-pic-base since the option is
not available in clang. LLVM/clang always assumes a fixed
displacement between text/data and hence uses PC relative
addressing.
Signed-off-by: Stefan Agner
---
drivers/firmware/efi/libstub/Makefile | 3 ++-
1 file changed, 2
Use cc-options call for compiler options which are not available
in clang. With this patch an ARMv7 multi platform kernel can be
successfully build using clang (tested with version 5.0.1).
Based-on-patches-by: Behan Webster
Signed-off-by: Stefan Agner
---
Changes in v2:
- Drop cc-options in
return
in asm. There is no need for the unreachable() call.
Suggested-by: Russell King
Signed-off-by: Stefan Agner
---
Changes in v2:
- Don't add assembly ASM_UNREACHABLE, just drop unreachable()
drivers/bus/arm-cci.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/bus/arm-cc
e generated code was exactly the same.
Signed-off-by: Stefan Agner
---
Similar issue has already been discussed here:
https://patchwork.kernel.org/patch/9693821/
arch/arm/include/asm/uaccess.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/uaccess.h b
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