Some edp screen do not have hpd signal, so we can't just return
failed when hpd plug in detect failed.
This is an hardware property, so we need add a devicetree property
"analogix,need-force-hpd" to indicate this sutiation.
Signed-off-by: Yakir Yang
---
Changes in v5: None
Chan
There are some IP limit on rk3288 that only support 4 physical lanes
of 2.7/1.6 Gbps/lane, so seprate them out by device_type flag.
Signed-off-by: Yakir Yang
---
Changes in v5: None
Changes in v4:
- Seprate the link-rate and lane-count limit out with the device_type
flag. (Thierry)
Changes in
RK3288 need some special registers setting, we can separate
them out by the dev_type of plat_data.
Signed-off-by: Yakir Yang
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- Fix compile failed dut to phy_pd_addr variable misspell error
drivers/gpu/drm/bridge
: Yakir Yang
---
Changes in v5:
- Switch video timing type to "u32", so driver could use "of_property_read_u32"
to get the backword timing values. Krzysztof suggest me that driver could use
the "of_property_read_bool" to get backword timing values, but that interfa
From: Mark Yao
Add bpc and color mode setting in rockchip_drm_vop driver, so
connector could try to use the edid drm_display_info to config
vop output mode.
Signed-off-by: Mark Yao
Signed-off-by: Yakir Yang
---
Changes in v5:
- Fix compiled error (Heiko)
- Using the connector display info
;;
clock-names = "24m";
#phy-cells = <0>;
};
Signed-off-by: Yakir Yang
---
Changes in v5:
- Split binding doc's from driver changes. (Rob)
- Update the rockchip,grf explain in document, and correct the clock required
elemets in documen
Rockchip DP driver is a helper driver of analogix_dp coder driver,
so most of the DT property should be descriped in analogix_dp document.
Signed-off-by: Yakir Yang
---
Changes in v5:
- Split binding doc's from driver changes. (Rob)
- Add eDP hotplug pinctrl property. (Heiko)
Changes
This phy driver would control the Rockchip DisplayPort module
phy clock and phy power, it is relate to analogix_dp-rockchip
dp driver. If you want DP works rightly on rockchip platform,
then you should select both of them.
Signed-off-by: Yakir Yang
---
Changes in v5:
- Remove "reg" D
Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.
Signed-off-by: Yakir Yang
---
Changes in v5:
- Remove the empty line at the end of document, and correct the endpoint
numbers in the example
compatibility is fully preserved, so there are no
bisectability break that make this change in a separate patch.
Signed-off-by: Yakir Yang
---
Changes in v5:
- Correct the misspell in commit message. (Krzysztof)
Changes in v4:
- Separate all DTS changes to a separate patch. (Krzysztof)
Changes in v3
Analogix dp driver is split from exynos dp driver, so we just
make an copy of exynos_dp.txt, and then simplify exynos_dp.txt
Beside update some exynos dtsi file with the latest change
according to the devicetree binding documents.
Signed-off-by: Yakir Yang
---
Changes in v5: None
Changes in v4
2Gbps, 2.7Gbps, 5.4Gbps}.
Signed-off-by: Yakir Yang
---
Changes in v5: None
Changes in v4:
- Update commit message more readable. (Jingoo)
- Adjust the order from 05 to 04
Changes in v3:
- The link_rate and lane_count shouldn't config to the DT property value
directly, but we can take those a
Fix some obvious alignment problems, like alignment and line
over 80 characters problems, make this easy to be maintained
later.
Signed-off-by: Yakir Yang
---
Changes in v5:
- Resequence this patch after analogix_dp driver have been split
from exynos_dp code, and rephrase reasonable commit
In order to move exynos dp code to bridge directory,
we need to convert driver drm bridge mode first. As
dp driver already have a ptn3460 bridge, so we need
to move ptn bridge to the next bridge of dp bridge.
Signed-off-by: Yakir Yang
---
Changes in v5: None
Changes in v4: None
Changes in v3
rt
Changes in v2:
- Keep author name list no changed (Jingoo)
- Remove new copyright (Jingoo)
- Fix compiled failed due to analogix_dp_device misspell
- Improved commit message more readable, and avoid using some
uncommon style like bellow: (Joe Preches)
- retval = exynos_dp_read_bytes_from_i
Hi Thierry,
Thanks for your suggest :)
On 09/21/2015 05:15 PM, Thierry Reding wrote:
On Mon, Sep 21, 2015 at 04:45:44PM +0800, Yakir Yang wrote:
Hi Heiko,
On 09/02/2015 10:15 AM, Yakir Yang wrote:
Hi Heiko,
在 09/02/2015 05:47 AM, Heiko Stuebner 写道:
Hi Yakir,
Am Dienstag, 1. September
Hi Krzysztof,
在 09/07/2015 08:22 AM, Krzysztof Kozlowski 写道:
On 06.09.2015 16:49, Yakir Yang wrote:
Hi Krzysztof,
在 09/04/2015 08:41 AM, Krzysztof Kozlowski 写道:
On 03.09.2015 14:30, Yakir Yang wrote:
Hi Krzysztof,
在 09/03/2015 08:58 AM, Krzysztof Kozlowski 写道:
On 01.09.2015 14:49, Yakir
Hi Krzysztof,
在 09/07/2015 07:55 AM, Krzysztof Kozlowski 写道:
On 06.09.2015 13:07, Yakir Yang wrote:
Hi Krzysztof,
在 09/04/2015 08:36 AM, Krzysztof Kozlowski 写道:
On 01.09.2015 15:07, Yakir Yang wrote:
Empty commit message. Please explain here why you want to add platform
device type support
Hi Rob,
在 09/05/2015 05:46 AM, Rob Herring 写道:
On Wed, Sep 2, 2015 at 11:27 PM, Yakir Yang wrote:
Hi Rob,
在 09/03/2015 04:17 AM, Rob Herring 写道:
On Tue, Sep 1, 2015 at 1:14 AM, Yakir Yang wrote:
Some edp screen do not have hpd signal, so we can't just return
failed when hpd plug in d
Hi Krzysztof,
在 09/04/2015 08:41 AM, Krzysztof Kozlowski 写道:
On 03.09.2015 14:30, Yakir Yang wrote:
Hi Krzysztof,
在 09/03/2015 08:58 AM, Krzysztof Kozlowski 写道:
On 01.09.2015 14:49, Yakir Yang wrote:
Split the dp core driver from exynos directory to bridge
directory, and rename the core
Hi Krzysztof,
在 09/04/2015 08:36 AM, Krzysztof Kozlowski 写道:
On 01.09.2015 15:07, Yakir Yang wrote:
Empty commit message. Please explain here why you want to add platform
device type support.
Actually the title is confusing. You are not adding support for platform
device types but rather
Hi Thierry,
在 09/03/2015 04:38 PM, Thierry Reding 写道:
On Wed, Sep 02, 2015 at 06:02:25PM +0800, Yakir Yang wrote:
在 2015/9/2 16:34, Thierry Reding 写道:
[...]
At the very least your code must compile when applied against a recent
upstream tree. I would also expect you to make sure the code
Hi Krzysztof,
在 09/03/2015 04:04 PM, Krzysztof Kozlowski 写道:
On 01.09.2015 14:55, Yakir Yang wrote:
Both hsync/vsync polarity and interlace mode can be parsed from
drm display mode, and dynamic_range and ycbcr_coeff can be judge
by the video code, same to color space and color depth can be
Hi Joe,
在 09/03/2015 01:57 PM, Joe Perches 写道:
On Thu, 2015-09-03 at 13:33 +0800, Yakir Yang wrote:
[]
diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c
[]
@@ -155,24 +156,22 @@ static int exynos_dp_read_edid(struct
exynos_dp_device *dp
Hi Krzysztof,
在 09/03/2015 01:08 PM, Krzysztof Kozlowski 写道:
On 03.09.2015 14:04, Yakir Yang wrote:
Hi Krzysztof,
在 09/03/2015 08:21 AM, Krzysztof Kozlowski 写道:
On 01.09.2015 14:46, Yakir Yang wrote:
After run "checkpatch.pl -f --subjective" command, I see there
are lots of
Hi Krzysztof,
在 09/03/2015 08:58 AM, Krzysztof Kozlowski 写道:
On 01.09.2015 14:49, Yakir Yang wrote:
Split the dp core driver from exynos directory to bridge
directory, and rename the core driver to analogix_dp_*,
leave the platform code to analogix_dp-exynos.
Signed-off-by: Yakir Yang
Hi Krzysztof,
在 09/03/2015 08:21 AM, Krzysztof Kozlowski 写道:
On 01.09.2015 14:46, Yakir Yang wrote:
After run "checkpatch.pl -f --subjective" command, I see there
are lots of alignment problem in exynos_dp driver, so let just
fix them.
Hi,
Warnings from checkpatch are not a re
Hi Rob,
在 09/03/2015 04:17 AM, Rob Herring 写道:
On Tue, Sep 1, 2015 at 1:14 AM, Yakir Yang wrote:
Some edp screen do not have hpd signal, so we can't just return
failed when hpd plug in detect failed.
This is a property of the panel (or connector perhaps), so this
property should be lo
Hi Emil,
在 09/02/2015 10:50 PM, Emil Velikov 写道:
[Dropping the CC list]
Hmm...Don't understand what this means. If you can explain, that
would be better, so I would not miss your suggest. :-)
Hi Yakir Yang,
On 1 September 2015 at 06:49, Yakir Yang wrote:
Split the dp core driver
Hi Rob,
在 09/02/2015 09:27 PM, Rob Herring 写道:
On Tue, Sep 1, 2015 at 1:04 AM, Yakir Yang wrote:
This phy driver would control the Rockchip DisplayPort module
phy clock and phy power, it is relate to analogix_dp-rockchip
dp driver. If you want DP works rightly on rockchip platform,
then you
Thierry,
在 2015/9/2 16:34, Thierry Reding 写道:
On Wed, Sep 02, 2015 at 10:06:36AM +0800, Yakir Yang wrote:
在 09/02/2015 05:00 AM, Heiko Stuebner 写道:
Am Dienstag, 1. September 2015, 14:01:48 schrieb Yakir Yang:
[...]
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
b/drivers/gpu/drm
Hi Heiko,
在 09/02/2015 05:47 AM, Heiko Stuebner 写道:
Hi Yakir,
Am Dienstag, 1. September 2015, 13:46:11 schrieb Yakir Yang:
The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
share the same IP, so a lot of parts can be re-used. I split the common
code into bridge
Hi Heiko,
在 09/02/2015 05:00 AM, Heiko Stuebner 写道:
Hi Yakir,
Am Dienstag, 1. September 2015, 14:01:48 schrieb Yakir Yang:
From: Mark Yao
Add bpc and color mode setting in rockchip_drm_vop driver, so
connector could try to use the edid drm_display_info to config
vop output mode.
Signed-off
Hi Heiko,
在 09/02/2015 05:00 AM, Heiko Stuebner 写道:
Hi Yakir,
Am Dienstag, 1. September 2015, 14:01:28 schrieb Yakir Yang:
Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.
Signed-off-by
Hi Heiko,
在 09/02/2015 04:58 AM, Heiko Stuebner 写道:
Hi Yakir,
small nit more below
Am Dienstag, 1. September 2015, 18:51:16 schrieb Heiko Stuebner:
Am Dienstag, 1. September 2015, 14:04:15 schrieb Yakir Yang:
+- clocks: from common clock binding: handle to dp clock.
+ of memory mapped
Heiko,
在 09/02/2015 04:46 AM, Heiko Stuebner 写道:
Am Dienstag, 1. September 2015, 13:49:58 schrieb Yakir Yang:
Split the dp core driver from exynos directory to bridge
directory, and rename the core driver to analogix_dp_*,
leave the platform code to analogix_dp-exynos.
Signed-off-by: Yakir
Hi Heiko,
在 09/02/2015 12:51 AM, Heiko Stuebner 写道:
Am Dienstag, 1. September 2015, 14:04:15 schrieb Yakir Yang:
This phy driver would control the Rockchip DisplayPort module
phy clock and phy power, it is relate to analogix_dp-rockchip
dp driver. If you want DP works rightly on rockchip
Hi Heiko,
在 2015/9/1 22:24, Heiko Stuebner 写道:
Am Dienstag, 1. September 2015, 14:01:28 schrieb Yakir Yang:
Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.
Signed-off-by: Yakir Yang
Display Port monitor could support kinds of mode which indicate
in monitor edid, not just one single display resolution which
defined in panel or devivetree property display timing.
Signed-off-by: Yakir Yang
---
Changes in v4:
- Call drm_panel_prepare() in .get_modes function, ensure panel
This change just make a little clean to make code more like
drm core expect, move hdp detect code from bridge->enable(),
and place them into connector->detect().
Signed-off-by: Yakir Yang
---
Changes in v4:
- Take Jingoo suggest, add commit messages.
Changes in v3:
- move dp hpd det
Some edp screen do not have hpd signal, so we can't just return
failed when hpd plug in detect failed.
This is an hardware property, so we need add a devicetree property
"analogix,need-force-hpd" to indicate this sutiation.
Signed-off-by: Yakir Yang
---
Changes in v4: None
Chang
There are some IP limit on rk3288 that only support 4 physical lanes
of 2.7/1.6 Gbps/lane, so seprate them out by device_type flag.
Signed-off-by: Yakir Yang
---
Changes in v4:
- Take Thierry suggest, seprate the link-rate and lane-count limit
out with the device_type flag.
Changes in v3
RK3288 need some special registers setting, we can separate
them out by the dev_type of plat_data.
Signed-off-by: Yakir Yang
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- Fix compile failed dut to phy_pd_addr variable misspell error
drivers/gpu/drm/bridge/analogix
Signed-off-by: Yakir Yang
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- Add GNU license v2 declared and samsung copyright
drivers/gpu/drm/exynos/exynos_dp.c | 1 +
drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 1 +
include/drm/bridge/analogix_dp.h
This phy driver would control the Rockchip DisplayPort module
phy clock and phy power, it is relate to analogix_dp-rockchip
dp driver. If you want DP works rightly on rockchip platform,
then you should select both of them.
Signed-off-by: Yakir Yang
---
Changes in v4:
- Take Kishon suggest, add
From: Mark Yao
Add bpc and color mode setting in rockchip_drm_vop driver, so
connector could try to use the edid drm_display_info to config
vop output mode.
Signed-off-by: Mark Yao
Signed-off-by: Yakir Yang
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/gpu/drm
Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.
Signed-off-by: Yakir Yang
---
Changes in v4:
- Remove some deprecated DT properties in rockchip dp document.
Changes in v3:
- Take Thierry
Analogix dp driver is split from exynos dp driver, so we just
make an copy of exynos_dp.txt, and then simplify exynos_dp.txt
Beside update some exynos dtsi file with the latest change
according to the devicetree binding documents.
Signed-off-by: Yakir Yang
---
Changes in v4:
- Take Krzysztof
provide the backward compatibility, so there are no
bisectability break that make this change in a separate patch.
Signed-off-by: Yakir Yang
---
Changes in v4:
- Take Krzysztof suggest, separate all DTS changes to a separate patch.
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts
() in to achieve the compatibility hacks.
Signed-off-by: Yakir Yang
---
Changes in v4:
- Take Krzysztof suggest, provide backword compatibility with samsung.
- Take Thierry suggest, add "color-depth" and "color-space" dynamic parsed.
Changes in v3:
- Take Thierry Reding su
2Gbps, 2.7Gbps, 5.4Gbps}.
Signed-off-by: Yakir Yang
---
Changes in v4:
- Take Jingoo Han suggest, update commit message more readable.
- Adjust the order from 05 to 04
Changes in v3:
- Take Thierry Reding suggest, link_rate and lane_count shouldn't config to
the DT property value directly,
In order to move exynos dp code to bridge directory,
we need to convert driver drm bridge mode first. As
dp driver already have a ptn3460 bridge, so we need
to move ptn bridge to the next bridge of dp bridge.
Signed-off-by: Yakir Yang
---
Changes in v4:
- Take Romain suggest, rebase on linux
After run "checkpatch.pl -f --subjective" command, I see there
are lots of alignment problem in exynos_dp driver, so let just
fix them.
- Take Romain suggest, rebase on linux-next branch
Signed-off-by: Yakir Yang
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- Take J
node with remote-endpoint method,
and create devicetree binding for driver.
- Remove the clock enable/disbale with "sclk_edp" & "sclk_edp_24m",
leave those clock to rockchip dp phy driver.
- Add GNU license v2 declared and samsung copyright
- Fix compile failed dut
/next/linux-next.git when I'm preparing v4 series.
Thanks,
- Yakir
Regards,
Romain
2015-08-21 15:16 GMT+02:00 Thierry Reding :
On Fri, Aug 21, 2015 at 08:24:16PM +0900, Jingoo Han wrote:
On 2015. 8. 21., at PM 7:01, Yakir Yang wrote:
Hi Jingoo,
在 2015/8/21 16:20, Jingoo Han 写道:
On 2015.
Hi Thierry,
在 2015/8/25 22:16, Thierry Reding 写道:
On Tue, Aug 25, 2015 at 09:48:01PM +0800, Yakir Yang wrote:
Hi Thierry & Rob,
在 2015/8/25 21:27, Rob Herring 写道:
On Tue, Aug 25, 2015 at 4:15 AM, Thierry Reding wrote:
On Sun, Aug 23, 2015 at 06:23:14PM -0500, Rob Herring wrote:
On
Hi Thierry,
在 2015/8/25 17:58, Thierry Reding 写道:
On Wed, Aug 19, 2015 at 09:50:34AM -0500, Yakir Yang wrote:
[...]
+ -analogix,color-space:
+ input video data format.
+ COLOR_RGB = 0, COLOR_YCBCR422 = 1, COLOR_YCBCR444 = 2
I don't think DT
Hi Thierry,
在 2015/8/25 18:06, Thierry Reding 写道:
On Tue, Aug 25, 2015 at 05:41:19PM +0800, Yakir Yang wrote:
Hi Thierry,
在 2015/8/25 17:12, Thierry Reding 写道:
On Mon, Aug 24, 2015 at 09:48:27AM -0500, Rob Herring wrote:
On Mon, Aug 24, 2015 at 7:57 AM, Russell King - ARM Linux
wrote:
On
Hi Thierry,
在 2015/8/25 17:12, Thierry Reding 写道:
On Mon, Aug 24, 2015 at 09:48:27AM -0500, Rob Herring wrote:
On Mon, Aug 24, 2015 at 7:57 AM, Russell King - ARM Linux
wrote:
On Sun, Aug 23, 2015 at 06:23:14PM -0500, Rob Herring wrote:
On Wed, Aug 19, 2015 at 9:50 AM, Yakir Yang wrote
Hi Thierry,
在 2015/8/25 17:15, Thierry Reding 写道:
On Sun, Aug 23, 2015 at 06:23:14PM -0500, Rob Herring wrote:
On Wed, Aug 19, 2015 at 9:50 AM, Yakir Yang wrote:
[...]
+ -analogix,link-rate:
+ max link rate supported by the eDP controller
Hi Heiko,
在 2015/8/24 21:03, Heiko Stuebner 写道:
Hi Yakir,
Am Montag, 24. August 2015, 20:48:01 schrieb Yakir Yang:
在 08/24/2015 12:20 PM, Krzysztof Kozlowski 写道:
On 24.08.2015 11:42, Yakir Yang wrote:
Hi Krzysztof,
在 08/23/2015 07:43 PM, Krzysztof Kozlowski 写道:
2015-08-24 8:23 GMT+09:00
Hi Krzysztof,
在 2015/8/25 7:49, Krzysztof Kozlowski 写道:
On 24.08.2015 21:48, Yakir Yang wrote:
Hi Krzysztof,
在 08/24/2015 12:20 PM, Krzysztof Kozlowski 写道:
On 24.08.2015 11:42, Yakir Yang wrote:
Hi Krzysztof,
在 08/23/2015 07:43 PM, Krzysztof Kozlowski 写道:
2015-08-24 8:23 GMT+09:00 Rob
在 2015/8/24 22:48, Rob Herring 写道:
On Mon, Aug 24, 2015 at 7:57 AM, Russell King - ARM Linux
wrote:
On Sun, Aug 23, 2015 at 06:23:14PM -0500, Rob Herring wrote:
On Wed, Aug 19, 2015 at 9:50 AM, Yakir Yang wrote:
+ -analogix,color-depth:
+ number of bits per colour
Hi Jingoo,
在 08/24/2015 03:40 PM, Jingoo Han 写道:
On 2015. 8. 24., at AM 9:43, Krzysztof Kozlowski
wrote:
2015-08-24 8:23 GMT+09:00 Rob Herring :
On Wed, Aug 19, 2015 at 9:50 AM, Yakir Yang wrote:
Analogix dp driver is split from exynos dp driver, so we just
make an copy of exynos_dp.txt
Hi Krzysztof,
在 08/24/2015 12:20 PM, Krzysztof Kozlowski 写道:
On 24.08.2015 11:42, Yakir Yang wrote:
Hi Krzysztof,
在 08/23/2015 07:43 PM, Krzysztof Kozlowski 写道:
2015-08-24 8:23 GMT+09:00 Rob Herring :
On Wed, Aug 19, 2015 at 9:50 AM, Yakir Yang wrote:
Analogix dp driver is split from
Hi Krzysztof,
在 08/23/2015 07:43 PM, Krzysztof Kozlowski 写道:
2015-08-24 8:23 GMT+09:00 Rob Herring :
On Wed, Aug 19, 2015 at 9:50 AM, Yakir Yang wrote:
Analogix dp driver is split from exynos dp driver, so we just
make an copy of exynos_dp.txt, and then simplify exynos_dp.txt
Beside update
Hi Rob,
在 08/23/2015 06:23 PM, Rob Herring 写道:
On Wed, Aug 19, 2015 at 9:50 AM, Yakir Yang wrote:
Analogix dp driver is split from exynos dp driver, so we just
make an copy of exynos_dp.txt, and then simplify exynos_dp.txt
Beside update some exynos dtsi file with the latest change
according
Hi Ravi,
I'm wondering is your e-mail come from eDP thread ? cause I see lots of
cc guys some as eDP emails :)
And for your question, I am not sure I understand rightly. Do you mean
that your ".ko" module not in
the same directory with driver source code?
If it's your question, I think you
Hi Jingoo,
On 08/20/2015 02:49 AM, Jingoo Han wrote:
On 2015. 8. 19., at PM 11:52, Yakir Yang wrote:
What is the reason to make this patch?
Please make commit message including the reason.
Okay, I think the below words would be okay :)
"This change just make a little clean to make
Hi Jingoo,
On 08/20/2015 02:22 AM, Jingoo Han wrote:
On 2015. 8. 19., at PM 11:50, Yakir Yang wrote:
link_rate and lane_count already configed in analogix_dp_set_link_train(),
s/configed/configured
Also, the commit name such as "fix ... bug" is not good.
How about following?
d
Hi Jingoo,
On 08/20/2015 01:55 AM, Jingoo Han wrote:
On 2015. 8. 20., at PM 3:23, Yakir Yang wrote:
Hi Jingoo & Archit,
On 08/20/2015 12:54 AM, Jingoo Han wrote:
On 2015. 8. 20., at PM 1:29, Archit Taneja wrote:
Hi,
On 08/19/2015 08:18 PM, Yakir Yang wrote:
Hi all,
The Sam
Hi Jingoo,
On 08/20/2015 01:11 AM, Jingoo Han wrote:
On 2015. 8. 19., at PM 11:52, Yakir Yang wrote:
Some edp screen with no hpd signal would need some delay time
to ensure that screen would be ready for work, so we can expand
the delay time in hpd detect function, it works prefectly on my
Hi Jingoo & Archit,
On 08/20/2015 12:54 AM, Jingoo Han wrote:
On 2015. 8. 20., at PM 1:29, Archit Taneja wrote:
Hi,
On 08/19/2015 08:18 PM, Yakir Yang wrote:
Hi all,
The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
share the same IP, so a lot of parts can b
Hi Dave,
On 08/19/2015 06:54 PM, Dave Airlie wrote:
On 20 August 2015 at 00:48, Yakir Yang wrote:
Hi all,
The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
share the same IP, so a lot of parts can be re-used. I split the common
code into bridge directory, then rk3288
Signed-off-by: Yakir Yang
---
Changes in v3: None
Changes in v2:
- Add GNU license v2 declared and samsung copyright
drivers/gpu/drm/exynos/analogix_dp-exynos.c | 1 +
drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 1 +
include/drm/bridge/analogix_dp.h| 16
Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.
Signed-off-by: Yakir Yang
---
Changes in v3:
- Take Thierry Reding and Heiko suggest, leave "sclk_edp_24m" to rockchip
dp phy dr
Display Port monitor could support kinds of mode which indicate
in monitor edid, not just one single display resolution which
defined in panel or devivetree property display timing.
Signed-off-by: Yakir Yang
---
Changes in v3:
- Add edid modes parse support
Changes in v2: None
drivers/gpu/drm
Some edp screen with no hpd signal would need some delay time
to ensure that screen would be ready for work, so we can expand
the delay time in hpd detect function, it works prefectly on my
rk3288 sdk board.
Signed-off-by: Yakir Yang
---
Changes in v3: None
Changes in v2: None
drivers/gpu/drm
Signed-off-by: Yakir Yang
---
Changes in v3:
- move dp hpd detect to connector detect function.
Changes in v2: None
drivers/gpu/drm/bridge/analogix_dp_core.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/bridge/analogix_dp_core.c
b/drivers
Some edp screen do not have hpd signal, so we can't just return
failed when hpd plug in detect failed.
This is an hardware property, so we need add a devicetree property
"analogix,need-force-hpd" to indicate this sutiation.
Signed-off-by: Yakir Yang
---
Changes in v3:
- Add "
RK3288 need some special registers setting, we can separate
them out by the dev_type of plat_data.
Signed-off-by: Yakir Yang
---
Changes in v3: None
Changes in v2:
- Fix compile failed dut to phy_pd_addr variable misspell error
drivers/gpu/drm/bridge/analogix_dp_reg.c | 76
Signed-off-by: Yakir Yang
---
Changes in v3:
- Take Heiko suggest, add rockchip dp phy driver,
collect the phy clocks and power control.
Changes in v2: None
.../devicetree/bindings/phy/rockchip-dp-phy.txt| 26 +++
drivers/phy/Kconfig| 7 +
drivers/phy
Analogix dp driver is split from exynos dp driver, so we just
make an copy of exynos_dp.txt, and then simplify exynos_dp.txt
Beside update some exynos dtsi file with the latest change
according to the devicetree binding documents.
Signed-off-by: Yakir Yang
---
Changes in v3:
- Take Heiko
2Gbps, 2.7Gbps, 5.4Gbps}.
Signed-off-by: Yakir Yang
---
Changes in v3:
- Take Thierry Reding suggest, link_rate and lane_count shouldn't config to
the DT property value directly, but we can take those as hardware limite.
For example, RK3288 only support 4 physical lanes of 2.7/1.62 Gbps/lan
: Yakir Yang
---
Changes in v3:
- Take Thierry Reding suggest, dynamic parse video timing info from
struct drm_display_mode and struct drm_display_info.
Changes in v2: None
drivers/gpu/drm/bridge/analogix_dp_core.c | 50 --
drivers/gpu/drm/exynos/analogix_dp-exynos.c | 65
In order to move exynos dp code to bridge directory,
we need to convert driver drm bridge mode first. As
dp driver already have a ptn3460 bridge, so we need
to move ptn bridge to the next bridge of dp bridge.
Signed-off-by: Yakir Yang
---
Changes in v3: None
Changes in v2:
- Take Jingoo Han
After run "checkpatch.pl -f --subjective" command, I see there
are lots of alignment problem in exynos_dp driver, so let just
fix them.
Signed-off-by: Yakir Yang
---
Changes in v3: None
Changes in v2:
- Take Joe Preches advise, improved commit message more readable, and
avoid
reate devicetree binding for driver.
- Remove the clock enable/disbale with "sclk_edp" & "sclk_edp_24m",
leave those clock to rockchip dp phy driver.
- Add GNU license v2 declared and samsung copyright
- Fix compile failed dut to phy_pd_addr variable misspell error
Yakir Y
Hi Russell,
在 2015/8/10 23:48, Russell King - ARM Linux 写道:
On Sat, Aug 08, 2015 at 05:10:47PM +0100, Russell King wrote:
From: Yakir Yang
Add ALSA based HDMI I2S audio driver for dw_hdmi. Sound card
driver could connect to this codec through the codec dai name
"dw-hdmi-i2s-audio"
Hi Thierry,
在 2015/8/10 21:17, Thierry Reding 写道:
On Mon, Aug 10, 2015 at 08:59:44PM +0800, Yakir Yang wrote:
Hi Thierry,
在 2015/8/10 18:00, Thierry Reding 写道:
On Sat, Aug 08, 2015 at 11:54:38AM +0800, Yakir Yang wrote:
[...]
edp: edp@ff97 {
[...]
hsync
Hi Heiko,
在 2015/8/10 20:08, Heiko Stübner 写道:
Hi Yakir,
Am Samstag, 8. August 2015, 11:54:38 schrieb Yakir Yang:
+static int rockchip_dp_init(struct rockchip_dp_device *dp)
+{
+ struct device *dev = dp->dev;
+ struct device_node *np = dev->of_node;
+ int ret;
+
+
Hi Thierry,
在 2015/8/10 18:00, Thierry Reding 写道:
On Sat, Aug 08, 2015 at 11:54:38AM +0800, Yakir Yang wrote:
[...]
edp: edp@ff97 {
[...]
hsync-active-high = <0>;
vsync-active-high = <0>;
interlaced = <0>;
Th
x27;m
still trying to integrate this into my development-tree.
Am Freitag, 7. August 2015, 05:46:20 schrieb Yakir Yang:
Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.
Signed-off-by: Yakir
Daniel,
在 2015/8/7 19:25, Daniel Vetter 写道:
On Thu, Aug 06, 2015 at 10:29:29PM +0800, Yakir Yang wrote:
Hi Jingoo,
在 2015/8/6 22:19, Jingoo Han 写道:
On Thursday, August 06, 2015 11:07 PM, Yakir Yang wrote:
In order to move exynos dp code to bridge directory,
we need to convert driver drm
RK3288 need some special registers setting, we can separate
them out by the dev_type of plat_data.
Signed-off-by: Yakir Yang
---
Changes in v2:
- Fix compile failed dut to phy_pd_addr variable misspell error
drivers/gpu/drm/bridge/analogix_dp_reg.c | 76
Signed-off-by: Yakir Yang
---
Changes in v2:
- Add GNU license v2 declared and samsung copyright
drivers/gpu/drm/exynos/analogix_dp-exynos.c | 1 +
drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 1 +
include/drm/bridge/analogix_dp.h| 16
3 files changed
Some edp screen with no hpd signal would need some delay time
to ensure that screen would be ready for work, so we can expand
the delay time in hpd detect function, it works prefectly on my
rk3288 sdk board.
Signed-off-by: Yakir Yang
---
Changes in v2: None
drivers/gpu/drm/bridge
Some edp screen do not have hpd signal, so we can't just return
failed when hpd plug in detect failed.
Besides TRM indicate that if HPD_STATUS(RO) is 0, AUX CH will not
work, so we need to give a force hpd action to set HPD_STATUS manually.
Signed-off-by: Yakir Yang
---
Changes in v2:
Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.
Signed-off-by: Yakir Yang
---
Changes in v2: None
drivers/gpu/drm/rockchip/Kconfig| 10 +
drivers/gpu/drm/rockchip/Makefile
In order to move exynos dp code to bridge directory,
we need to convert driver drm bridge mode first. As
dp driver already have a ptn3460 bridge, so we need
to move ptn bridge to the next bridge of dp bridge.
Signed-off-by: Yakir Yang
---
Changes in v2:
- Take Jingoo Han suggest, cause I jsut
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