[PATCH 1/1] mtd:nor:timeout:fix do_write_buffer() timeout error

The size of the buffer program has been increased from 256 to 512 , 2ms maximum timeout can not adapt to all the different vendor's norflash, There maximum timeout information in the CFI area,so the best way is to choose the result calculated according to timeout field of struct cfi_ident that

[PATCH v3] mtd:nor:timeout:fix do_write_buffer() timeout error

The size of the buffer program has been increased from 256 to 512 , 2ms maximum timeout for do_write_buffer can not adapt to all the different vendor's norflash.There maximum timeout information in the CFI area,so the best way is to choose the result calculated according to timeout field of struct

[PATCH v3] mtd:nor:timeout:fix do_write_buffer() timeout error

The size of the buffer program has been increased from 256 to 512 , 2ms maximum timeout for do_write_buffer can not adapt to all the different vendor's norflash.There maximum timeout information in the CFI area,so the best way is to choose the result calculated according to timeout field of

[PATCH v3] mtd:nor:timeout:fix do_write_buffer() timeout error

The size of the buffer program has been increased from 256 to 512 , 2ms maximum timeout for do_write_buffer can not adapt to all the different vendor's norflash.There maximum timeout information in the CFI area,so the best way is to choose the result calculated according to timeout field of

[PATCH v3] mtd:nor:timeout:fix do_write_buffer() timeout error

The size of the buffer program has been increased from 256 to 512 , 2ms maximum timeout for do_write_buffer can not adapt to all the different vendor's norflash.There maximum timeout information in the CFI area,so the best way is to choose the result calculated according to timeout field of

RE: [PATCH 1/1 v3] driver:mtd:spi-nor: Add Micron quad I/O support

This patch adds code which enables Quad I/O mode on Micron SPI NOR flashes. For Micron SPI NOR flash, enabling or disabling quad I/O protocol is controlled by EVCR (Enhanced Volatile Configuration Register), Quad I/O protocol bit 7. When EVCR bit 7 is reset to 0, the SPI NOR flash will operate

[PATCH 1/1 v3] driver:mtd:spi-nor: Add Micron quad I/O support

This patch adds code which enables Quad I/O mode on Micron SPI NOR flashes. For Micron SPI NOR flash, enabling or disabling quad I/O protocol is controlled by EVCR (Enhanced Volatile Configuration Register), Quad I/O protocol bit 7. When EVCR bit 7 is reset to 0, the SPI NOR flash will operate

RE: [PATCH 1/1 v2] driver:mtd:spi-nor:fix spi_nor_scan overwrite platform ID point

There are a lot of changes happening/requested around this code. I also proposed some patch touching this code, see https://patchwork.ozlabs.org/patch/377917/ Right now there is a slow ongoing work on fixing some m25p80 regression, which also may touch the code you change. So I'll suggest

[PATCH 1/1 v3] driver:mtd:spi-nor: Add Micron quad I/O support

This patch adds code which enables Quad I/O mode on Micron SPI NOR flashes. For Micron SPI NOR flash, enabling or disabling quad I/O protocol is controlled by EVCR (Enhanced Volatile Configuration Register), Quad I/O protocol bit 7. When EVCR bit 7 is reset to 0, the SPI NOR flash will operate

RE: [PATCH 1/1 v3] driver:mtd:spi-nor: Add Micron quad I/O support

For Micron spi norflash,enables or disables quad I/O protocol ,which controled by EVCR(Enhanced Volatile Configuration Register) Quad I/O protocol bit 7.When EVCR bit 7 is reset to 0, the spi norflash will operate in quad I/O following the next WRITE ENHANCED VOLATILE CONFIGURATION

[PATCH 1/1 v3] driver:mtd:spi-nor: Add Micron quad I/O support

For Micron spi norflash,enables or disables quad I/O protocol ,which controled by EVCR(Enhanced Volatile Configuration Register) Quad I/O protocol bit 7.When EVCR bit 7 is reset to 0, the spi norflash will operate in quad I/O following the next WRITE ENHANCED VOLATILE CONFIGURATION command.

RE: [V3 PATCH 1/1] devicetree: bindings: Add vendor prefix for Micron Technology Co., Ltd.

This patch is used to add vendor prefix for Micron Technology Inc in the vendor-prefixes.txt file. Micron Technology,Inc.is an American multinational corporation based in Boise, Idaho,best known for producing many forms of semiconductor devices.This includes DRAM,SDRAM,flash memory, eMMC and

RE: [V6 PATCH 1/1] driver:mtd:spi-nor: Add quad I/O support for Micron spi nor

+ { n25q256a,INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) }, + { n25q512a,INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, + { n25q512ax3, INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },

RE: [V6 PATCH 1/1] driver:mtd:spi-nor: Add quad I/O support for Micron spi nor

+{ n25q032, INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) }, +{ n25q064, INFO(0x20ba17, 0, 64 * 1024, 128, SPI_NOR_QUAD_READ) }, +{ n25q128a11, INFO(0x20bb18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) }, +{ n25q128a13, INFO(0x20ba18, 0, 64 * 1024, 256,

[V7 PATCH 1/1] driver:mtd:spi-nor: Add quad I/O support for Micron spi nor

This patch adds code which enables Quad I/O mode on Micron SPI NOR flashes. For Micron SPI NOR flash, enabling or disabling quad I/O protocol can be done By two methods, which are to use EVCR(Enhanced Volatile Configuration Register) and the ENTER QUAD I/O MODE command. There is no difference

[PATCH 1/1 v2] driver:mtd:spi-nor:fix spi_nor_scan overwrite platform ID point

This patch used to modify the method of spi_nor_scan overwrite platform ID point. If type of platform data match with the name of spi_nor_ids set, and JEDEC ID also match with INFO ID of spi_nor_ids set,spi device ID point(this is before probed according to device name) shouldn't be

RE: [V5 PATCH 1/1] driver:mtd:spi-nor: Add quad I/O support for Micron spi nor

Also, which SPI NOR is this enabled for? I don't see any Micron entries in spi_nor_ids[] which contain the SPI_NOR_QUAD_READ flag. Yes, we now don't see any Micron entries in spi_nor_ids[] which contain the SPI_NOR_QUAD_READ flag. But Micron spi nor in spi_nor_ids[] all support Quad I/O

[V6 PATCH 1/1] driver:mtd:spi-nor: Add quad I/O support for Micron spi nor

This patch adds code which enables Quad I/O mode on Micron SPI NOR flashes. For Micron SPI NOR flash,enabling or disabling quad I/O protocol can be done By two methods, which are to use EVCR(Enhanced Volatile Configuration Register) and the ENTER QUAD I/O MODE command.There is no difference

RE: [V6 PATCH 1/1] driver:mtd:spi-nor: Add quad I/O support for Micron spi nor

This patch adds code which enables Quad I/O mode on Micron SPI NOR flashes. For Micron SPI NOR flash,enabling or disabling quad I/O protocol can be done By two methods, which are to use EVCR(Enhanced Volatile Configuration Register) and the ENTER QUAD I/O MODE command.There is no difference

RE: [V7 PATCH 1/1] driver:mtd:spi-nor: Add quad I/O support for Micron spi nor

This patch adds code which enables Quad I/O mode on Micron SPI NOR flashes. For Micron SPI NOR flash, enabling or disabling quad I/O protocol can be done By two methods, which are to use EVCR(Enhanced Volatile Configuration Register) and the ENTER QUAD I/O MODE command. There is no difference

RE: [PATCH] mtd: spi-nor: Only set Micron quad-read mode when controller in 4-lane TX mode

drivers/mtd/spi-nor/spi-nor.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index e8f6131..10ba94f 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -1398,6 +1398,8 @@ static int

RE: [PATCH v4 0/7] Add spi-nor SPI transfer error handling

Hello, with these patches SPI transfer errors are not silently ignored but rather reported to spi-nor users. This should prevent silently dropping data to the floor in cases when the SPI transfer fails and the failure is detected. It has been pointed out that MTD users do not handle the case

enhance ONFI table reliability/stable

Hi, Recently, I faced some case about ONFI table reliability, now it used CRC. If there is bit flips in ONFI parameter pages, parameter backup page will be taken. For latest linux,default read three copys. chip-cmdfunc(mtd, NAND_CMD_PARAM, 0, -1); for (i = 0; i 3; i++) {

RE: [PATCH linux-next v4 5/5] mtd: atmel-quadspi: add driver for Atmel QSPI controller

+ nor-read_reg = atmel_qspi_read_reg; + nor-write_reg = atmel_qspi_write_reg; + nor-read = atmel_qspi_read; + nor-write = atmel_qspi_write; + nor-erase = atmel_qspi_erase; + nor-set_protocol = atmel_qspi_set_protocol; This is very good, the structure of spi_nor

RE: [PATCH v7 4/7] mtd: nand: gpmi: may use minimum required ecc for 744 oobsize NAND

> By default NAND driver will choose the highest ecc strength that oob could > contain, in this case, for some 8K+744 NAND flash, the ecc strength will be up > to 52bit, which beyonds the i.MX6QDL BCH capability (40bit). For normal working environment, if hardware BCH ECC cannot meet NAND ecc

Recall: [PATCH v7 4/7] mtd: nand: gpmi: may use minimum required ecc

Bean Huo 霍斌斌 (beanhuo) would like to recall the message, "[PATCH v7 4/7] mtd: nand: gpmi: may use minimum required ecc".-- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at ht

RE: [PATCH v7 4/7] mtd: nand: gpmi: may use minimum required ecc

> By default NAND driver will choose the highest ecc strength that oob could > contain, in this case, for some 8K+744 NAND flash, the ecc strength will be up > to 52bit, which beyonds the i.MX6QDL BCH capability (40bit). For normal working environment, if hardware BCH ECC cannot meet NAND ecc

RE: [PATCH v7 4/7] mtd: nand: gpmi: may use minimum required ecc

> > > By default NAND driver will choose the highest ecc strength that oob > > > could contain, in this case, for some 8K+744 NAND flash, the ecc > > > strength will be up to 52bit, which beyonds the i.MX6QDL BCH capability > (40bit). > > > > > > For normal working environment, if hardware BCH ECC

RE: [PATCH 0/9] drivers:mtd:UBI: add bakvol module for MLC NAND paired page issue

> > Hi, Richard > > Thanks for your concern. I am a new patch submitter. > > Can you tell me Nacked-by means? > > I basically means that I'm (as maintainer) really unhappy with this patches > and > don't see a way to get them merged as the whole concept is not acceptable. > > > By the way, Do

RE: [PATCH 0/9] drivers:mtd:UBI: add bakvol module for MLC NAND paired page issue

> Am 30.09.2015 um 08:55 schrieb Richard Weinberger: > >> By the way, Do you review my patches series ? I don't backup duplicated > data in OOB . > >> Can you specify which sector codes ? so that I can explain it in detail. > > > > Okay. Maybe both Boris and I misread your code, can you please

RE: [PATCH 0/9] drivers:mtd:UBI: add bakvol module for MLC NAND paired page issue

> > > As stated before, using OOB in UBI is not going to happen unless > > > proven that there is absolutely no other way to solve the paired pages > problem. > > > > > > Nacked-by: Richard Weinberger > > > > > > Sorry, > > > //Richard > > > > Hi, Richard > > Thanks for your

RE: [RESEND RESEND RESEND PATCH v2] mtd: nand_bbt: scan for next free bbt block if writing bbt fails

+ Bean, who is looking at refactoring this driver. Perhaps he can review this. On Tue, Aug 25, 2015 at 12:49:26PM -0500, Xander Huff wrote: From: Ben Shelton ben.shel...@ni.com If erasing or writing the BBT fails, we should mark the current BBT block as bad and use the BBT descriptor

RE: [PATCH 1/9] drivers:nand:mtd: add support for UBI bakvol in mtd layer

> Hi Bean, > > On Mon, 28 Sep 2015 07:02:37 + > Bean Huo 霍斌斌 (beanhuo) <bean...@micron.com> wrote: > > > Add support for UBI bakvol in mtd layer. > > > > This solution based on MLC NAND dual plane program. > > so add hook in mtd layer. > >

RE: [PATCH 0/9] drivers:mtd:UBI: add bakvol module for MLC NAND paired page issue

> Am 28.09.2015 um 09:02 schrieb Bean Huo 霍斌斌 (beanhuo): > > Hello, > > > > This series aims at adding a bakvol module for MLC NAND paired page > > Power loss protection. > > MLC NAND paired page power loss is a known issue so far, MLC NAND > > pages are c

[PATCH 3/9] drivers:mtd:ubi:add metadata struct for UBI bakvol

Add metadata struct for UBI bakvol. Currently , bakvol reserves 20 PEBs for internal log volume. Shares wear-leveling operation with ubi. Signed-off-by: Bean Huo --- drivers/mtd/ubi/ubi-media.h | 40 1 file changed, 40 insertions(+)

[PATCH 9/9] driver:mtd:ubi:add bakvol module in UBI layer

ntents of this file are subject to the Mozilla Public + License Version 1.1 (the "License"); You may obtain a copy of + the License at http://www.mozilla.org/MPL/.But you can use this + file, no matter in compliance with the License or not. + + The initial developer of the original co

[PATCH 4/9] fs:ubifs: add hook for UBI bakvol in ubifs layer

Add hook for UBI bakvol in ubifs layer. open/close bakvol operation in ubifs mount. Signed-off-by: Bean Huo --- fs/ubifs/super.c | 6 ++ fs/ubifs/ubifs.h | 1 + 2 files changed, 7 insertions(+) diff --git a/fs/ubifs/super.c b/fs/ubifs/super.c index 9547a278..f3bf548

[PATCH 6/9] drivers:mtd:ubi:add hook for UBI bakvol in ubi_io_write

Add hook for UBI bakvol in ubi_io_write. Modify ubi_io_write, if program lower page of MLC NAND, Duplicated it and backup one copy into internal log volume by Dual plane program method. Signed-off-by: Bean Huo --- drivers/mtd/ubi/io.c | 63

[PATCH 1/9] drivers:nand:mtd: add support for UBI bakvol in mtd layer

Add support for UBI bakvol in mtd layer. This solution based on MLC NAND dual plane program. so add hook in mtd layer. Signed-off-by: Bean Huo --- include/linux/mtd/mtd.h | 19 +++ include/linux/mtd/nand.h | 4 include/linux/mtd/ubi.h | 9 +

[PATCH 0/9] drivers:mtd:UBI: add bakvol module for MLC NAND paired page issue

Hello, This series aims at adding a bakvol module for MLC NAND paired page Power loss protection. MLC NAND paired page power loss is a known issue so far, MLC NAND pages are coupled in a sense that if you cut power while writing to a page, you corrupt not only this page, but also one of the

[PATCH 7/9] drivers:mtd:add NAND dual plane program support

Add NAND dual plane program function. Signed-off-by: Bean Huo --- drivers/mtd/mtdpart.c| 21 +++ drivers/mtd/nand/nand_base.c | 401 +++ 2 files changed, 422 insertions(+) diff --git a/drivers/mtd/mtdpart.c

[PATCH 5/9] drivers:mtd:ubi:add support for getting block according to plane

Dual plane program must address two blocks located two different planes. Signed-off-by: Bean Huo --- drivers/mtd/ubi/wl.c | 134 +++ 1 file changed, 134 insertions(+) diff --git a/drivers/mtd/ubi/wl.c b/drivers/mtd/ubi/wl.c

[PATCH 8/9] drivers:mtd:ubi:init UBI bakvol and recover corrupted lower page

During UBI attach, bakvol be initialized, And if exist corrupted lower page, recover it by its backup data in internal Log volume. Signed-off-by: Bean Huo --- drivers/mtd/ubi/attach.c | 26 +- drivers/mtd/ubi/build.c | 7 +++ 2 files changed,

[PATCH 2/9] drivers:mtd:ubi:add definition for UBI bakvol operation

Add macro definition for UBI bakvol operation. Signed-off-by: Bean Huo --- drivers/mtd/ubi/ubi.h | 17 + 1 file changed, 17 insertions(+) diff --git a/drivers/mtd/ubi/ubi.h b/drivers/mtd/ubi/ubi.h index 2974b67..746dfbe 100644 --- a/drivers/mtd/ubi/ubi.h +++

RE: [PATCH 0/9] drivers:mtd:UBI: add bakvol module for MLC NAND paired page issue

> Hi Bean, > > Next time you send a patch series, could send all the patches in reply to the > cover letter? No problem, we will format our submit-patch method, and standard it. > > Hello, > > > > This series aims at adding a bakvol module for MLC NAND paired page > > Power loss protection. >

RE: [PATCH linux-next 0/5] mtd: spi-nor: add driver for Atmel QSPI controller

g; > linux-arm-ker...@lists.infradead.org; devicet...@vger.kernel.org; > robh...@kernel.org; pawel.m...@arm.com; mark.rutl...@arm.com; > ijc+devicet...@hellion.org.uk; ga...@codeaurora.org; Bean Huo 霍斌斌 > (beanhuo) > Subject: Re: [PATCH linux-next 0/5] mtd: spi-nor: add driver for Atmel

RE: [PATCH linux-next 0/5] mtd: spi-nor: add driver for Atmel QSPI controller

> > I'll admit I'm a little fuzzy on the differences between dual and quad modes > on > various flash manufacturers. Can you help clear it up for me? For SPI NOR, currently, don't have an official standard to define an uniform Quad I/O mode protocol. So we can see that there are some

RE: [PATCH 1/1] fs:ubifs:recovery:fixup UBIFS cannot recover master node issue

Dear Richard > Bean, > > Am 11.12.2015 um 09:26 schrieb Bean Huo 霍斌斌 (beanhuo): > > For MLC NAND, paired page issue is now a common known issue. > > This patch is just for master node cannot be recovered while there > > will two pages be damaged in o

[PATCH 1/1] fs:ubifs:recovery:fixup UBIFS cannot recover master node issue

For MLC NAND, paired page issue is now a common known issue. This patch is just for master node cannot be recovered while there will two pages be damaged in one single master node block. As for this patch, if there are more than one page data in master node block being damaged, and as long as

RE: enhance ONFI table reliability/stable

> > Hi Bean, > > I was sorting through old email and I found this. > > On Tue, Jul 21, 2015 at 02:42:34PM +0000, Bean Huo 霍斌斌 (beanhuo) > wrote: > > Hi, > > > > Recently, I faced some case about ONFI table reliability, now it used CRC. > >

RE: [PATCH 1/1] fs:ubifs:recovery:fixup UBIFS cannot recover master node issue

> Bean, > > Am 14.12.2015 um 04:55 schrieb Bean Huo 霍斌斌 (beanhuo): > > Dear Richard > > > >> Bean, > >> > >> Am 11.12.2015 um 09:26 schrieb Bean Huo 霍斌斌 (beanhuo): > >>> For MLC NAND, paired page issue is now a common known issue. > &

RE: [PATCH v2 00/17] Add a bakvol module in UBI layer for MLC paired page power loss issue

Dear Richard Thanks for reviewing my patches and valuable feedback. I also want to work with you and Boris on such solution, I know this is a complicated task, need our joint effort. Following is my explanation for each of concerns: > Bean, > > Am 02.02.2016 um 03:30 schrieb Bean Huo: > >

RE: [PATCH v2 17/17] drivers:mtd:ubi: Kconfig Makefile

. Brian Sorry for this. this patches codes are too long, Next time I will push my patches based on latest kernel. Beat Regards! Beanhuo

RE: [PATCH 1/1] fs:ubifs:recovery:fixup UBIFS cannot recover master node issue

Hi, Richard > From: Richard Weinberger [mailto:rich...@nod.at] > Sent: Thursday, January 28, 2016 5:32 PM > To: Bean Huo 霍斌斌 (beanhuo); Artem Bityutskiy; Adrian Hunter; Brian > Norris > Cc: linux-...@lists.infradead.org; linux-kernel@vger.kernel.org; Boris > Brezillon; Peter Pa

RE: [PATCH v2 17/17] drivers:mtd:ubi: Kconfig Makefile

> Hi Bean, > > [auto build test WARNING on v4.5-rc2] This version 2.0 patches are based on 4.2-rc7. > [also build test WARNING on next-20160201] [if your patch is applied to the > wrong git tree, please drop us a note to help improving the system]

RE: [RFC] spi-nor: fix cross die reads on Micron multi-die devices

here are any plans for MT25* based multi-die devices and if > they would have the same issue? > > Thanks, > > Adam > > On Wed, Jan 20, 2016 at 2:45 AM, Bean Huo 霍斌斌 (beanhuo) > <bean...@micron.com> wrote: > > Hi, Adam > > This is true, but this only exist

RE: [RFC] spi-nor: fix cross die reads on Micron multi-die devices

> Hi Bean, > > On Thu, 21 Jan 2016 01:06:48 + > Bean Huo 霍斌斌 (beanhuo) <bean...@micron.com> wrote: > > > Hi, Adam and Boris > > > > For Micron MT25Q ,MT25T and MT35Q, they does not exist this action > > even they are Multi-die devices. So when

RE: [PATCH v3 4/4] mtd: spi-nor: Disable Micron flash HW protection

Hi, Yunhai You mean that EVCR.bit7 cannot clear(enable quad mode) if not write SR.bit7 to 0? They don't have any connection each other. > -Original Message- > From: Yunhui Cui [mailto:yunhui@nxp.com] > Sent: Friday, March 18, 2016 6:09 PM > To: Bean Huo 霍斌斌 (beanhuo); Yun

Re: [PATCH v3 4/4] mtd: spi-nor: Disable Micron flash HW protection

> From: Yunhui Cui > To: , , > > Cc: , , > , , Yunhui > Cui >

[PATCH 1/1] mtd:nor:timeout:fix do_write_buffer() timeout error

The size of the buffer program has been increased from 256 to 512 , 2ms maximum timeout can not adapt to all the different vendor's norflash, There maximum timeout information in the CFI area,so the best way is to choose the result calculated according to timeout field of struct cfi_ident that

[PATCH v3] mtd:nor:timeout:fix do_write_buffer() timeout error

The size of the buffer program has been increased from 256 to 512 , 2ms maximum timeout for do_write_buffer can not adapt to all the different vendor's norflash.There maximum timeout information in the CFI area,so the best way is to choose the result calculated according to timeout field of struct

[PATCH v3] mtd:nor:timeout:fix do_write_buffer() timeout error

The size of the buffer program has been increased from 256 to 512 , 2ms maximum timeout for do_write_buffer can not adapt to all the different vendor's norflash.There maximum timeout information in the CFI area,so the best way is to choose the result calculated according to timeout field of

[PATCH v3] mtd:nor:timeout:fix do_write_buffer() timeout error

The size of the buffer program has been increased from 256 to 512 , 2ms maximum timeout for do_write_buffer can not adapt to all the different vendor's norflash.There maximum timeout information in the CFI area,so the best way is to choose the result calculated according to timeout field of

[PATCH v3] mtd:nor:timeout:fix do_write_buffer() timeout error

The size of the buffer program has been increased from 256 to 512 , 2ms maximum timeout for do_write_buffer can not adapt to all the different vendor's norflash.There maximum timeout information in the CFI area,so the best way is to choose the result calculated according to timeout field of

[V6 PATCH 1/1] driver:mtd:spi-nor: Add quad I/O support for Micron spi nor

This patch adds code which enables Quad I/O mode on Micron SPI NOR flashes. For Micron SPI NOR flash,enabling or disabling quad I/O protocol can be done By two methods, which are to use EVCR(Enhanced Volatile Configuration Register) and the ENTER QUAD I/O MODE command.There is no difference

RE: [V5 PATCH 1/1] driver:mtd:spi-nor: Add quad I/O support for Micron spi nor

>>>Also, which SPI NOR is this enabled for? I don't see any Micron entries in >>>spi_nor_ids[] which contain the SPI_NOR_QUAD_READ flag. >> >> Yes, we now don't see any Micron entries in spi_nor_ids[] which >> contain the SPI_NOR_QUAD_READ flag. But Micron spi nor in >> spi_nor_ids[] all

RE: [V3 PATCH 1/1] devicetree: bindings: Add vendor prefix for Micron Technology Co., Ltd.

>This patch is used to add vendor prefix for Micron Technology >Inc in the vendor-prefixes.txt file. >Micron Technology,Inc.is an American multinational corporation >based in Boise, Idaho,best known for producing many forms of >semiconductor devices.This includes DRAM,SDRAM,flash memory, >eMMC

RE: [V6 PATCH 1/1] driver:mtd:spi-nor: Add quad I/O support for Micron spi nor

>> +{ "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) >> }, >> +{ "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SPI_NOR_QUAD_READ) >> }, >> +{ "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) >> }, >> +{ "n25q128a13", INFO(0x20ba18,

[V7 PATCH 1/1] driver:mtd:spi-nor: Add quad I/O support for Micron spi nor

This patch adds code which enables Quad I/O mode on Micron SPI NOR flashes. For Micron SPI NOR flash, enabling or disabling quad I/O protocol can be done By two methods, which are to use EVCR(Enhanced Volatile Configuration Register) and the ENTER QUAD I/O MODE command. There is no difference

[PATCH 1/1 v3] driver:mtd:spi-nor: Add Micron quad I/O support

For Micron spi norflash,enables or disables quad I/O protocol ,which controled by EVCR(Enhanced Volatile Configuration Register) Quad I/O protocol bit 7.When EVCR bit 7 is reset to 0, the spi norflash will operate in quad I/O following the next WRITE ENHANCED VOLATILE CONFIGURATION command.

enhance ONFI table reliability/stable

Hi, Recently, I faced some case about ONFI table reliability, now it used CRC. If there is bit flips in ONFI parameter pages, parameter backup page will be taken. For latest linux,default read three copys. chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1); for (i = 0; i < 3; i++) {

RE: [RESEND RESEND RESEND PATCH v2] mtd: nand_bbt: scan for next free bbt block if writing bbt fails

> + Bean, who is looking at refactoring this driver. Perhaps he can review > this. > > On Tue, Aug 25, 2015 at 12:49:26PM -0500, Xander Huff wrote: > > From: Ben Shelton > > > > If erasing or writing the BBT fails, we should mark the current BBT > > block as bad and use the BBT descriptor to

RE: [PATCH v4 0/7] Add spi-nor SPI transfer error handling

>Hello, >with these patches SPI transfer errors are not silently ignored but rather >reported to spi-nor users. >This should prevent silently dropping data to the floor in cases when the SPI >transfer fails and the failure is detected. >It has been pointed out that MTD users do not handle the

RE: [PATCH linux-next v4 5/5] mtd: atmel-quadspi: add driver for Atmel QSPI controller

>+ nor->read_reg = atmel_qspi_read_reg; >+ nor->write_reg = atmel_qspi_write_reg; >+ nor->read = atmel_qspi_read; >+ nor->write = atmel_qspi_write; >+ nor->erase = atmel_qspi_erase; >+ nor->set_protocol = atmel_qspi_set_protocol; This is very good, the structure of

RE: [V6 PATCH 1/1] driver:mtd:spi-nor: Add quad I/O support for Micron spi nor

>> + { "n25q256a",INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | >> SPI_NOR_QUAD_READ) }, >> + { "n25q512a",INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | >> USE_FSR | SPI_NOR_QUAD_READ) }, >> + { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | >> USE_FSR |

[PATCH 1/1 v3] driver:mtd:spi-nor: Add Micron quad I/O support

This patch adds code which enables Quad I/O mode on Micron SPI NOR flashes. For Micron SPI NOR flash, enabling or disabling quad I/O protocol is controlled by EVCR (Enhanced Volatile Configuration Register), Quad I/O protocol bit 7. When EVCR bit 7 is reset to 0, the SPI NOR flash will operate

[PATCH 1/1 v2] driver:mtd:spi-nor:fix spi_nor_scan overwrite platform ID point

This patch used to modify the method of spi_nor_scan overwrite platform ID point. If type of platform data match with the name of spi_nor_ids set, and JEDEC ID also match with INFO ID of spi_nor_ids set,spi device ID point(this is before probed according to device name) shouldn't be

RE: [PATCH 1/1 v2] driver:mtd:spi-nor:fix spi_nor_scan overwrite platform ID point

>There are a lot of changes happening/requested around this code. I also >proposed some patch touching this code, see >https://patchwork.ozlabs.org/patch/377917/ >Right now there is a slow ongoing work on fixing some m25p80 regression, which >also may touch the code you change. So I'll suggest

RE: [PATCH 1/1 v3] driver:mtd:spi-nor: Add Micron quad I/O support

>> For Micron spi norflash,enables or disables quad I/O protocol ,which >> controled by EVCR(Enhanced Volatile Configuration Register) Quad I/O >> protocol bit 7.When EVCR bit 7 is reset to 0, the spi norflash will >> operate in quad I/O following the next WRITE ENHANCED VOLATILE >>

RE: [PATCH] mtd: spi-nor: Only set Micron quad-read mode when controller in 4-lane TX mode

>drivers/mtd/spi-nor/spi-nor.c | 2 ++ > 1 file changed, 2 insertions(+) >diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c >index e8f6131..10ba94f 100644 >--- a/drivers/mtd/spi-nor/spi-nor.c >+++ b/drivers/mtd/spi-nor/spi-nor.c >@@ -1398,6 +1398,8 @@ static int

RE: [V6 PATCH 1/1] driver:mtd:spi-nor: Add quad I/O support for Micron spi nor

>This patch adds code which enables Quad I/O mode on Micron SPI NOR flashes. >For Micron SPI NOR flash,enabling or disabling quad I/O protocol can be done >By two methods, which are to >use EVCR(Enhanced Volatile Configuration Register) and the ENTER QUAD I/O MODE >command.There is no

RE: [PATCH 1/1 v3] driver:mtd:spi-nor: Add Micron quad I/O support

>This patch adds code which enables Quad I/O mode on Micron SPI NOR flashes. >For Micron SPI NOR flash, enabling or disabling quad I/O protocol is >controlled by >EVCR (Enhanced Volatile Configuration Register), Quad I/O protocol bit 7. >When EVCR bit 7 is reset to 0, the SPI NOR flash will

[PATCH 1/1 v3] driver:mtd:spi-nor: Add Micron quad I/O support

This patch adds code which enables Quad I/O mode on Micron SPI NOR flashes. For Micron SPI NOR flash, enabling or disabling quad I/O protocol is controlled by EVCR (Enhanced Volatile Configuration Register), Quad I/O protocol bit 7. When EVCR bit 7 is reset to 0, the SPI NOR flash will operate

RE: [V7 PATCH 1/1] driver:mtd:spi-nor: Add quad I/O support for Micron spi nor

>This patch adds code which enables Quad I/O mode on Micron SPI NOR flashes. >For Micron SPI NOR flash, enabling or disabling quad I/O protocol can be done >By two methods, >which are to use EVCR(Enhanced Volatile Configuration Register) and the ENTER >QUAD I/O MODE command. >There is no

RE: [PATCH v7 4/7] mtd: nand: gpmi: may use minimum required ecc

> By default NAND driver will choose the highest ecc strength that oob could > contain, in this case, for some 8K+744 NAND flash, the ecc strength will be up > to 52bit, which beyonds the i.MX6QDL BCH capability (40bit). For normal working environment, if hardware BCH ECC cannot meet NAND ecc

Recall: [PATCH v7 4/7] mtd: nand: gpmi: may use minimum required ecc

Bean Huo 霍斌斌 (beanhuo) would like to recall the message, "[PATCH v7 4/7] mtd: nand: gpmi: may use minimum required ecc".-- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at ht

RE: [PATCH v7 4/7] mtd: nand: gpmi: may use minimum required ecc for 744 oobsize NAND

> By default NAND driver will choose the highest ecc strength that oob could > contain, in this case, for some 8K+744 NAND flash, the ecc strength will be up > to 52bit, which beyonds the i.MX6QDL BCH capability (40bit). For normal working environment, if hardware BCH ECC cannot meet NAND ecc

RE: [PATCH v7 4/7] mtd: nand: gpmi: may use minimum required ecc

> > > By default NAND driver will choose the highest ecc strength that oob > > > could contain, in this case, for some 8K+744 NAND flash, the ecc > > > strength will be up to 52bit, which beyonds the i.MX6QDL BCH capability > (40bit). > > > > > > For normal working environment, if hardware BCH ECC

RE: [RFC] spi-nor: fix cross die reads on Micron multi-die devices

here are any plans for MT25* based multi-die devices and if > they would have the same issue? > > Thanks, > > Adam > > On Wed, Jan 20, 2016 at 2:45 AM, Bean Huo 霍斌斌 (beanhuo) > wrote: > > Hi, Adam > > This is true, but this only exist in Micron 65nm spi no

RE: [PATCH linux-next 0/5] mtd: spi-nor: add driver for Atmel QSPI controller

g; > linux-arm-ker...@lists.infradead.org; devicet...@vger.kernel.org; > robh...@kernel.org; pawel.m...@arm.com; mark.rutl...@arm.com; > ijc+devicet...@hellion.org.uk; ga...@codeaurora.org; Bean Huo 霍斌斌 > (beanhuo) > Subject: Re: [PATCH linux-next 0/5] mtd: spi-nor: add driver for Atmel

RE: [PATCH linux-next 0/5] mtd: spi-nor: add driver for Atmel QSPI controller

> > I'll admit I'm a little fuzzy on the differences between dual and quad modes > on > various flash manufacturers. Can you help clear it up for me? For SPI NOR, currently, don't have an official standard to define an uniform Quad I/O mode protocol. So we can see that there are some

RE: [PATCH 0/9] drivers:mtd:UBI: add bakvol module for MLC NAND paired page issue

> > Hi, Richard > > Thanks for your concern. I am a new patch submitter. > > Can you tell me Nacked-by means? > > I basically means that I'm (as maintainer) really unhappy with this patches > and > don't see a way to get them merged as the whole concept is not acceptable. > > > By the way, Do

RE: [PATCH 0/9] drivers:mtd:UBI: add bakvol module for MLC NAND paired page issue

> > > As stated before, using OOB in UBI is not going to happen unless > > > proven that there is absolutely no other way to solve the paired pages > problem. > > > > > > Nacked-by: Richard Weinberger > > > > > > Sorry, > > > //Richard > > > > Hi, Richard > > Thanks for your concern. I am a new

RE: [PATCH 0/9] drivers:mtd:UBI: add bakvol module for MLC NAND paired page issue

> Am 30.09.2015 um 08:55 schrieb Richard Weinberger: > >> By the way, Do you review my patches series ? I don't backup duplicated > data in OOB . > >> Can you specify which sector codes ? so that I can explain it in detail. > > > > Okay. Maybe both Boris and I misread your code, can you please

RE: enhance ONFI table reliability/stable

> > Hi Bean, > > I was sorting through old email and I found this. > > On Tue, Jul 21, 2015 at 02:42:34PM +0000, Bean Huo 霍斌斌 (beanhuo) > wrote: > > Hi, > > > > Recently, I faced some case about ONFI table reliability, now it used CRC. > >

RE: [PATCH v3 4/4] mtd: spi-nor: Disable Micron flash HW protection

Hi, Yunhai You mean that EVCR.bit7 cannot clear(enable quad mode) if not write SR.bit7 to 0? They don't have any connection each other. > -Original Message- > From: Yunhui Cui [mailto:yunhui@nxp.com] > Sent: Friday, March 18, 2016 6:09 PM > To: Bean Huo 霍斌斌 (beanhuo); Yun

RE: [PATCH 1/1] fs:ubifs:recovery:fixup UBIFS cannot recover master node issue

> Bean, > > Am 14.12.2015 um 04:55 schrieb Bean Huo 霍斌斌 (beanhuo): > > Dear Richard > > > >> Bean, > >> > >> Am 11.12.2015 um 09:26 schrieb Bean Huo 霍斌斌 (beanhuo): > >>> For MLC NAND, paired page issue is now a common known issue. > &

Re: [PATCH v3 4/4] mtd: spi-nor: Disable Micron flash HW protection

> From: Yunhui Cui > To: , , > > Cc: , , > , , Yunhui > Cui > > Subject: [PATCH v3 4/4] mtd: spi-nor: Disable Micron flash HW > protection > Message-ID: <1456988044-37061-4-git-send-email-b56...@freescale.com> > Content-Type: text/plain > > From: Yunhui Cui > > For

RE: [PATCH v2 00/17] Add a bakvol module in UBI layer for MLC paired page power loss issue

Dear Richard Thanks for reviewing my patches and valuable feedback. I also want to work with you and Boris on such solution, I know this is a complicated task, need our joint effort. Following is my explanation for each of concerns: > Bean, > > Am 02.02.2016 um 03:30 schrieb Bean Huo: > >

RE: [PATCH v2 17/17] drivers:mtd:ubi: Kconfig Makefile

. Brian Sorry for this. this patches codes are too long, Next time I will push my patches based on latest kernel. Beat Regards! Beanhuo

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