From: Stephen Boyd
On some devices (MSM8974 for example), the HFPLLs are
instantiated within the Krait processor subsystem as separate
register regions. Add a driver for these PLLs so that we can
provide HFPLL clocks for use by the system.
Cc:
Signed-off-by: Stephen Boyd
---
From: Stephen Boyd
Krait CPUs have a handful of L2 cache controller registers that
live behind a cp15 based indirection register. First you program
the indirection register (l2cpselr) to point the L2 'window'
register (l2cpdr) at what you want to read/write. Then you
read/write the 'window'
From: Stephen Boyd
HFPLLs are the main frequency source for Krait CPU clocks. Add
support for changing the rate of these PLLs.
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/Makefile| 1 +
drivers/clk/qcom/clk-hfpll.c | 244 +++
From: Stephen Boyd
Krait CPUs have a handful of L2 cache controller registers that
live behind a cp15 based indirection register. First you program
the indirection register (l2cpselr) to point the L2 'window'
register (l2cpdr) at what you want to read/write. Then you
read/write the 'window'
From: Stephen Boyd
HFPLLs are the main frequency source for Krait CPU clocks. Add
support for changing the rate of these PLLs.
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/Makefile| 1 +
drivers/clk/qcom/clk-hfpll.c | 244 +++
32608.html
[4] https://lwn.net/Articles/740994/
[5] https://lkml.org/lkml/2017/12/19/537
Sricharan R (3):
clk: qcom: Add safe switch hook for krait mux clocks
cpufreq: qcom: Re-organise kryo cpufreq to use it for other nvmem
based qcom socs
cpufreq: qcom: Add support for krait based so
32608.html
[4] https://lwn.net/Articles/740994/
[5] https://lkml.org/lkml/2017/12/19/537
Sricharan R (3):
clk: qcom: Add safe switch hook for krait mux clocks
cpufreq: qcom: Re-organise kryo cpufreq to use it for other nvmem
based qcom socs
cpufreq: qcom: Add support for krait based so
Hi Rob,
On 8/7/2018 2:05 AM, Rob Herring wrote:
> On Fri, Aug 3, 2018 at 8:10 AM Sricharan R wrote:
>>
>> Add a new board dts for ipq8064-ap161.
>>
>> Signed-off-by: Sricharan R
>> ---
>> Documentation/devicetree/bindings/arm/qcom.tx
Hi Rob,
On 8/7/2018 2:05 AM, Rob Herring wrote:
> On Fri, Aug 3, 2018 at 8:10 AM Sricharan R wrote:
>>
>> Add a new board dts for ipq8064-ap161.
>>
>> Signed-off-by: Sricharan R
>> ---
>> Documentation/devicetree/bindings/arm/qcom.tx
Add a new board dts for ipq8064-ap161.
Signed-off-by: Sricharan R
---
Documentation/devicetree/bindings/arm/qcom.txt | 2 ++
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq8064-ap161.dts | 7 +++
3 files changed, 10 insertions(+)
create mode 100644
The nodes in ipq8064-ap148.dts currently are common with
boards that we will add next. So move the common data to
ipq8064-v.1.0.dtsi.
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 83 ++--
arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi | 65
Add a new board dts for ipq8064-ap161.
Signed-off-by: Sricharan R
---
Documentation/devicetree/bindings/arm/qcom.txt | 2 ++
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq8064-ap161.dts | 7 +++
3 files changed, 10 insertions(+)
create mode 100644
The nodes in ipq8064-ap148.dts currently are common with
boards that we will add next. So move the common data to
ipq8064-v.1.0.dtsi.
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 83 ++--
arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi | 65
Add the dt nodes for enabling the leds and gpio-buttons.
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 8 +
arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi | 60
arch/arm/boot/dts/qcom-ipq8064.dtsi | 19 ++
3 files changed
Adding pcie,sdcc nodes and a new board file ipq8064-ap161
Sricharan R (5):
arm: dts: qcom: Add pcie nodes for ipq8064
arm: dts: qcom: Add sdcc nodes for ipq8064
arm: dts: qcom: Move common nodes to ipq8064-v.1.0.dtsi
arm: dts: qcom: Add ipq8064-ap161.dts
arm: dts: qcom: Add led and gpio
Add the dt nodes for enabling the leds and gpio-buttons.
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 8 +
arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi | 60
arch/arm/boot/dts/qcom-ipq8064.dtsi | 19 ++
3 files changed
Adding pcie,sdcc nodes and a new board file ipq8064-ap161
Sricharan R (5):
arm: dts: qcom: Add pcie nodes for ipq8064
arm: dts: qcom: Add sdcc nodes for ipq8064
arm: dts: qcom: Move common nodes to ipq8064-v.1.0.dtsi
arm: dts: qcom: Add ipq8064-ap161.dts
arm: dts: qcom: Add led and gpio
The relevant data for sdcc.
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 76 +
1 file changed, 76 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi
b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index e02d588..e78618e 100644
Adding the pcie nodes and pins.
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 182
1 file changed, 182 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi
b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 70790ac..e02d588 100644
The relevant data for sdcc.
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 76 +
1 file changed, 76 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi
b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index e02d588..e78618e 100644
Adding the pcie nodes and pins.
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 182
1 file changed, 182 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi
b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 70790ac..e02d588 100644
xes: 3a3d4163e0bf ("remoteproc: qcom: Introduce Hexagon V5 based WCSS
> driver")
> Signed-off-by: Arnd Bergmann
Oops, missed it. Sorry.
Acked-by: Sricharan R
Regards,
Sricharan
> ---
> drivers/remoteproc/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --gi
xes: 3a3d4163e0bf ("remoteproc: qcom: Introduce Hexagon V5 based WCSS
> driver")
> Signed-off-by: Arnd Bergmann
Oops, missed it. Sorry.
Acked-by: Sricharan R
Regards,
Sricharan
> ---
> drivers/remoteproc/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --gi
Hi Thierry,
On 6/27/2018 3:01 PM, Thierry Escande wrote:
> Hi Sricharan,
>
> On 19/06/2018 15:45, Sricharan R wrote:
>> Sricharan R (2):
>> clk: qcom: Add safe switch hook for krait mux clocks
>> dt-bindings: cpufreq: Document operating-points-v2-krait
Hi Thierry,
On 6/27/2018 3:01 PM, Thierry Escande wrote:
> Hi Sricharan,
>
> On 19/06/2018 15:45, Sricharan R wrote:
>> Sricharan R (2):
>> clk: qcom: Add safe switch hook for krait mux clocks
>> dt-bindings: cpufreq: Document operating-points-v2-krait
Fix all nodes to use proper GIC_* macros for the interrupt type and the
interrupt trigger settings to avoid the boot warnings.
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 41 ++---
1 file changed, 24 insertions(+), 17 deletions(-)
diff
Fix all nodes to use proper GIC_* macros for the interrupt type and the
interrupt trigger settings to avoid the boot warnings.
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 41 ++---
1 file changed, 24 insertions(+), 17 deletions(-)
diff
er as well by
Viresh.
Now that kryo is merged, i will check once and see if they can be
nicely
merged.
Regards,
Sricharan
er as well by
Viresh.
Now that kryo is merged, i will check once and see if they can be
nicely
merged.
Regards,
Sricharan
with the hfpll driver that runs on 8974. I will try
to test
on that hardware.
That said, just realized that i missed a minor comment from Bjorn.
Will anyway update it.
Regards,
Sricharan
On Tue, Jun 19, 2018 at 07:15:24PM +0530, Sricharan R wrote:
From: Stephen Boyd
Register
with the hfpll driver that runs on 8974. I will try
to test
on that hardware.
That said, just realized that i missed a minor comment from Bjorn.
Will anyway update it.
Regards,
Sricharan
On Tue, Jun 19, 2018 at 07:15:24PM +0530, Sricharan R wrote:
From: Stephen Boyd
Register
From: Stephen Boyd
HFPLLs are the main frequency source for Krait CPU clocks. Add
support for changing the rate of these PLLs.
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/Makefile| 1 +
drivers/clk/qcom/clk-hfpll.c | 244 +++
From: Stephen Boyd
HFPLLs are the main frequency source for Krait CPU clocks. Add
support for changing the rate of these PLLs.
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/Makefile| 1 +
drivers/clk/qcom/clk-hfpll.c | 244 +++
From: Stephen Boyd
Describe the HFPLLs present on IPQ806X devices.
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/gcc-ipq806x.c | 82 ++
1 file changed, 82 insertions(+)
diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
From: Stephen Boyd
Describe the HFPLLs present on IPQ806X devices.
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/gcc-ipq806x.c | 82 ++
1 file changed, 82 insertions(+)
diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
From: Stephen Boyd
The ACC and GCC regions present in KPSSv1 contain registers to
control clocks and power to each Krait CPU and L2. For CPUfreq
purposes probe these devices and expose a mux clock that chooses
between PXO and PLL8.
Cc:
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/Kconfig
From: Stephen Boyd
The ACC and GCC regions present in KPSSv1 contain registers to
control clocks and power to each Krait CPU and L2. For CPUfreq
purposes probe these devices and expose a mux clock that chooses
between PXO and PLL8.
Cc:
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/Kconfig
From: Stephen Boyd
The ACC and GCC regions present in KPSSv1 contain registers to
control clocks and power to each Krait CPU and L2. Documenting
the bindings here.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
---
[v10] Updated to add clocks and clock-names property newly
From: Stephen Boyd
The ACC and GCC regions present in KPSSv1 contain registers to
control clocks and power to each Krait CPU and L2. Documenting
the bindings here.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
---
[v10] Updated to add clocks and clock-names property newly
to the safe parent in the PRE_RATE_CHANGE notifier
and back to the original parent in the POST_RATE_CHANGE notifier.
Signed-off-by: Sricharan R
---
drivers/clk/qcom/clk-krait.c | 2 ++
drivers/clk/qcom/clk-krait.h | 3 +++
drivers/clk/qcom/krait-cc.c | 56
to the safe parent in the PRE_RATE_CHANGE notifier
and back to the original parent in the POST_RATE_CHANGE notifier.
Signed-off-by: Sricharan R
---
drivers/clk/qcom/clk-krait.c | 2 ++
drivers/clk/qcom/clk-krait.h | 3 +++
drivers/clk/qcom/krait-cc.c | 56
From: Stephen Boyd
Register a cpufreq-generic device whenever we detect that a
"qcom,krait" compatible CPU is present in DT.
Acked-by: Viresh Kumar
[Sricharan: updated to use dev_pm_opp_set_prop_name and
nvmem apis]
Signed-off-by: Sricharan R
[Thierry Escande: upd
From: Stephen Boyd
Register a cpufreq-generic device whenever we detect that a
"qcom,krait" compatible CPU is present in DT.
Acked-by: Viresh Kumar
[Sricharan: updated to use dev_pm_opp_set_prop_name and
nvmem apis]
Signed-off-by: Sricharan R
[Thierry Escande: upd
-cpufreq driver
reads the efuse value from the SoC to provide the required information
that is used to determine the voltage and current value for each OPP of
operating-points-v2 table when it is parsed by the OPP framework.
Reviewed-by: Rob Herring
Acked-by: Viresh Kumar
Signed-off-by: Sricharan
-cpufreq driver
reads the efuse value from the SoC to provide the required information
that is used to determine the voltage and current value for each OPP of
operating-points-v2 table when it is parsed by the OPP framework.
Reviewed-by: Rob Herring
Acked-by: Viresh Kumar
Signed-off-by: Sricharan
From: Stephen Boyd
The Krait clock controller controls the krait CPU and the L2 clocks
consisting a primary mux and secondary mux. Add document for that.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
---
[v10] updated to include clocks and clock-names property newly
From: Stephen Boyd
The Krait CPU clocks are made up of a primary mux and secondary
mux for each CPU and the L2, controlled via cp15 accessors. For
Kraits within KPSSv1 each secondary mux accepts a different aux
source, but on KPSSv2 each secondary mux accepts the same aux
source.
Cc:
From: Stephen Boyd
The Krait CPU clocks are made up of a primary mux and secondary
mux for each CPU and the L2, controlled via cp15 accessors. For
Kraits within KPSSv1 each secondary mux accepts a different aux
source, but on KPSSv2 each secondary mux accepts the same aux
source.
Cc:
From: Stephen Boyd
The Krait clock controller controls the krait CPU and the L2 clocks
consisting a primary mux and secondary mux. Add document for that.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
---
[v10] updated to include clocks and clock-names property newly
From: Stephen Boyd
The Krait clocks are made up of a series of muxes and a divider
that choose between a fixed rate clock and dedicated HFPLLs for
each CPU. Instead of using mmio accesses to remux parents, the
Krait implementation exposes the remux control via cp15
registers. Support these
From: Stephen Boyd
The Krait clocks are made up of a series of muxes and a divider
that choose between a fixed rate clock and dedicated HFPLLs for
each CPU. Instead of using mmio accesses to remux parents, the
Krait implementation exposes the remux control via cp15
registers. Support these
From: Stephen Boyd
Adds bindings document for qcom,hfpll instantiated within
the Krait processor subsystem as separate register region.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
---
[v10] Updated to add clocks and clock-names properties newly
From: Stephen Boyd
Describe the HFPLLs present on MSM8960 and APQ8064 devices.
Acked-by: Rob Herring (bindings)
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/gcc-msm8960.c | 172 +++
include/dt-bindings/clock/qcom,gcc-msm8960.h | 2 +
2 files
From: Stephen Boyd
Adds bindings document for qcom,hfpll instantiated within
the Krait processor subsystem as separate register region.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
---
[v10] Updated to add clocks and clock-names properties newly
From: Stephen Boyd
Describe the HFPLLs present on MSM8960 and APQ8064 devices.
Acked-by: Rob Herring (bindings)
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/gcc-msm8960.c | 172 +++
include/dt-bindings/clock/qcom,gcc-msm8960.h | 2 +
2 files
From: Stephen Boyd
On some devices (MSM8974 for example), the HFPLLs are
instantiated within the Krait processor subsystem as separate
register regions. Add a driver for these PLLs so that we can
provide HFPLL clocks for use by the system.
Cc:
Signed-off-by: Stephen Boyd
---
From: Stephen Boyd
On some devices (MSM8974 for example), the HFPLLs are
instantiated within the Krait processor subsystem as separate
register regions. Add a driver for these PLLs so that we can
provide HFPLL clocks for use by the system.
Cc:
Signed-off-by: Stephen Boyd
---
From: Stephen Boyd
Krait CPUs have a handful of L2 cache controller registers that
live behind a cp15 based indirection register. First you program
the indirection register (l2cpselr) to point the L2 'window'
register (l2cpdr) at what you want to read/write. Then you
read/write the 'window'
From: Stephen Boyd
Krait CPUs have a handful of L2 cache controller registers that
live behind a cp15 based indirection register. First you program
the indirection register (l2cpselr) to point the L2 'window'
register (l2cpdr) at what you want to read/write. Then you
read/write the 'window'
332615.html
[3] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/332608.html
[4] https://lwn.net/Articles/740994/
[5] https://lkml.org/lkml/2017/12/19/537
Sricharan R (2):
clk: qcom: Add safe switch hook for krait mux clocks
dt-bindings: cpufreq: Document operating-points-v2-kra
332615.html
[3] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/332608.html
[4] https://lwn.net/Articles/740994/
[5] https://lkml.org/lkml/2017/12/19/537
Sricharan R (2):
clk: qcom: Add safe switch hook for krait mux clocks
dt-bindings: cpufreq: Document operating-points-v2-kra
)
Signed-off-by: Sricharan R
[bjorn: Rewrote as a separate driver, intead of extending q6v5_pil.c]
Signed-off-by: Bjorn Andersson
---
[v2] Fixed Kconfig to remove SMD dependency and addressed
Vinod's comments.
.../devicetree/bindings/remoteproc/qcom,q6v5.txt | 7 +-
drivers/remoteproc
)
Signed-off-by: Sricharan R
[bjorn: Rewrote as a separate driver, intead of extending q6v5_pil.c]
Signed-off-by: Bjorn Andersson
---
[v2] Fixed Kconfig to remove SMD dependency and addressed
Vinod's comments.
.../devicetree/bindings/remoteproc/qcom,q6v5.txt | 7 +-
drivers/remoteproc
and wcss
> is y. Why don't we see link fail for glink being n? Yes I understand that
> platform uses wcss but am curious how that works out :)
For glink being n, the stub functions gets linked, and not for glink=m.
Regards,
Sricharan
--
"QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of
Code Aurora Forum, hosted by The Linux Foundation
---
This email has been checked for viruses by Avast antivirus software.
https://www.avast.com/antivirus
and wcss
> is y. Why don't we see link fail for glink being n? Yes I understand that
> platform uses wcss but am curious how that works out :)
For glink being n, the stub functions gets linked, and not for glink=m.
Regards,
Sricharan
--
"QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of
Code Aurora Forum, hosted by The Linux Foundation
---
This email has been checked for viruses by Avast antivirus software.
https://www.avast.com/antivirus
Hi Bjorn,
On 6/7/2018 11:18 AM, Bjorn Andersson wrote:
> On Wed 06 Jun 22:29 PDT 2018, Sricharan R wrote:
>
>> Hi Bjorn,
>>
>> On 6/7/2018 9:54 AM, Bjorn Andersson wrote:
>>> On Wed 06 Jun 21:11 PDT 2018, Vinod wrote:
>>>
>>>> On 06-06-18, 0
Hi Bjorn,
On 6/7/2018 11:18 AM, Bjorn Andersson wrote:
> On Wed 06 Jun 22:29 PDT 2018, Sricharan R wrote:
>
>> Hi Bjorn,
>>
>> On 6/7/2018 9:54 AM, Bjorn Andersson wrote:
>>> On Wed 06 Jun 21:11 PDT 2018, Vinod wrote:
>>>
>>>> On 06-06-18, 0
Hi Bjorn,
On 6/7/2018 9:54 AM, Bjorn Andersson wrote:
> On Wed 06 Jun 21:11 PDT 2018, Vinod wrote:
>
>> On 06-06-18, 09:17, Bjorn Andersson wrote:
>>> On Tue 05 Jun 05:56 PDT 2018, Sricharan R wrote:
>>>
>>>> Hi Vinod,
>>>>
>>&g
Hi Bjorn,
On 6/7/2018 9:54 AM, Bjorn Andersson wrote:
> On Wed 06 Jun 21:11 PDT 2018, Vinod wrote:
>
>> On 06-06-18, 09:17, Bjorn Andersson wrote:
>>> On Tue 05 Jun 05:56 PDT 2018, Sricharan R wrote:
>>>
>>>> Hi Vinod,
>>>>
>>&g
Hi Vinod,
On 6/6/2018 12:19 PM, Vinod wrote:
> Hi Sricharan,
>
> On 06-06-18, 12:09, Sricharan R wrote:
>
>>>>>> +config QCOM_Q6V5_WCSS
>>>>>> +tristate "Qualcomm Hexagon based WCSS Peripheral Image Loader"
>>>>>&
Hi Vinod,
On 6/6/2018 12:19 PM, Vinod wrote:
> Hi Sricharan,
>
> On 06-06-18, 12:09, Sricharan R wrote:
>
>>>>>> +config QCOM_Q6V5_WCSS
>>>>>> +tristate "Qualcomm Hexagon based WCSS Peripheral Image Loader"
>>>>>&
Hi Vinod,
On 6/5/2018 10:10 PM, Vinod Koul wrote:
> On 05-06-18, 18:26, Sricharan R wrote:
>> Hi Vinod,
>>
>> On 6/5/2018 11:49 AM, Vinod wrote:
>>> On 05-06-18, 11:12, Sricharan R wrote:
>>>
>>>> +config QCOM_Q6V5_WCSS
>>>> +
Hi Vinod,
On 6/5/2018 10:10 PM, Vinod Koul wrote:
> On 05-06-18, 18:26, Sricharan R wrote:
>> Hi Vinod,
>>
>> On 6/5/2018 11:49 AM, Vinod wrote:
>>> On 05-06-18, 11:12, Sricharan R wrote:
>>>
>>>> +config QCOM_Q6V5_WCSS
>>>> +
Hi Vinod,
On 6/5/2018 11:49 AM, Vinod wrote:
> On 05-06-18, 11:12, Sricharan R wrote:
>
>> +config QCOM_Q6V5_WCSS
>> +tristate "Qualcomm Hexagon based WCSS Peripheral Image Loader"
>> +depends on OF && ARCH_QCOM
>> +depend
Hi Vinod,
On 6/5/2018 11:49 AM, Vinod wrote:
> On 05-06-18, 11:12, Sricharan R wrote:
>
>> +config QCOM_Q6V5_WCSS
>> +tristate "Qualcomm Hexagon based WCSS Peripheral Image Loader"
>> +depends on OF && ARCH_QCOM
>> +depend
)
Signed-off-by: Sricharan R
[bjorn: Rewrote as a separate driver, intead of extending q6v5_pil.c]
Signed-off-by: Bjorn Andersson
---
Fixed review comments from Vinod.
Retained the reg read/update/write sequence instead of modify for
readability
In q6v5_wcss_powerdown SSCAON_CONFIG bits
)
Signed-off-by: Sricharan R
[bjorn: Rewrote as a separate driver, intead of extending q6v5_pil.c]
Signed-off-by: Bjorn Andersson
---
Fixed review comments from Vinod.
Retained the reg read/update/write sequence instead of modify for
readability
In q6v5_wcss_powerdown SSCAON_CONFIG bits
Hi Sibi,
On 6/1/2018 8:48 PM, Sibi S wrote:
> Hi Sricharan,
>
> On 06/01/2018 11:46 AM, Sricharan R wrote:
>> Hi Bjorn,
>> Thanks for this much needed consolidation.
>>
>> On 5/23/2018 10:50 AM, Bjorn Andersson wrote:
>>> Shared between all He
Hi Sibi,
On 6/1/2018 8:48 PM, Sibi S wrote:
> Hi Sricharan,
>
> On 06/01/2018 11:46 AM, Sricharan R wrote:
>> Hi Bjorn,
>> Thanks for this much needed consolidation.
>>
>> On 5/23/2018 10:50 AM, Bjorn Andersson wrote:
>>> Shared between all He
Hi Stephen,
On 5/31/2018 1:11 PM, Stephen Boyd wrote:
> Quoting Sricharan R (2018-05-30 21:57:20)
>> Hi Stephen,
>>
>> On 5/30/2018 9:25 PM, Stephen Boyd wrote:
>>> Quoting Sricharan R (2018-05-24 22:40:11)
>>>> Hi Bjorn,
>>>>
>>>>
Hi Stephen,
On 5/31/2018 1:11 PM, Stephen Boyd wrote:
> Quoting Sricharan R (2018-05-30 21:57:20)
>> Hi Stephen,
>>
>> On 5/30/2018 9:25 PM, Stephen Boyd wrote:
>>> Quoting Sricharan R (2018-05-24 22:40:11)
>>>> Hi Bjorn,
>>>>
>>>>
disable_irq(qproc->handover_irq);
> -
> - if (!qproc->proxy_unvoted) {
> + ret = qcom_q6v5_unprepare(>q6v5);
> + if (ret) {
> q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
> qproc->proxy_clk_count);
>
disable_irq(qproc->handover_irq);
> -
> - if (!qproc->proxy_unvoted) {
> + ret = qcom_q6v5_unprepare(>q6v5);
> + if (ret) {
> q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
> qproc->proxy_clk_count);
>
ret = adsp_request_irq(adsp, pdev, "ready", adsp_ready_interrupt);
> - if (ret < 0)
> - goto free_rproc;
> - adsp->ready_irq = ret;
> -
> - ret = adsp_request_irq(adsp, pdev, "handover", adsp_handover_interrupt);
> - if (ret < 0)
ret = adsp_request_irq(adsp, pdev, "ready", adsp_ready_interrupt);
> - if (ret < 0)
> - goto free_rproc;
> - adsp->ready_irq = ret;
> -
> - ret = adsp_request_irq(adsp, pdev, "handover", adsp_handover_interrupt);
> - if (ret < 0)
top state\n");
> + return PTR_ERR(q6v5->state);
> + }
> +
> + return 0;
> +}
> diff --git a/drivers/remoteproc/qcom_q6v5.h b/drivers/remoteproc/qcom_q6v5.h
> new file mode 100644
> index ..7ac92c1e0f49
> --- /dev/null
> +++
top state\n");
> + return PTR_ERR(q6v5->state);
> + }
> +
> + return 0;
> +}
> diff --git a/drivers/remoteproc/qcom_q6v5.h b/drivers/remoteproc/qcom_q6v5.h
> new file mode 100644
> index ..7ac92c1e0f49
> --- /dev/null
> +++
Hi Stephen,
On 5/30/2018 9:25 PM, Stephen Boyd wrote:
> Quoting Sricharan R (2018-05-24 22:40:11)
>> Hi Bjorn,
>>
>> On 5/24/2018 11:09 PM, Bjorn Andersson wrote:
>>> On Tue 06 Mar 06:38 PST 2018, Sricharan R wrote:
>>>
>>>> From: Stephen Bo
Hi Stephen,
On 5/30/2018 9:25 PM, Stephen Boyd wrote:
> Quoting Sricharan R (2018-05-24 22:40:11)
>> Hi Bjorn,
>>
>> On 5/24/2018 11:09 PM, Bjorn Andersson wrote:
>>> On Tue 06 Mar 06:38 PST 2018, Sricharan R wrote:
>>>
>>>> From: Stephen Bo
Hi Bjorn,
On 5/29/2018 9:37 AM, Bjorn Andersson wrote:
> On Wed 23 May 07:48 PDT 2018, Sricharan R wrote:
>> On 5/23/2018 1:07 PM, Vinod wrote:
>>> On 22-05-18, 23:58, Bjorn Andersson wrote:
>>>> On Tue 22 May 23:05 PDT 2018, Vinod wrote:
>>>>&
Hi Bjorn,
On 5/29/2018 9:37 AM, Bjorn Andersson wrote:
> On Wed 23 May 07:48 PDT 2018, Sricharan R wrote:
>> On 5/23/2018 1:07 PM, Vinod wrote:
>>> On 22-05-18, 23:58, Bjorn Andersson wrote:
>>>> On Tue 22 May 23:05 PDT 2018, Vinod wrote:
>>>>&
The driver/phy support for ipq8074 is available now.
So enabling the nodes in DT.
Reviewed-by: Abhishek Sahu <abs...@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.anders...@linaro.org>
Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
arch/arm64/boot/dts/qcom/
Reviewed-by: Abhishek Sahu <abs...@codeaurora.org>
Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts | 64 +
2 files changed, 65 insertions(+)
The driver/phy support for ipq8074 is available now.
So enabling the nodes in DT.
Reviewed-by: Abhishek Sahu
Acked-by: Bjorn Andersson
Signed-off-by: Sricharan R
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 157 +-
1 file changed, 156 insertions(+), 1 deletion
Reviewed-by: Abhishek Sahu
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts | 64 +
2 files changed, 65 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
Reviewed-by: Abhishek Sahu <abs...@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.anders...@linaro.org>
Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 54 +++
1 file changed, 54 insertions(+)
Reviewed-by: Abhishek Sahu <abs...@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.anders...@linaro.org>
Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq4019-ap.
Reviewed-by: Abhishek Sahu
Acked-by: Bjorn Andersson
Signed-off-by: Sricharan R
---
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 54 +++
1 file changed, 54 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
b/arch/arm64/boot/dts/qcom/ipq8074-hk01
Reviewed-by: Abhishek Sahu
Acked-by: Bjorn Andersson
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts | 25 +
2 files changed, 26 insertions(+)
create mode 100644 arch/arm/boot/dts
Add serial, i2c, bam, spi, qpic peripheral nodes.
While here, fix the PMU node's irq trigger to avoid
the boot warnings from GIC.
Reviewed-by: Abhishek Sahu <abs...@codeaurora.org>
Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
arch/arm64/boot/dts/qcom/ipq8074-hk
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