On 2018-03-20 13:04, Stephen Boyd wrote:
Quoting Sricharan R (2018-03-19 20:58:49)
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
new file mode 100644
index 000..871ac3f
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019
Hi Stephen,
On 2018-03-20 13:03, Stephen Boyd wrote:
Quoting Sricharan R (2018-03-19 20:58:47)
Reviewed-by: Abhishek Sahu <abs...@codeaurora.org>
That is an odd place for a reviewed-by tag.
oops, by mistake. will fix.
Adds missing memory, reserved-memory nodes.
Sign
Hi Stephen,
On 2018-03-20 13:03, Stephen Boyd wrote:
Quoting Sricharan R (2018-03-19 20:58:47)
Reviewed-by: Abhishek Sahu
That is an odd place for a reviewed-by tag.
oops, by mistake. will fix.
Adds missing memory, reserved-memory nodes.
Signed-off-by: Sricharan R
---
arch/arm
Reviewed-by: Abhishek Sahu <abs...@codeaurora.org>
Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts | 8
2 files changed, 9 insertions(+)
create mode 100644 arch/
Reviewed-by: Abhishek Sahu
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts | 8
2 files changed, 9 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
diff --git a/arch
Reviewed-by: Abhishek Sahu <abs...@codeaurora.org>
Adds missing memory, reserved-memory nodes.
Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 28 +++
1 file changed, 28 insertions(+)
diff --git a/a
Reviewed-by: Abhishek Sahu
Adds missing memory, reserved-memory nodes.
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 28 +++
1 file changed, 28 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
b/arch/arm/boot
Add the common parts for the dk04 boards.
Reviewed-by: Abhishek Sahu <abs...@codeaurora.org>
Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi | 129 ++
1 file changed, 129 insertions(+)
create mode 100
Add the common parts for the dk04 boards.
Reviewed-by: Abhishek Sahu
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi | 129 ++
1 file changed, 129 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
diff --git
Reviewed-by: Abhishek Sahu <abs...@codeaurora.org>
Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts | 65 +
2 files changed, 66 insertions(+)
Reviewed-by: Abhishek Sahu
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts | 65 +
2 files changed, 66 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
Reviewed-by: Abhishek Sahu <abs...@codeaurora.org>
Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts | 26 +
2 files changed, 27 insertions(+)
Reviewed-by: Abhishek Sahu
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts | 26 +
2 files changed, 27 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts
Reviewed-by: Abhishek Sahu <abs...@codeaurora.org>
Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 103 ++
1 file changed, 103 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
b/arc
Reviewed-by: Abhishek Sahu
Signed-off-by: Sricharan R
---
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 103 ++
1 file changed, 103 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
index 6a838b5
The driver/phy support for ipq8074 is available now.
So enabling the nodes in DT.
Reviewed-by: Abhishek Sahu <abs...@codeaurora.org>
Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 157 +-
1 file
The driver/phy support for ipq8074 is available now.
So enabling the nodes in DT.
Reviewed-by: Abhishek Sahu
Signed-off-by: Sricharan R
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 157 +-
1 file changed, 156 insertions(+), 1 deletion(-)
diff --git a/arch/arm64
Reviewed-by: Abhishek Sahu <abs...@codeaurora.org>
Add the common data for all dk07 based boards.
Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi | 83 +++
1 file changed, 83 insertions(+)
create mode
Reviewed-by: Abhishek Sahu
Add the common data for all dk07 based boards.
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi | 83 +++
1 file changed, 83 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi
diff
Add serial, i2c, bam, spi, qpic peripheral nodes.
Reviewed-by: Abhishek Sahu <abs...@codeaurora.org>
Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 105 ++
1 file changed, 105 insertions(+)
diff
Add serial, i2c, bam, spi, qpic peripheral nodes.
Reviewed-by: Abhishek Sahu
Signed-off-by: Sricharan R
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 105 ++
1 file changed, 105 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
b/arch/arm64/boot
Reviewed-by: Abhishek Sahu <abs...@codeaurora.org>
Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts | 20
2 files changed, 21 insertions(+)
create
Reviewed-by: Abhishek Sahu
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts | 20
2 files changed, 21 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
Add the compatible for ipq4019.
This does not need clocks to do scm calls.
Reviewed-by: Rob Herring <r...@kernel.org>
Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
Documentation/devicetree/bindings/firmware/qcom,scm.txt | 3 ++-
drivers/firmwar
Add the compatible for ipq4019.
This does not need clocks to do scm calls.
Reviewed-by: Rob Herring
Signed-off-by: Sricharan R
---
Documentation/devicetree/bindings/firmware/qcom,scm.txt | 3 ++-
drivers/firmware/qcom_scm.c | 3 +++
2 files changed, 5 insertions
* Based all patches on top of Andy's for-next branch
[V1]
* https://www.spinics.net/lists/arm-kernel/msg631318.html
Sricharan R (13):
firmware: qcom: scm: Add ipq4019 soc compatible
ARM: dts: ipq4019: Add a few peripheral nodes
ARM: dts: ipq4019: Change the max opp frequency
ARM: dts
Now with the driver updates for some peripherals being there,
add i2c, spi, pcie, bam, qpic-nand, scm nodes to enhance the available
peripheral support.
Reviewed-by: Abhishek Sahu <abs...@codeaurora.org>
Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
arch/arm/boot/dts/
* Based all patches on top of Andy's for-next branch
[V1]
* https://www.spinics.net/lists/arm-kernel/msg631318.html
Sricharan R (13):
firmware: qcom: scm: Add ipq4019 soc compatible
ARM: dts: ipq4019: Add a few peripheral nodes
ARM: dts: ipq4019: Change the max opp frequency
ARM: dts
Now with the driver updates for some peripherals being there,
add i2c, spi, pcie, bam, qpic-nand, scm nodes to enhance the available
peripheral support.
Reviewed-by: Abhishek Sahu
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 134
1
The max opp frequency is 716MHZ. So update that.
Reviewed-by: Abhishek Sahu <abs...@codeaurora.org>
Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/
The max opp frequency is 716MHZ. So update that.
Reviewed-by: Abhishek Sahu
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi
b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index
On 3/16/2018 3:55 PM, Abhishek Sahu wrote:
> On 2018-03-16 15:08, Sricharan R wrote:
>> Signed-off-by: Sricharan R <sricha...@codeaurora.org>
>> ---
>> arch/arm/boot/dts/Makefile | 1 +
>> arch/arm/boot/dts/q
On 3/16/2018 3:55 PM, Abhishek Sahu wrote:
> On 2018-03-16 15:08, Sricharan R wrote:
>> Signed-off-by: Sricharan R
>> ---
>> arch/arm/boot/dts/Makefile | 1 +
>> arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts | 65
>>
On 3/16/2018 4:17 PM, Abhishek Sahu wrote:
> On 2018-03-16 15:08, Sricharan R wrote:
>> Add serial, i2c, bam, spi, qpic peripheral nodes.
>>
>> Signed-off-by: Sricharan R <sricha...@codeaurora.org>
>> ---
>> arch
On 3/16/2018 4:17 PM, Abhishek Sahu wrote:
> On 2018-03-16 15:08, Sricharan R wrote:
>> Add serial, i2c, bam, spi, qpic peripheral nodes.
>>
>> Signed-off-by: Sricharan R
>> ---
>> arch/arm64/boot/dts/qcom/ipq8074.dtsi | 105
>> +++
Hi Abhishek,
On 3/16/2018 4:27 PM, Abhishek Sahu wrote:
> On 2018-03-16 15:08, Sricharan R wrote:
>> Signed-off-by: Sricharan R <sricha...@codeaurora.org>
>> ---
>> arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 103
>> ++
>> 1 fil
Hi Abhishek,
On 3/16/2018 4:27 PM, Abhishek Sahu wrote:
> On 2018-03-16 15:08, Sricharan R wrote:
>> Signed-off-by: Sricharan R
>> ---
>> arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 103
>> ++
>> 1 file changed, 103 insertions(+)
&
Hi Abhishek,
On 3/16/2018 4:50 PM, Abhishek Sahu wrote:
> On 2018-03-16 15:08, Sricharan R wrote:
>> The driver/phy support for ipq8074 is available now.
>> So enabling the nodes in DT.
>>
>> Signed-off-by: Sricharan R <sricha...@codeaurora.org>
>> ---
&g
Hi Abhishek,
On 3/16/2018 4:50 PM, Abhishek Sahu wrote:
> On 2018-03-16 15:08, Sricharan R wrote:
>> The driver/phy support for ipq8074 is available now.
>> So enabling the nodes in DT.
>>
>> Signed-off-by: Sricharan R
>> ---
>> arch
Hi Marc,
On 3/16/2018 5:47 PM, Marc Zyngier wrote:
> On 16/03/18 09:38, Sricharan R wrote:
>> Now with the driver updates for some peripherals being there,
>> add i2c, spi, pcie, bam, qpic-nand, scm nodes to enhance the available
>> peripheral support.
>>
>> S
Hi Marc,
On 3/16/2018 5:47 PM, Marc Zyngier wrote:
> On 16/03/18 09:38, Sricharan R wrote:
>> Now with the driver updates for some peripherals being there,
>> add i2c, spi, pcie, bam, qpic-nand, scm nodes to enhance the available
>> peripheral support.
>>
&g
The max opp frequency is 716MHZ. So update that.
Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi
b/arch/arm/boot/dts/qcom-ipq4019.dtsi
The max opp frequency is 716MHZ. So update that.
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi
b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index e38fffa..2ee71c2 100644
Add the common parts for the dk04 boards.
Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi | 129 ++
1 file changed, 129 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
diff
Add the common parts for the dk04 boards.
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi | 129 ++
1 file changed, 129 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
diff --git a/arch/arm/boot/dts/qcom
Add the common data for all dk07 based boards.
Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi | 83 +++
1 file changed, 83 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi
diff
Add the common data for all dk07 based boards.
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi | 83 +++
1 file changed, 83 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi
diff --git a/arch/arm/boot/dts/qcom
Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts | 26 +
2 files changed, 27 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts | 26 +
2 files changed, 27 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts
diff --git a/arch/arm/boot
Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 103 ++
1 file changed, 103 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
index 6a838b5..81
Signed-off-by: Sricharan R
---
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 103 ++
1 file changed, 103 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
index 6a838b5..81dff867 100644
--- a/arch/arm64
The driver/phy support for ipq8074 is available now.
So enabling the nodes in DT.
Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 157 +-
1 file changed, 156 insertions(+), 1 deletion(-)
diff --git a/arch
The driver/phy support for ipq8074 is available now.
So enabling the nodes in DT.
Signed-off-by: Sricharan R
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 157 +-
1 file changed, 156 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
Add serial, i2c, bam, spi, qpic peripheral nodes.
Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 105 ++
1 file changed, 105 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
b/arch/arm64/bo
Add serial, i2c, bam, spi, qpic peripheral nodes.
Signed-off-by: Sricharan R
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 105 ++
1 file changed, 105 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index
Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts | 65 +
2 files changed, 66 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts | 65 +
2 files changed, 66 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
diff --git a/arch/arm/boot
Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts | 20
2 files changed, 21 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts | 8
2 files changed, 9 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
diff --git
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts | 20
2 files changed, 21 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
diff --git a/arch/arm/boot/dts
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts | 8
2 files changed, 9 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch
Now with the driver updates for some peripherals being there,
add i2c, spi, pcie, bam, qpic-nand, scm nodes to enhance the available
peripheral support.
Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 134 +
Adds missing memory, reserved-memory nodes.
Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 28 +++
1 file changed, 28 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
b/arch/arm/bo
Now with the driver updates for some peripherals being there,
add i2c, spi, pcie, bam, qpic-nand, scm nodes to enhance the available
peripheral support.
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 134
1 file changed, 134 insertions
Adds missing memory, reserved-memory nodes.
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 28 +++
1 file changed, 28 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1
[v2]
* Addressed all comments from Abhishek
* Removed dk01-c2 and dk04-c5 spinand based boards
as support for spinand is not complete
* Based all patches on top of Andy's for-next branch
[V1]
* https://www.spinics.net/lists/arm-kernel/msg631318.html
Sricharan R (13
Add the compatible for ipq4019.
This does not need clocks to do scm calls.
Reviewed-by: Rob Herring <r...@kernel.org>
Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
Documentation/devicetree/bindings/firmware/qcom,scm.txt | 3 ++-
drivers/firmwar
[v2]
* Addressed all comments from Abhishek
* Removed dk01-c2 and dk04-c5 spinand based boards
as support for spinand is not complete
* Based all patches on top of Andy's for-next branch
[V1]
* https://www.spinics.net/lists/arm-kernel/msg631318.html
Sricharan R (13
Add the compatible for ipq4019.
This does not need clocks to do scm calls.
Reviewed-by: Rob Herring
Signed-off-by: Sricharan R
---
Documentation/devicetree/bindings/firmware/qcom,scm.txt | 3 ++-
drivers/firmware/qcom_scm.c | 3 +++
2 files changed, 5 insertions
t; BAM will generate the completion interrupt.
>
> Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
> ---
>
Reviewed-by: Sricharan R <sricha...@codeaurora.org>
Regards,
Sricharan
> * Changes from v1:
>
> 1. Modified commit message with more details
>
t; BAM will generate the completion interrupt.
>
> Signed-off-by: Abhishek Sahu
> ---
>
Reviewed-by: Sricharan R
Regards,
Sricharan
> * Changes from v1:
>
> 1. Modified commit message with more details
>
> drivers/i2c/busses/i2c-qup.c | 39
hedule each block separately. QUP v2 supports reconfiguration
>during run in which QUP can transfer multiple blocks without issuing a
>stop events.
> 7. Port the SMBus block read support for new code changes.
>
> Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
&g
hedule each block separately. QUP v2 supports reconfiguration
>during run in which QUP can transfer multiple blocks without issuing a
>stop events.
> 7. Port the SMBus block read support for new code changes.
>
> Signed-off-by: Abhishek Sahu
> ---
>
Reviewed-by: Srichar
EQ interrupts
>whenever it has block size of available data.
>
> Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
> ---
>
Reviewed-by: Sricharan R <sricha...@codeaurora.org>
Regards,
Sricharan
> * Changes from v1:
>
> 1. Fixed auto build test
EQ interrupts
>whenever it has block size of available data.
>
> Signed-off-by: Abhishek Sahu
> ---
>
Reviewed-by: Sricharan R
Regards,
Sricharan
> * Changes from v1:
>
> 1. Fixed auto build test WARNING ‘idx' may be used uninitialized
>in thi
ng has
been done already. Pull that logic out into reusable functions
that operate on an optional table and some flags so that other
drivers can use the same logic.
[Sricharan: Rebased for mainline]
Signed-off-by: Sricharan R <sricha...@codeaurora.org>
Signed-off-by: Stephen Boyd <sb...
that logic out into reusable functions
that operate on an optional table and some flags so that other
drivers can use the same logic.
[Sricharan: Rebased for mainline]
Signed-off-by: Sricharan R
Signed-off-by: Stephen Boyd
---
drivers/clk/clk-mux.c | 74
From: Stephen Boyd
Adds bindings document for qcom,hfpll instantiated within
the Krait processor subsystem as separate register region.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
---
From: Stephen Boyd
Adds bindings document for qcom,hfpll instantiated within
the Krait processor subsystem as separate register region.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
---
.../devicetree/bindings/clock/qcom,hfpll.txt | 46 ++
1 file changed, 46
From: Stephen Boyd
The ACC and GCC regions present in KPSSv1 contain registers to
control clocks and power to each Krait CPU and L2. For CPUfreq
purposes probe these devices and expose a mux clock that chooses
between PXO and PLL8.
Cc:
From: Stephen Boyd
Describe the HFPLLs present on MSM8960 and APQ8064 devices.
Acked-by: Rob Herring (bindings)
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/gcc-msm8960.c | 172 +++
From: Stephen Boyd
The ACC and GCC regions present in KPSSv1 contain registers to
control clocks and power to each Krait CPU and L2. For CPUfreq
purposes probe these devices and expose a mux clock that chooses
between PXO and PLL8.
Cc:
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/Kconfig
From: Stephen Boyd
Describe the HFPLLs present on MSM8960 and APQ8064 devices.
Acked-by: Rob Herring (bindings)
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/gcc-msm8960.c | 172 +++
include/dt-bindings/clock/qcom,gcc-msm8960.h | 2 +
2 files
From: Stephen Boyd <sb...@codeaurora.org>
Register a cpufreq-generic device whenever we detect that a
"qcom,krait" compatible CPU is present in DT.
Acked-by: Viresh Kumar <viresh.ku...@linaro.org>
[Sricharan: updated to use dev_pm_opp_set_prop_name and
From: Stephen Boyd
Register a cpufreq-generic device whenever we detect that a
"qcom,krait" compatible CPU is present in DT.
Acked-by: Viresh Kumar
[Sricharan: updated to use dev_pm_opp_set_prop_name and
nvmem apis]
Signed-off-by: Sricharan R
Signed-off-by: St
Kumar <viresh.ku...@linaro.org>
Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
.../devicetree/bindings/cpufreq/krait-cpufreq.txt | 363 +
1 file changed, 363 insertions(+)
create mode 100644 Documentation/devicetree/bindings/cpufreq/krait-cpufreq.txt
diff --g
-cpufreq driver
reads the efuse value from the SoC to provide the required information
that is used to determine the voltage and current value for each OPP of
operating-points-v2 table when it is parsed by the OPP framework.
Reviewed-by: Rob Herring
Acked-by: Viresh Kumar
Signed-off-by: Sricharan
to the safe parent in the PRE_RATE_CHANGE notifier
and back to the original parent in the POST_RATE_CHANGE notifier.
Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
drivers/clk/qcom/clk-krait.c | 2 ++
drivers/clk/qcom/clk-krait.h | 3 +++
drivers/clk/qcom/krait-cc.c
to the safe parent in the PRE_RATE_CHANGE notifier
and back to the original parent in the POST_RATE_CHANGE notifier.
Signed-off-by: Sricharan R
---
drivers/clk/qcom/clk-krait.c | 2 ++
drivers/clk/qcom/clk-krait.h | 3 +++
drivers/clk/qcom/krait-cc.c | 56
From: Stephen Boyd
The Krait clock controller controls the krait CPU and the L2 clocks
consisting a primary mux and secondary mux. Add document for that.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
---
From: Stephen Boyd
The Krait clock controller controls the krait CPU and the L2 clocks
consisting a primary mux and secondary mux. Add document for that.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
---
.../devicetree/bindings/clock/qcom,krait-cc.txt| 22 ++
1
From: Stephen Boyd
The Krait CPU clocks are made up of a primary mux and secondary
mux for each CPU and the L2, controlled via cp15 accessors. For
Kraits within KPSSv1 each secondary mux accepts a different aux
source, but on KPSSv2 each secondary mux accepts the same aux
From: Stephen Boyd
The Krait CPU clocks are made up of a primary mux and secondary
mux for each CPU and the L2, controlled via cp15 accessors. For
Kraits within KPSSv1 each secondary mux accepts a different aux
source, but on KPSSv2 each secondary mux accepts the same aux
source.
Cc:
From: Stephen Boyd
The ACC and GCC regions present in KPSSv1 contain registers to
control clocks and power to each Krait CPU and L2. Documenting
the bindings here.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
---
From: Stephen Boyd
The ACC and GCC regions present in KPSSv1 contain registers to
control clocks and power to each Krait CPU and L2. Documenting
the bindings here.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
---
.../devicetree/bindings/arm/msm/qcom,kpss-acc.txt | 7 +
From: Stephen Boyd
The Krait clocks are made up of a series of muxes and a divider
that choose between a fixed rate clock and dedicated HFPLLs for
each CPU. Instead of using mmio accesses to remux parents, the
Krait implementation exposes the remux control via cp15
From: Stephen Boyd
The Krait clocks are made up of a series of muxes and a divider
that choose between a fixed rate clock and dedicated HFPLLs for
each CPU. Instead of using mmio accesses to remux parents, the
Krait implementation exposes the remux control via cp15
registers. Support these
From: Stephen Boyd
Describe the HFPLLs present on IPQ806X devices.
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/gcc-ipq806x.c | 82 ++
1 file changed, 82 insertions(+)
diff --git
From: Stephen Boyd
Describe the HFPLLs present on IPQ806X devices.
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/gcc-ipq806x.c | 82 ++
1 file changed, 82 insertions(+)
diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
From: Stephen Boyd
On some devices (MSM8974 for example), the HFPLLs are
instantiated within the Krait processor subsystem as separate
register regions. Add a driver for these PLLs so that we can
provide HFPLL clocks for use by the system.
Cc:
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