Re: [PATCH 03/12] i2c: qup: remove redundant variables for BAM SG count

len, blocks, rem; > u32 i, tlen, tx_len, tx_buf = 0, rx_buf = 0, off = 0; > u8 *tags; > This is correct. Just a nit, may be rx/tx_buf can be changed to rx/tx_count to make it more clear. Regards, Sricharan -- "QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH 01/12] i2c: qup: fixed releasing dma without flush operation completion

ompletion(>xfer); > + > if (qup_i2c_change_state(qup, QUP_RUN_STATE)) { > dev_err(qup->dev, "change to run state timed out"); > goto desc_err; > Except for the above nit, Acked-by: Sricharan R <sricha...

Re: [PATCH 01/12] i2c: qup: fixed releasing dma without flush operation completion

> if (qup_i2c_change_state(qup, QUP_RUN_STATE)) { > dev_err(qup->dev, "change to run state timed out"); > goto desc_err; > Except for the above nit, Acked-by: Sricharan R Regards, Sricharan -- "QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH 12/15] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c2 board file

ev device. So the right probably is to have the additional pins required for the device populated under the spi's child node. >> +    }; >> +    }; >> + >> +    serial@78b { >> +    pinctrl-0 = <_1_pins>; >> +    pinctrl-names = "default"; >> +    status = "ok"; >> +    }; >> + >> +    spi_0: spi@78b5000 { /* BLSP1 QUP1 */ >> +    pinctrl-0 = <_0_pins>; >> +    pinctrl-names = "default"; >> +    status = "ok"; > >  From pinmux, it looks like multiple gpio based cs are being >  used so do we need to specify cs-gpios like dk01-c2. > ok, let me check. Regards, Sricharan -- "QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH 12/15] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c2 board file

ev device. So the right probably is to have the additional pins required for the device populated under the spi's child node. >> +    }; >> +    }; >> + >> +    serial@78b { >> +    pinctrl-0 = <_1_pins>; >> +    pinctrl-names = "default"; >> +    status = "ok"; >> +    }; >> + >> +    spi_0: spi@78b5000 { /* BLSP1 QUP1 */ >> +    pinctrl-0 = <_0_pins>; >> +    pinctrl-names = "default"; >> +    status = "ok"; > >  From pinmux, it looks like multiple gpio based cs are being >  used so do we need to specify cs-gpios like dk01-c2. > ok, let me check. Regards, Sricharan -- "QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH 09/15] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk04.1-c3 board file

Hi Abhishek, On 2/3/2018 5:07 PM, Abhishek Sahu wrote: > On 2018-01-29 10:41, Sricharan R wrote: >> Signed-off-by: Sricharan R <sricha...@codeaurora.org> >> --- >>  arch/arm/boot/dts/Makefile  |  1 + >>  arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1

Re: [PATCH 09/15] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk04.1-c3 board file

Hi Abhishek, On 2/3/2018 5:07 PM, Abhishek Sahu wrote: > On 2018-01-29 10:41, Sricharan R wrote: >> Signed-off-by: Sricharan R >> --- >>  arch/arm/boot/dts/Makefile  |  1 + >>  arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts | 14 +++

Re: [PATCH 07/15] ARM: dts: ipq4019: Add ipq4019-ap.dk04.1-c1 board file

Hi Abhishek, On 2/3/2018 5:00 PM, Abhishek Sahu wrote: > On 2018-01-29 10:41, Sricharan R wrote: >> Signed-off-by: Sricharan R <sricha...@codeaurora.org> >> --- >>  arch/arm/boot/dts/Makefile  | 1 + >>  arch/arm/boot/dts/qcom-ipq4019-ap.dk04.

Re: [PATCH 07/15] ARM: dts: ipq4019: Add ipq4019-ap.dk04.1-c1 board file

Hi Abhishek, On 2/3/2018 5:00 PM, Abhishek Sahu wrote: > On 2018-01-29 10:41, Sricharan R wrote: >> Signed-off-by: Sricharan R >> --- >>  arch/arm/boot/dts/Makefile  | 1 + >>  arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts | 8 >&g

Re: [PATCH 06/15] ARM: dts: ipq4019: Add ipq4019-ap.dk04.dtsi

Hi Abhishek, On 2/3/2018 4:47 PM, Abhishek Sahu wrote: > On 2018-01-29 10:41, Sricharan R wrote: >> Add the common parts for the dk04 boards. >> >> Signed-off-by: Sricharan R <sricha...@codeaurora.org> >> --- >>  arch/arm/boo

Re: [PATCH 06/15] ARM: dts: ipq4019: Add ipq4019-ap.dk04.dtsi

Hi Abhishek, On 2/3/2018 4:47 PM, Abhishek Sahu wrote: > On 2018-01-29 10:41, Sricharan R wrote: >> Add the common parts for the dk04 boards. >> >> Signed-off-by: Sricharan R >> --- >>  arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi | 147 > >   &g

Re: [PATCH 05/15] ARM: dts: ipq4019: Add ipq4019-ap-dk01-c2 board file

Hi Abhishek, On 2/3/2018 4:25 PM, Abhishek Sahu wrote: > On 2018-01-29 10:41, Sricharan R wrote: >> The board has a spi-nand interface on spi0 bus chipselect1. >> >> Signed-off-by: Sricharan R <sricha...@codeaurora.org> >> --- >>  arch/arm/boot/dts/Makefi

Re: [PATCH 05/15] ARM: dts: ipq4019: Add ipq4019-ap-dk01-c2 board file

Hi Abhishek, On 2/3/2018 4:25 PM, Abhishek Sahu wrote: > On 2018-01-29 10:41, Sricharan R wrote: >> The board has a spi-nand interface on spi0 bus chipselect1. >> >> Signed-off-by: Sricharan R >> --- >>  arch/arm/boot/dts/Makefile  |  1 + &

Re: [PATCH 01/15] firmware: qcom: scm: Add ipq4019 soc compatible

Hi Rob, On 2/5/2018 11:37 AM, Rob Herring wrote: > On Mon, Jan 29, 2018 at 10:41:15AM +0530, Sricharan R wrote: >> Add the compatible for ipq4019. >> This does not need clocks to do scm calls. >> >> Signed-off-by: Sricharan R <sricha...@codeaurora.org> >> --

Re: [PATCH 01/15] firmware: qcom: scm: Add ipq4019 soc compatible

Hi Rob, On 2/5/2018 11:37 AM, Rob Herring wrote: > On Mon, Jan 29, 2018 at 10:41:15AM +0530, Sricharan R wrote: >> Add the compatible for ipq4019. >> This does not need clocks to do scm calls. >> >> Signed-off-by: Sricharan R >> --- >> Documentation/device

Re: [PATCH v6 15/15] dt-bindings: cpufreq: Document operating-points-v2-krait-cpu

Hi Viresh, On 2/6/2018 9:57 AM, Viresh Kumar wrote: > On 06-02-18, 09:38, Sricharan R wrote: >> In Certain QCOM SoCs like ipq8064, apq8064, msm8960, msm8974 >> that has KRAIT processors the voltage/current value of each OPP >> varies based on the silicon variant in use. &

Re: [PATCH v6 15/15] dt-bindings: cpufreq: Document operating-points-v2-krait-cpu

Hi Viresh, On 2/6/2018 9:57 AM, Viresh Kumar wrote: > On 06-02-18, 09:38, Sricharan R wrote: >> In Certain QCOM SoCs like ipq8064, apq8064, msm8960, msm8974 >> that has KRAIT processors the voltage/current value of each OPP >> varies based on the silicon variant in use. &

Re: [PATCH v6 14/15] cpufreq: Add module to register cpufreq on Krait CPUs

Hi Viresh, On 2/6/2018 9:56 AM, Viresh Kumar wrote: > On 06-02-18, 09:38, Sricharan R wrote: >> diff --git a/drivers/cpufreq/qcom-cpufreq.c b/drivers/cpufreq/qcom-cpufreq.c >> new file mode 100644 >> index 000..5b988d4 >> --- /dev/null >> +++ b/drivers/cpufreq

Re: [PATCH v6 14/15] cpufreq: Add module to register cpufreq on Krait CPUs

Hi Viresh, On 2/6/2018 9:56 AM, Viresh Kumar wrote: > On 06-02-18, 09:38, Sricharan R wrote: >> diff --git a/drivers/cpufreq/qcom-cpufreq.c b/drivers/cpufreq/qcom-cpufreq.c >> new file mode 100644 >> index 000..5b988d4 >> --- /dev/null >> +++ b/drivers/cpufreq

[PATCH v6 11/15] clk: qcom: Add Krait clock controller driver

From: Stephen Boyd The Krait CPU clocks are made up of a primary mux and secondary mux for each CPU and the L2, controlled via cp15 accessors. For Kraits within KPSSv1 each secondary mux accepts a different aux source, but on KPSSv2 each secondary mux accepts the same aux

[PATCH v6 10/15] dt-bindings: arm: Document qcom,kpss-gcc

From: Stephen Boyd The ACC and GCC regions present in KPSSv1 contain registers to control clocks and power to each Krait CPU and L2. Documenting the bindings here. Reviewed-by: Rob Herring Signed-off-by: Stephen Boyd ---

[PATCH v6 11/15] clk: qcom: Add Krait clock controller driver

From: Stephen Boyd The Krait CPU clocks are made up of a primary mux and secondary mux for each CPU and the L2, controlled via cp15 accessors. For Kraits within KPSSv1 each secondary mux accepts a different aux source, but on KPSSv2 each secondary mux accepts the same aux source. Cc:

[PATCH v6 10/15] dt-bindings: arm: Document qcom,kpss-gcc

From: Stephen Boyd The ACC and GCC regions present in KPSSv1 contain registers to control clocks and power to each Krait CPU and L2. Documenting the bindings here. Reviewed-by: Rob Herring Signed-off-by: Stephen Boyd --- .../devicetree/bindings/arm/msm/qcom,kpss-acc.txt | 7 +

[PATCH v6 13/15] clk: qcom: Add safe switch hook for krait mux clocks

to the safe parent in the PRE_RATE_CHANGE notifier and back to the original parent in the POST_RATE_CHANGE notifier. Signed-off-by: Sricharan R <sricha...@codeaurora.org> --- drivers/clk/qcom/clk-krait.c | 2 ++ drivers/clk/qcom/clk-krait.h | 3 +++ drivers/clk/qcom/krait-cc.c

[PATCH v6 15/15] dt-bindings: cpufreq: Document operating-points-v2-krait-cpu

-cpufreq driver reads the efuse value from the SoC to provide the required information that is used to determine the voltage and current value for each OPP of operating-points-v2 table when it is parsed by the OPP framework. Signed-off-by: Sricharan R <sricha...@codeaurora.org> --- .../devi

[PATCH v6 12/15] dt-bindings: clock: Document qcom,krait-cc

From: Stephen Boyd The Krait clock controller controls the krait CPU and the L2 clocks consisting a primary mux and secondary mux. Add document for that. Reviewed-by: Rob Herring Signed-off-by: Stephen Boyd ---

[PATCH v6 14/15] cpufreq: Add module to register cpufreq on Krait CPUs

From: Stephen Boyd <sb...@codeaurora.org> Register a cpufreq-generic device whenever we detect that a "qcom,krait" compatible CPU is present in DT. Cc: <devicet...@vger.kernel.org> [Sricharan: updated to use dev_pm_opp_set_prop_name, NVMEM apis, new binding] Si

[PATCH v6 13/15] clk: qcom: Add safe switch hook for krait mux clocks

to the safe parent in the PRE_RATE_CHANGE notifier and back to the original parent in the POST_RATE_CHANGE notifier. Signed-off-by: Sricharan R --- drivers/clk/qcom/clk-krait.c | 2 ++ drivers/clk/qcom/clk-krait.h | 3 +++ drivers/clk/qcom/krait-cc.c | 56

[PATCH v6 15/15] dt-bindings: cpufreq: Document operating-points-v2-krait-cpu

-cpufreq driver reads the efuse value from the SoC to provide the required information that is used to determine the voltage and current value for each OPP of operating-points-v2 table when it is parsed by the OPP framework. Signed-off-by: Sricharan R --- .../devicetree/bindings/cpufreq/krait

[PATCH v6 12/15] dt-bindings: clock: Document qcom,krait-cc

From: Stephen Boyd The Krait clock controller controls the krait CPU and the L2 clocks consisting a primary mux and secondary mux. Add document for that. Reviewed-by: Rob Herring Signed-off-by: Stephen Boyd --- .../devicetree/bindings/clock/qcom,krait-cc.txt| 22 ++ 1

[PATCH v6 14/15] cpufreq: Add module to register cpufreq on Krait CPUs

From: Stephen Boyd Register a cpufreq-generic device whenever we detect that a "qcom,krait" compatible CPU is present in DT. Cc: [Sricharan: updated to use dev_pm_opp_set_prop_name, NVMEM apis, new binding] Signed-off-by: Sricharan R Signed-off-by: Stephen Boyd --

[PATCH v6 04/15] clk: qcom: Add HFPLL driver

From: Stephen Boyd On some devices (MSM8974 for example), the HFPLLs are instantiated within the Krait processor subsystem as separate register regions. Add a driver for these PLLs so that we can provide HFPLL clocks for use by the system. Cc:

[PATCH v6 04/15] clk: qcom: Add HFPLL driver

From: Stephen Boyd On some devices (MSM8974 for example), the HFPLLs are instantiated within the Krait processor subsystem as separate register regions. Add a driver for these PLLs so that we can provide HFPLL clocks for use by the system. Cc: Signed-off-by: Stephen Boyd ---

[PATCH v6 07/15] clk: qcom: Add IPQ806X's HFPLLs

From: Stephen Boyd Describe the HFPLLs present on IPQ806X devices. Signed-off-by: Stephen Boyd --- drivers/clk/qcom/gcc-ipq806x.c | 82 ++ 1 file changed, 82 insertions(+) diff --git

[PATCH v6 07/15] clk: qcom: Add IPQ806X's HFPLLs

From: Stephen Boyd Describe the HFPLLs present on IPQ806X devices. Signed-off-by: Stephen Boyd --- drivers/clk/qcom/gcc-ipq806x.c | 82 ++ 1 file changed, 82 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c

[PATCH v6 06/15] clk: qcom: Add MSM8960/APQ8064's HFPLLs

From: Stephen Boyd Describe the HFPLLs present on MSM8960 and APQ8064 devices. Acked-by: Rob Herring (bindings) Signed-off-by: Stephen Boyd --- drivers/clk/qcom/gcc-msm8960.c | 172 +++

[PATCH v6 09/15] clk: qcom: Add KPSS ACC/GCC driver

From: Stephen Boyd The ACC and GCC regions present in KPSSv1 contain registers to control clocks and power to each Krait CPU and L2. For CPUfreq purposes probe these devices and expose a mux clock that chooses between PXO and PLL8. Cc:

[PATCH v6 06/15] clk: qcom: Add MSM8960/APQ8064's HFPLLs

From: Stephen Boyd Describe the HFPLLs present on MSM8960 and APQ8064 devices. Acked-by: Rob Herring (bindings) Signed-off-by: Stephen Boyd --- drivers/clk/qcom/gcc-msm8960.c | 172 +++ include/dt-bindings/clock/qcom,gcc-msm8960.h | 2 + 2 files

[PATCH v6 09/15] clk: qcom: Add KPSS ACC/GCC driver

From: Stephen Boyd The ACC and GCC regions present in KPSSv1 contain registers to control clocks and power to each Krait CPU and L2. For CPUfreq purposes probe these devices and expose a mux clock that chooses between PXO and PLL8. Cc: Signed-off-by: Stephen Boyd --- drivers/clk/qcom/Kconfig

[PATCH v6 08/15] clk: qcom: Add support for Krait clocks

From: Stephen Boyd The Krait clocks are made up of a series of muxes and a divider that choose between a fixed rate clock and dedicated HFPLLs for each CPU. Instead of using mmio accesses to remux parents, the Krait implementation exposes the remux control via cp15

[PATCH v6 08/15] clk: qcom: Add support for Krait clocks

From: Stephen Boyd The Krait clocks are made up of a series of muxes and a divider that choose between a fixed rate clock and dedicated HFPLLs for each CPU. Instead of using mmio accesses to remux parents, the Krait implementation exposes the remux control via cp15 registers. Support these

[PATCH v6 03/15] clk: qcom: Add support for High-Frequency PLLs (HFPLLs)

From: Stephen Boyd HFPLLs are the main frequency source for Krait CPU clocks. Add support for changing the rate of these PLLs. Signed-off-by: Stephen Boyd --- drivers/clk/qcom/Makefile| 1 + drivers/clk/qcom/clk-hfpll.c | 244

[PATCH v6 03/15] clk: qcom: Add support for High-Frequency PLLs (HFPLLs)

From: Stephen Boyd HFPLLs are the main frequency source for Krait CPU clocks. Add support for changing the rate of these PLLs. Signed-off-by: Stephen Boyd --- drivers/clk/qcom/Makefile| 1 + drivers/clk/qcom/clk-hfpll.c | 244 +++

[PATCH v6 05/15] dt-bindings: clock: Document qcom,hfpll

From: Stephen Boyd Adds bindings document for qcom,hfpll instantiated within the Krait processor subsystem as separate register region. Reviewed-by: Rob Herring Signed-off-by: Stephen Boyd ---

[PATCH v6 05/15] dt-bindings: clock: Document qcom,hfpll

From: Stephen Boyd Adds bindings document for qcom,hfpll instantiated within the Krait processor subsystem as separate register region. Reviewed-by: Rob Herring Signed-off-by: Stephen Boyd --- .../devicetree/bindings/clock/qcom,hfpll.txt | 46 ++ 1 file changed, 46

[PATCH v6 01/15] ARM: Add Krait L2 register accessor functions

From: Stephen Boyd Krait CPUs have a handful of L2 cache controller registers that live behind a cp15 based indirection register. First you program the indirection register (l2cpselr) to point the L2 'window' register (l2cpdr) at what you want to read/write. Then you

[PATCH v6 01/15] ARM: Add Krait L2 register accessor functions

From: Stephen Boyd Krait CPUs have a handful of L2 cache controller registers that live behind a cp15 based indirection register. First you program the indirection register (l2cpselr) to point the L2 'window' register (l2cpdr) at what you want to read/write. Then you read/write the 'window'

[PATCH v6 02/15] clk: mux: Split out register accessors for reuse

ng has been done already. Pull that logic out into reusable functions that operate on an optional table and some flags so that other drivers can use the same logic. [Sricharan: Rebased for mainline] Signed-off-by: Sricharan R <sricha...@codeaurora.org> Signed-off-by: Stephen Boyd <sb...

[PATCH v6 02/15] clk: mux: Split out register accessors for reuse

that logic out into reusable functions that operate on an optional table and some flags so that other drivers can use the same logic. [Sricharan: Rebased for mainline] Signed-off-by: Sricharan R Signed-off-by: Stephen Boyd --- drivers/clk/clk-mux.c| 75

[PATCH v6 00/15] [v6] Krait clocks + Krait CPUfreq

el/2015-March/332615.html [3] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/332608.html [4] https://lwn.net/Articles/740994/ [5] https://lkml.org/lkml/2017/12/19/537 Sricharan R (2): clk: qcom: Add safe switch hook for krait mux clocks dt-bindings: cpufreq: Document operating

[PATCH v6 00/15] [v6] Krait clocks + Krait CPUfreq

el/2015-March/332615.html [3] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/332608.html [4] https://lwn.net/Articles/740994/ [5] https://lkml.org/lkml/2017/12/19/537 Sricharan R (2): clk: qcom: Add safe switch hook for krait mux clocks dt-bindings: cpufreq: Document operating

Re: [PATCH v6 4/6] iommu/arm-smmu: Add the device_link between masters and smmu

Hi Robin, On 2/2/2018 5:01 PM, Robin Murphy wrote: > On 02/02/18 05:40, Sricharan R wrote: >> Hi Robin/Vivek, >> >> On 2/1/2018 2:23 PM, Vivek Gautam wrote: >>> Hi, >>> >>> >>> On 1/31/2018 6:39 PM, Robin Murphy wrote: >>>> O

Re: [PATCH v6 4/6] iommu/arm-smmu: Add the device_link between masters and smmu

Hi Robin, On 2/2/2018 5:01 PM, Robin Murphy wrote: > On 02/02/18 05:40, Sricharan R wrote: >> Hi Robin/Vivek, >> >> On 2/1/2018 2:23 PM, Vivek Gautam wrote: >>> Hi, >>> >>> >>> On 1/31/2018 6:39 PM, Robin Murphy wrote: >>&g

Re: [PATCH v6 4/6] iommu/arm-smmu: Add the device_link between masters and smmu

Hi Robin/Vivek, On 2/1/2018 2:23 PM, Vivek Gautam wrote: > Hi, > > > On 1/31/2018 6:39 PM, Robin Murphy wrote: >> On 19/01/18 11:43, Vivek Gautam wrote: >>> From: Sricharan R <sricha...@codeaurora.org> >>> >>> Finally add the device link betwe

Re: [PATCH v6 4/6] iommu/arm-smmu: Add the device_link between masters and smmu

Hi Robin/Vivek, On 2/1/2018 2:23 PM, Vivek Gautam wrote: > Hi, > > > On 1/31/2018 6:39 PM, Robin Murphy wrote: >> On 19/01/18 11:43, Vivek Gautam wrote: >>> From: Sricharan R >>> >>> Finally add the device link between the master device and &g

Re: [PATCH v6 3/6] iommu/arm-smmu: Invoke pm_runtime during probe, add/remove device

Hi Robin, On 1/31/2018 6:36 PM, Robin Murphy wrote: > On 19/01/18 11:43, Vivek Gautam wrote: >> From: Sricharan R <sricha...@codeaurora.org> >> >> The smmu device probe/remove and add/remove master device callbacks >> gets called when the smmu is not link

Re: [PATCH v6 3/6] iommu/arm-smmu: Invoke pm_runtime during probe, add/remove device

Hi Robin, On 1/31/2018 6:36 PM, Robin Murphy wrote: > On 19/01/18 11:43, Vivek Gautam wrote: >> From: Sricharan R >> >> The smmu device probe/remove and add/remove master device callbacks >> gets called when the smmu is not linked to its master, that is without &

[PATCH 02/15] ARM: dts: ipq4019: Add a few peripheral nodes

Now with the driver updates for some peripherals being there, add i2c, spi, pcie, bam, qpic-nand, scm nodes to enhance the available peripheral support. Signed-off-by: Sricharan R <sricha...@codeaurora.org> --- arch/arm/boot/dts/qcom-ipq4019.dtsi | 134 +

[PATCH 02/15] ARM: dts: ipq4019: Add a few peripheral nodes

Now with the driver updates for some peripherals being there, add i2c, spi, pcie, bam, qpic-nand, scm nodes to enhance the available peripheral support. Signed-off-by: Sricharan R --- arch/arm/boot/dts/qcom-ipq4019.dtsi | 134 1 file changed, 134 insertions

[PATCH 01/15] firmware: qcom: scm: Add ipq4019 soc compatible

Add the compatible for ipq4019. This does not need clocks to do scm calls. Signed-off-by: Sricharan R <sricha...@codeaurora.org> --- Documentation/devicetree/bindings/firmware/qcom,scm.txt | 3 ++- drivers/firmware/qcom_scm.c | 3 +++ 2 files changed, 5 inse

[PATCH 01/15] firmware: qcom: scm: Add ipq4019 soc compatible

Add the compatible for ipq4019. This does not need clocks to do scm calls. Signed-off-by: Sricharan R --- Documentation/devicetree/bindings/firmware/qcom,scm.txt | 3 ++- drivers/firmware/qcom_scm.c | 3 +++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git

[PATCH 08/15] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk04.1-c5 board file

dk04.1-c5 has a spinand connected to spi bus0 chipselect 1. Signed-off-by: Sricharan R <sricha...@codeaurora.org> --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c5.dts | 23 +++ 2 files changed, 24 insertions(+)

[PATCH 08/15] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk04.1-c5 board file

dk04.1-c5 has a spinand connected to spi bus0 chipselect 1. Signed-off-by: Sricharan R --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c5.dts | 23 +++ 2 files changed, 24 insertions(+) create mode 100644 arch/arm/boot

[PATCH 05/15] ARM: dts: ipq4019: Add ipq4019-ap-dk01-c2 board file

The board has a spi-nand interface on spi0 bus chipselect1. Signed-off-by: Sricharan R <sricha...@codeaurora.org> --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c2.dts | 25 + 2 files changed, 26 insertions(+)

[PATCH 05/15] ARM: dts: ipq4019: Add ipq4019-ap-dk01-c2 board file

The board has a spi-nand interface on spi0 bus chipselect1. Signed-off-by: Sricharan R --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c2.dts | 25 + 2 files changed, 26 insertions(+) create mode 100644 arch/arm/boot

[PATCH 13/15] ARM: dts: ipq8074: Add peripheral nodes

Add serial, i2c, bam, spi, qpic peripheral nodes. Signed-off-by: Sricharan R <sricha...@codeaurora.org> --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 103 ++ 1 file changed, 103 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/bo

[PATCH 10/15] ARM: dts: ipq4019: Add ipq4019-ap.dk07.1 common data

Add the common data for all dk07 based boards. Signed-off-by: Sricharan R <sricha...@codeaurora.org> --- arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi | 128 ++ 1 file changed, 128 insertions(+) create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi diff

[PATCH 13/15] ARM: dts: ipq8074: Add peripheral nodes

Add serial, i2c, bam, spi, qpic peripheral nodes. Signed-off-by: Sricharan R --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 103 ++ 1 file changed, 103 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index

[PATCH 10/15] ARM: dts: ipq4019: Add ipq4019-ap.dk07.1 common data

Add the common data for all dk07 based boards. Signed-off-by: Sricharan R --- arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi | 128 ++ 1 file changed, 128 insertions(+) create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi diff --git a/arch/arm/boot/dts/qcom

[PATCH 12/15] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c2 board file

Signed-off-by: Sricharan R <sricha...@codeaurora.org> --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts | 78 + 2 files changed, 79 insertions(+) create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-

[PATCH 12/15] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c2 board file

Signed-off-by: Sricharan R --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts | 78 + 2 files changed, 79 insertions(+) create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts diff --git a/arch/arm/boot

[PATCH 09/15] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk04.1-c3 board file

Signed-off-by: Sricharan R <sricha...@codeaurora.org> --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts | 14 ++ 2 files changed, 15 insertions(+) create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts diff

[PATCH 11/15] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c1 board file

Signed-off-by: Sricharan R <sricha...@codeaurora.org> --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts | 60 + 2 files changed, 61 insertions(+) create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-

[PATCH 07/15] ARM: dts: ipq4019: Add ipq4019-ap.dk04.1-c1 board file

Signed-off-by: Sricharan R <sricha...@codeaurora.org> --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts | 8 2 files changed, 9 insertions(+) create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts diff --git

[PATCH 14/15] ARM: dts: ipq8074: Add pcie nodes

The driver/phy support for ipq8074 is available now. So enabling the nodes in DT. Signed-off-by: Sricharan R <sricha...@codeaurora.org> --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 155 +- 1 file changed, 154 insertions(+), 1 deletion(-) diff --git a/arch

[PATCH 09/15] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk04.1-c3 board file

Signed-off-by: Sricharan R --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts | 14 ++ 2 files changed, 15 insertions(+) create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts diff --git a/arch/arm/boot/dts

[PATCH 11/15] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c1 board file

Signed-off-by: Sricharan R --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts | 60 + 2 files changed, 61 insertions(+) create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts diff --git a/arch/arm/boot

[PATCH 07/15] ARM: dts: ipq4019: Add ipq4019-ap.dk04.1-c1 board file

Signed-off-by: Sricharan R --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts | 8 2 files changed, 9 insertions(+) create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts diff --git a/arch/arm/boot/dts/Makefile b/arch

[PATCH 14/15] ARM: dts: ipq8074: Add pcie nodes

The driver/phy support for ipq8074 is available now. So enabling the nodes in DT. Signed-off-by: Sricharan R --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 155 +- 1 file changed, 154 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi

[PATCH 15/15] ARM: dts: ipq8074: Enable few peripherals for hk01 board

Signed-off-by: Sricharan R <sricha...@codeaurora.org> --- arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 99 +++ 1 file changed, 99 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts index 6a838b5..6

[PATCH 06/15] ARM: dts: ipq4019: Add ipq4019-ap.dk04.dtsi

Add the common parts for the dk04 boards. Signed-off-by: Sricharan R <sricha...@codeaurora.org> --- arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi | 147 ++ 1 file changed, 147 insertions(+) create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi diff

[PATCH 15/15] ARM: dts: ipq8074: Enable few peripherals for hk01 board

Signed-off-by: Sricharan R --- arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 99 +++ 1 file changed, 99 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts index 6a838b5..69a1b0c 100644 --- a/arch/arm64/boot

[PATCH 06/15] ARM: dts: ipq4019: Add ipq4019-ap.dk04.dtsi

Add the common parts for the dk04 boards. Signed-off-by: Sricharan R --- arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi | 147 ++ 1 file changed, 147 insertions(+) create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi diff --git a/arch/arm/boot/dts/qcom

[PATCH 04/15] ARM: dts: ipq4019: Update ipq4019-dk01.1 board data

Adds missing memory and reserved-memory node. Signed-off-by: Sricharan R <sricha...@codeaurora.org> --- arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 28 +++ 1 file changed, 28 insertions(+) diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi b/arch/ar

[PATCH 04/15] ARM: dts: ipq4019: Update ipq4019-dk01.1 board data

Adds missing memory and reserved-memory node. Signed-off-by: Sricharan R --- arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 28 +++ 1 file changed, 28 insertions(+) diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1

[PATCH 03/15] ARM: dts: ipq4019: Change the max opp frequency

The max opp frequency is 716MHZ. So update that. Signed-off-by: Sricharan R <sricha...@codeaurora.org> --- arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi

[PATCH 03/15] ARM: dts: ipq4019: Change the max opp frequency

The max opp frequency is 716MHZ. So update that. Signed-off-by: Sricharan R --- arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index e38fffa..2ee71c2 100644

[PATCH 00/15] ARM: dts: ipq: updates to enable a few peripherals

The driver support for ipq based platform's spi, i2c, nand, spi-nor, pcie is available now. So update the dts to enable those peripherals. Sricharan R (15): firmware: qcom: scm: Add ipq soc compatibles ARM: dts: ipq4019: Add a few peripheral nodes ARM: dts: ipq4019: Change the max opp

[PATCH 00/15] ARM: dts: ipq: updates to enable a few peripherals

The driver support for ipq based platform's spi, i2c, nand, spi-nor, pcie is available now. So update the dts to enable those peripherals. Sricharan R (15): firmware: qcom: scm: Add ipq soc compatibles ARM: dts: ipq4019: Add a few peripheral nodes ARM: dts: ipq4019: Change the max opp

Re: [PATCH v5 15/15] devicetree: bindings: Document qcom,pvs

Hi Rob, On 12/26/2017 11:06 PM, Rob Herring wrote: > On Thu, Dec 21, 2017 at 5:53 AM, Sricharan R <sricha...@codeaurora.org> wrote: >> Hi Rob, >> >> On 12/21/2017 2:48 AM, Rob Herring wrote: >>> On Wed, Dec 20, 2017 at 11:55:33AM +0530, Sricharan R wrote: >&

Re: [PATCH v5 15/15] devicetree: bindings: Document qcom,pvs

Hi Rob, On 12/26/2017 11:06 PM, Rob Herring wrote: > On Thu, Dec 21, 2017 at 5:53 AM, Sricharan R wrote: >> Hi Rob, >> >> On 12/21/2017 2:48 AM, Rob Herring wrote: >>> On Wed, Dec 20, 2017 at 11:55:33AM +0530, Sricharan R wrote: >>>> Hi Viresh, >>&

Re: [PATCH v5 15/15] devicetree: bindings: Document qcom,pvs

Hi Rob, On 12/21/2017 2:48 AM, Rob Herring wrote: > On Wed, Dec 20, 2017 at 11:55:33AM +0530, Sricharan R wrote: >> Hi Viresh, >> >> On 12/20/2017 8:56 AM, Viresh Kumar wrote: >>> On 19-12-17, 21:25, Sricharan R wrote: >>>> + cpu@0

Re: [PATCH v5 15/15] devicetree: bindings: Document qcom,pvs

Hi Rob, On 12/21/2017 2:48 AM, Rob Herring wrote: > On Wed, Dec 20, 2017 at 11:55:33AM +0530, Sricharan R wrote: >> Hi Viresh, >> >> On 12/20/2017 8:56 AM, Viresh Kumar wrote: >>> On 19-12-17, 21:25, Sricharan R wrote: >>>> + cpu@0

Re: [PATCH v5 12/15] devicetree: bindings: Document qcom,krait-cc

On 12/21/2017 2:44 AM, Rob Herring wrote: > On Tue, Dec 19, 2017 at 09:24:57PM +0530, Sricharan R wrote: >> From: Stephen Boyd <sb...@codeaurora.org> >> >> The Krait clock controller controls the krait CPU and the L2 clocks >> consisting a primary mu

Re: [PATCH v5 12/15] devicetree: bindings: Document qcom,krait-cc

On 12/21/2017 2:44 AM, Rob Herring wrote: > On Tue, Dec 19, 2017 at 09:24:57PM +0530, Sricharan R wrote: >> From: Stephen Boyd >> >> The Krait clock controller controls the krait CPU and the L2 clocks >> consisting a primary mux and secondary mux. Add document

Re: [PATCH v5 10/15] devicetree: bindings: Document qcom,kpss-gcc

On 12/21/2017 2:43 AM, Rob Herring wrote: > On Tue, Dec 19, 2017 at 09:24:55PM +0530, Sricharan R wrote: >> From: Stephen Boyd <sb...@codeaurora.org> >> >> The ACC and GCC regions present in KPSSv1 contain registers to >> control clocks and power to e

Re: [PATCH v5 10/15] devicetree: bindings: Document qcom,kpss-gcc

On 12/21/2017 2:43 AM, Rob Herring wrote: > On Tue, Dec 19, 2017 at 09:24:55PM +0530, Sricharan R wrote: >> From: Stephen Boyd >> >> The ACC and GCC regions present in KPSSv1 contain registers to >> control clocks and power to each Krait CPU and L2. Docum

Re: [PATCH v5 05/15] devicetree: bindings: Document qcom,hfpll

Hi Rob, On 12/21/2017 2:41 AM, Rob Herring wrote: > On Tue, Dec 19, 2017 at 09:24:50PM +0530, Sricharan R wrote: >> From: Stephen Boyd <sb...@codeaurora.org> >> >> Adds bindings document for qcom,hfpll instantiated within >> the Krait processor subsystem as separ

Re: [PATCH v5 05/15] devicetree: bindings: Document qcom,hfpll

Hi Rob, On 12/21/2017 2:41 AM, Rob Herring wrote: > On Tue, Dec 19, 2017 at 09:24:50PM +0530, Sricharan R wrote: >> From: Stephen Boyd >> >> Adds bindings document for qcom,hfpll instantiated within >> the Krait processor subsystem as separate register region. >&g

Re: [PATCH v5 15/15] devicetree: bindings: Document qcom,pvs

Hi Viresh, On 12/20/2017 11:57 AM, Viresh Kumar wrote: > On 20-12-17, 11:55, Sricharan R wrote: >>>> + opp-14 { >>>> + opp-hz = /bits/ 64 <14>; >>>> + opp-microvolt-speed0-pvs0-v0 = <1250

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