From: Greg KH Sent: Wednesday, October 28, 2020
3:07 PM
> On Wed, Oct 28, 2020 at 06:05:28AM +, Sherry Sun wrote:
> > Hi Greg,
> >
> > > Subject: Re: [PATCH V5 0/2] Change vring space from nomal memory to
> > > dma coherent memory
> > >
> > > On Wed, Oct 28, 2020 at 10:03:03AM +0800, Sherry S
From: Greg KH Sent: Wednesday, October 28, 2020
7:14 PM
> On Wed, Oct 28, 2020 at 10:17:39AM +0000, Andy Duan wrote:
> > From: Greg KH Sent: Wednesday, October
> > 28, 2020 3:07 PM
> > > On Wed, Oct 28, 2020 at 06:05:28AM +, Sherry Sun wrote:
> > > > Hi
From: Vladimir Oltean Sent: Friday, October 23, 2020
9:34 AM
> Prior to the commit that this one fixes, the FIFO size was derived from the
> read-only register LPUARTx_FIFO[TXFIFOSIZE] using the following
> formula:
>
> TX FIFO size = 2 ^ (LPUARTx_FIFO[TXFIFOSIZE] - 1)
>
> The documentation for
for fields TXFIFOSIZE and RXFIFOSIZE is the same for
> LS1028A as for LS1021A.
>
> The RXFIFOSIZE in the Layerscape SoCs is fixed at this value:
> 101 Receive FIFO/Buffer depth = 32 datawords.
>
> When Andy Duan wrote the commit in Fixes: below, he assumed that the 101
> encodin
From: Peng Fan Sent: Tuesday, September 29, 2020 5:55 PM
> The watermark is set to 1, so we need to input two chars to trigger RDRF using
> the original logic. With the new logic, we could always get the char when
> there
> is data in FIFO.
>
> Suggested-by: Fugang Duan
> Signed-off-by: Peng Fa
From: David Miller Sent: Thursday, September 24, 2020
4:32 AM
> From: Stefan Riedmueller
> Date: Wed, 23 Sep 2020 16:25:28 +0200
>
> > From: Christian Hemp
> >
> > Make use of device tree alias for device enumeration to keep the
> > device order consistent with the naming in the datasheet.
> >
From: Zhang Changzhong Sent: Monday, September 14,
2020 9:14 PM
> Fixes the following W=1 kernel build warning(s):
>
> drivers/net/ethernet/freescale/fec_ptp.c:523:6: warning:
> variable 'ns' set but not used [-Wunused-but-set-variable]
> 523 | u64 ns;
> | ^~
>
> After commit 660
From: Zhang Changzhong Sent: Monday, September 7,
2020 8:50 PM
> Because clk_prepare_enable() and clk_disable_unprepare() already checked
> NULL clock parameter, so the additional checks are unnecessary, just remove
> them.
>
> Reported-by: Hulk Robot
> Signed-off-by: Zhang Changzhong
Acked-b
From: Shawn Guo Sent: Monday, August 17, 2020 3:17 PM
> On Sun, Jul 12, 2020 at 08:25:07PM -0400, Sven Van Asbroeck wrote:
> > On the imx6qp QuadPlus, the h/w designers have improved enet clocking.
> >
> > This patchset extends the clock tree to reflect the situation on QuadPlus.
> >
> > This allo
From: Sergey Organov Sent: Wednesday, July 15, 2020 11:43
PM
> This is a collection of simple improvements that reduce and/or simplify code.
> They got developed out of attempt to use DP83640 PTP PHY connected to
> built-in FEC (that has its own PTP support) of the iMX 6SX micro-controller.
> The
From: Sergey Organov Sent: Wednesday, July 8, 2020 4:49 PM
> Andy Duan writes:
>
> > From: Sergey Organov Sent: Tuesday, July 7, 2020
> > 10:43 PM
> >> Andy Duan writes:
> >>
> >> > From: Sergey Organov Sent: Monday, July 6,
> >> &
From: Sergey Organov Sent: Tuesday, July 7, 2020 10:43 PM
> Andy Duan writes:
>
> > From: Sergey Organov Sent: Monday, July 6, 2020
> 10:26 PM
> >> Code of the form "if(x) x = 0" replaced with "x = 0".
> >>
> >> Code of the fo
From: Sven Van Asbroeck Sent: Tuesday, July 7, 2020 11:21
PM
> Andy, Fabio,
>
> Sounds like we now have a solution which makes logical sense, although it
> requires changes and additions to drivers/clk/imx/. Before I create a patch,
> can you read the plan below and check that it makes sense, pl
From: Sergey Organov Sent: Monday, July 6, 2020 10:26 PM
> Code of the form "if(x) x = 0" replaced with "x = 0".
>
> Code of the form "if(x == a) x = a" removed.
>
> Signed-off-by: Sergey Organov
> ---
> drivers/net/ethernet/freescale/fec_ptp.c | 4 +---
> 1 file changed, 1 insertion(+), 3 del
From: Sergey Organov Sent: Monday, July 6, 2020 10:26 PM
> PPS feature could be useful even when hardware time stamping of network
> packets is not in use, so remove offending check for this condition from
> fec_ptp_enable_pps().
If hardware time stamping of network packets is not in use, PPS is
From: Sven Van Asbroeck Sent: Monday, July 6, 2020 11:00
PM
> On Mon, Jul 6, 2020 at 10:58 AM Sven Van Asbroeck
> wrote:
> >
> > Hi Fabio,
> >
> > On Mon, Jul 6, 2020 at 9:46 AM Fabio Estevam
> wrote:
> > >
> > > Would it make sense to use compatible = "mmio-mux"; like we do on
> > > imx7s, imx
From: Sven Van Asbroeck Sent: Sunday, July 5, 2020 11:34
PM
>
> ext phy-| \
> | |
> enet_ref-o--|M |pad--| \
>| |_/ | |
>| |M |mac_gtx
>| | |
>
From: Sven Van Asbroeck
> Hi Fabio, Andy,
>
> On Thu, Jul 2, 2020 at 6:29 PM Fabio Estevam wrote:
> >
> > With the device tree approach, I think that a better place to touch
> > GPR5 would be inside the fec driver.
> >
>
> Are we 100% sure this is the best way forward, though?
>
> All the FEC
From: Sven Van Asbroeck Sent: Friday, July 3, 2020 8:51 AM
> Hi Fabio,
>
> On Thu, Jul 2, 2020 at 6:29 PM Fabio Estevam wrote:
> >
> > With the device tree approach, I think that a better place to touch
> > GPR5 would be inside the fec driver.
> >
>
> Cool idea. I notice that the latest FEC dri
From: Sven Van Asbroeck Sent: Wednesday, July 1, 2020
9:52 PM
> Andy, Fabio,
>
> Does the following describe the mainline situation?
> Please correct if not.
>
> 1. imx6 ethernet ref_clk can be generated internally (by imx6) or
>externally (by PHY or oscillator on PCB) 2. if internal, fec's
From: Fabio Estevam Sent: Wednesday, July 1, 2020 11:39 AM
> Hi Andy,
>
> On Wed, Jul 1, 2020 at 12:18 AM Andy Duan wrote:
>
> > --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
> > +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
> > @@ -202,6 +202,8 @@
> &g
From: Sven Van Asbroeck Sent: Tuesday, June 30, 2020
11:24 PM
> Andy, Fabio,
>
> On Tue, Jun 30, 2020 at 2:36 AM Andy Duan wrote:
> >
> > Sven, no matter PHY supply 125Mhz clock to pad or not, GPR5[9] is to
> > select RGMII gtx clock source from:
> > - 0 Cloc
From: Fabio Estevam Sent: Tuesday, June 30, 2020 7:49 PM
> Hi Andy,
>
> On Tue, Jun 30, 2020 at 3:36 AM Andy Duan wrote:
>
> > Fabio, our QA double verify 5.4.24_2.1.0, no matter SD boot or
> > tftp/nfs boot, both work fine on i.MX6QP sabresd board, please double
From: Sven Van Asbroeck Sent: Monday, June 29, 2020 10:37
PM
> On Mon, Jun 29, 2020 at 10:26 AM Fabio Estevam
> wrote:
> >
> > Just tested 5.4.24_2.1.0 on an imx6qp sabresd and DHCP also fails there.
>
> I think I discovered the problem !
>
> When I compare the sabresd devicetree on mainline w
From: Fabio Estevam Sent: Monday, June 29, 2020 10:26 PM
> Hi Sven,
>
> On Mon, Jun 29, 2020 at 10:40 AM Sven Van Asbroeck
> wrote:
>
> > Thank you for testing this out on a different platform !
> >
> > I had a look at how things are done in the Freescale fork of the
> > kernel
> > (5.4.24_2.1.
:
> - Fabio Estevam: use of_machine_is_compatible() to determine if we
> are running on an imx6 plus.
>
> To: Shawn Guo
> To: Andy Duan
> Cc: Sascha Hauer
> Cc: Pengutronix Kernel Team
> Cc: Fabio Estevam
> Cc: NXP Linux Team
> Cc: lin
From: Sven Van Asbroeck Sent: Wednesday, June 24, 2020
10:56 AM
> Hi Andy,
>
> On Tue, Jun 23, 2020 at 9:40 PM Andy Duan wrote:
> >
> > The patch looks good.
> > Reviewed-by: Fugang Duan
>
> Thank you !
>
> To check we're on a plus, the patch us
From: Shawn Guo Sent: Tuesday, June 23, 2020 7:54 PM
> Hi Fugang,
>
> Can you take a look at this patch? Thanks!
>
The patch looks good.
Reviewed-by: Fugang Duan
> Shawn
>
> On Sat, Jun 13, 2020 at 04:17:03PM -0400, Sven Van Asbroeck wrote:
> > On imx6, the ethernet reference clock (clk_enet
From: David Miller Sent: Tuesday, June 16, 2020 4:42 AM
> From: Navid Emamdoost
> Date: Sun, 14 Jun 2020 00:38:01 -0500
>
> > in fec_enet_mdio_read, fec_enet_mdio_write, fec_enet_get_regs,
> > fec_enet_open and fec_drv_remove, pm_runtime_get_sync is called which
> > increments the counter even i
From: wu000...@umn.edu Sent: Sunday, June 14, 2020 6:12 AM
> From: Qiushi Wu
>
> pm_runtime_get_sync() increments the runtime PM usage counter even
> when it returns an error code. Thus call pm_runtime_put_noidle() if
> pm_runtime_get_sync() fails.
>
> Fixes: 13d6eb20fc79 ("i2c: imx-lpi2c: add
From: Dinghao Liu Sent: Monday, June 1, 2020 2:17 PM
> pm_runtime_get_sync() increments the runtime PM usage counter even the
> call returns an error code. Thus a corresponding decrement is needed on the
> error handling path to keep the counter balanced.
>
> Fix this by adding the missed functio
From: Anson Huang Sent: Thursday, May 28, 2020 11:13 AM
> In the nvmem yaml schema, it requires the nodename to be one of
> "eeprom|efuse|nvram", so need to change all i.MX/MXS SoCs ocotp/iim node
> name to efuse:
>
> MXS platforms: i.MX23/28;
> i.MX platforms with IIM: i.MX25/27/31/35/51/53.
> i
From: Shawn Guo Sent: Wednesday, May 13, 2020 4:50 PM
> On Wed, Apr 29, 2020 at 06:04:14PM +0800, fugang.d...@nxp.com wrote:
> > From: Fugang Duan
> >
> > Add "fsl,imx6sx-fec" compatible string for fec node, then i.MX8MP EVK
> > ethernet function can work now.
> >
> > Signed-off-by: Fugang Duan
From: Philippe Schenker Sent: Wednesday,
October 16, 2019 11:19 PM
> This commits adds RS485 support for LPUART hardware that uses 32-bit
> registers. These are typically found in i.MX8 processors.
>
> Signed-off-by: Philippe Schenker
Reviewed-by: Fugang Duan
>
> ---
>
> drivers/tty/serial
From: Philippe Schenker Sent: Wednesday,
October 16, 2019 11:19 PM
> Use UARTMODIR defines instead of UARTMODEM as it is a 32-bit function
>
> Signed-off-by: Philippe Schenker
Reviewed-by: Fugang Duan
> ---
>
> drivers/tty/serial/fsl_lpuart.c | 4 ++--
> 1 file changed, 2 insertions(+), 2
From: Philippe Schenker Sent: Wednesday,
October 16, 2019 11:19 PM
> Currently flow control is not working due to lpuart32_set_mctrl that is
> clearing TXCTSE bit in all cases. This bit gets earlier setup by
> lpuart32_set_termios.
>
> As I read in Documentation set_mctrl is also not meant for h
From: Anson Huang Sent: Wednesday, October 9, 2019 6:16 PM
> Failed to get irq using name is NOT fatal as driver will use index to get irq
> instead, use platform_get_irq_byname_optional() instead of
> platform_get_irq_byname() to avoid below error message during
> probe:
>
> [0.819312] fec 3
From: Anson Huang Sent: Wednesday, October 9, 2019 6:16 PM
> Use platform_get_irq_byname_optional() and platform_get_irq_optional()
> instead of platform_get_irq_byname() and platform_get_irq() for optional
> IRQs to avoid below error message during probe:
>
> [0.795803] fec 30be.ethernet
From: Philipp Puschmann Sent: Friday, September
20, 2019 3:06 PM
> Am 20.09.19 um 05:42 schrieb Andy Duan:
> > From: Philipp Puschmann Sent: Thursday,
> > September 19, 2019 10:51 PM
> >> Using only 4 DMA periods for UART RX is very few if we have a high
> >> fr
From: Philipp Puschmann Sent: Thursday, September
19, 2019 10:51 PM
> Using only 4 DMA periods for UART RX is very few if we have a high frequency
> of small transfers - like in our case using Bluetooth with many small packets
> via UART - causing many dma transfers but in each only filling a fra
From: Philipp Puschmann Sent: Thursday, September
19, 2019 10:30 PM
> For some years and since many kernel versions there are reports that RX
> UART DMA channel stops working at one point. So far the usual workaround
> was to disable RX DMA. This patches fix the underlying problem.
>
> When a ru
From: Philipp Puschmann Sent: Monday, September
16, 2019 9:55 PM
> Hi Fabio,
>
> Am 12.09.19 um 20:23 schrieb Fabio Estevam:
> > Hi Philipp,
> >
> > Thanks for submitting these fixes.
> >
> > On Wed, Sep 11, 2019 at 11:50 AM Philipp Puschmann
> > wrote:
> >>
> >> For some years and since many k
From: Marco Hartman Sent: Wednesday, August 21, 2019 7:44 PM
> IEEE 802.3ae clause 45 defines a modified MDIO protocol that uses a two
> staged access model in order to increase the address space.
>
> This patch adds support for C45 MDIO read and write accesses, which are
> used whenever the MII_A
From: Andrew Lunn Sent: Tuesday, August 20, 2019 9:04 PM
> On Tue, Aug 20, 2019 at 02:32:26AM +0000, Andy Duan wrote:
> > From: Andrew Lunn
> > > On Mon, Aug 19, 2019 at 05:11:14PM +, Marco Hartmann wrote:
> > > > As of yet, the Fast Ethernet Control
From: Andrew Lunn
> On Mon, Aug 19, 2019 at 05:11:14PM +, Marco Hartmann wrote:
> > As of yet, the Fast Ethernet Controller (FEC) driver only supports
> > Clause 22 conform MDIO transactions. IEEE 802.3ae Clause 45 defines a
> > modified MDIO protocol that uses a two staged access model in ord
From: Marco Hartmann Sent: Tuesday, August 20, 2019 1:11 AM
> IEEE 802.3ae clause 45 defines a modified MDIO protocol that uses a two
> staged access model in order to increase the address space.
>
> This patch adds support for C45 MDIO read and write accesses, which are
> used whenever the MII_AD
From: Srinivas Kandagatla Sent: Tuesday,
August 6, 2019 6:04 PM
> On 04/07/2019 15:20, fugang.d...@nxp.com wrote:
> > From: Fugang Duan
> >
> > i.MX8QM efuse table has some difference with i.MX8QXP platform, so add
> > i.MX8QM platform support.
> >
> > Signed-off-by: Fugang Duan
> > ---
> > d
From: Srinivas Kandagatla Sent: Tuesday,
August 6, 2019 6:04 PM
> On 04/07/2019 15:20, fugang.d...@nxp.com wrote:
> > From: Fugang Duan
> >
> > i.MX8QM efuse table has some difference with i.MX8QXP platform, so add
> > i.MX8QM platform support.
> >
> > Signed-off-by: Fugang Duan
> > ---
> > d
From: Sven Van Asbroeck Sent: Wednesday, July 17, 2019
8:48 PM
> On Tue, Jul 16, 2019 at 9:32 PM Andy Duan wrote:
> >
> > Yes, so the old legacy code is kept there. But it is better to clean
> > up all if there have enough boards to verify them.
>
> Would it ma
From: Sven Van Asbroeck Sent: Tuesday, July 16, 2019 9:19
PM
> Hi Andy,
>
> On Mon, Jul 15, 2019 at 10:02 PM Andy Duan
> wrote:
> >
> > the phylib already can handle mii bus reset and phy device reset
>
> That's a great suggestion, thank you !! I completel
From: Sven Van Asbroeck Sent: Tuesday, July 16, 2019 5:05
AM
> The current fec driver allows the PHY to be reset via a gpio, specified in the
> devicetree. However, some PHYs need to be reset in a more complex way.
>
> To accommodate such PHYs, allow an optional reset controller in the fec
> dev
From: gre...@linuxfoundation.org Sent: Monday,
July 15, 2019 3:37 PM
> On Mon, Jul 15, 2019 at 05:34:47AM +0000, Andy Duan wrote:
> > Ping...
>
> It's the middle of the merge window, we can't do anything with any patches
> until after that. Please be patient.
>
Ping ...
> From: Fugang Duan
>
> iMX8 fuse word index represent as one 4-bytes word, it should not be divided
> by 4.
>
> Exp:
> - MAC0 address layout in fuse:
> offset 708: MAC[3] MAC[2] MAC[1] MAC[0]
> offset 709: XX xx MAC[5] MAC[4]
>
> Signed-off-by: Fugang Duan
> ---
> drivers/n
Ping...
> From: Fugang Duan
>
> i.MX8QM efuse table has some difference with i.MX8QXP platform, so add
> i.MX8QM platform support.
>
> Signed-off-by: Fugang Duan
> ---
> drivers/nvmem/imx-ocotp-scu.c | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/nvmem/imx-ocotp-scu.
From: Andy Duan Sent: Friday, July 5, 2019 3:33 PM
> From: Lothar Waßmann Sent: Friday, July 5, 2019
> 3:13 PM
> > Hi,
> >
> > On Fri, 5 Jul 2019 02:46:32 + Andy Duan wrote:
> > > From: Andy Duan Sent: Friday, July 5, 2019 12:08 AM
> > > >
From: Lothar Waßmann Sent: Friday, July 5, 2019 3:13
PM
> Hi,
>
> On Fri, 5 Jul 2019 02:46:32 +0000 Andy Duan wrote:
> > From: Andy Duan Sent: Friday, July 5, 2019 12:08 AM
> > > From: Lothar Waßmann Sent: Thursday, July
> > > 4,
> > > 2019 11:46 PM
From: Andy Duan Sent: Friday, July 5, 2019 12:08 AM
> From: Lothar Waßmann Sent: Thursday, July 4,
> 2019 11:46 PM
> > Hi,
> >
> > On Thu, 4 Jul 2019 22:20:15 +0800 fugang.d...@nxp.com wrote:
> > > From: Fugang Duan
> > >
> > > iMX8 fuse word
From: Lothar Waßmann Sent: Thursday, July 4, 2019
11:46 PM
> Hi,
>
> On Thu, 4 Jul 2019 22:20:15 +0800 fugang.d...@nxp.com wrote:
> > From: Fugang Duan
> >
> > iMX8 fuse word index represent as one 4-bytes word, it should not be
> > divided by 4.
> >
> > Exp:
> > - MAC0 address layout in fuse:
From: Fuqian Huang Sent: Friday, June 28, 2019 1:47
AM
> In commit af7ddd8a627c
> ("Merge tag 'dma-mapping-4.21' of
> git://git.infradead.org/users/hch/dma-mapping"),
> dma_alloc_coherent has already zeroed the memory.
> So memset is not needed.
>
> Signed-off-by: Fuqian Huang
Acked-by: Fugang
From: Mark Brown Sent: Wednesday, May 29, 2019 7:16 PM
> To: Andy Duan
> Cc: da...@lechnology.com; raf...@kernel.org; Robby Cai
> ; gre...@linuxfoundation.org; linux-kernel
>
> Subject: Re: [EXT] Re: Issue: regmap: use debugfs even when no device
>
> On Wed, May 29, 201
From: Mark Brown Sent: Tuesday, May 28, 2019 9:27 PM
> On Tue, May 28, 2019 at 02:20:15AM +0000, Andy Duan wrote:
>
> > So on i.MX8MM/8QM/8QXP platforms, we catch the issue that user dump
> > regmap registers without power cause system hang.
> > Maybe revert the
From: Fabio Estevam
> Hi Andy,
>
> On Sun, May 5, 2019 at 5:15 AM Andy Duan wrote:
>
> > Nack the patch !
> >
...
> > Secondly, for your issue you caught, which was fixed by patch:
> > commit d7c3a206e6338e4ccdf030719dec028e26a521d5
> > Author: Andy
NET>,
> > > - <&clks
> > IMX6SX_CLK_ENET_AHB>,
> > > +<&clks
> IMX6SX_CLK_ENET>,
> >
> > Yes, there is really no IMX6SX_CLK_ENET_AHB as per the Refernce Manual
> > and
From: Stefan Agner Sent: Monday, January 21, 2019 10:59 PM
> According to the device tree binding the phy-supply property is optional. Use
> the regulator_get_optional API accordingly. The code already handles NULL
> just fine.
>
> This gets rid of the following warning:
> fec 2188000.ethernet:
From: Stefano Cappa
> Hi everyone,
> I already posted this in NXP forum as a comment
> (https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fco
> mmunity.nxp.com%2Fthread%2F359397&data=02%7C01%7Cfugang.dua
> n%40nxp.com%7C189d5cad534e470a162508d66c068de2%7C686ea1d3bc2b
> 4c6fa92cd99c
From: Uwe Kleine-König Sent: 2018年9月20日 20:11
> Back in 2015 when irda was dropped from the driver imx1 was broken.
> This change reintroduces the support for the third interrupt of the UART.
>
> Fixes: afe9cbb1a6ad ("serial: imx: drop support for IRDA")
> Signed-off-by: Uwe Kleine-König
> ---
>
From: Lucas Stach Sent: 2018年9月20日 18:42
> Am Donnerstag, den 20.09.2018, 10:33 + schrieb Andy Duan:
> > From: Lucas Stach Sent: 2018年9月20日
> 17:40
> > > Am Donnerstag, den 20.09.2018, 08:39 + schrieb Robin Gong:
> > > > > -Original Message--
From: Lucas Stach Sent: 2018年9月20日 17:40
> Am Donnerstag, den 20.09.2018, 08:39 + schrieb Robin Gong:
> > > -Original Message-
> > > From: Uwe Kleine-König
> > > Sent: 2018年9月20日 15:55
> > > To: Robin Gong
> > > Cc: jsl...@suse.com
TS on imx1, this is an old
> chip and later variants have a single combined irq.
>
> The correct fix for the warning would be to restore that request_irq.
>
> --
> Regards,
> Leonard
Yes, your explain is very correct! Thanks for your comment.
We should restore rtsirq request that for i.MX1.
Regards,
Andy Duan
From: A.s. Dong Sent: 2018年6月24日 12:24
> Copy Andy & Frank,
>
> > -Original Message-
> > From: Michal Vokáč [mailto:michal.vo...@ysoft.com]
> > Sent: Tuesday, June 12, 2018 11:10 PM
> > To: linux-g...@vger.kernel.org
> > Cc: linux-arm-ker...@lists.infradead.org; Shawn Guo
> > ; Sascha Haue
From: Arnd Bergmann Sent: 2018年5月28日 23:50
> While compile-testing on arm64 with gcc-8.1, I ran into a build diagnostic:
>
> drivers/net/ethernet/freescale/fec_main.c: In function 'fec_probe':
> drivers/net/ethernet/freescale/fec_main.c:3517:25: error: '%d' directive
> writing between 1 and 10 by
> From: YueHaibing Sent: 2018年5月24日 19:27
> This comment is outdated as fec_ptp_ioctl has been replaced by
> fec_ptp_set/fec_ptp_get since commit 1d5244d0e43b ("fec: Implement
> the SIOCGHWTSTAMP ioctl")
>
> Signed-off-by: YueHaibing
Thanks.
Acked-by: Fugang Duan
> ---
> drivers/net/ethernet/
From: Florian Fainelli Sent: 2018年5月18日 4:08
> The Freescale FEC driver builds fine with COMPILE_TEST, so make that
> possible.
>
> Signed-off-by: Florian Fainelli
Acked-by: Fugang Duan
> ---
> drivers/net/ethernet/freescale/Kconfig| 2 +-
> drivers/net/ethernet/freescale/fec.h | 2
From: Florian Fainelli Sent: 2018年5月16日 7:56
> A number of drivers have the following pattern:
>
> if (np)
> of_mdiobus_register()
> else
> mdiobus_register()
>
> which the implementation of of_mdiobus_register() now takes care of.
> Remove that pattern in drivers that strictly adher
From: Florian Fainelli Sent: 2018年5月16日 7:48
> The Freescale FEC driver builds fine with COMPILE_TEST, so make that
> possible.
>
> Signed-off-by: Florian Fainelli
Acked-by: Fugang Duan
> ---
> drivers/net/ethernet/freescale/Kconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
From: Marco Franchi Sent: Friday, January 05, 2018 11:03 PM
>Hi,
>
>I am getting the following warning on a imx6ul-evk board running linux-next
>20180105:
>
>[9.233290] [ cut here ]
>[9.242068] WARNING: CPU: 0 PID: 0 at
>./include/linux/netfilter.h:233 arp_rcv+0x1f8
From: Rob Herring Sent: Saturday, January 06, 2018 12:45 AM
>To: Stefan Agner
>Cc: shawn...@kernel.org; ker...@pengutronix.de; Fabio Estevam
>; mark.rutl...@arm.com; linux-arm-
>ker...@lists.infradead.org; devicet...@vger.kernel.org; linux-
>ker...@vger.kernel.org; Andy Dua
From: Richard Leitner Sent: Monday, December 11, 2017 8:17 PM
>This patch series fixes the use of the SMSC LAN8710/20 with a Freescale ETH
>when the refclk is generated by the FSL.
>
>This patchset depends on the "phylib: Add device reset GPIO support" patch
>submitted by Geert Uytterhoeven/Sergei
From: Richard Leitner Sent: Wednesday, December
06, 2017 4:12 PM
>To: Andy Duan ; Richard Leitner ;
>robh...@kernel.org; mark.rutl...@arm.com; and...@lunn.ch;
>f.faine...@gmail.com; frowand.l...@gmail.com
>Cc: da...@davemloft.net; geert+rene...@glider.be;
>sergei.shtyl...@cogentem
From: Richard Leitner Sent: Tuesday, December 05, 2017 9:26 PM
>Some PHYs (for example the SMSC LAN8710/LAN8720) doesn't allow turning
>the refclk on and off again during operation (according to their datasheet).
>Nonetheless exactly this behaviour was introduced for power saving reasons
>by commi
From: Richard Leitner Sent: Monday, November 20,
2017 8:55 PM
>On 11/20/2017 11:35 AM, Andy Duan wrote:
>> From: Richard Leitner Sent: Monday,
>> November 20, 2017 5:57 PM
>>> To: Andy Duan ; f.faine...@gmail.com;
>>> and...@lunn.ch
>>> Cc: Richa
From: Richard Leitner Sent: Monday, November 20,
2017 5:57 PM
>To: Andy Duan ; f.faine...@gmail.com;
>and...@lunn.ch
>Cc: Richard Leitner ; net...@vger.kernel.org; linux-
>ker...@vger.kernel.org
>Subject: Re: [PATCH v2 3/3] net: ethernet: fec: fix refclk enable for SMSC
>LAN871
From: Richard Leitner Sent: Monday, November 20, 2017 4:34 PM
>To: f.faine...@gmail.com; Andy Duan ;
>and...@lunn.ch
>Cc: net...@vger.kernel.org; linux-kernel@vger.kernel.org;
>richard.leit...@skidata.com
>Subject: [PATCH v2 3/3] net: ethernet: fec: fix refclk enable for SMSC
>
From: Richard Leitner Sent: Monday, November 20, 2017 4:34 PM
>The fec_reset_phy function allowed only one execution during probeing.
>To make it more usable move the dt parsing and gpio allocation to the probe
>function. The parameters of the phy reset are added to the fec_enet_private
>struct. A
From: Richard Leitner Sent: Friday, July 07, 2017
5:53 PM
>To: Andy Duan ; robh...@kernel.org;
>mark.rutl...@arm.com
>Cc: net...@vger.kernel.org; devicet...@vger.kernel.org; linux-
>ker...@vger.kernel.org; d...@g0hl1n.net; Andrew Lunn
>Subject: Re: [PATCH 2/2] net: ethernet: fsl
From: Richard Leitner Sent: Friday, July 07, 2017
1:51 PM
>> Since it is common issue so long as using the PHY, can you move it into smsc
>phy driver like in .smsc_phy_reset() function ?
>> And get the reset pin from phy dts node.
>
>Some more points that come into my mind:
> - The smsc_phy_rese
From: Richard Leitner Sent: Thursday, July 06,
2017 9:06 PM
>To: Andy Duan ; robh...@kernel.org;
>mark.rutl...@arm.com
>Cc: net...@vger.kernel.org; devicet...@vger.kernel.org; linux-
>ker...@vger.kernel.org; d...@g0hl1n.net; Richard Leitner
>
>Subject: [PATCH 2/2] net: ethe
From: Dong Aisheng Sent: Monday, June 12, 2017 11:37 PM
>To: linux-ser...@vger.kernel.org
>Cc: linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org;
>gre...@linuxfoundation.org; jsl...@suse.com; Andy Duan
>; ste...@agner.ch; Mingkai Hu
>; Y.b. Lu ;
>nikita.yo...@
From: Dong Aisheng Sent: Monday, June 12, 2017 11:37 PM
>The lpuart of imx7ulp is basically the same as ls1021a. It's also
>32 bit width register, but unlike ls1021a, it's little endian.
>Besides that, imx7ulp lpuart has a minor different register layout from ls1021a
>that it has four extra regist
From: Florian Fainelli Sent: Thursday, June 01, 2017
9:53 AM
>To: Andy Duan ; Rob Herring ;
>Quentin Schulz
>Cc: mark.rutl...@arm.com; net...@vger.kernel.org;
>devicet...@vger.kernel.org; linux-kernel@vger.kernel.org;
>thomas.petazz...@free-electrons.com
>Subject: Re: [PATCH
From: Rob Herring Sent: Thursday, June 01, 2017 12:44 AM
>On Tue, May 23, 2017 at 11:48:08AM +0200, Quentin Schulz wrote:
>> Some PHY require to wait for a bit after the reset GPIO has been
>> toggled. This adds support for the DT property `phy-reset-post-delay`
>> which gives the delay in millise
From: Quentin Schulz Sent: Tuesday, May 23,
2017 5:48 PM
>Some PHY require to wait for a bit after the reset GPIO has been toggled. This
>adds support for the DT property `phy-reset-post-delay` which gives the delay
>in milliseconds to wait after reset.
>
>If the DT property is not given, no dela
From: Quentin Schulz Sent: Monday, May 22,
2017 5:15 PM
>Some PHY require to wait for a bit after the reset GPIO has been toggled. This
>adds support for the DT property `phy-reset-post-delay` which gives the delay
>in milliseconds to wait after reset.
>
>If the DT property is not given, no delay
From: Stefan Agner Sent: Monday, May 15, 2017 1:39 PM
>To: Andy Duan
>Cc: David Miller ; and...@lunn.ch;
>feste...@gmail.com; net...@vger.kernel.org; linux-
>ker...@vger.kernel.org
>Subject: Re: [PATCH] net: fec: select queue depending on VLAN priority
>
>On 2017-05-10 2
From: Stefan Agner Sent: Thursday, May 11, 2017 12:08 PM
>To: Andy Duan
>Cc: David Miller ; and...@lunn.ch;
>feste...@gmail.com; net...@vger.kernel.org; linux-
>ker...@vger.kernel.org
>Subject: Re: [PATCH] net: fec: select queue depending on VLAN priority
>
>On 2017-05-09 1
From: David Miller Sent: Tuesday, May 09, 2017 9:39 PM
>To: ste...@agner.ch
>Cc: Andy Duan ; and...@lunn.ch;
>feste...@gmail.com; net...@vger.kernel.org; linux-
>ker...@vger.kernel.org
>Subject: Re: [PATCH] net: fec: select queue depending on VLAN priority
>
>From: Stefan
From: Dong Aisheng Sent: Tuesday, May 09, 2017 3:51 PM
>To: linux-ser...@vger.kernel.org
>Cc: linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org;
>gre...@linuxfoundation.org; jsl...@suse.com; Andy Duan
>; ste...@agner.ch; Mingkai Hu
>; Y.B. Lu ; A.S. Dong
>
&g
From: Leonard Crestez Sent: Wednesday, March 22, 2017
10:28 PM
>To: Shawn Guo ; Sascha Hauer
>
>Cc: Leonard Crestez ; linux-arm-
>ker...@lists.infradead.org; Fabio Estevam ; Andy
>Duan ; Octavian Purdila
>; Florian Fainelli ; linux-
>ker...@vger.kernel.org
From: Nikita Yushchenko Sent: Sunday,
December 04, 2016 11:18 PM
>To: David S. Miller ; Andy Duan
>; Troy Kisky ;
>Andrew Lunn ; Eric Nelson ; Philippe
>Reynes ; Johannes Berg ;
>net...@vger.kernel.org
>Cc: Chris Healy ; Fabio Estevam
>; linux-kernel@vger.kernel.org
From: Nikita Yushchenko Sent: Monday,
December 05, 2016 4:16 PM
>To: David S. Miller ; Andy Duan
>; Troy Kisky ;
>Andrew Lunn ; Eric Nelson ; Philippe
>Reynes ; Johannes Berg ;
>net...@vger.kernel.org
>Cc: Chris Healy ; Fabio Estevam
>; linux-kernel@vger.kernel.org
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