[PATCH v6 09/11] dt-bindings: power: rockchip: Convert to json-schema
Convert the soc/rockchip/power_domain.txt binding document to json-schema and move to the power bindings directory. Signed-off-by: Elaine Zhang From: Enric Balletbo i Serra Link:https://patchwork.kernel.org/project/linux-rockchip/patch/20210225102643.653095-1-enric.balle...@collabora.com/ --- .../power/rockchip,power-controller.yaml | 291 ++ .../bindings/soc/rockchip/power_domain.txt| 136 2 files changed, 291 insertions(+), 136 deletions(-) create mode 100644 Documentation/devicetree/bindings/power/rockchip,power-controller.yaml delete mode 100644 Documentation/devicetree/bindings/soc/rockchip/power_domain.txt diff --git a/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml new file mode 100644 index ..9fec9e227432 --- /dev/null +++ b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml @@ -0,0 +1,291 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/rockchip,power-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip Power Domains + +maintainers: + - Elaine Zhang + - Heiko Stuebner + +description: | + Rockchip processors include support for multiple power domains which can be + powered up/down by software based on different application scenarios to save power. + + Power domains contained within power-controller node are generic power domain + providers documented in Documentation/devicetree/bindings/power/power-domain.yaml. + + IP cores belonging to a power domain should contain a "power-domains" + property that is a phandle for the power domain node representing the domain. + +properties: + $nodename: +const: power-controller + + compatible: +enum: + - rockchip,px30-power-controller + - rockchip,rk3036-power-controller + - rockchip,rk3066-power-controller + - rockchip,rk3128-power-controller + - rockchip,rk3188-power-controller + - rockchip,rk3228-power-controller + - rockchip,rk3288-power-controller + - rockchip,rk3328-power-controller + - rockchip,rk3366-power-controller + - rockchip,rk3368-power-controller + - rockchip,rk3399-power-controller + + "#power-domain-cells": +const: 1 + + "#address-cells": +const: 1 + + "#size-cells": +const: 0 + + clocks: true + + assigned-clocks: +minItems: 1 + + assigned-clock-parents: +minItems: 1 + +patternProperties: + "^power-domain@[0-9a-f]+$": +type: object +description: | + Represents the power domains within the power controller node as documented + in Documentation/devicetree/bindings/power/power-domain.yaml. + +properties: + + "#power-domain-cells": +description: + Must be 0 for nodes representing a single PM domain and 1 for nodes + providing multiple PM domains. + + "#address-cells": +const: 1 + + "#size-cells": +const: 0 + + reg: +maxItems: 1 +description: | + Power domain index. Valid values are defined in + "include/dt-bindings/power/px30-power.h" + "include/dt-bindings/power/rk3036-power.h" + "include/dt-bindings/power/rk3066-power.h" + "include/dt-bindings/power/rk3128-power.h" + "include/dt-bindings/power/rk3188-power.h" + "include/dt-bindings/power/rk3228-power.h" + "include/dt-bindings/power/rk3288-power.h" + "include/dt-bindings/power/rk3328-power.h" + "include/dt-bindings/power/rk3366-power.h" + "include/dt-bindings/power/rk3368-power.h" + "include/dt-bindings/power/rk3399-power.h" + + clocks: +description: | + A number of phandles to clocks that need to be enabled while power domain + switches state. + + pm_qos: +description: | + A number of phandles to qos blocks which need to be saved and restored + while power domain switches state. + +patternProperties: + "^power-domain@[0-9a-f]+$": +type: object +description: | + Represents a power domain child within a power domain parent node. + +properties: + + "#power-domain-cells": +description: + Must be 0 for nodes representing a single PM domain and 1 for nodes + providing multiple PM domains. + + "#address-cells": +const: 1 + + "#size-cells": +const: 0 + + reg: +maxItems: 1 + + clocks: +description: | + A number of phandles to clocks that need to b
[PATCH v6 07/11] soc: rockchip: pm-domains: Add a meaningful power domain name
Add the power domains names to the power domain info struct so we
have meaningful name for every power domain.
Signed-off-by: Elaine Zhang
---
drivers/soc/rockchip/pm_domains.c | 221 +++---
1 file changed, 114 insertions(+), 107 deletions(-)
diff --git a/drivers/soc/rockchip/pm_domains.c
b/drivers/soc/rockchip/pm_domains.c
index 54eb6cfc5d5b..1d39ad92470a 100644
--- a/drivers/soc/rockchip/pm_domains.c
+++ b/drivers/soc/rockchip/pm_domains.c
@@ -29,6 +29,7 @@
#include
struct rockchip_domain_info {
+ const char *name;
int pwr_mask;
int status_mask;
int req_mask;
@@ -85,8 +86,9 @@ struct rockchip_pmu {
#define to_rockchip_pd(gpd) container_of(gpd, struct rockchip_pm_domain, genpd)
-#define DOMAIN(pwr, status, req, idle, ack, wakeup)\
+#define DOMAIN(_name, pwr, status, req, idle, ack, wakeup) \
{ \
+ .name = _name, \
.pwr_mask = (pwr), \
.status_mask = (status),\
.req_mask = (req), \
@@ -95,8 +97,9 @@ struct rockchip_pmu {
.active_wakeup = (wakeup), \
}
-#define DOMAIN_M(pwr, status, req, idle, ack, wakeup) \
+#define DOMAIN_M(_name, pwr, status, req, idle, ack, wakeup) \
{ \
+ .name = _name, \
.pwr_w_mask = (pwr) << 16, \
.pwr_mask = (pwr), \
.status_mask = (status),\
@@ -107,8 +110,9 @@ struct rockchip_pmu {
.active_wakeup = wakeup,\
}
-#define DOMAIN_RK3036(req, ack, idle, wakeup) \
+#define DOMAIN_RK3036(_name, req, ack, idle, wakeup) \
{ \
+ .name = _name, \
.req_mask = (req), \
.req_w_mask = (req) << 16, \
.ack_mask = (ack), \
@@ -116,20 +120,20 @@ struct rockchip_pmu {
.active_wakeup = wakeup,\
}
-#define DOMAIN_PX30(pwr, status, req, wakeup) \
- DOMAIN_M(pwr, status, req, (req) << 16, req, wakeup)
+#define DOMAIN_PX30(name, pwr, status, req, wakeup)\
+ DOMAIN_M(name, pwr, status, req, (req) << 16, req, wakeup)
-#define DOMAIN_RK3288(pwr, status, req, wakeup)\
- DOMAIN(pwr, status, req, req, (req) << 16, wakeup)
+#define DOMAIN_RK3288(name, pwr, status, req, wakeup) \
+ DOMAIN(name, pwr, status, req, req, (req) << 16, wakeup)
-#define DOMAIN_RK3328(pwr, status, req, wakeup)\
- DOMAIN_M(pwr, pwr, req, (req) << 10, req, wakeup)
+#define DOMAIN_RK3328(name, pwr, status, req, wakeup) \
+ DOMAIN_M(name, pwr, pwr, req, (req) << 10, req, wakeup)
-#define DOMAIN_RK3368(pwr, status, req, wakeup)\
- DOMAIN(pwr, status, req, (req) << 16, req, wakeup)
+#define DOMAIN_RK3368(name, pwr, status, req, wakeup) \
+ DOMAIN(name, pwr, status, req, (req) << 16, req, wakeup)
-#define DOMAIN_RK3399(pwr, status, req, wakeup)\
- DOMAIN(pwr, status, req, req, req, wakeup)
+#define DOMAIN_RK3399(name, pwr, status, req, wakeup) \
+ DOMAIN(name, pwr, status, req, req, req, wakeup)
static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd)
{
@@ -490,7 +494,10 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu
*pmu,
goto err_unprepare_clocks;
}
- pd->genpd.name = node->name;
+ if (pd->info->name)
+ pd->genpd.name = pd->info->name;
+ else
+ pd->genpd.name = kbasename(node->full_name);
pd->genpd.power_off = rockchip_pd_power_off;
pd->genpd.power_on = rockchip_pd_power_on;
pd->genpd.attach_dev = rockchip_pd_attach_dev;
@@ -716,129 +723,129 @@ static int rockchip_pm_domain_probe(struct
platform_device *pdev)
}
static const struct rockchip_domain_info px30_pm_domains[] = {
- [PX30_PD_USB] = DOMAIN_PX30(BIT(5), BIT(5), BIT(10), false),
- [PX30_PD_SDCARD]= DOMAIN_PX30(BIT(8), BIT(8), BIT(9), false),
- [PX30_PD_GMAC] = DOMAIN_PX30(BIT(10), BIT(10), BIT(6), false),
- [PX30_PD_MMC_NAND] = DOMAIN_PX30(BIT(11), BIT(11), BIT(5), false),
- [PX30_PD_VPU] = DOMAIN_PX30(BIT(12), BIT(12), BIT(14), false),
- [PX30_PD_VO]= DOMAIN_PX30(BIT(13), BIT(13), BIT(7), false),
- [PX30_PD_VI]= DOMAIN_PX30(BIT(14), BIT(14), BIT(8), false),
- [PX30_PD_GPU] = DOMAIN_PX30(BIT(15
[PATCH v6 08/11] dt-bindings: add power-domain header for RK3568 SoCs
According to a description from TRM, add all the power domains Signed-off-by: Elaine Zhang Reviewed-by: Enric Balletbo i Serra --- include/dt-bindings/power/rk3568-power.h | 32 1 file changed, 32 insertions(+) create mode 100644 include/dt-bindings/power/rk3568-power.h diff --git a/include/dt-bindings/power/rk3568-power.h b/include/dt-bindings/power/rk3568-power.h new file mode 100644 index ..6cc1af1a9d26 --- /dev/null +++ b/include/dt-bindings/power/rk3568-power.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_POWER_RK3568_POWER_H__ +#define __DT_BINDINGS_POWER_RK3568_POWER_H__ + +/* VD_CORE */ +#define RK3568_PD_CPU_00 +#define RK3568_PD_CPU_11 +#define RK3568_PD_CPU_22 +#define RK3568_PD_CPU_33 +#define RK3568_PD_CORE_ALIVE 4 + +/* VD_PMU */ +#define RK3568_PD_PMU 5 + +/* VD_NPU */ +#define RK3568_PD_NPU 6 + +/* VD_GPU */ +#define RK3568_PD_GPU 7 + +/* VD_LOGIC */ +#define RK3568_PD_VI 8 +#define RK3568_PD_VO 9 +#define RK3568_PD_RGA 10 +#define RK3568_PD_VPU 11 +#define RK3568_PD_CENTER 12 +#define RK3568_PD_RKVDEC 13 +#define RK3568_PD_RKVENC 14 +#define RK3568_PD_PIPE 15 +#define RK3568_PD_LOGIC_ALIVE 16 + +#endif -- 2.17.1
[PATCH v6 10/11] dt-bindings: power: rockchip: Add bindings for RK3568 Soc
Add the compatible string for RK3568 SoC. Signed-off-by: Elaine Zhang Reviewed-by: Enric Balletbo i Serra --- .../devicetree/bindings/power/rockchip,power-controller.yaml| 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml index 9fec9e227432..a4d223255c3b 100644 --- a/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml +++ b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml @@ -37,6 +37,7 @@ properties: - rockchip,rk3366-power-controller - rockchip,rk3368-power-controller - rockchip,rk3399-power-controller + - rockchip,rk3568-power-controller "#power-domain-cells": const: 1 @@ -90,6 +91,7 @@ patternProperties: "include/dt-bindings/power/rk3366-power.h" "include/dt-bindings/power/rk3368-power.h" "include/dt-bindings/power/rk3399-power.h" + "include/dt-bindings/power/rk3568-power.h" clocks: description: | -- 2.17.1
[PATCH v6 11/11] soc: rockchip: power-domain: add rk3568 powerdomains
Add power-domains found on rk3568 socs.
Signed-off-by: Elaine Zhang
---
drivers/soc/rockchip/pm_domains.c | 31 +++
1 file changed, 31 insertions(+)
diff --git a/drivers/soc/rockchip/pm_domains.c
b/drivers/soc/rockchip/pm_domains.c
index 1d39ad92470a..940504cfb0f1 100644
--- a/drivers/soc/rockchip/pm_domains.c
+++ b/drivers/soc/rockchip/pm_domains.c
@@ -27,6 +27,7 @@
#include
#include
#include
+#include
struct rockchip_domain_info {
const char *name;
@@ -135,6 +136,9 @@ struct rockchip_pmu {
#define DOMAIN_RK3399(name, pwr, status, req, wakeup) \
DOMAIN(name, pwr, status, req, req, req, wakeup)
+#define DOMAIN_RK3568(name, pwr, req, wakeup) \
+ DOMAIN_M(name, pwr, pwr, req, req, req, wakeup)
+
static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd)
{
struct rockchip_pmu *pmu = pd->pmu;
@@ -848,6 +852,18 @@ static const struct rockchip_domain_info
rk3399_pm_domains[] = {
[RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399("sdioaudio", BIT(31), BIT(31),
BIT(29), true),
};
+static const struct rockchip_domain_info rk3568_pm_domains[] = {
+ [RK3568_PD_NPU] = DOMAIN_RK3568("npu", BIT(1), BIT(2), false),
+ [RK3568_PD_GPU] = DOMAIN_RK3568("gpu", BIT(0), BIT(1), false),
+ [RK3568_PD_VI] = DOMAIN_RK3568("vi", BIT(6), BIT(3), false),
+ [RK3568_PD_VO] = DOMAIN_RK3568("vo", BIT(7), BIT(4), false),
+ [RK3568_PD_RGA] = DOMAIN_RK3568("rga", BIT(5), BIT(5), false),
+ [RK3568_PD_VPU] = DOMAIN_RK3568("vpu", BIT(2), BIT(6), false),
+ [RK3568_PD_RKVDEC] = DOMAIN_RK3568("vdec", BIT(4), BIT(8), false),
+ [RK3568_PD_RKVENC] = DOMAIN_RK3568("venc", BIT(3), BIT(7), false),
+ [RK3568_PD_PIPE]= DOMAIN_RK3568("pipe", BIT(8), BIT(11), false),
+};
+
static const struct rockchip_pmu_info px30_pmu = {
.pwr_offset = 0x18,
.status_offset = 0x20,
@@ -983,6 +999,17 @@ static const struct rockchip_pmu_info rk3399_pmu = {
.domain_info = rk3399_pm_domains,
};
+static const struct rockchip_pmu_info rk3568_pmu = {
+ .pwr_offset = 0xa0,
+ .status_offset = 0x98,
+ .req_offset = 0x50,
+ .idle_offset = 0x68,
+ .ack_offset = 0x60,
+
+ .num_domains = ARRAY_SIZE(rk3568_pm_domains),
+ .domain_info = rk3568_pm_domains,
+};
+
static const struct of_device_id rockchip_pm_domain_dt_match[] = {
{
.compatible = "rockchip,px30-power-controller",
@@ -1028,6 +1055,10 @@ static const struct of_device_id
rockchip_pm_domain_dt_match[] = {
.compatible = "rockchip,rk3399-power-controller",
.data = (void *)_pmu,
},
+ {
+ .compatible = "rockchip,rk3568-power-controller",
+ .data = (void *)_pmu,
+ },
{ /* sentinel */ },
};
--
2.17.1
[PATCH v6 06/11] arm64: dts: rockchip: Fix power-controller node names for rk3399
Use more generic names (as recommended in the device tree specification
or the binding documentation)
Signed-off-by: Elaine Zhang
Reviewed-by: Enric Balletbo i Serra
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 40
1 file changed, 20 insertions(+), 20 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index edbbf35fe19e..142f5593d48b 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -971,26 +971,26 @@
#size-cells = <0>;
/* These power domains are grouped by VD_CENTER */
- pd_iep@RK3399_PD_IEP {
+ power-domain@RK3399_PD_IEP {
reg = ;
clocks = < ACLK_IEP>,
< HCLK_IEP>;
pm_qos = <_iep>;
};
- pd_rga@RK3399_PD_RGA {
+ power-domain@RK3399_PD_RGA {
reg = ;
clocks = < ACLK_RGA>,
< HCLK_RGA>;
pm_qos = <_rga_r>,
<_rga_w>;
};
- pd_vcodec@RK3399_PD_VCODEC {
+ power-domain@RK3399_PD_VCODEC {
reg = ;
clocks = < ACLK_VCODEC>,
< HCLK_VCODEC>;
pm_qos = <_video_m0>;
};
- pd_vdu@RK3399_PD_VDU {
+ power-domain@RK3399_PD_VDU {
reg = ;
clocks = < ACLK_VDU>,
< HCLK_VDU>;
@@ -999,94 +999,94 @@
};
/* These power domains are grouped by VD_GPU */
- pd_gpu@RK3399_PD_GPU {
+ power-domain@RK3399_PD_GPU {
reg = ;
clocks = < ACLK_GPU>;
pm_qos = <_gpu>;
};
/* These power domains are grouped by VD_LOGIC */
- pd_edp@RK3399_PD_EDP {
+ power-domain@RK3399_PD_EDP {
reg = ;
clocks = < PCLK_EDP_CTRL>;
};
- pd_emmc@RK3399_PD_EMMC {
+ power-domain@RK3399_PD_EMMC {
reg = ;
clocks = < ACLK_EMMC>;
pm_qos = <_emmc>;
};
- pd_gmac@RK3399_PD_GMAC {
+ power-domain@RK3399_PD_GMAC {
reg = ;
clocks = < ACLK_GMAC>,
< PCLK_GMAC>;
pm_qos = <_gmac>;
};
- pd_sd@RK3399_PD_SD {
+ power-domain@RK3399_PD_SD {
reg = ;
clocks = < HCLK_SDMMC>,
< SCLK_SDMMC>;
pm_qos = <_sd>;
};
- pd_sdioaudio@RK3399_PD_SDIOAUDIO {
+ power-domain@RK3399_PD_SDIOAUDIO {
reg = ;
clocks = < HCLK_SDIO>;
pm_qos = <_sdioaudio>;
};
- pd_tcpc0@RK3399_PD_TCPD0 {
+ power-domain@RK3399_PD_TCPD0 {
reg = ;
clocks = < SCLK_UPHY0_TCPDCORE>,
< SCLK_UPHY0_TCPDPHY_REF>;
};
- pd_tcpc1@RK3399_PD_TCPD1 {
+ power-domain@RK3399_PD_TCPD1 {
reg = ;
clocks = < SCLK_UPHY1_TCPDCORE>,
< SCLK_UPHY1_TCPDPHY_REF>;
};
- pd_usb3@RK3399_PD_USB3 {
+ power-domain@RK3399_PD_USB3 {
reg = ;
clocks = < ACLK_USB3>;
pm_qos = <_usb_otg0>,
[PATCH v6 05/11] arm64: dts: rockchip: Fix power-controller node names for rk3328
Use more generic names (as recommended in the device tree specification
or the binding documentation)
Signed-off-by: Elaine Zhang
Reviewed-by: Enric Balletbo i Serra
---
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index 063ed0adbec4..084acfd597af 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -303,13 +303,13 @@
#address-cells = <1>;
#size-cells = <0>;
- pd_hevc@RK3328_PD_HEVC {
+ power-domain@RK3328_PD_HEVC {
reg = ;
};
- pd_video@RK3328_PD_VIDEO {
+ power-domain@RK3328_PD_VIDEO {
reg = ;
};
- pd_vpu@RK3328_PD_VPU {
+ power-domain@RK3328_PD_VPU {
reg = ;
clocks = < ACLK_VPU>, < HCLK_VPU>;
};
--
2.17.1
[PATCH v6 00/11] soc: rockchip: power-domain: add rk3568 powerdomains
Fix power-controller node names for dtbs_check. Convert power domain documentation to json-schema. Add a meaningful power domain name. Support power domain function for RK3568 Soc. Change in V6: [PATCH v6 1/11]: No change. [PATCH v6 2/11]: No change. [PATCH v6 3/11]: No change. [PATCH v6 4/11]: No change. [PATCH v6 5/11]: No change. [PATCH v6 6/11]: No change. [PATCH v6 7/11]: Use kbasename(node->full_name). [PATCH v6 8/11]: No change. [PATCH v6 9/11]: Update the commit message. [PATCH v6 10/11]: No change. [PATCH v6 11/11]: No change. Change in V5: [PATCH v5 1/11]: New. [PATCH v5 2/11]: New. [PATCH v5 3/11]: New. [PATCH v5 4/11]: New. [PATCH v5 5/11]: New. [PATCH v5 6/11]: New. [PATCH v5 7/11]: New. [PATCH v5 8/11]: No change. Same as [PATCH v4 1/4]. [PATCH v5 9/11]: [PATCH v4 2/4] Fix up yaml code styles. [PATCH v5 10/11]: No change. Same as [PATCH v4 3/4]. [PATCH v5 11/11]: [PATCH v4 4/4] add a meaningful power domain name for RK3568 Soc. Change in V4: [PATCH v4 1/4]: No change. [PATCH v4 2/4]: Fix up yaml code styles. Remove the new compatible to [PATCH v4 3/4] [PATCH v4 3/4]: Adding new compatible for RK3568 Soc. [PATCH v4 4/4]: No change. Same as [PATCH v3 3/3]. Change in V3: [PATCH v3 1/3]: No change. [PATCH v3 2/3]: Fix up the code styles and add rk3568 base on: https://patchwork.kernel.org/project/linux-rockchip/patch/20210225102643.653095-1-enric.balle...@collabora.com/ [PATCH v3 3/3]: No change. Change in V2: [PATCH v2 1/3]: No change. [PATCH v2 2/3]: Fix up yaml code styles. [PATCH v2 3/3]: No change. Elaine Zhang (11): arm: dts: rockchip: Fix power-controller node names for rk3066a arm: dts: rockchip: Fix power-controller node names for rk3188 arm: dts: rockchip: Fix power-controller node names for rk3288 arm64: dts: rockchip: Fix power-controller node names for px30 arm64: dts: rockchip: Fix power-controller node names for rk3328 arm64: dts: rockchip: Fix power-controller node names for rk3399 soc: rockchip: pm-domains: Add a meaningful power domain name dt-bindings: add power-domain header for RK3568 SoCs dt-bindings: power: rockchip: Convert to json-schema dt-bindings: power: rockchip: Add bindings for RK3568 Soc soc: rockchip: power-domain: add rk3568 powerdomains .../power/rockchip,power-controller.yaml | 293 ++ .../bindings/soc/rockchip/power_domain.txt| 136 arch/arm/boot/dts/rk3066a.dtsi| 6 +- arch/arm/boot/dts/rk3188.dtsi | 6 +- arch/arm/boot/dts/rk3288.dtsi | 8 +- arch/arm64/boot/dts/rockchip/px30.dtsi| 16 +- arch/arm64/boot/dts/rockchip/rk3328.dtsi | 6 +- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 40 +-- drivers/soc/rockchip/pm_domains.c | 252 --- include/dt-bindings/power/rk3568-power.h | 32 ++ 10 files changed, 511 insertions(+), 284 deletions(-) create mode 100644 Documentation/devicetree/bindings/power/rockchip,power-controller.yaml delete mode 100644 Documentation/devicetree/bindings/soc/rockchip/power_domain.txt create mode 100644 include/dt-bindings/power/rk3568-power.h -- 2.17.1
[PATCH v6 04/11] arm64: dts: rockchip: Fix power-controller node names for px30
Use more generic names (as recommended in the device tree specification
or the binding documentation)
Signed-off-by: Elaine Zhang
Reviewed-by: Enric Balletbo i Serra
---
arch/arm64/boot/dts/rockchip/px30.dtsi | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi
b/arch/arm64/boot/dts/rockchip/px30.dtsi
index c45b0cfcae09..fb3a863e0caf 100644
--- a/arch/arm64/boot/dts/rockchip/px30.dtsi
+++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
@@ -247,20 +247,20 @@
#size-cells = <0>;
/* These power domains are grouped by VD_LOGIC */
- pd_usb@PX30_PD_USB {
+ power-domain@PX30_PD_USB {
reg = ;
clocks = < HCLK_HOST>,
< HCLK_OTG>,
< SCLK_OTG_ADP>;
pm_qos = <_usb_host>, <_usb_otg>;
};
- pd_sdcard@PX30_PD_SDCARD {
+ power-domain@PX30_PD_SDCARD {
reg = ;
clocks = < HCLK_SDMMC>,
< SCLK_SDMMC>;
pm_qos = <_sdmmc>;
};
- pd_gmac@PX30_PD_GMAC {
+ power-domain@PX30_PD_GMAC {
reg = ;
clocks = < ACLK_GMAC>,
< PCLK_GMAC>,
@@ -268,7 +268,7 @@
< SCLK_GMAC_RX_TX>;
pm_qos = <_gmac>;
};
- pd_mmc_nand@PX30_PD_MMC_NAND {
+ power-domain@PX30_PD_MMC_NAND {
reg = ;
clocks = < HCLK_NANDC>,
< HCLK_EMMC>,
@@ -281,14 +281,14 @@
pm_qos = <_emmc>, <_nand>,
<_sdio>, <_sfc>;
};
- pd_vpu@PX30_PD_VPU {
+ power-domain@PX30_PD_VPU {
reg = ;
clocks = < ACLK_VPU>,
< HCLK_VPU>,
< SCLK_CORE_VPU>;
pm_qos = <_vpu>, <_vpu_r128>;
};
- pd_vo@PX30_PD_VO {
+ power-domain@PX30_PD_VO {
reg = ;
clocks = < ACLK_RGA>,
< ACLK_VOPB>,
@@ -304,7 +304,7 @@
pm_qos = <_rga_rd>, <_rga_wr>,
<_vop_m0>, <_vop_m1>;
};
- pd_vi@PX30_PD_VI {
+ power-domain@PX30_PD_VI {
reg = ;
clocks = < ACLK_CIF>,
< ACLK_ISP>,
@@ -315,7 +315,7 @@
<_isp_wr>, <_isp_m1>,
<_vip>;
};
- pd_gpu@PX30_PD_GPU {
+ power-domain@PX30_PD_GPU {
reg = ;
clocks = < SCLK_GPU>;
pm_qos = <_gpu>;
--
2.17.1
[PATCH v6 03/11] arm: dts: rockchip: Fix power-controller node names for rk3288
Use more generic names (as recommended in the device tree specification
or the binding documentation)
Signed-off-by: Elaine Zhang
Reviewed-by: Enric Balletbo i Serra
---
arch/arm/boot/dts/rk3288.dtsi | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index ea7416c31f9b..6f4d7929e351 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -769,7 +769,7 @@
* *_HDMI HDMI
* *_MIPI_*MIPI
*/
- pd_vio@RK3288_PD_VIO {
+ power-domain@RK3288_PD_VIO {
reg = ;
clocks = < ACLK_IEP>,
< ACLK_ISP>,
@@ -811,7 +811,7 @@
* Note: The following 3 are HEVC(H.265) clocks,
* and on the ACLK_HEVC_NIU (NOC).
*/
- pd_hevc@RK3288_PD_HEVC {
+ power-domain@RK3288_PD_HEVC {
reg = ;
clocks = < ACLK_HEVC>,
< SCLK_HEVC_CABAC>,
@@ -825,7 +825,7 @@
* (video endecoder & decoder) clocks that on the
* ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
*/
- pd_video@RK3288_PD_VIDEO {
+ power-domain@RK3288_PD_VIDEO {
reg = ;
clocks = < ACLK_VCODEC>,
< HCLK_VCODEC>;
@@ -836,7 +836,7 @@
* Note: ACLK_GPU is the GPU clock,
* and on the ACLK_GPU_NIU (NOC).
*/
- pd_gpu@RK3288_PD_GPU {
+ power-domain@RK3288_PD_GPU {
reg = ;
clocks = < ACLK_GPU>;
pm_qos = <_gpu_r>,
--
2.17.1
[PATCH v6 01/11] arm: dts: rockchip: Fix power-controller node names for rk3066a
Use more generic names (as recommended in the device tree specification
or the binding documentation)
Signed-off-by: Elaine Zhang
Reviewed-by: Enric Balletbo i Serra
---
arch/arm/boot/dts/rk3066a.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index 252750c97f97..bbc3bff50856 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -755,7 +755,7 @@
#address-cells = <1>;
#size-cells = <0>;
- pd_vio@RK3066_PD_VIO {
+ power-domain@RK3066_PD_VIO {
reg = ;
clocks = < ACLK_LCDC0>,
< ACLK_LCDC1>,
@@ -782,7 +782,7 @@
<_rga>;
};
- pd_video@RK3066_PD_VIDEO {
+ power-domain@RK3066_PD_VIDEO {
reg = ;
clocks = < ACLK_VDPU>,
< ACLK_VEPU>,
@@ -791,7 +791,7 @@
pm_qos = <_vpu>;
};
- pd_gpu@RK3066_PD_GPU {
+ power-domain@RK3066_PD_GPU {
reg = ;
clocks = < ACLK_GPU>;
pm_qos = <_gpu>;
--
2.17.1
[PATCH v6 02/11] arm: dts: rockchip: Fix power-controller node names for rk3188
Use more generic names (as recommended in the device tree specification
or the binding documentation)
Signed-off-by: Elaine Zhang
Reviewed-by: Enric Balletbo i Serra
---
arch/arm/boot/dts/rk3188.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
index 2298a8d840ba..5db32fdbe6e7 100644
--- a/arch/arm/boot/dts/rk3188.dtsi
+++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -699,7 +699,7 @@
#address-cells = <1>;
#size-cells = <0>;
- pd_vio@RK3188_PD_VIO {
+ power-domain@RK3188_PD_VIO {
reg = ;
clocks = < ACLK_LCDC0>,
< ACLK_LCDC1>,
@@ -721,7 +721,7 @@
<_rga>;
};
- pd_video@RK3188_PD_VIDEO {
+ power-domain@RK3188_PD_VIDEO {
reg = ;
clocks = < ACLK_VDPU>,
< ACLK_VEPU>,
@@ -730,7 +730,7 @@
pm_qos = <_vpu>;
};
- pd_gpu@RK3188_PD_GPU {
+ power-domain@RK3188_PD_GPU {
reg = ;
clocks = < ACLK_GPU>;
pm_qos = <_gpu>;
--
2.17.1
[RESEND PATCH v5 07/11] soc: rockchip: pm-domains: Add a meaningful power domain name
Add the power domains names to the power domain info struct so we
have meaningful name for every power domain.
Signed-off-by: Elaine Zhang
---
drivers/soc/rockchip/pm_domains.c | 221 +++---
1 file changed, 114 insertions(+), 107 deletions(-)
diff --git a/drivers/soc/rockchip/pm_domains.c
b/drivers/soc/rockchip/pm_domains.c
index 54eb6cfc5d5b..3e6268c30d7e 100644
--- a/drivers/soc/rockchip/pm_domains.c
+++ b/drivers/soc/rockchip/pm_domains.c
@@ -29,6 +29,7 @@
#include
struct rockchip_domain_info {
+ const char *name;
int pwr_mask;
int status_mask;
int req_mask;
@@ -85,8 +86,9 @@ struct rockchip_pmu {
#define to_rockchip_pd(gpd) container_of(gpd, struct rockchip_pm_domain, genpd)
-#define DOMAIN(pwr, status, req, idle, ack, wakeup)\
+#define DOMAIN(_name, pwr, status, req, idle, ack, wakeup) \
{ \
+ .name = _name, \
.pwr_mask = (pwr), \
.status_mask = (status),\
.req_mask = (req), \
@@ -95,8 +97,9 @@ struct rockchip_pmu {
.active_wakeup = (wakeup), \
}
-#define DOMAIN_M(pwr, status, req, idle, ack, wakeup) \
+#define DOMAIN_M(_name, pwr, status, req, idle, ack, wakeup) \
{ \
+ .name = _name, \
.pwr_w_mask = (pwr) << 16, \
.pwr_mask = (pwr), \
.status_mask = (status),\
@@ -107,8 +110,9 @@ struct rockchip_pmu {
.active_wakeup = wakeup,\
}
-#define DOMAIN_RK3036(req, ack, idle, wakeup) \
+#define DOMAIN_RK3036(_name, req, ack, idle, wakeup) \
{ \
+ .name = _name, \
.req_mask = (req), \
.req_w_mask = (req) << 16, \
.ack_mask = (ack), \
@@ -116,20 +120,20 @@ struct rockchip_pmu {
.active_wakeup = wakeup,\
}
-#define DOMAIN_PX30(pwr, status, req, wakeup) \
- DOMAIN_M(pwr, status, req, (req) << 16, req, wakeup)
+#define DOMAIN_PX30(name, pwr, status, req, wakeup)\
+ DOMAIN_M(name, pwr, status, req, (req) << 16, req, wakeup)
-#define DOMAIN_RK3288(pwr, status, req, wakeup)\
- DOMAIN(pwr, status, req, req, (req) << 16, wakeup)
+#define DOMAIN_RK3288(name, pwr, status, req, wakeup) \
+ DOMAIN(name, pwr, status, req, req, (req) << 16, wakeup)
-#define DOMAIN_RK3328(pwr, status, req, wakeup)\
- DOMAIN_M(pwr, pwr, req, (req) << 10, req, wakeup)
+#define DOMAIN_RK3328(name, pwr, status, req, wakeup) \
+ DOMAIN_M(name, pwr, pwr, req, (req) << 10, req, wakeup)
-#define DOMAIN_RK3368(pwr, status, req, wakeup)\
- DOMAIN(pwr, status, req, (req) << 16, req, wakeup)
+#define DOMAIN_RK3368(name, pwr, status, req, wakeup) \
+ DOMAIN(name, pwr, status, req, (req) << 16, req, wakeup)
-#define DOMAIN_RK3399(pwr, status, req, wakeup)\
- DOMAIN(pwr, status, req, req, req, wakeup)
+#define DOMAIN_RK3399(name, pwr, status, req, wakeup) \
+ DOMAIN(name, pwr, status, req, req, req, wakeup)
static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd)
{
@@ -490,7 +494,10 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu
*pmu,
goto err_unprepare_clocks;
}
- pd->genpd.name = node->name;
+ if (!pd->info->name)
+ pd->genpd.name = node->name;
+ else
+ pd->genpd.name = pd->info->name;
pd->genpd.power_off = rockchip_pd_power_off;
pd->genpd.power_on = rockchip_pd_power_on;
pd->genpd.attach_dev = rockchip_pd_attach_dev;
@@ -716,129 +723,129 @@ static int rockchip_pm_domain_probe(struct
platform_device *pdev)
}
static const struct rockchip_domain_info px30_pm_domains[] = {
- [PX30_PD_USB] = DOMAIN_PX30(BIT(5), BIT(5), BIT(10), false),
- [PX30_PD_SDCARD]= DOMAIN_PX30(BIT(8), BIT(8), BIT(9), false),
- [PX30_PD_GMAC] = DOMAIN_PX30(BIT(10), BIT(10), BIT(6), false),
- [PX30_PD_MMC_NAND] = DOMAIN_PX30(BIT(11), BIT(11), BIT(5), false),
- [PX30_PD_VPU] = DOMAIN_PX30(BIT(12), BIT(12), BIT(14), false),
- [PX30_PD_VO]= DOMAIN_PX30(BIT(13), BIT(13), BIT(7), false),
- [PX30_PD_VI]= DOMAIN_PX30(BIT(14), BIT(14), BIT(8), false),
- [PX30_PD_GPU] = DOMAIN_PX30(BIT(15), BIT(15)
[PATCH v5 11/11] soc: rockchip: power-domain: add rk3568 powerdomains
Add power-domains found on rk3568 socs.
Signed-off-by: Elaine Zhang
---
drivers/soc/rockchip/pm_domains.c | 31 +++
1 file changed, 31 insertions(+)
diff --git a/drivers/soc/rockchip/pm_domains.c
b/drivers/soc/rockchip/pm_domains.c
index d661d967079f..7b231cbcc17b 100644
--- a/drivers/soc/rockchip/pm_domains.c
+++ b/drivers/soc/rockchip/pm_domains.c
@@ -27,6 +27,7 @@
#include
#include
#include
+#include
struct rockchip_domain_info {
const char *name;
@@ -135,6 +136,9 @@ struct rockchip_pmu {
#define DOMAIN_RK3399(name, pwr, status, req, wakeup) \
DOMAIN(name, pwr, status, req, req, req, wakeup)
+#define DOMAIN_RK3568(name, pwr, req, wakeup) \
+ DOMAIN_M(name, pwr, pwr, req, req, req, wakeup)
+
static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd)
{
struct rockchip_pmu *pmu = pd->pmu;
@@ -848,6 +852,18 @@ static const struct rockchip_domain_info
rk3399_pm_domains[] = {
[RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399("sdioaudio", BIT(31), BIT(31),
BIT(29), true),
};
+static const struct rockchip_domain_info rk3568_pm_domains[] = {
+ [RK3568_PD_NPU] = DOMAIN_RK3568("npu", BIT(1), BIT(2), false),
+ [RK3568_PD_GPU] = DOMAIN_RK3568("gpu", BIT(0), BIT(1), false),
+ [RK3568_PD_VI] = DOMAIN_RK3568("vi", BIT(6), BIT(3), false),
+ [RK3568_PD_VO] = DOMAIN_RK3568("vo", BIT(7), BIT(4), false),
+ [RK3568_PD_RGA] = DOMAIN_RK3568("rga", BIT(5), BIT(5), false),
+ [RK3568_PD_VPU] = DOMAIN_RK3568("vpu", BIT(2), BIT(6), false),
+ [RK3568_PD_RKVDEC] = DOMAIN_RK3568("vdec", BIT(4), BIT(8), false),
+ [RK3568_PD_RKVENC] = DOMAIN_RK3568("venc", BIT(3), BIT(7), false),
+ [RK3568_PD_PIPE]= DOMAIN_RK3568("pipe", BIT(8), BIT(11), false),
+};
+
static const struct rockchip_pmu_info px30_pmu = {
.pwr_offset = 0x18,
.status_offset = 0x20,
@@ -983,6 +999,17 @@ static const struct rockchip_pmu_info rk3399_pmu = {
.domain_info = rk3399_pm_domains,
};
+static const struct rockchip_pmu_info rk3568_pmu = {
+ .pwr_offset = 0xa0,
+ .status_offset = 0x98,
+ .req_offset = 0x50,
+ .idle_offset = 0x68,
+ .ack_offset = 0x60,
+
+ .num_domains = ARRAY_SIZE(rk3568_pm_domains),
+ .domain_info = rk3568_pm_domains,
+};
+
static const struct of_device_id rockchip_pm_domain_dt_match[] = {
{
.compatible = "rockchip,px30-power-controller",
@@ -1028,6 +1055,10 @@ static const struct of_device_id
rockchip_pm_domain_dt_match[] = {
.compatible = "rockchip,rk3399-power-controller",
.data = (void *)_pmu,
},
+ {
+ .compatible = "rockchip,rk3568-power-controller",
+ .data = (void *)_pmu,
+ },
{ /* sentinel */ },
};
--
2.17.1
[PATCH v5 10/11] dt-bindings: power: rockchip: Add bindings for RK3568 Soc
Add the compatible string for RK3568 SoC. Signed-off-by: Elaine Zhang --- .../devicetree/bindings/power/rockchip,power-controller.yaml| 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml index 9fec9e227432..a4d223255c3b 100644 --- a/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml +++ b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml @@ -37,6 +37,7 @@ properties: - rockchip,rk3366-power-controller - rockchip,rk3368-power-controller - rockchip,rk3399-power-controller + - rockchip,rk3568-power-controller "#power-domain-cells": const: 1 @@ -90,6 +91,7 @@ patternProperties: "include/dt-bindings/power/rk3366-power.h" "include/dt-bindings/power/rk3368-power.h" "include/dt-bindings/power/rk3399-power.h" + "include/dt-bindings/power/rk3568-power.h" clocks: description: | -- 2.17.1
[PATCH v5 09/11] dt-bindings: power: rockchip: Convert to json-schema
Convert the soc/rockchip/power_domain.txt binding document to json-schema and move to the power bindings directory. Signed-off-by: Enric Balletbo i Serra Signed-off-by: Elaine Zhang --- .../power/rockchip,power-controller.yaml | 291 ++ .../bindings/soc/rockchip/power_domain.txt| 136 2 files changed, 291 insertions(+), 136 deletions(-) create mode 100644 Documentation/devicetree/bindings/power/rockchip,power-controller.yaml delete mode 100644 Documentation/devicetree/bindings/soc/rockchip/power_domain.txt diff --git a/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml new file mode 100644 index ..9fec9e227432 --- /dev/null +++ b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml @@ -0,0 +1,291 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/rockchip,power-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip Power Domains + +maintainers: + - Elaine Zhang + - Heiko Stuebner + +description: | + Rockchip processors include support for multiple power domains which can be + powered up/down by software based on different application scenarios to save power. + + Power domains contained within power-controller node are generic power domain + providers documented in Documentation/devicetree/bindings/power/power-domain.yaml. + + IP cores belonging to a power domain should contain a "power-domains" + property that is a phandle for the power domain node representing the domain. + +properties: + $nodename: +const: power-controller + + compatible: +enum: + - rockchip,px30-power-controller + - rockchip,rk3036-power-controller + - rockchip,rk3066-power-controller + - rockchip,rk3128-power-controller + - rockchip,rk3188-power-controller + - rockchip,rk3228-power-controller + - rockchip,rk3288-power-controller + - rockchip,rk3328-power-controller + - rockchip,rk3366-power-controller + - rockchip,rk3368-power-controller + - rockchip,rk3399-power-controller + + "#power-domain-cells": +const: 1 + + "#address-cells": +const: 1 + + "#size-cells": +const: 0 + + clocks: true + + assigned-clocks: +minItems: 1 + + assigned-clock-parents: +minItems: 1 + +patternProperties: + "^power-domain@[0-9a-f]+$": +type: object +description: | + Represents the power domains within the power controller node as documented + in Documentation/devicetree/bindings/power/power-domain.yaml. + +properties: + + "#power-domain-cells": +description: + Must be 0 for nodes representing a single PM domain and 1 for nodes + providing multiple PM domains. + + "#address-cells": +const: 1 + + "#size-cells": +const: 0 + + reg: +maxItems: 1 +description: | + Power domain index. Valid values are defined in + "include/dt-bindings/power/px30-power.h" + "include/dt-bindings/power/rk3036-power.h" + "include/dt-bindings/power/rk3066-power.h" + "include/dt-bindings/power/rk3128-power.h" + "include/dt-bindings/power/rk3188-power.h" + "include/dt-bindings/power/rk3228-power.h" + "include/dt-bindings/power/rk3288-power.h" + "include/dt-bindings/power/rk3328-power.h" + "include/dt-bindings/power/rk3366-power.h" + "include/dt-bindings/power/rk3368-power.h" + "include/dt-bindings/power/rk3399-power.h" + + clocks: +description: | + A number of phandles to clocks that need to be enabled while power domain + switches state. + + pm_qos: +description: | + A number of phandles to qos blocks which need to be saved and restored + while power domain switches state. + +patternProperties: + "^power-domain@[0-9a-f]+$": +type: object +description: | + Represents a power domain child within a power domain parent node. + +properties: + + "#power-domain-cells": +description: + Must be 0 for nodes representing a single PM domain and 1 for nodes + providing multiple PM domains. + + "#address-cells": +const: 1 + + "#size-cells": +const: 0 + + reg: +maxItems: 1 + + clocks: +description: | + A number of phandles to clocks that need to be enabled while power domain + switches state. + + pm_qos: +description: | +
[PATCH v5 08/11] dt-bindings: add power-domain header for RK3568 SoCs
According to a description from TRM, add all the power domains Signed-off-by: Elaine Zhang --- include/dt-bindings/power/rk3568-power.h | 32 1 file changed, 32 insertions(+) create mode 100644 include/dt-bindings/power/rk3568-power.h diff --git a/include/dt-bindings/power/rk3568-power.h b/include/dt-bindings/power/rk3568-power.h new file mode 100644 index ..6cc1af1a9d26 --- /dev/null +++ b/include/dt-bindings/power/rk3568-power.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_POWER_RK3568_POWER_H__ +#define __DT_BINDINGS_POWER_RK3568_POWER_H__ + +/* VD_CORE */ +#define RK3568_PD_CPU_00 +#define RK3568_PD_CPU_11 +#define RK3568_PD_CPU_22 +#define RK3568_PD_CPU_33 +#define RK3568_PD_CORE_ALIVE 4 + +/* VD_PMU */ +#define RK3568_PD_PMU 5 + +/* VD_NPU */ +#define RK3568_PD_NPU 6 + +/* VD_GPU */ +#define RK3568_PD_GPU 7 + +/* VD_LOGIC */ +#define RK3568_PD_VI 8 +#define RK3568_PD_VO 9 +#define RK3568_PD_RGA 10 +#define RK3568_PD_VPU 11 +#define RK3568_PD_CENTER 12 +#define RK3568_PD_RKVDEC 13 +#define RK3568_PD_RKVENC 14 +#define RK3568_PD_PIPE 15 +#define RK3568_PD_LOGIC_ALIVE 16 + +#endif -- 2.17.1
[PATCH v5 07/11] soc: rockchip: pm-domains: Add a meaningful power domain name
Add the power domains names to the power domain info struct so we
have meaningful name for every power domain.
Signed-off-by: Elaine Zhang
---
drivers/soc/rockchip/pm_domains.c | 217 +++---
1 file changed, 112 insertions(+), 105 deletions(-)
diff --git a/drivers/soc/rockchip/pm_domains.c
b/drivers/soc/rockchip/pm_domains.c
index 54eb6cfc5d5b..d661d967079f 100644
--- a/drivers/soc/rockchip/pm_domains.c
+++ b/drivers/soc/rockchip/pm_domains.c
@@ -29,6 +29,7 @@
#include
struct rockchip_domain_info {
+ const char *name;
int pwr_mask;
int status_mask;
int req_mask;
@@ -85,8 +86,9 @@ struct rockchip_pmu {
#define to_rockchip_pd(gpd) container_of(gpd, struct rockchip_pm_domain, genpd)
-#define DOMAIN(pwr, status, req, idle, ack, wakeup)\
+#define DOMAIN(_name, pwr, status, req, idle, ack, wakeup) \
{ \
+ .name = _name, \
.pwr_mask = (pwr), \
.status_mask = (status),\
.req_mask = (req), \
@@ -95,8 +97,9 @@ struct rockchip_pmu {
.active_wakeup = (wakeup), \
}
-#define DOMAIN_M(pwr, status, req, idle, ack, wakeup) \
+#define DOMAIN_M(_name, pwr, status, req, idle, ack, wakeup) \
{ \
+ .name = _name, \
.pwr_w_mask = (pwr) << 16, \
.pwr_mask = (pwr), \
.status_mask = (status),\
@@ -107,8 +110,9 @@ struct rockchip_pmu {
.active_wakeup = wakeup,\
}
-#define DOMAIN_RK3036(req, ack, idle, wakeup) \
+#define DOMAIN_RK3036(_name, req, ack, idle, wakeup) \
{ \
+ .name = _name, \
.req_mask = (req), \
.req_w_mask = (req) << 16, \
.ack_mask = (ack), \
@@ -119,17 +123,17 @@ struct rockchip_pmu {
#define DOMAIN_PX30(pwr, status, req, wakeup) \
DOMAIN_M(pwr, status, req, (req) << 16, req, wakeup)
-#define DOMAIN_RK3288(pwr, status, req, wakeup)\
- DOMAIN(pwr, status, req, req, (req) << 16, wakeup)
+#define DOMAIN_RK3288(name, pwr, status, req, wakeup) \
+ DOMAIN(name, pwr, status, req, req, (req) << 16, wakeup)
-#define DOMAIN_RK3328(pwr, status, req, wakeup)\
- DOMAIN_M(pwr, pwr, req, (req) << 10, req, wakeup)
+#define DOMAIN_RK3328(name, pwr, status, req, wakeup) \
+ DOMAIN_M(name, pwr, pwr, req, (req) << 10, req, wakeup)
-#define DOMAIN_RK3368(pwr, status, req, wakeup)\
- DOMAIN(pwr, status, req, (req) << 16, req, wakeup)
+#define DOMAIN_RK3368(name, pwr, status, req, wakeup) \
+ DOMAIN(name, pwr, status, req, (req) << 16, req, wakeup)
-#define DOMAIN_RK3399(pwr, status, req, wakeup)\
- DOMAIN(pwr, status, req, req, req, wakeup)
+#define DOMAIN_RK3399(name, pwr, status, req, wakeup) \
+ DOMAIN(name, pwr, status, req, req, req, wakeup)
static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd)
{
@@ -490,7 +494,10 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu
*pmu,
goto err_unprepare_clocks;
}
- pd->genpd.name = node->name;
+ if (!pd->info->name)
+ pd->genpd.name = node->name;
+ else
+ pd->genpd.name = pd->info->name;
pd->genpd.power_off = rockchip_pd_power_off;
pd->genpd.power_on = rockchip_pd_power_on;
pd->genpd.attach_dev = rockchip_pd_attach_dev;
@@ -716,129 +723,129 @@ static int rockchip_pm_domain_probe(struct
platform_device *pdev)
}
static const struct rockchip_domain_info px30_pm_domains[] = {
- [PX30_PD_USB] = DOMAIN_PX30(BIT(5), BIT(5), BIT(10), false),
- [PX30_PD_SDCARD]= DOMAIN_PX30(BIT(8), BIT(8), BIT(9), false),
- [PX30_PD_GMAC] = DOMAIN_PX30(BIT(10), BIT(10), BIT(6), false),
- [PX30_PD_MMC_NAND] = DOMAIN_PX30(BIT(11), BIT(11), BIT(5), false),
- [PX30_PD_VPU] = DOMAIN_PX30(BIT(12), BIT(12), BIT(14), false),
- [PX30_PD_VO]= DOMAIN_PX30(BIT(13), BIT(13), BIT(7), false),
- [PX30_PD_VI]= DOMAIN_PX30(BIT(14), BIT(14), BIT(8), false),
- [PX30_PD_GPU] = DOMAIN_PX30(BIT(15), BIT(15), BIT(2), false),
+ [PX30_PD_USB] = DOMAIN_PX30("usb", BIT(5), BIT(5), BIT(10),
false),
+ [PX30_PD_SDCARD]= DOMAIN_PX30("sdcard", BIT(8), BIT(
[PATCH v5 06/11] arm64: dts: rockchip: Fix power-controller node names for rk3399
Use more generic names (as recommended in the device tree specification
or the binding documentation)
Signed-off-by: Elaine Zhang
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 40
1 file changed, 20 insertions(+), 20 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index edbbf35fe19e..142f5593d48b 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -971,26 +971,26 @@
#size-cells = <0>;
/* These power domains are grouped by VD_CENTER */
- pd_iep@RK3399_PD_IEP {
+ power-domain@RK3399_PD_IEP {
reg = ;
clocks = < ACLK_IEP>,
< HCLK_IEP>;
pm_qos = <_iep>;
};
- pd_rga@RK3399_PD_RGA {
+ power-domain@RK3399_PD_RGA {
reg = ;
clocks = < ACLK_RGA>,
< HCLK_RGA>;
pm_qos = <_rga_r>,
<_rga_w>;
};
- pd_vcodec@RK3399_PD_VCODEC {
+ power-domain@RK3399_PD_VCODEC {
reg = ;
clocks = < ACLK_VCODEC>,
< HCLK_VCODEC>;
pm_qos = <_video_m0>;
};
- pd_vdu@RK3399_PD_VDU {
+ power-domain@RK3399_PD_VDU {
reg = ;
clocks = < ACLK_VDU>,
< HCLK_VDU>;
@@ -999,94 +999,94 @@
};
/* These power domains are grouped by VD_GPU */
- pd_gpu@RK3399_PD_GPU {
+ power-domain@RK3399_PD_GPU {
reg = ;
clocks = < ACLK_GPU>;
pm_qos = <_gpu>;
};
/* These power domains are grouped by VD_LOGIC */
- pd_edp@RK3399_PD_EDP {
+ power-domain@RK3399_PD_EDP {
reg = ;
clocks = < PCLK_EDP_CTRL>;
};
- pd_emmc@RK3399_PD_EMMC {
+ power-domain@RK3399_PD_EMMC {
reg = ;
clocks = < ACLK_EMMC>;
pm_qos = <_emmc>;
};
- pd_gmac@RK3399_PD_GMAC {
+ power-domain@RK3399_PD_GMAC {
reg = ;
clocks = < ACLK_GMAC>,
< PCLK_GMAC>;
pm_qos = <_gmac>;
};
- pd_sd@RK3399_PD_SD {
+ power-domain@RK3399_PD_SD {
reg = ;
clocks = < HCLK_SDMMC>,
< SCLK_SDMMC>;
pm_qos = <_sd>;
};
- pd_sdioaudio@RK3399_PD_SDIOAUDIO {
+ power-domain@RK3399_PD_SDIOAUDIO {
reg = ;
clocks = < HCLK_SDIO>;
pm_qos = <_sdioaudio>;
};
- pd_tcpc0@RK3399_PD_TCPD0 {
+ power-domain@RK3399_PD_TCPD0 {
reg = ;
clocks = < SCLK_UPHY0_TCPDCORE>,
< SCLK_UPHY0_TCPDPHY_REF>;
};
- pd_tcpc1@RK3399_PD_TCPD1 {
+ power-domain@RK3399_PD_TCPD1 {
reg = ;
clocks = < SCLK_UPHY1_TCPDCORE>,
< SCLK_UPHY1_TCPDPHY_REF>;
};
- pd_usb3@RK3399_PD_USB3 {
+ power-domain@RK3399_PD_USB3 {
reg = ;
clocks = < ACLK_USB3>;
pm_qos = <_usb_otg0>,
<_usb_otg1>;
[PATCH v5 05/11] arm64: dts: rockchip: Fix power-controller node names for rk3328
Use more generic names (as recommended in the device tree specification
or the binding documentation)
Signed-off-by: Elaine Zhang
---
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index 063ed0adbec4..084acfd597af 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -303,13 +303,13 @@
#address-cells = <1>;
#size-cells = <0>;
- pd_hevc@RK3328_PD_HEVC {
+ power-domain@RK3328_PD_HEVC {
reg = ;
};
- pd_video@RK3328_PD_VIDEO {
+ power-domain@RK3328_PD_VIDEO {
reg = ;
};
- pd_vpu@RK3328_PD_VPU {
+ power-domain@RK3328_PD_VPU {
reg = ;
clocks = < ACLK_VPU>, < HCLK_VPU>;
};
--
2.17.1
[PATCH v5 01/11] arm: dts: rockchip: Fix power-controller node names for rk3066a
Use more generic names (as recommended in the device tree specification
or the binding documentation)
Signed-off-by: Elaine Zhang
---
arch/arm/boot/dts/rk3066a.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index 252750c97f97..bbc3bff50856 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -755,7 +755,7 @@
#address-cells = <1>;
#size-cells = <0>;
- pd_vio@RK3066_PD_VIO {
+ power-domain@RK3066_PD_VIO {
reg = ;
clocks = < ACLK_LCDC0>,
< ACLK_LCDC1>,
@@ -782,7 +782,7 @@
<_rga>;
};
- pd_video@RK3066_PD_VIDEO {
+ power-domain@RK3066_PD_VIDEO {
reg = ;
clocks = < ACLK_VDPU>,
< ACLK_VEPU>,
@@ -791,7 +791,7 @@
pm_qos = <_vpu>;
};
- pd_gpu@RK3066_PD_GPU {
+ power-domain@RK3066_PD_GPU {
reg = ;
clocks = < ACLK_GPU>;
pm_qos = <_gpu>;
--
2.17.1
[PATCH v5 00/11] soc: rockchip: power-domain: add rk3568 powerdomains
Fix power-controller node names for dtbs_check. Convert power domain documentation to json-schema. Add a meaningful power domain name. Support power domain function for RK3568 Soc. Change in V5: [PATCH v5 1/11]: New. [PATCH v5 2/11]: New. [PATCH v5 3/11]: New. [PATCH v5 4/11]: New. [PATCH v5 5/11]: New. [PATCH v5 6/11]: New. [PATCH v5 7/11]: New. [PATCH v5 8/11]: No change. Same as [PATCH v4 1/4]. [PATCH v5 9/11]: [PATCH v4 2/4] Fix up yaml code styles. [PATCH v5 10/11]: No change. Same as [PATCH v4 3/4]. [PATCH v5 11/11]: [PATCH v4 4/4] add a meaningful power domain name for RK3568 Soc. Change in V4: [PATCH v4 1/4]: No change. [PATCH v4 2/4]: Fix up yaml code styles. Remove the new compatible to [PATCH v4 3/4] [PATCH v4 3/4]: Adding new compatible for RK3568 Soc. [PATCH v4 4/4]: No change. Same as [PATCH v3 3/3]. Change in V3: [PATCH v3 1/3]: No change. [PATCH v3 2/3]: Fix up the code styles and add rk3568 base on: https://patchwork.kernel.org/project/linux-rockchip/patch/20210225102643.653095-1-enric.balle...@collabora.com/ [PATCH v3 3/3]: No change. Change in V2: [PATCH v2 1/3]: No change. [PATCH v2 2/3]: Fix up yaml code styles. [PATCH v2 3/3]: No change. Elaine Zhang (11): arm: dts: rockchip: Fix power-controller node names for rk3066a arm: dts: rockchip: Fix power-controller node names for rk3188 arm: dts: rockchip: Fix power-controller node names for rk3288 arm64: dts: rockchip: Fix power-controller node names for px30 arm64: dts: rockchip: Fix power-controller node names for rk3328 arm64: dts: rockchip: Fix power-controller node names for rk3399 soc: rockchip: pm-domains: Add a meaningful power domain name dt-bindings: add power-domain header for RK3568 SoCs dt-bindings: power: rockchip: Convert to json-schema dt-bindings: power: rockchip: Add bindings for RK3568 Soc soc: rockchip: power-domain: add rk3568 powerdomains .../power/rockchip,power-controller.yaml | 293 ++ .../bindings/soc/rockchip/power_domain.txt| 136 arch/arm/boot/dts/rk3066a.dtsi| 6 +- arch/arm/boot/dts/rk3188.dtsi | 6 +- arch/arm/boot/dts/rk3288.dtsi | 8 +- arch/arm64/boot/dts/rockchip/px30.dtsi| 16 +- arch/arm64/boot/dts/rockchip/rk3328.dtsi | 6 +- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 40 +-- drivers/soc/rockchip/pm_domains.c | 248 --- include/dt-bindings/power/rk3568-power.h | 32 ++ 10 files changed, 509 insertions(+), 282 deletions(-) create mode 100644 Documentation/devicetree/bindings/power/rockchip,power-controller.yaml delete mode 100644 Documentation/devicetree/bindings/soc/rockchip/power_domain.txt create mode 100644 include/dt-bindings/power/rk3568-power.h -- 2.17.1
[PATCH v5 02/11] arm: dts: rockchip: Fix power-controller node names for rk3188
Use more generic names (as recommended in the device tree specification
or the binding documentation)
Signed-off-by: Elaine Zhang
---
arch/arm/boot/dts/rk3188.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
index 2298a8d840ba..5db32fdbe6e7 100644
--- a/arch/arm/boot/dts/rk3188.dtsi
+++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -699,7 +699,7 @@
#address-cells = <1>;
#size-cells = <0>;
- pd_vio@RK3188_PD_VIO {
+ power-domain@RK3188_PD_VIO {
reg = ;
clocks = < ACLK_LCDC0>,
< ACLK_LCDC1>,
@@ -721,7 +721,7 @@
<_rga>;
};
- pd_video@RK3188_PD_VIDEO {
+ power-domain@RK3188_PD_VIDEO {
reg = ;
clocks = < ACLK_VDPU>,
< ACLK_VEPU>,
@@ -730,7 +730,7 @@
pm_qos = <_vpu>;
};
- pd_gpu@RK3188_PD_GPU {
+ power-domain@RK3188_PD_GPU {
reg = ;
clocks = < ACLK_GPU>;
pm_qos = <_gpu>;
--
2.17.1
[PATCH v5 03/11] arm: dts: rockchip: Fix power-controller node names for rk3288
Use more generic names (as recommended in the device tree specification
or the binding documentation)
Signed-off-by: Elaine Zhang
---
arch/arm/boot/dts/rk3288.dtsi | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index ea7416c31f9b..6f4d7929e351 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -769,7 +769,7 @@
* *_HDMI HDMI
* *_MIPI_*MIPI
*/
- pd_vio@RK3288_PD_VIO {
+ power-domain@RK3288_PD_VIO {
reg = ;
clocks = < ACLK_IEP>,
< ACLK_ISP>,
@@ -811,7 +811,7 @@
* Note: The following 3 are HEVC(H.265) clocks,
* and on the ACLK_HEVC_NIU (NOC).
*/
- pd_hevc@RK3288_PD_HEVC {
+ power-domain@RK3288_PD_HEVC {
reg = ;
clocks = < ACLK_HEVC>,
< SCLK_HEVC_CABAC>,
@@ -825,7 +825,7 @@
* (video endecoder & decoder) clocks that on the
* ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
*/
- pd_video@RK3288_PD_VIDEO {
+ power-domain@RK3288_PD_VIDEO {
reg = ;
clocks = < ACLK_VCODEC>,
< HCLK_VCODEC>;
@@ -836,7 +836,7 @@
* Note: ACLK_GPU is the GPU clock,
* and on the ACLK_GPU_NIU (NOC).
*/
- pd_gpu@RK3288_PD_GPU {
+ power-domain@RK3288_PD_GPU {
reg = ;
clocks = < ACLK_GPU>;
pm_qos = <_gpu_r>,
--
2.17.1
[PATCH v5 04/11] arm64: dts: rockchip: Fix power-controller node names for px30
Use more generic names (as recommended in the device tree specification
or the binding documentation)
Signed-off-by: Elaine Zhang
---
arch/arm64/boot/dts/rockchip/px30.dtsi | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi
b/arch/arm64/boot/dts/rockchip/px30.dtsi
index c45b0cfcae09..fb3a863e0caf 100644
--- a/arch/arm64/boot/dts/rockchip/px30.dtsi
+++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
@@ -247,20 +247,20 @@
#size-cells = <0>;
/* These power domains are grouped by VD_LOGIC */
- pd_usb@PX30_PD_USB {
+ power-domain@PX30_PD_USB {
reg = ;
clocks = < HCLK_HOST>,
< HCLK_OTG>,
< SCLK_OTG_ADP>;
pm_qos = <_usb_host>, <_usb_otg>;
};
- pd_sdcard@PX30_PD_SDCARD {
+ power-domain@PX30_PD_SDCARD {
reg = ;
clocks = < HCLK_SDMMC>,
< SCLK_SDMMC>;
pm_qos = <_sdmmc>;
};
- pd_gmac@PX30_PD_GMAC {
+ power-domain@PX30_PD_GMAC {
reg = ;
clocks = < ACLK_GMAC>,
< PCLK_GMAC>,
@@ -268,7 +268,7 @@
< SCLK_GMAC_RX_TX>;
pm_qos = <_gmac>;
};
- pd_mmc_nand@PX30_PD_MMC_NAND {
+ power-domain@PX30_PD_MMC_NAND {
reg = ;
clocks = < HCLK_NANDC>,
< HCLK_EMMC>,
@@ -281,14 +281,14 @@
pm_qos = <_emmc>, <_nand>,
<_sdio>, <_sfc>;
};
- pd_vpu@PX30_PD_VPU {
+ power-domain@PX30_PD_VPU {
reg = ;
clocks = < ACLK_VPU>,
< HCLK_VPU>,
< SCLK_CORE_VPU>;
pm_qos = <_vpu>, <_vpu_r128>;
};
- pd_vo@PX30_PD_VO {
+ power-domain@PX30_PD_VO {
reg = ;
clocks = < ACLK_RGA>,
< ACLK_VOPB>,
@@ -304,7 +304,7 @@
pm_qos = <_rga_rd>, <_rga_wr>,
<_vop_m0>, <_vop_m1>;
};
- pd_vi@PX30_PD_VI {
+ power-domain@PX30_PD_VI {
reg = ;
clocks = < ACLK_CIF>,
< ACLK_ISP>,
@@ -315,7 +315,7 @@
<_isp_wr>, <_isp_m1>,
<_vip>;
};
- pd_gpu@PX30_PD_GPU {
+ power-domain@PX30_PD_GPU {
reg = ;
clocks = < SCLK_GPU>;
pm_qos = <_gpu>;
--
2.17.1
[PATCH v4 2/4] dt-bindings: power: rockchip: Convert to json-schema
Convert the soc/rockchip/power_domain.txt binding document to
json-schema and move to the power bindings directory.
Signed-off-by: Enric Balletbo i Serra
Signed-off-by: Elaine Zhang
---
.../power/rockchip,power-controller.yaml | 284 ++
.../bindings/soc/rockchip/power_domain.txt| 136 -
2 files changed, 284 insertions(+), 136 deletions(-)
create mode 100644
Documentation/devicetree/bindings/power/rockchip,power-controller.yaml
delete mode 100644
Documentation/devicetree/bindings/soc/rockchip/power_domain.txt
diff --git
a/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml
b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml
new file mode 100644
index ..a220322c5139
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml
@@ -0,0 +1,284 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/power/rockchip,power-controller.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip Power Domains
+
+maintainers:
+ - Elaine Zhang
+ - Rob Herring
+ - Heiko Stuebner
+
+description: |
+ Rockchip processors include support for multiple power domains which can be
+ powered up/down by software based on different application scenarios to save
power.
+
+ Power domains contained within power-controller node are generic power domain
+ providers documented in
Documentation/devicetree/bindings/power/power-domain.yaml.
+
+ IP cores belonging to a power domain should contain a "power-domains"
+ property that is a phandle for the power domain node representing the domain.
+
+properties:
+ $nodename:
+const: power-controller
+
+ compatible:
+enum:
+ - rockchip,px30-power-controller
+ - rockchip,rk3036-power-controller
+ - rockchip,rk3066-power-controller
+ - rockchip,rk3128-power-controller
+ - rockchip,rk3188-power-controller
+ - rockchip,rk3228-power-controller
+ - rockchip,rk3288-power-controller
+ - rockchip,rk3328-power-controller
+ - rockchip,rk3366-power-controller
+ - rockchip,rk3368-power-controller
+ - rockchip,rk3399-power-controller
+
+ "#power-domain-cells":
+const: 1
+
+ "#address-cells":
+const: 1
+
+ "#size-cells":
+const: 0
+
+patternProperties:
+ "^pd_[0-9a-z_]{2,10}@[0-9a-f]+$":
+type: object
+description: |
+ Represents the power domains within the power controller node as
documented
+ in Documentation/devicetree/bindings/power/power-domain.yaml.
+
+properties:
+
+ "#power-domain-cells":
+description:
+ Must be 0 for nodes representing a single PM domain and 1 for nodes
+ providing multiple PM domains.
+
+ "#address-cells":
+const: 1
+
+ "#size-cells":
+const: 0
+
+ reg:
+maxItems: 1
+description: |
+ Power domain index. Valid values are defined in
+ "include/dt-bindings/power/px30-power.h"
+ "include/dt-bindings/power/rk3036-power.h"
+ "include/dt-bindings/power/rk3066-power.h"
+ "include/dt-bindings/power/rk3128-power.h"
+ "include/dt-bindings/power/rk3188-power.h"
+ "include/dt-bindings/power/rk3228-power.h"
+ "include/dt-bindings/power/rk3288-power.h"
+ "include/dt-bindings/power/rk3328-power.h"
+ "include/dt-bindings/power/rk3366-power.h"
+ "include/dt-bindings/power/rk3368-power.h"
+ "include/dt-bindings/power/rk3399-power.h"
+
+ clocks:
+description: |
+ A number of phandles to clocks that need to be enabled while power
domain
+ switches state.
+
+ pm_qos:
+description: |
+ A number of phandles to qos blocks which need to be saved and
restored
+ while power domain switches state.
+
+patternProperties:
+ "^pd_[0-9a-z_]{2,10}@[0-9a-f]+$":
+type: object
+description: |
+ Represents a power domain child within a power domain parent node.
+
+properties:
+
+ "#power-domain-cells":
+description:
+ Must be 0 for nodes representing a single PM domain and 1 for
nodes
+ providing multiple PM domains.
+
+ "#address-cells":
+const: 1
+
+ "#size-cells":
+const: 0
+
+ reg:
+maxItems: 1
+
+ clocks:
+description: |
+ A number of phandles to clocks that need to be enabled while
power domain
+ switches state.
+
+ pm_qos:
+description: |
+ A number of phandles to qos blocks which need to be saved and
restored
+
[PATCH v4 0/4] soc: rockchip: power-domain: add rk3568 powerdomains
Support power domain function for RK3568 Soc. Change in V4: [PATCH v4 1/4]: No change. [PATCH v4 2/4]: Fix up yaml code styles. Remove the new compatible to [PATCH v4 3/4] [PATCH v4 3/4]: Adding new compatible for RK3568 Soc. [PATCH v4 4/4]: No change. Same as [PATCH v3 3/3]. Change in V3: [PATCH v3 1/3]: No change. [PATCH v3 2/3]: Fix up the code styles and add rk3568 base on: https://patchwork.kernel.org/project/linux-rockchip/patch/20210225102643.653095-1-enric.balle...@collabora.com/ [PATCH v3 3/3]: No change. Change in V2: [PATCH v2 1/3]: No change. [PATCH v2 2/3]: Fix up yaml code styles. [PATCH v2 3/3]: No change. Elaine Zhang (4): dt-bindings: add power-domain header for RK3568 SoCs dt-bindings: power: rockchip: Convert to json-schema dt-bindings: power: rockchip: Add bindings for RK3568 Soc soc: rockchip: power-domain: add rk3568 powerdomains .../power/rockchip,power-controller.yaml | 286 ++ .../bindings/soc/rockchip/power_domain.txt| 136 - drivers/soc/rockchip/pm_domains.c | 31 ++ include/dt-bindings/power/rk3568-power.h | 32 ++ 4 files changed, 349 insertions(+), 136 deletions(-) create mode 100644 Documentation/devicetree/bindings/power/rockchip,power-controller.yaml delete mode 100644 Documentation/devicetree/bindings/soc/rockchip/power_domain.txt create mode 100644 include/dt-bindings/power/rk3568-power.h -- 2.17.1
[PATCH v4 4/4] soc: rockchip: power-domain: add rk3568 powerdomains
Add power-domains found on rk3568 socs.
Signed-off-by: Elaine Zhang
---
drivers/soc/rockchip/pm_domains.c | 31 +++
1 file changed, 31 insertions(+)
diff --git a/drivers/soc/rockchip/pm_domains.c
b/drivers/soc/rockchip/pm_domains.c
index 54eb6cfc5d5b..a2c19c845cf2 100644
--- a/drivers/soc/rockchip/pm_domains.c
+++ b/drivers/soc/rockchip/pm_domains.c
@@ -27,6 +27,7 @@
#include
#include
#include
+#include
struct rockchip_domain_info {
int pwr_mask;
@@ -131,6 +132,9 @@ struct rockchip_pmu {
#define DOMAIN_RK3399(pwr, status, req, wakeup)\
DOMAIN(pwr, status, req, req, req, wakeup)
+#define DOMAIN_RK3568(pwr, req, wakeup)\
+ DOMAIN_M(pwr, pwr, req, req, req, wakeup)
+
static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd)
{
struct rockchip_pmu *pmu = pd->pmu;
@@ -841,6 +845,18 @@ static const struct rockchip_domain_info
rk3399_pm_domains[] = {
[RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399(BIT(31), BIT(31), BIT(29),
true),
};
+static const struct rockchip_domain_info rk3568_pm_domains[] = {
+ [RK3568_PD_NPU] = DOMAIN_RK3568(BIT(1), BIT(2), false),
+ [RK3568_PD_GPU] = DOMAIN_RK3568(BIT(0), BIT(1), false),
+ [RK3568_PD_VI] = DOMAIN_RK3568(BIT(6), BIT(3), false),
+ [RK3568_PD_VO] = DOMAIN_RK3568(BIT(7), BIT(4), false),
+ [RK3568_PD_RGA] = DOMAIN_RK3568(BIT(5), BIT(5), false),
+ [RK3568_PD_VPU] = DOMAIN_RK3568(BIT(2), BIT(6), false),
+ [RK3568_PD_RKVDEC] = DOMAIN_RK3568(BIT(4), BIT(8), false),
+ [RK3568_PD_RKVENC] = DOMAIN_RK3568(BIT(3), BIT(7), false),
+ [RK3568_PD_PIPE]= DOMAIN_RK3568(BIT(8), BIT(11), false),
+};
+
static const struct rockchip_pmu_info px30_pmu = {
.pwr_offset = 0x18,
.status_offset = 0x20,
@@ -976,6 +992,17 @@ static const struct rockchip_pmu_info rk3399_pmu = {
.domain_info = rk3399_pm_domains,
};
+static const struct rockchip_pmu_info rk3568_pmu = {
+ .pwr_offset = 0xa0,
+ .status_offset = 0x98,
+ .req_offset = 0x50,
+ .idle_offset = 0x68,
+ .ack_offset = 0x60,
+
+ .num_domains = ARRAY_SIZE(rk3568_pm_domains),
+ .domain_info = rk3568_pm_domains,
+};
+
static const struct of_device_id rockchip_pm_domain_dt_match[] = {
{
.compatible = "rockchip,px30-power-controller",
@@ -1021,6 +1048,10 @@ static const struct of_device_id
rockchip_pm_domain_dt_match[] = {
.compatible = "rockchip,rk3399-power-controller",
.data = (void *)_pmu,
},
+ {
+ .compatible = "rockchip,rk3568-power-controller",
+ .data = (void *)_pmu,
+ },
{ /* sentinel */ },
};
--
2.17.1
[PATCH v4 1/4] dt-bindings: add power-domain header for RK3568 SoCs
According to a description from TRM, add all the power domains Signed-off-by: Elaine Zhang --- include/dt-bindings/power/rk3568-power.h | 32 1 file changed, 32 insertions(+) create mode 100644 include/dt-bindings/power/rk3568-power.h diff --git a/include/dt-bindings/power/rk3568-power.h b/include/dt-bindings/power/rk3568-power.h new file mode 100644 index ..6cc1af1a9d26 --- /dev/null +++ b/include/dt-bindings/power/rk3568-power.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_POWER_RK3568_POWER_H__ +#define __DT_BINDINGS_POWER_RK3568_POWER_H__ + +/* VD_CORE */ +#define RK3568_PD_CPU_00 +#define RK3568_PD_CPU_11 +#define RK3568_PD_CPU_22 +#define RK3568_PD_CPU_33 +#define RK3568_PD_CORE_ALIVE 4 + +/* VD_PMU */ +#define RK3568_PD_PMU 5 + +/* VD_NPU */ +#define RK3568_PD_NPU 6 + +/* VD_GPU */ +#define RK3568_PD_GPU 7 + +/* VD_LOGIC */ +#define RK3568_PD_VI 8 +#define RK3568_PD_VO 9 +#define RK3568_PD_RGA 10 +#define RK3568_PD_VPU 11 +#define RK3568_PD_CENTER 12 +#define RK3568_PD_RKVDEC 13 +#define RK3568_PD_RKVENC 14 +#define RK3568_PD_PIPE 15 +#define RK3568_PD_LOGIC_ALIVE 16 + +#endif -- 2.17.1
[PATCH v4 3/4] dt-bindings: power: rockchip: Add bindings for RK3568 Soc
Add the compatible string for RK3568 SoC. Signed-off-by: Elaine Zhang --- .../devicetree/bindings/power/rockchip,power-controller.yaml| 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml index a220322c5139..6927e56e0674 100644 --- a/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml +++ b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml @@ -38,6 +38,7 @@ properties: - rockchip,rk3366-power-controller - rockchip,rk3368-power-controller - rockchip,rk3399-power-controller + - rockchip,rk3568-power-controller "#power-domain-cells": const: 1 @@ -83,6 +84,7 @@ patternProperties: "include/dt-bindings/power/rk3366-power.h" "include/dt-bindings/power/rk3368-power.h" "include/dt-bindings/power/rk3399-power.h" + "include/dt-bindings/power/rk3568-power.h" clocks: description: | -- 2.17.1
[PATCH v3 0/3] soc: rockchip: power-domain: add rk3568 powerdomains
Support power domain function for RK3568 Soc. Change in V3: [PATCH v3 1/3]: No change. [PATCH v3 2/3]: Fix up the code styles and add rk3568 base on: https://patchwork.kernel.org/project/linux-rockchip/patch/20210225102643.653095-1-enric.balle...@collabora.com/ [PATCH v3 3/3]: No change. Change in V2: [PATCH v2 1/3]: No change. [PATCH v2 2/3]: Fix up yaml code styles. [PATCH v2 3/3]: No change. Elaine Zhang (3): dt-bindings: add power-domain header for RK3568 SoCs dt-bindings: Convert the rockchip power_domain to YAML and extend soc: rockchip: power-domain: add rk3568 powerdomains .../power/rockchip,power-controller.yaml | 286 ++ .../bindings/soc/rockchip/power_domain.txt| 136 - drivers/soc/rockchip/pm_domains.c | 31 ++ include/dt-bindings/power/rk3568-power.h | 32 ++ 4 files changed, 349 insertions(+), 136 deletions(-) create mode 100644 Documentation/devicetree/bindings/power/rockchip,power-controller.yaml delete mode 100644 Documentation/devicetree/bindings/soc/rockchip/power_domain.txt create mode 100644 include/dt-bindings/power/rk3568-power.h -- 2.17.1
[PATCH v3 3/3] soc: rockchip: power-domain: add rk3568 powerdomains
Add power-domains found on rk3568 socs.
Signed-off-by: Elaine Zhang
---
drivers/soc/rockchip/pm_domains.c | 31 +++
1 file changed, 31 insertions(+)
diff --git a/drivers/soc/rockchip/pm_domains.c
b/drivers/soc/rockchip/pm_domains.c
index 54eb6cfc5d5b..a2c19c845cf2 100644
--- a/drivers/soc/rockchip/pm_domains.c
+++ b/drivers/soc/rockchip/pm_domains.c
@@ -27,6 +27,7 @@
#include
#include
#include
+#include
struct rockchip_domain_info {
int pwr_mask;
@@ -131,6 +132,9 @@ struct rockchip_pmu {
#define DOMAIN_RK3399(pwr, status, req, wakeup)\
DOMAIN(pwr, status, req, req, req, wakeup)
+#define DOMAIN_RK3568(pwr, req, wakeup)\
+ DOMAIN_M(pwr, pwr, req, req, req, wakeup)
+
static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd)
{
struct rockchip_pmu *pmu = pd->pmu;
@@ -841,6 +845,18 @@ static const struct rockchip_domain_info
rk3399_pm_domains[] = {
[RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399(BIT(31), BIT(31), BIT(29),
true),
};
+static const struct rockchip_domain_info rk3568_pm_domains[] = {
+ [RK3568_PD_NPU] = DOMAIN_RK3568(BIT(1), BIT(2), false),
+ [RK3568_PD_GPU] = DOMAIN_RK3568(BIT(0), BIT(1), false),
+ [RK3568_PD_VI] = DOMAIN_RK3568(BIT(6), BIT(3), false),
+ [RK3568_PD_VO] = DOMAIN_RK3568(BIT(7), BIT(4), false),
+ [RK3568_PD_RGA] = DOMAIN_RK3568(BIT(5), BIT(5), false),
+ [RK3568_PD_VPU] = DOMAIN_RK3568(BIT(2), BIT(6), false),
+ [RK3568_PD_RKVDEC] = DOMAIN_RK3568(BIT(4), BIT(8), false),
+ [RK3568_PD_RKVENC] = DOMAIN_RK3568(BIT(3), BIT(7), false),
+ [RK3568_PD_PIPE]= DOMAIN_RK3568(BIT(8), BIT(11), false),
+};
+
static const struct rockchip_pmu_info px30_pmu = {
.pwr_offset = 0x18,
.status_offset = 0x20,
@@ -976,6 +992,17 @@ static const struct rockchip_pmu_info rk3399_pmu = {
.domain_info = rk3399_pm_domains,
};
+static const struct rockchip_pmu_info rk3568_pmu = {
+ .pwr_offset = 0xa0,
+ .status_offset = 0x98,
+ .req_offset = 0x50,
+ .idle_offset = 0x68,
+ .ack_offset = 0x60,
+
+ .num_domains = ARRAY_SIZE(rk3568_pm_domains),
+ .domain_info = rk3568_pm_domains,
+};
+
static const struct of_device_id rockchip_pm_domain_dt_match[] = {
{
.compatible = "rockchip,px30-power-controller",
@@ -1021,6 +1048,10 @@ static const struct of_device_id
rockchip_pm_domain_dt_match[] = {
.compatible = "rockchip,rk3399-power-controller",
.data = (void *)_pmu,
},
+ {
+ .compatible = "rockchip,rk3568-power-controller",
+ .data = (void *)_pmu,
+ },
{ /* sentinel */ },
};
--
2.17.1
[PATCH v3 2/3] dt-bindings: power: rockchip: Convert to json-schema and extend
Convert the soc/rockchip/power_domain.txt binding document to
json-schema and move to the power bindings directory.
Add RK3568 SoCs for rockchip power binding document.
Signed-off-by: Enric Balletbo i Serra
Signed-off-by: Elaine Zhang
---
.../power/rockchip,power-controller.yaml | 286 ++
.../bindings/soc/rockchip/power_domain.txt| 136 -
2 files changed, 286 insertions(+), 136 deletions(-)
create mode 100644
Documentation/devicetree/bindings/power/rockchip,power-controller.yaml
delete mode 100644
Documentation/devicetree/bindings/soc/rockchip/power_domain.txt
diff --git
a/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml
b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml
new file mode 100644
index ..0d6b8962d098
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml
@@ -0,0 +1,286 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/power/rockchip,power-controller.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip Power Domains
+
+maintainers:
+ - Elaine Zhang
+ - Rob Herring
+ - Heiko Stuebner
+
+description: |
+ Rockchip processors include support for multiple power domains which can be
+ powered up/down by software based on different application scenes to save
power.
+
+ Power domains contained within power-controller node are generic power domain
+ providers documented in
Documentation/devicetree/bindings/power/power-domain.yaml.
+
+ IP cores belonging to a power domain should contain a 'power-domains'
+ property that is a phandle for the power domain node representing the domain.
+
+properties:
+ $nodename:
+const: power-controller
+
+ compatible:
+enum:
+ - rockchip,px30-power-controller
+ - rockchip,rk3036-power-controller
+ - rockchip,rk3066-power-controller
+ - rockchip,rk3128-power-controller
+ - rockchip,rk3188-power-controller
+ - rockchip,rk3228-power-controller
+ - rockchip,rk3288-power-controller
+ - rockchip,rk3328-power-controller
+ - rockchip,rk3366-power-controller
+ - rockchip,rk3368-power-controller
+ - rockchip,rk3399-power-controller
+ - rockchip,rk3568-power-controller
+
+ '#power-domain-cells':
+const: 1
+
+ '#address-cells':
+const: 1
+
+ '#size-cells':
+const: 0
+
+patternProperties:
+ "^pd_[0-9a-z_]{2,10}@[0-9a-f]+$":
+type: object
+description: |
+ Represents the power domains within the power controller node as
documented
+ in Documentation/devicetree/bindings/power/power-domain.yaml.
+
+properties:
+
+ '#power-domain-cells':
+description:
+ Must be 0 for nodes representing a single PM domain and 1 for nodes
+ providing multiple PM domains.
+
+ '#address-cells':
+const: 1
+
+ '#size-cells':
+const: 0
+
+ reg:
+maxItems: 1
+description: |
+ Power domain index. Valid values are defined in:
+ "include/dt-bindings/power/px30-power.h"
+ "include/dt-bindings/power/rk3036-power.h"
+ "include/dt-bindings/power/rk3066-power.h"
+ "include/dt-bindings/power/rk3128-power.h"
+ "include/dt-bindings/power/rk3188-power.h"
+ "include/dt-bindings/power/rk3228-power.h"
+ "include/dt-bindings/power/rk3288-power.h"
+ "include/dt-bindings/power/rk3328-power.h"
+ "include/dt-bindings/power/rk3366-power.h"
+ "include/dt-bindings/power/rk3368-power.h"
+ "include/dt-bindings/power/rk3399-power.h"
+ "include/dt-bindings/power/rk3399-power.h"
+
+ clocks:
+description: |
+ A number of phandles to clocks that need to be enabled while power
domain
+ switches state.
+
+ pm_qos:
+description: |
+ A number of phandles to qos blocks which need to be saved and
restored
+ while power domain switches state.
+
+patternProperties:
+ "^pd_[0-9a-z_]{2,10}@[0-9a-f]+$":
+type: object
+description: |
+ Represents a power domain child within a power domain parent node.
+
+properties:
+
+ '#power-domain-cells':
+description:
+ Must be 0 for nodes representing a single PM domain and 1 for
nodes
+ providing multiple PM domains.
+
+ '#address-cells':
+const: 1
+
+ '#size-cells':
+const: 0
+
+ reg:
+maxItems: 1
+
+ clocks:
+description: |
+ A number of phandles to clocks that need to be enabled while
power domain
+ switches state.
+
+ pm_qos:
+description: |
+ A number o
[PATCH v3 1/3] dt-bindings: add power-domain header for RK3568 SoCs
According to a description from TRM, add all the power domains Signed-off-by: Elaine Zhang --- include/dt-bindings/power/rk3568-power.h | 32 1 file changed, 32 insertions(+) create mode 100644 include/dt-bindings/power/rk3568-power.h diff --git a/include/dt-bindings/power/rk3568-power.h b/include/dt-bindings/power/rk3568-power.h new file mode 100644 index ..6cc1af1a9d26 --- /dev/null +++ b/include/dt-bindings/power/rk3568-power.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_POWER_RK3568_POWER_H__ +#define __DT_BINDINGS_POWER_RK3568_POWER_H__ + +/* VD_CORE */ +#define RK3568_PD_CPU_00 +#define RK3568_PD_CPU_11 +#define RK3568_PD_CPU_22 +#define RK3568_PD_CPU_33 +#define RK3568_PD_CORE_ALIVE 4 + +/* VD_PMU */ +#define RK3568_PD_PMU 5 + +/* VD_NPU */ +#define RK3568_PD_NPU 6 + +/* VD_GPU */ +#define RK3568_PD_GPU 7 + +/* VD_LOGIC */ +#define RK3568_PD_VI 8 +#define RK3568_PD_VO 9 +#define RK3568_PD_RGA 10 +#define RK3568_PD_VPU 11 +#define RK3568_PD_CENTER 12 +#define RK3568_PD_RKVDEC 13 +#define RK3568_PD_RKVENC 14 +#define RK3568_PD_PIPE 15 +#define RK3568_PD_LOGIC_ALIVE 16 + +#endif -- 2.17.1
[PATCH v2 0/3] soc: rockchip: power-domain: add rk3568 powerdomains
Support power domain function for RK3568 Soc. Change in V2: [PATCH v2 1/3]: No change. [PATCH v2 2/3]: Fix up yaml code styles. [PATCH v2 3/3]: No change. Elaine Zhang (3): dt-bindings: add power-domain header for RK3568 SoCs dt-bindings: Convert the rockchip power_domain to YAML and extend soc: rockchip: power-domain: add rk3568 powerdomains .../bindings/soc/rockchip/power_domain.txt| 136 - .../rockchip/rockchip,power-controller.yaml | 259 ++ drivers/soc/rockchip/pm_domains.c | 31 +++ include/dt-bindings/power/rk3568-power.h | 32 +++ 4 files changed, 322 insertions(+), 136 deletions(-) delete mode 100644 Documentation/devicetree/bindings/soc/rockchip/power_domain.txt create mode 100644 Documentation/devicetree/bindings/soc/rockchip/rockchip,power-controller.yaml create mode 100644 include/dt-bindings/power/rk3568-power.h -- 2.17.1
[PATCH v2 2/3] dt-bindings: Convert the rockchip power_domain to YAML and extend
This converts the rockchip power domain family bindings to YAML schema,
and add binding documentation for the power domains found on Rockchip
RK3568 SoCs.
Signed-off-by: Elaine Zhang
---
.../bindings/soc/rockchip/power_domain.txt| 136 -
.../rockchip/rockchip,power-controller.yaml | 259 ++
2 files changed, 259 insertions(+), 136 deletions(-)
delete mode 100644
Documentation/devicetree/bindings/soc/rockchip/power_domain.txt
create mode 100644
Documentation/devicetree/bindings/soc/rockchip/rockchip,power-controller.yaml
diff --git a/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt
b/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt
deleted file mode 100644
index 8304eceb62e4..
--- a/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt
+++ /dev/null
@@ -1,136 +0,0 @@
-* Rockchip Power Domains
-
-Rockchip processors include support for multiple power domains which can be
-powered up/down by software based on different application scenes to save
power.
-
-Required properties for power domain controller:
-- compatible: Should be one of the following.
- "rockchip,px30-power-controller" - for PX30 SoCs.
- "rockchip,rk3036-power-controller" - for RK3036 SoCs.
- "rockchip,rk3066-power-controller" - for RK3066 SoCs.
- "rockchip,rk3128-power-controller" - for RK3128 SoCs.
- "rockchip,rk3188-power-controller" - for RK3188 SoCs.
- "rockchip,rk3228-power-controller" - for RK3228 SoCs.
- "rockchip,rk3288-power-controller" - for RK3288 SoCs.
- "rockchip,rk3328-power-controller" - for RK3328 SoCs.
- "rockchip,rk3366-power-controller" - for RK3366 SoCs.
- "rockchip,rk3368-power-controller" - for RK3368 SoCs.
- "rockchip,rk3399-power-controller" - for RK3399 SoCs.
-- #power-domain-cells: Number of cells in a power-domain specifier.
- Should be 1 for multiple PM domains.
-- #address-cells: Should be 1.
-- #size-cells: Should be 0.
-
-Required properties for power domain sub nodes:
-- reg: index of the power domain, should use macros in:
- "include/dt-bindings/power/px30-power.h" - for PX30 type power domain.
- "include/dt-bindings/power/rk3036-power.h" - for RK3036 type power
domain.
- "include/dt-bindings/power/rk3066-power.h" - for RK3066 type power
domain.
- "include/dt-bindings/power/rk3128-power.h" - for RK3128 type power
domain.
- "include/dt-bindings/power/rk3188-power.h" - for RK3188 type power
domain.
- "include/dt-bindings/power/rk3228-power.h" - for RK3228 type power
domain.
- "include/dt-bindings/power/rk3288-power.h" - for RK3288 type power
domain.
- "include/dt-bindings/power/rk3328-power.h" - for RK3328 type power
domain.
- "include/dt-bindings/power/rk3366-power.h" - for RK3366 type power
domain.
- "include/dt-bindings/power/rk3368-power.h" - for RK3368 type power
domain.
- "include/dt-bindings/power/rk3399-power.h" - for RK3399 type power
domain.
-- clocks (optional): phandles to clocks which need to be enabled while power
domain
- switches state.
-- pm_qos (optional): phandles to qos blocks which need to be saved and restored
- while power domain switches state.
-
-Qos Example:
-
- qos_gpu: qos_gpu@ffaf {
- compatible ="syscon";
- reg = <0x0 0xffaf 0x0 0x20>;
- };
-
-Example:
-
- power: power-controller {
- compatible = "rockchip,rk3288-power-controller";
- #power-domain-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- pd_gpu {
- reg = ;
- clocks = < ACLK_GPU>;
- pm_qos = <_gpu>;
- };
- };
-
-power: power-controller {
-compatible = "rockchip,rk3368-power-controller";
-#power-domain-cells = <1>;
-#address-cells = <1>;
-#size-cells = <0>;
-
-pd_gpu_1 {
-reg = ;
-clocks = < ACLK_GPU_CFG>;
-};
-};
-
-Example 2:
- power: power-controller {
- compatible = "rockchip,rk3399-power-controller";
- #power-domain-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- pd_vio {
- #address-cells = <1>;
- #size-cells = <0>;
-
[PATCH v2 3/3] soc: rockchip: power-domain: add rk3568 powerdomains
Add power-domains found on rk3568 socs.
Signed-off-by: Elaine Zhang
---
drivers/soc/rockchip/pm_domains.c | 31 +++
1 file changed, 31 insertions(+)
diff --git a/drivers/soc/rockchip/pm_domains.c
b/drivers/soc/rockchip/pm_domains.c
index 54eb6cfc5d5b..a2c19c845cf2 100644
--- a/drivers/soc/rockchip/pm_domains.c
+++ b/drivers/soc/rockchip/pm_domains.c
@@ -27,6 +27,7 @@
#include
#include
#include
+#include
struct rockchip_domain_info {
int pwr_mask;
@@ -131,6 +132,9 @@ struct rockchip_pmu {
#define DOMAIN_RK3399(pwr, status, req, wakeup)\
DOMAIN(pwr, status, req, req, req, wakeup)
+#define DOMAIN_RK3568(pwr, req, wakeup)\
+ DOMAIN_M(pwr, pwr, req, req, req, wakeup)
+
static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd)
{
struct rockchip_pmu *pmu = pd->pmu;
@@ -841,6 +845,18 @@ static const struct rockchip_domain_info
rk3399_pm_domains[] = {
[RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399(BIT(31), BIT(31), BIT(29),
true),
};
+static const struct rockchip_domain_info rk3568_pm_domains[] = {
+ [RK3568_PD_NPU] = DOMAIN_RK3568(BIT(1), BIT(2), false),
+ [RK3568_PD_GPU] = DOMAIN_RK3568(BIT(0), BIT(1), false),
+ [RK3568_PD_VI] = DOMAIN_RK3568(BIT(6), BIT(3), false),
+ [RK3568_PD_VO] = DOMAIN_RK3568(BIT(7), BIT(4), false),
+ [RK3568_PD_RGA] = DOMAIN_RK3568(BIT(5), BIT(5), false),
+ [RK3568_PD_VPU] = DOMAIN_RK3568(BIT(2), BIT(6), false),
+ [RK3568_PD_RKVDEC] = DOMAIN_RK3568(BIT(4), BIT(8), false),
+ [RK3568_PD_RKVENC] = DOMAIN_RK3568(BIT(3), BIT(7), false),
+ [RK3568_PD_PIPE]= DOMAIN_RK3568(BIT(8), BIT(11), false),
+};
+
static const struct rockchip_pmu_info px30_pmu = {
.pwr_offset = 0x18,
.status_offset = 0x20,
@@ -976,6 +992,17 @@ static const struct rockchip_pmu_info rk3399_pmu = {
.domain_info = rk3399_pm_domains,
};
+static const struct rockchip_pmu_info rk3568_pmu = {
+ .pwr_offset = 0xa0,
+ .status_offset = 0x98,
+ .req_offset = 0x50,
+ .idle_offset = 0x68,
+ .ack_offset = 0x60,
+
+ .num_domains = ARRAY_SIZE(rk3568_pm_domains),
+ .domain_info = rk3568_pm_domains,
+};
+
static const struct of_device_id rockchip_pm_domain_dt_match[] = {
{
.compatible = "rockchip,px30-power-controller",
@@ -1021,6 +1048,10 @@ static const struct of_device_id
rockchip_pm_domain_dt_match[] = {
.compatible = "rockchip,rk3399-power-controller",
.data = (void *)_pmu,
},
+ {
+ .compatible = "rockchip,rk3568-power-controller",
+ .data = (void *)_pmu,
+ },
{ /* sentinel */ },
};
--
2.17.1
[PATCH v2 1/3] dt-bindings: add power-domain header for RK3568 SoCs
According to a description from TRM, add all the power domains Signed-off-by: Elaine Zhang --- include/dt-bindings/power/rk3568-power.h | 32 1 file changed, 32 insertions(+) create mode 100644 include/dt-bindings/power/rk3568-power.h diff --git a/include/dt-bindings/power/rk3568-power.h b/include/dt-bindings/power/rk3568-power.h new file mode 100644 index ..6cc1af1a9d26 --- /dev/null +++ b/include/dt-bindings/power/rk3568-power.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_POWER_RK3568_POWER_H__ +#define __DT_BINDINGS_POWER_RK3568_POWER_H__ + +/* VD_CORE */ +#define RK3568_PD_CPU_00 +#define RK3568_PD_CPU_11 +#define RK3568_PD_CPU_22 +#define RK3568_PD_CPU_33 +#define RK3568_PD_CORE_ALIVE 4 + +/* VD_PMU */ +#define RK3568_PD_PMU 5 + +/* VD_NPU */ +#define RK3568_PD_NPU 6 + +/* VD_GPU */ +#define RK3568_PD_GPU 7 + +/* VD_LOGIC */ +#define RK3568_PD_VI 8 +#define RK3568_PD_VO 9 +#define RK3568_PD_RGA 10 +#define RK3568_PD_VPU 11 +#define RK3568_PD_CENTER 12 +#define RK3568_PD_RKVDEC 13 +#define RK3568_PD_RKVENC 14 +#define RK3568_PD_PIPE 15 +#define RK3568_PD_LOGIC_ALIVE 16 + +#endif -- 2.17.1
[PATCH v1 0/3] soc: rockchip: power-domain: add rk3568 powerdomains
Support power domain function for RK3568 Soc. Elaine Zhang (3): dt-bindings: add power-domain header for RK3568 SoCs dt-bindings: Convert the rockchip power_domain to YAML and extend soc: rockchip: power-domain: add rk3568 powerdomains .../bindings/soc/rockchip/power_domain.txt| 136 .../rockchip/rockchip,power-controller.yaml | 199 ++ drivers/soc/rockchip/pm_domains.c | 31 +++ include/dt-bindings/power/rk3568-power.h | 32 +++ 4 files changed, 262 insertions(+), 136 deletions(-) delete mode 100644 Documentation/devicetree/bindings/soc/rockchip/power_domain.txt create mode 100644 Documentation/devicetree/bindings/soc/rockchip/rockchip,power-controller.yaml create mode 100644 include/dt-bindings/power/rk3568-power.h -- 2.17.1
[PATCH v1 1/3] dt-bindings: add power-domain header for RK3568 SoCs
According to a description from TRM, add all the power domains Signed-off-by: Elaine Zhang --- include/dt-bindings/power/rk3568-power.h | 32 1 file changed, 32 insertions(+) create mode 100644 include/dt-bindings/power/rk3568-power.h diff --git a/include/dt-bindings/power/rk3568-power.h b/include/dt-bindings/power/rk3568-power.h new file mode 100644 index ..6cc1af1a9d26 --- /dev/null +++ b/include/dt-bindings/power/rk3568-power.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_POWER_RK3568_POWER_H__ +#define __DT_BINDINGS_POWER_RK3568_POWER_H__ + +/* VD_CORE */ +#define RK3568_PD_CPU_00 +#define RK3568_PD_CPU_11 +#define RK3568_PD_CPU_22 +#define RK3568_PD_CPU_33 +#define RK3568_PD_CORE_ALIVE 4 + +/* VD_PMU */ +#define RK3568_PD_PMU 5 + +/* VD_NPU */ +#define RK3568_PD_NPU 6 + +/* VD_GPU */ +#define RK3568_PD_GPU 7 + +/* VD_LOGIC */ +#define RK3568_PD_VI 8 +#define RK3568_PD_VO 9 +#define RK3568_PD_RGA 10 +#define RK3568_PD_VPU 11 +#define RK3568_PD_CENTER 12 +#define RK3568_PD_RKVDEC 13 +#define RK3568_PD_RKVENC 14 +#define RK3568_PD_PIPE 15 +#define RK3568_PD_LOGIC_ALIVE 16 + +#endif -- 2.17.1
[PATCH v1 2/3] dt-bindings: Convert the rockchip power_domain to YAML and extend
This converts the rockchip power domain family bindings to YAML schema,
and add binding documentation for the power domains found on Rockchip
RK3568 SoCs.
Signed-off-by: Elaine Zhang
---
.../bindings/soc/rockchip/power_domain.txt| 136
.../rockchip/rockchip,power-controller.yaml | 196 ++
2 files changed, 196 insertions(+), 136 deletions(-)
delete mode 100644
Documentation/devicetree/bindings/soc/rockchip/power_domain.txt
create mode 100644
Documentation/devicetree/bindings/soc/rockchip/rockchip,power-controller.yaml
diff --git a/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt
b/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt
deleted file mode 100644
index 8304eceb62e4..
--- a/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt
+++ /dev/null
@@ -1,136 +0,0 @@
-* Rockchip Power Domains
-
-Rockchip processors include support for multiple power domains which can be
-powered up/down by software based on different application scenes to save
power.
-
-Required properties for power domain controller:
-- compatible: Should be one of the following.
- "rockchip,px30-power-controller" - for PX30 SoCs.
- "rockchip,rk3036-power-controller" - for RK3036 SoCs.
- "rockchip,rk3066-power-controller" - for RK3066 SoCs.
- "rockchip,rk3128-power-controller" - for RK3128 SoCs.
- "rockchip,rk3188-power-controller" - for RK3188 SoCs.
- "rockchip,rk3228-power-controller" - for RK3228 SoCs.
- "rockchip,rk3288-power-controller" - for RK3288 SoCs.
- "rockchip,rk3328-power-controller" - for RK3328 SoCs.
- "rockchip,rk3366-power-controller" - for RK3366 SoCs.
- "rockchip,rk3368-power-controller" - for RK3368 SoCs.
- "rockchip,rk3399-power-controller" - for RK3399 SoCs.
-- #power-domain-cells: Number of cells in a power-domain specifier.
- Should be 1 for multiple PM domains.
-- #address-cells: Should be 1.
-- #size-cells: Should be 0.
-
-Required properties for power domain sub nodes:
-- reg: index of the power domain, should use macros in:
- "include/dt-bindings/power/px30-power.h" - for PX30 type power domain.
- "include/dt-bindings/power/rk3036-power.h" - for RK3036 type power
domain.
- "include/dt-bindings/power/rk3066-power.h" - for RK3066 type power
domain.
- "include/dt-bindings/power/rk3128-power.h" - for RK3128 type power
domain.
- "include/dt-bindings/power/rk3188-power.h" - for RK3188 type power
domain.
- "include/dt-bindings/power/rk3228-power.h" - for RK3228 type power
domain.
- "include/dt-bindings/power/rk3288-power.h" - for RK3288 type power
domain.
- "include/dt-bindings/power/rk3328-power.h" - for RK3328 type power
domain.
- "include/dt-bindings/power/rk3366-power.h" - for RK3366 type power
domain.
- "include/dt-bindings/power/rk3368-power.h" - for RK3368 type power
domain.
- "include/dt-bindings/power/rk3399-power.h" - for RK3399 type power
domain.
-- clocks (optional): phandles to clocks which need to be enabled while power
domain
- switches state.
-- pm_qos (optional): phandles to qos blocks which need to be saved and restored
- while power domain switches state.
-
-Qos Example:
-
- qos_gpu: qos_gpu@ffaf {
- compatible ="syscon";
- reg = <0x0 0xffaf 0x0 0x20>;
- };
-
-Example:
-
- power: power-controller {
- compatible = "rockchip,rk3288-power-controller";
- #power-domain-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- pd_gpu {
- reg = ;
- clocks = < ACLK_GPU>;
- pm_qos = <_gpu>;
- };
- };
-
-power: power-controller {
-compatible = "rockchip,rk3368-power-controller";
-#power-domain-cells = <1>;
-#address-cells = <1>;
-#size-cells = <0>;
-
-pd_gpu_1 {
-reg = ;
-clocks = < ACLK_GPU_CFG>;
-};
-};
-
-Example 2:
- power: power-controller {
- compatible = "rockchip,rk3399-power-controller";
- #power-domain-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- pd_vio {
- #address-cells = <1>;
- #size-cells = <0>;
-
[PATCH v1 3/3] soc: rockchip: power-domain: add rk3568 powerdomains
Add power-domains found on rk3568 socs.
Signed-off-by: Elaine Zhang
---
drivers/soc/rockchip/pm_domains.c | 31 +++
1 file changed, 31 insertions(+)
diff --git a/drivers/soc/rockchip/pm_domains.c
b/drivers/soc/rockchip/pm_domains.c
index 54eb6cfc5d5b..a2c19c845cf2 100644
--- a/drivers/soc/rockchip/pm_domains.c
+++ b/drivers/soc/rockchip/pm_domains.c
@@ -27,6 +27,7 @@
#include
#include
#include
+#include
struct rockchip_domain_info {
int pwr_mask;
@@ -131,6 +132,9 @@ struct rockchip_pmu {
#define DOMAIN_RK3399(pwr, status, req, wakeup)\
DOMAIN(pwr, status, req, req, req, wakeup)
+#define DOMAIN_RK3568(pwr, req, wakeup)\
+ DOMAIN_M(pwr, pwr, req, req, req, wakeup)
+
static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd)
{
struct rockchip_pmu *pmu = pd->pmu;
@@ -841,6 +845,18 @@ static const struct rockchip_domain_info
rk3399_pm_domains[] = {
[RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399(BIT(31), BIT(31), BIT(29),
true),
};
+static const struct rockchip_domain_info rk3568_pm_domains[] = {
+ [RK3568_PD_NPU] = DOMAIN_RK3568(BIT(1), BIT(2), false),
+ [RK3568_PD_GPU] = DOMAIN_RK3568(BIT(0), BIT(1), false),
+ [RK3568_PD_VI] = DOMAIN_RK3568(BIT(6), BIT(3), false),
+ [RK3568_PD_VO] = DOMAIN_RK3568(BIT(7), BIT(4), false),
+ [RK3568_PD_RGA] = DOMAIN_RK3568(BIT(5), BIT(5), false),
+ [RK3568_PD_VPU] = DOMAIN_RK3568(BIT(2), BIT(6), false),
+ [RK3568_PD_RKVDEC] = DOMAIN_RK3568(BIT(4), BIT(8), false),
+ [RK3568_PD_RKVENC] = DOMAIN_RK3568(BIT(3), BIT(7), false),
+ [RK3568_PD_PIPE]= DOMAIN_RK3568(BIT(8), BIT(11), false),
+};
+
static const struct rockchip_pmu_info px30_pmu = {
.pwr_offset = 0x18,
.status_offset = 0x20,
@@ -976,6 +992,17 @@ static const struct rockchip_pmu_info rk3399_pmu = {
.domain_info = rk3399_pm_domains,
};
+static const struct rockchip_pmu_info rk3568_pmu = {
+ .pwr_offset = 0xa0,
+ .status_offset = 0x98,
+ .req_offset = 0x50,
+ .idle_offset = 0x68,
+ .ack_offset = 0x60,
+
+ .num_domains = ARRAY_SIZE(rk3568_pm_domains),
+ .domain_info = rk3568_pm_domains,
+};
+
static const struct of_device_id rockchip_pm_domain_dt_match[] = {
{
.compatible = "rockchip,px30-power-controller",
@@ -1021,6 +1048,10 @@ static const struct of_device_id
rockchip_pm_domain_dt_match[] = {
.compatible = "rockchip,rk3399-power-controller",
.data = (void *)_pmu,
},
+ {
+ .compatible = "rockchip,rk3568-power-controller",
+ .data = (void *)_pmu,
+ },
{ /* sentinel */ },
};
--
2.17.1
[PATCH v5 3/4] clk: rockchip: support more core div setting
Use arrays to support more core independent div settings.
A55 supports each core to work at different frequencies, and each core
has an independent divider control.
Signed-off-by: Elaine Zhang
Reviewed-by: Kever Yang
---
drivers/clk/rockchip/clk-cpu.c| 53 +--
drivers/clk/rockchip/clk-px30.c | 7 ++--
drivers/clk/rockchip/clk-rk3036.c | 7 ++--
drivers/clk/rockchip/clk-rk3128.c | 7 ++--
drivers/clk/rockchip/clk-rk3188.c | 14
drivers/clk/rockchip/clk-rk3228.c | 7 ++--
drivers/clk/rockchip/clk-rk3288.c | 7 ++--
drivers/clk/rockchip/clk-rk3308.c | 7 ++--
drivers/clk/rockchip/clk-rk3328.c | 7 ++--
drivers/clk/rockchip/clk-rk3368.c | 14
drivers/clk/rockchip/clk-rk3399.c | 14
drivers/clk/rockchip/clk-rv1108.c | 7 ++--
drivers/clk/rockchip/clk.h| 24 +++---
13 files changed, 98 insertions(+), 77 deletions(-)
diff --git a/drivers/clk/rockchip/clk-cpu.c b/drivers/clk/rockchip/clk-cpu.c
index fa9027fb1920..47288197c9d7 100644
--- a/drivers/clk/rockchip/clk-cpu.c
+++ b/drivers/clk/rockchip/clk-cpu.c
@@ -84,10 +84,10 @@ static unsigned long rockchip_cpuclk_recalc_rate(struct
clk_hw *hw,
{
struct rockchip_cpuclk *cpuclk = to_rockchip_cpuclk_hw(hw);
const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data;
- u32 clksel0 = readl_relaxed(cpuclk->reg_base + reg_data->core_reg);
+ u32 clksel0 = readl_relaxed(cpuclk->reg_base + reg_data->core_reg[0]);
- clksel0 >>= reg_data->div_core_shift;
- clksel0 &= reg_data->div_core_mask;
+ clksel0 >>= reg_data->div_core_shift[0];
+ clksel0 &= reg_data->div_core_mask[0];
return parent_rate / (clksel0 + 1);
}
@@ -120,6 +120,7 @@ static int rockchip_cpuclk_pre_rate_change(struct
rockchip_cpuclk *cpuclk,
const struct rockchip_cpuclk_rate_table *rate;
unsigned long alt_prate, alt_div;
unsigned long flags;
+ int i = 0;
/* check validity of the new rate */
rate = rockchip_get_cpuclk_settings(cpuclk, ndata->new_rate);
@@ -142,10 +143,10 @@ static int rockchip_cpuclk_pre_rate_change(struct
rockchip_cpuclk *cpuclk,
if (alt_prate > ndata->old_rate) {
/* calculate dividers */
alt_div = DIV_ROUND_UP(alt_prate, ndata->old_rate) - 1;
- if (alt_div > reg_data->div_core_mask) {
+ if (alt_div > reg_data->div_core_mask[0]) {
pr_warn("%s: limiting alt-divider %lu to %d\n",
- __func__, alt_div, reg_data->div_core_mask);
- alt_div = reg_data->div_core_mask;
+ __func__, alt_div, reg_data->div_core_mask[0]);
+ alt_div = reg_data->div_core_mask[0];
}
/*
@@ -158,19 +159,17 @@ static int rockchip_cpuclk_pre_rate_change(struct
rockchip_cpuclk *cpuclk,
pr_debug("%s: setting div %lu as alt-rate %lu > old-rate %lu\n",
__func__, alt_div, alt_prate, ndata->old_rate);
- writel(HIWORD_UPDATE(alt_div, reg_data->div_core_mask,
- reg_data->div_core_shift) |
- HIWORD_UPDATE(reg_data->mux_core_alt,
-reg_data->mux_core_mask,
-reg_data->mux_core_shift),
- cpuclk->reg_base + reg_data->core_reg);
- } else {
- /* select alternate parent */
- writel(HIWORD_UPDATE(reg_data->mux_core_alt,
-reg_data->mux_core_mask,
-reg_data->mux_core_shift),
- cpuclk->reg_base + reg_data->core_reg);
+ for (i = 0; i < reg_data->num_cores; i++) {
+ writel(HIWORD_UPDATE(alt_div,
reg_data->div_core_mask[i],
+reg_data->div_core_shift[i]),
+ cpuclk->reg_base + reg_data->core_reg[i]);
+ }
}
+ /* select alternate parent */
+ writel(HIWORD_UPDATE(reg_data->mux_core_alt,
+reg_data->mux_core_mask,
+reg_data->mux_core_shift),
+ cpuclk->reg_base + reg_data->core_reg[0]);
spin_unlock_irqrestore(cpuclk->lock, flags);
return 0;
@@ -182,6 +181,7 @@ static int rockchip_cpuclk_post_rate_change(struct
rockchip_cpuclk *cpuclk,
const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data;
const struct rockchip_cpuclk_rate_table *rate;
unsigned long flags;
+ int i = 0;
rate = rockchip_get_cpuclk_settings(cpuclk, ndata->new_rate
[PATCH v5 4/4] clk: rockchip: add clock controller for rk3568
Add the clock tree definition for the new rk3568 SoC.
Signed-off-by: Elaine Zhang
Reviewed-by: Kever Yang
---
drivers/clk/rockchip/Kconfig |7 +
drivers/clk/rockchip/Makefile |1 +
drivers/clk/rockchip/clk-rk3568.c | 1725 +
drivers/clk/rockchip/clk.h| 30 +-
4 files changed, 1762 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/rockchip/clk-rk3568.c
diff --git a/drivers/clk/rockchip/Kconfig b/drivers/clk/rockchip/Kconfig
index effd05032e85..fc21a493c431 100644
--- a/drivers/clk/rockchip/Kconfig
+++ b/drivers/clk/rockchip/Kconfig
@@ -85,4 +85,11 @@ config CLK_RK3399
default y
help
Build the driver for RK3399 Clock Driver.
+
+config CLK_RK3568
+ tristate "Rockchip RK3568 clock controller support"
+ depends on ARM64 || COMPILE_TEST
+ default y
+ help
+ Build the driver for RK3568 Clock Driver.
endif
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index a99e4d9bbae1..2b78f1247372 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -26,3 +26,4 @@ obj-$(CONFIG_CLK_RK3308)+= clk-rk3308.o
obj-$(CONFIG_CLK_RK3328)+= clk-rk3328.o
obj-$(CONFIG_CLK_RK3368)+= clk-rk3368.o
obj-$(CONFIG_CLK_RK3399)+= clk-rk3399.o
+obj-$(CONFIG_CLK_RK3568) += clk-rk3568.o
diff --git a/drivers/clk/rockchip/clk-rk3568.c
b/drivers/clk/rockchip/clk-rk3568.c
new file mode 100644
index ..946ea2f45bf3
--- /dev/null
+++ b/drivers/clk/rockchip/clk-rk3568.c
@@ -0,0 +1,1725 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
+ * Author: Elaine Zhang
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "clk.h"
+
+#define RK3568_GRF_SOC_STATUS0 0x580
+
+enum rk3568_pmu_plls {
+ ppll, hpll,
+};
+
+enum rk3568_plls {
+ apll, dpll, gpll, cpll, npll, vpll,
+};
+
+static struct rockchip_pll_rate_table rk3568_pll_rates[] = {
+ /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
+ RK3036_PLL_RATE(220800, 1, 92, 1, 1, 1, 0),
+ RK3036_PLL_RATE(218400, 1, 91, 1, 1, 1, 0),
+ RK3036_PLL_RATE(216000, 1, 90, 1, 1, 1, 0),
+ RK3036_PLL_RATE(208800, 1, 87, 1, 1, 1, 0),
+ RK3036_PLL_RATE(206400, 1, 86, 1, 1, 1, 0),
+ RK3036_PLL_RATE(204000, 1, 85, 1, 1, 1, 0),
+ RK3036_PLL_RATE(201600, 1, 84, 1, 1, 1, 0),
+ RK3036_PLL_RATE(199200, 1, 83, 1, 1, 1, 0),
+ RK3036_PLL_RATE(192000, 1, 80, 1, 1, 1, 0),
+ RK3036_PLL_RATE(189600, 1, 79, 1, 1, 1, 0),
+ RK3036_PLL_RATE(18, 1, 75, 1, 1, 1, 0),
+ RK3036_PLL_RATE(170400, 1, 71, 1, 1, 1, 0),
+ RK3036_PLL_RATE(160800, 1, 67, 1, 1, 1, 0),
+ RK3036_PLL_RATE(16, 3, 200, 1, 1, 1, 0),
+ RK3036_PLL_RATE(158400, 1, 132, 2, 1, 1, 0),
+ RK3036_PLL_RATE(156000, 1, 130, 2, 1, 1, 0),
+ RK3036_PLL_RATE(153600, 1, 128, 2, 1, 1, 0),
+ RK3036_PLL_RATE(151200, 1, 126, 2, 1, 1, 0),
+ RK3036_PLL_RATE(148800, 1, 124, 2, 1, 1, 0),
+ RK3036_PLL_RATE(146400, 1, 122, 2, 1, 1, 0),
+ RK3036_PLL_RATE(144000, 1, 120, 2, 1, 1, 0),
+ RK3036_PLL_RATE(141600, 1, 118, 2, 1, 1, 0),
+ RK3036_PLL_RATE(14, 3, 350, 2, 1, 1, 0),
+ RK3036_PLL_RATE(139200, 1, 116, 2, 1, 1, 0),
+ RK3036_PLL_RATE(136800, 1, 114, 2, 1, 1, 0),
+ RK3036_PLL_RATE(134400, 1, 112, 2, 1, 1, 0),
+ RK3036_PLL_RATE(132000, 1, 110, 2, 1, 1, 0),
+ RK3036_PLL_RATE(129600, 1, 108, 2, 1, 1, 0),
+ RK3036_PLL_RATE(127200, 1, 106, 2, 1, 1, 0),
+ RK3036_PLL_RATE(124800, 1, 104, 2, 1, 1, 0),
+ RK3036_PLL_RATE(12, 1, 100, 2, 1, 1, 0),
+ RK3036_PLL_RATE(118800, 1, 99, 2, 1, 1, 0),
+ RK3036_PLL_RATE(110400, 1, 92, 2, 1, 1, 0),
+ RK3036_PLL_RATE(11, 3, 275, 2, 1, 1, 0),
+ RK3036_PLL_RATE(100800, 1, 84, 2, 1, 1, 0),
+ RK3036_PLL_RATE(10, 3, 250, 2, 1, 1, 0),
+ RK3036_PLL_RATE(91200, 1, 76, 2, 1, 1, 0),
+ RK3036_PLL_RATE(81600, 1, 68, 2, 1, 1, 0),
+ RK3036_PLL_RATE(8, 3, 200, 2, 1, 1, 0),
+ RK3036_PLL_RATE(7, 3, 350, 4, 1, 1, 0),
+ RK3036_PLL_RATE(69600, 1, 116, 4, 1, 1, 0),
+ RK3036_PLL_RATE(6, 1, 100, 4, 1, 1, 0),
+ RK3036_PLL_RATE(59400, 1, 99, 4, 1, 1, 0),
+ RK3036_PLL_RATE(5, 1, 125, 6, 1, 1, 0),
+ RK3036_PLL_RATE(40800, 1, 68, 2, 2, 1, 0),
+ RK3036_PLL_RATE(31200, 1, 78, 6, 1, 1, 0),
+ RK3036_PLL_RATE(21600, 1, 72, 4, 2, 1, 0),
+ RK3036_PLL_RATE(2, 1, 100, 3, 4, 1, 0),
+ RK3036_PLL_RATE(14850, 1, 99, 4, 4, 1, 0),
+ RK3036_PLL_RATE(1, 1, 150, 6, 6, 1, 0),
+ RK3036_PLL_RATE(960
[PATCH v5 0/4] clk: rockchip: add clock controller for rk3568
Add the clock tree definition for the new rk3568 SoC.
Change in V5:
[PATCH v5 1/4]: No change.
[PATCH v5 2/4]: No change.
[PATCH v5 3/4]: fix up the warning:
>> drivers/clk/rockchip/clk-rk3188.c:187:67: warning:
>> missing braces around initializer [-Wmissing-braces]
187 | static const struct rockchip_cpuclk_reg_data
rk3188_cpuclk_data = {
[PATCH v5 4/4]: No change.
Change in V4:
[PATCH v4 1/4]: No change.
[PATCH v4 2/4]: No change.
[PATCH v4 3/4]: No change.
[PATCH v4 4/4]: Drop parenthesis and module alias.
Change in V3:
[PATCH v3 1/4]: Fix some code styles.
[PATCH v3 2/4]: No change.
[PATCH v3 3/4]: No change.
[PATCH v3 4/4]: No change.
Change in V2:
[PATCH v2 1/4]: Convert rockchip,rk3568-cru.txt to YAML,
And update commit message.
[PATCH v2 2/4]: No change.
[PATCH v2 3/4]: Use arrays to support more core independent div
settings.
[PATCH v2 4/4]: Adapter [PATCH v2 3/4] changes.
Elaine Zhang (4):
dt-binding: clock: Document rockchip,rk3568-cru bindings
clk: rockchip: add dt-binding header for rk3568
clk: rockchip: support more core div setting
clk: rockchip: add clock controller for rk3568
.../bindings/clock/rockchip,rk3568-cru.yaml | 60 +
drivers/clk/rockchip/Kconfig |7 +
drivers/clk/rockchip/Makefile |1 +
drivers/clk/rockchip/clk-cpu.c| 53 +-
drivers/clk/rockchip/clk-px30.c |7 +-
drivers/clk/rockchip/clk-rk3036.c |7 +-
drivers/clk/rockchip/clk-rk3128.c |7 +-
drivers/clk/rockchip/clk-rk3188.c | 14 +-
drivers/clk/rockchip/clk-rk3228.c |7 +-
drivers/clk/rockchip/clk-rk3288.c |7 +-
drivers/clk/rockchip/clk-rk3308.c |7 +-
drivers/clk/rockchip/clk-rk3328.c |7 +-
drivers/clk/rockchip/clk-rk3368.c | 14 +-
drivers/clk/rockchip/clk-rk3399.c | 14 +-
drivers/clk/rockchip/clk-rk3568.c | 1725 +
drivers/clk/rockchip/clk-rv1108.c |7 +-
drivers/clk/rockchip/clk.h| 54 +-
include/dt-bindings/clock/rk3568-cru.h| 926 +
18 files changed, 2846 insertions(+), 78 deletions(-)
create mode 100644
Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml
create mode 100644 drivers/clk/rockchip/clk-rk3568.c
create mode 100644 include/dt-bindings/clock/rk3568-cru.h
--
2.17.1
[PATCH v5 2/4] clk: rockchip: add dt-binding header for rk3568
Add the dt-bindings header for the rk3568, that gets shared between the clock controller and the clock references in the dts. Add softreset ID for rk3568. Signed-off-by: Elaine Zhang Reviewed-by: Kever Yang Reviewed-by: Rob Herring --- include/dt-bindings/clock/rk3568-cru.h | 926 + 1 file changed, 926 insertions(+) create mode 100644 include/dt-bindings/clock/rk3568-cru.h diff --git a/include/dt-bindings/clock/rk3568-cru.h b/include/dt-bindings/clock/rk3568-cru.h new file mode 100644 index ..d29890865150 --- /dev/null +++ b/include/dt-bindings/clock/rk3568-cru.h @@ -0,0 +1,926 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2021 Rockchip Electronics Co. Ltd. + * Author: Elaine Zhang + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H + +/* pmucru-clocks indices */ + +/* pmucru plls */ +#define PLL_PPLL 1 +#define PLL_HPLL 2 + +/* pmucru clocks */ +#define XIN_OSC0_DIV 4 +#define CLK_RTC_32K5 +#define CLK_PMU6 +#define CLK_I2C0 7 +#define CLK_RTC32K_FRAC8 +#define CLK_UART0_DIV 9 +#define CLK_UART0_FRAC 10 +#define SCLK_UART0 11 +#define DBCLK_GPIO012 +#define CLK_PWM0 13 +#define CLK_CAPTURE_PWM0_NDFT 14 +#define CLK_PMUPVTM15 +#define CLK_CORE_PMUPVTM 16 +#define CLK_REF24M 17 +#define XIN_OSC0_USBPHY0_G 18 +#define CLK_USBPHY0_REF19 +#define XIN_OSC0_USBPHY1_G 20 +#define CLK_USBPHY1_REF21 +#define XIN_OSC0_MIPIDSIPHY0_G 22 +#define CLK_MIPIDSIPHY0_REF23 +#define XIN_OSC0_MIPIDSIPHY1_G 24 +#define CLK_MIPIDSIPHY1_REF25 +#define CLK_WIFI_DIV 26 +#define CLK_WIFI_OSC0 27 +#define CLK_WIFI 28 +#define CLK_PCIEPHY0_DIV 29 +#define CLK_PCIEPHY0_OSC0 30 +#define CLK_PCIEPHY0_REF 31 +#define CLK_PCIEPHY1_DIV 32 +#define CLK_PCIEPHY1_OSC0 33 +#define CLK_PCIEPHY1_REF 34 +#define CLK_PCIEPHY2_DIV 35 +#define CLK_PCIEPHY2_OSC0 36 +#define CLK_PCIEPHY2_REF 37 +#define CLK_PCIE30PHY_REF_M38 +#define CLK_PCIE30PHY_REF_N39 +#define CLK_HDMI_REF 40 +#define XIN_OSC0_EDPPHY_G 41 +#define PCLK_PDPMU 42 +#define PCLK_PMU 43 +#define PCLK_UART0 44 +#define PCLK_I2C0 45 +#define PCLK_GPIO0 46 +#define PCLK_PMUPVTM 47 +#define PCLK_PWM0 48 +#define CLK_PDPMU 49 +#define SCLK_32K_IOE 50 + +#define CLKPMU_NR_CLKS (SCLK_32K_IOE + 1) + +/* cru-clocks indices */ + +/* cru plls */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_CPLL 3 +#define PLL_GPLL 4 +#define PLL_VPLL 5 +#define PLL_NPLL 6 + +/* cru clocks */ +#define CPLL_333M 9 +#define ARMCLK 10 +#define USB480M11 +#define ACLK_CORE_NIU2BUS 18 +#define CLK_CORE_PVTM 19 +#define CLK_CORE_PVTM_CORE 20 +#define CLK_CORE_PVTPLL21 +#define CLK_GPU_SRC22 +#define CLK_GPU_PRE_NDFT 23 +#define CLK_GPU_PRE_MUX24 +#define ACLK_GPU_PRE 25 +#define PCLK_GPU_PRE 26 +#define CLK_GPU27 +#define CLK_GPU_NP528 +#define PCLK_GPU_PVTM 29 +#define CLK_GPU_PVTM 30 +#define CLK_GPU_PVTM_CORE 31 +#define CLK_GPU_PVTPLL 32 +#define CLK_NPU_SRC33 +#define CLK_NPU_PRE_NDFT 34 +#define CLK_NPU35 +#define CLK_NPU_NP536 +#define HCLK_NPU_PRE 37 +#define PCLK_NPU_PRE 38 +#define ACLK_NPU_PRE 39 +#define ACLK_NPU 40 +#define HCLK_NPU 41 +#define PCLK_NPU_PVTM 42 +#define CLK_NPU_PVTM 43 +#define CLK_NPU_PVTM_CORE 44 +#define CLK_NPU_PVTPLL 45 +#define CLK_DDRPHY1X_SRC 46 +#define CLK_DDRPHY1X_HWFFC_SRC 47 +#define CLK_DDR1X 48 +#define CLK_MSCH 49 +#define CLK24_DDRMON 50 +#define ACLK_GIC_AUDIO 51 +#define HCLK_GIC_AUDIO 52 +#define HCLK_SDMMC_BUFFER 53 +#define DCLK_SDMMC_BUFFER 54 +#define ACLK_GIC60055 +#define ACLK_SPINLOCK 56 +#define HCLK_I2S0_8CH 57 +#define HCLK_I2S1_8CH 58 +#define HCLK_I2S2_2CH 59 +#define HCLK_I2S3_2CH 60 +#define CLK_I2S0_8CH_TX_SRC61 +#define CLK_I2S0_8CH_TX_FRAC 62 +#define MCLK_I2S0_8CH_TX 63 +#define I2S0_MCLKOUT_TX64 +#define CLK_I2S0_8CH_RX_SRC65 +#define CLK_I2S0_8CH_RX_FRAC 66 +#define MCLK_I2S0_8CH_RX 67 +#define I2S0_MCLKOUT_RX68 +#define CLK_I2S1_8CH_TX_SRC69 +#define CLK_I2S1_8CH_TX_FRAC
[PATCH v5 1/4] dt-binding: clock: Document rockchip,rk3568-cru bindings
Document the device tree bindings of the rockchip Rk3568 SoC
clock driver in
Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml.
Signed-off-by: Elaine Zhang
Reviewed-by: Kever Yang
Reviewed-by: Rob Herring
---
.../bindings/clock/rockchip,rk3568-cru.yaml | 60 +++
1 file changed, 60 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml
b/Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml
new file mode 100644
index ..b2c26097827f
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/rockchip,rk3568-cru.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ROCKCHIP rk3568 Family Clock Control Module Binding
+
+maintainers:
+ - Elaine Zhang
+ - Heiko Stuebner
+
+description: |
+ The RK3568 clock controller generates the clock and also implements a
+ reset controller for SoC peripherals.
+ (examples: provide SCLK_UART1\PCLK_UART1 and SRST_P_UART1\SRST_S_UART1 for
UART module)
+ Each clock is assigned an identifier and client nodes can use this identifier
+ to specify the clock which they consume. All available clocks are defined as
+ preprocessor macros in the dt-bindings/clock/rk3568-cru.h headers and can be
+ used in device tree sources.
+
+properties:
+ compatible:
+enum:
+ - rockchip,rk3568-cru
+ - rockchip,rk3568-pmucru
+
+ reg:
+maxItems: 1
+
+ "#clock-cells":
+const: 1
+
+ "#reset-cells":
+const: 1
+
+required:
+ - compatible
+ - reg
+ - "#clock-cells"
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ # Clock Control Module node:
+ - |
+pmucru: clock-controller@fdd0 {
+ compatible = "rockchip,rk3568-pmucru";
+ reg = <0xfdd0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+};
+ - |
+cru: clock-controller@fdd2 {
+ compatible = "rockchip,rk3568-cru";
+ reg = <0xfdd2 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+};
--
2.17.1
[PATCH v4 3/4] clk: rockchip: support more core div setting
Use arrays to support more core independent div settings.
A55 supports each core to work at different frequencies, and each core
has an independent divider control.
Signed-off-by: Elaine Zhang
Reviewed-by: Kever Yang
---
drivers/clk/rockchip/clk-cpu.c| 53 +--
drivers/clk/rockchip/clk-px30.c | 7 ++--
drivers/clk/rockchip/clk-rk3036.c | 7 ++--
drivers/clk/rockchip/clk-rk3128.c | 7 ++--
drivers/clk/rockchip/clk-rk3188.c | 7 ++--
drivers/clk/rockchip/clk-rk3228.c | 7 ++--
drivers/clk/rockchip/clk-rk3288.c | 7 ++--
drivers/clk/rockchip/clk-rk3308.c | 7 ++--
drivers/clk/rockchip/clk-rk3328.c | 7 ++--
drivers/clk/rockchip/clk-rk3368.c | 14
drivers/clk/rockchip/clk-rk3399.c | 14
drivers/clk/rockchip/clk-rv1108.c | 7 ++--
drivers/clk/rockchip/clk.h| 24 +++---
13 files changed, 94 insertions(+), 74 deletions(-)
diff --git a/drivers/clk/rockchip/clk-cpu.c b/drivers/clk/rockchip/clk-cpu.c
index fa9027fb1920..47288197c9d7 100644
--- a/drivers/clk/rockchip/clk-cpu.c
+++ b/drivers/clk/rockchip/clk-cpu.c
@@ -84,10 +84,10 @@ static unsigned long rockchip_cpuclk_recalc_rate(struct
clk_hw *hw,
{
struct rockchip_cpuclk *cpuclk = to_rockchip_cpuclk_hw(hw);
const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data;
- u32 clksel0 = readl_relaxed(cpuclk->reg_base + reg_data->core_reg);
+ u32 clksel0 = readl_relaxed(cpuclk->reg_base + reg_data->core_reg[0]);
- clksel0 >>= reg_data->div_core_shift;
- clksel0 &= reg_data->div_core_mask;
+ clksel0 >>= reg_data->div_core_shift[0];
+ clksel0 &= reg_data->div_core_mask[0];
return parent_rate / (clksel0 + 1);
}
@@ -120,6 +120,7 @@ static int rockchip_cpuclk_pre_rate_change(struct
rockchip_cpuclk *cpuclk,
const struct rockchip_cpuclk_rate_table *rate;
unsigned long alt_prate, alt_div;
unsigned long flags;
+ int i = 0;
/* check validity of the new rate */
rate = rockchip_get_cpuclk_settings(cpuclk, ndata->new_rate);
@@ -142,10 +143,10 @@ static int rockchip_cpuclk_pre_rate_change(struct
rockchip_cpuclk *cpuclk,
if (alt_prate > ndata->old_rate) {
/* calculate dividers */
alt_div = DIV_ROUND_UP(alt_prate, ndata->old_rate) - 1;
- if (alt_div > reg_data->div_core_mask) {
+ if (alt_div > reg_data->div_core_mask[0]) {
pr_warn("%s: limiting alt-divider %lu to %d\n",
- __func__, alt_div, reg_data->div_core_mask);
- alt_div = reg_data->div_core_mask;
+ __func__, alt_div, reg_data->div_core_mask[0]);
+ alt_div = reg_data->div_core_mask[0];
}
/*
@@ -158,19 +159,17 @@ static int rockchip_cpuclk_pre_rate_change(struct
rockchip_cpuclk *cpuclk,
pr_debug("%s: setting div %lu as alt-rate %lu > old-rate %lu\n",
__func__, alt_div, alt_prate, ndata->old_rate);
- writel(HIWORD_UPDATE(alt_div, reg_data->div_core_mask,
- reg_data->div_core_shift) |
- HIWORD_UPDATE(reg_data->mux_core_alt,
-reg_data->mux_core_mask,
-reg_data->mux_core_shift),
- cpuclk->reg_base + reg_data->core_reg);
- } else {
- /* select alternate parent */
- writel(HIWORD_UPDATE(reg_data->mux_core_alt,
-reg_data->mux_core_mask,
-reg_data->mux_core_shift),
- cpuclk->reg_base + reg_data->core_reg);
+ for (i = 0; i < reg_data->num_cores; i++) {
+ writel(HIWORD_UPDATE(alt_div,
reg_data->div_core_mask[i],
+reg_data->div_core_shift[i]),
+ cpuclk->reg_base + reg_data->core_reg[i]);
+ }
}
+ /* select alternate parent */
+ writel(HIWORD_UPDATE(reg_data->mux_core_alt,
+reg_data->mux_core_mask,
+reg_data->mux_core_shift),
+ cpuclk->reg_base + reg_data->core_reg[0]);
spin_unlock_irqrestore(cpuclk->lock, flags);
return 0;
@@ -182,6 +181,7 @@ static int rockchip_cpuclk_post_rate_change(struct
rockchip_cpuclk *cpuclk,
const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data;
const struct rockchip_cpuclk_rate_table *rate;
unsigned long flags;
+ int i = 0;
rate = rockchip_get_cpuclk_settings(cpuclk, ndata->new_rate
[PATCH v4 4/4] clk: rockchip: add clock controller for rk3568
Add the clock tree definition for the new rk3568 SoC.
Signed-off-by: Elaine Zhang
Reviewed-by: Kever Yang
---
drivers/clk/rockchip/Kconfig |7 +
drivers/clk/rockchip/Makefile |1 +
drivers/clk/rockchip/clk-rk3568.c | 1725 +
drivers/clk/rockchip/clk.h| 30 +-
4 files changed, 1762 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/rockchip/clk-rk3568.c
diff --git a/drivers/clk/rockchip/Kconfig b/drivers/clk/rockchip/Kconfig
index effd05032e85..fc21a493c431 100644
--- a/drivers/clk/rockchip/Kconfig
+++ b/drivers/clk/rockchip/Kconfig
@@ -85,4 +85,11 @@ config CLK_RK3399
default y
help
Build the driver for RK3399 Clock Driver.
+
+config CLK_RK3568
+ tristate "Rockchip RK3568 clock controller support"
+ depends on ARM64 || COMPILE_TEST
+ default y
+ help
+ Build the driver for RK3568 Clock Driver.
endif
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index a99e4d9bbae1..2b78f1247372 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -26,3 +26,4 @@ obj-$(CONFIG_CLK_RK3308)+= clk-rk3308.o
obj-$(CONFIG_CLK_RK3328)+= clk-rk3328.o
obj-$(CONFIG_CLK_RK3368)+= clk-rk3368.o
obj-$(CONFIG_CLK_RK3399)+= clk-rk3399.o
+obj-$(CONFIG_CLK_RK3568) += clk-rk3568.o
diff --git a/drivers/clk/rockchip/clk-rk3568.c
b/drivers/clk/rockchip/clk-rk3568.c
new file mode 100644
index ..946ea2f45bf3
--- /dev/null
+++ b/drivers/clk/rockchip/clk-rk3568.c
@@ -0,0 +1,1725 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
+ * Author: Elaine Zhang
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "clk.h"
+
+#define RK3568_GRF_SOC_STATUS0 0x580
+
+enum rk3568_pmu_plls {
+ ppll, hpll,
+};
+
+enum rk3568_plls {
+ apll, dpll, gpll, cpll, npll, vpll,
+};
+
+static struct rockchip_pll_rate_table rk3568_pll_rates[] = {
+ /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
+ RK3036_PLL_RATE(220800, 1, 92, 1, 1, 1, 0),
+ RK3036_PLL_RATE(218400, 1, 91, 1, 1, 1, 0),
+ RK3036_PLL_RATE(216000, 1, 90, 1, 1, 1, 0),
+ RK3036_PLL_RATE(208800, 1, 87, 1, 1, 1, 0),
+ RK3036_PLL_RATE(206400, 1, 86, 1, 1, 1, 0),
+ RK3036_PLL_RATE(204000, 1, 85, 1, 1, 1, 0),
+ RK3036_PLL_RATE(201600, 1, 84, 1, 1, 1, 0),
+ RK3036_PLL_RATE(199200, 1, 83, 1, 1, 1, 0),
+ RK3036_PLL_RATE(192000, 1, 80, 1, 1, 1, 0),
+ RK3036_PLL_RATE(189600, 1, 79, 1, 1, 1, 0),
+ RK3036_PLL_RATE(18, 1, 75, 1, 1, 1, 0),
+ RK3036_PLL_RATE(170400, 1, 71, 1, 1, 1, 0),
+ RK3036_PLL_RATE(160800, 1, 67, 1, 1, 1, 0),
+ RK3036_PLL_RATE(16, 3, 200, 1, 1, 1, 0),
+ RK3036_PLL_RATE(158400, 1, 132, 2, 1, 1, 0),
+ RK3036_PLL_RATE(156000, 1, 130, 2, 1, 1, 0),
+ RK3036_PLL_RATE(153600, 1, 128, 2, 1, 1, 0),
+ RK3036_PLL_RATE(151200, 1, 126, 2, 1, 1, 0),
+ RK3036_PLL_RATE(148800, 1, 124, 2, 1, 1, 0),
+ RK3036_PLL_RATE(146400, 1, 122, 2, 1, 1, 0),
+ RK3036_PLL_RATE(144000, 1, 120, 2, 1, 1, 0),
+ RK3036_PLL_RATE(141600, 1, 118, 2, 1, 1, 0),
+ RK3036_PLL_RATE(14, 3, 350, 2, 1, 1, 0),
+ RK3036_PLL_RATE(139200, 1, 116, 2, 1, 1, 0),
+ RK3036_PLL_RATE(136800, 1, 114, 2, 1, 1, 0),
+ RK3036_PLL_RATE(134400, 1, 112, 2, 1, 1, 0),
+ RK3036_PLL_RATE(132000, 1, 110, 2, 1, 1, 0),
+ RK3036_PLL_RATE(129600, 1, 108, 2, 1, 1, 0),
+ RK3036_PLL_RATE(127200, 1, 106, 2, 1, 1, 0),
+ RK3036_PLL_RATE(124800, 1, 104, 2, 1, 1, 0),
+ RK3036_PLL_RATE(12, 1, 100, 2, 1, 1, 0),
+ RK3036_PLL_RATE(118800, 1, 99, 2, 1, 1, 0),
+ RK3036_PLL_RATE(110400, 1, 92, 2, 1, 1, 0),
+ RK3036_PLL_RATE(11, 3, 275, 2, 1, 1, 0),
+ RK3036_PLL_RATE(100800, 1, 84, 2, 1, 1, 0),
+ RK3036_PLL_RATE(10, 3, 250, 2, 1, 1, 0),
+ RK3036_PLL_RATE(91200, 1, 76, 2, 1, 1, 0),
+ RK3036_PLL_RATE(81600, 1, 68, 2, 1, 1, 0),
+ RK3036_PLL_RATE(8, 3, 200, 2, 1, 1, 0),
+ RK3036_PLL_RATE(7, 3, 350, 4, 1, 1, 0),
+ RK3036_PLL_RATE(69600, 1, 116, 4, 1, 1, 0),
+ RK3036_PLL_RATE(6, 1, 100, 4, 1, 1, 0),
+ RK3036_PLL_RATE(59400, 1, 99, 4, 1, 1, 0),
+ RK3036_PLL_RATE(5, 1, 125, 6, 1, 1, 0),
+ RK3036_PLL_RATE(40800, 1, 68, 2, 2, 1, 0),
+ RK3036_PLL_RATE(31200, 1, 78, 6, 1, 1, 0),
+ RK3036_PLL_RATE(21600, 1, 72, 4, 2, 1, 0),
+ RK3036_PLL_RATE(2, 1, 100, 3, 4, 1, 0),
+ RK3036_PLL_RATE(14850, 1, 99, 4, 4, 1, 0),
+ RK3036_PLL_RATE(1, 1, 150, 6, 6, 1, 0),
+ RK3036_PLL_RATE(960
[PATCH v4 2/4] clk: rockchip: add dt-binding header for rk3568
Add the dt-bindings header for the rk3568, that gets shared between the clock controller and the clock references in the dts. Add softreset ID for rk3568. Signed-off-by: Elaine Zhang Reviewed-by: Kever Yang Reviewed-by: Rob Herring --- include/dt-bindings/clock/rk3568-cru.h | 926 + 1 file changed, 926 insertions(+) create mode 100644 include/dt-bindings/clock/rk3568-cru.h diff --git a/include/dt-bindings/clock/rk3568-cru.h b/include/dt-bindings/clock/rk3568-cru.h new file mode 100644 index ..d29890865150 --- /dev/null +++ b/include/dt-bindings/clock/rk3568-cru.h @@ -0,0 +1,926 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2021 Rockchip Electronics Co. Ltd. + * Author: Elaine Zhang + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H + +/* pmucru-clocks indices */ + +/* pmucru plls */ +#define PLL_PPLL 1 +#define PLL_HPLL 2 + +/* pmucru clocks */ +#define XIN_OSC0_DIV 4 +#define CLK_RTC_32K5 +#define CLK_PMU6 +#define CLK_I2C0 7 +#define CLK_RTC32K_FRAC8 +#define CLK_UART0_DIV 9 +#define CLK_UART0_FRAC 10 +#define SCLK_UART0 11 +#define DBCLK_GPIO012 +#define CLK_PWM0 13 +#define CLK_CAPTURE_PWM0_NDFT 14 +#define CLK_PMUPVTM15 +#define CLK_CORE_PMUPVTM 16 +#define CLK_REF24M 17 +#define XIN_OSC0_USBPHY0_G 18 +#define CLK_USBPHY0_REF19 +#define XIN_OSC0_USBPHY1_G 20 +#define CLK_USBPHY1_REF21 +#define XIN_OSC0_MIPIDSIPHY0_G 22 +#define CLK_MIPIDSIPHY0_REF23 +#define XIN_OSC0_MIPIDSIPHY1_G 24 +#define CLK_MIPIDSIPHY1_REF25 +#define CLK_WIFI_DIV 26 +#define CLK_WIFI_OSC0 27 +#define CLK_WIFI 28 +#define CLK_PCIEPHY0_DIV 29 +#define CLK_PCIEPHY0_OSC0 30 +#define CLK_PCIEPHY0_REF 31 +#define CLK_PCIEPHY1_DIV 32 +#define CLK_PCIEPHY1_OSC0 33 +#define CLK_PCIEPHY1_REF 34 +#define CLK_PCIEPHY2_DIV 35 +#define CLK_PCIEPHY2_OSC0 36 +#define CLK_PCIEPHY2_REF 37 +#define CLK_PCIE30PHY_REF_M38 +#define CLK_PCIE30PHY_REF_N39 +#define CLK_HDMI_REF 40 +#define XIN_OSC0_EDPPHY_G 41 +#define PCLK_PDPMU 42 +#define PCLK_PMU 43 +#define PCLK_UART0 44 +#define PCLK_I2C0 45 +#define PCLK_GPIO0 46 +#define PCLK_PMUPVTM 47 +#define PCLK_PWM0 48 +#define CLK_PDPMU 49 +#define SCLK_32K_IOE 50 + +#define CLKPMU_NR_CLKS (SCLK_32K_IOE + 1) + +/* cru-clocks indices */ + +/* cru plls */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_CPLL 3 +#define PLL_GPLL 4 +#define PLL_VPLL 5 +#define PLL_NPLL 6 + +/* cru clocks */ +#define CPLL_333M 9 +#define ARMCLK 10 +#define USB480M11 +#define ACLK_CORE_NIU2BUS 18 +#define CLK_CORE_PVTM 19 +#define CLK_CORE_PVTM_CORE 20 +#define CLK_CORE_PVTPLL21 +#define CLK_GPU_SRC22 +#define CLK_GPU_PRE_NDFT 23 +#define CLK_GPU_PRE_MUX24 +#define ACLK_GPU_PRE 25 +#define PCLK_GPU_PRE 26 +#define CLK_GPU27 +#define CLK_GPU_NP528 +#define PCLK_GPU_PVTM 29 +#define CLK_GPU_PVTM 30 +#define CLK_GPU_PVTM_CORE 31 +#define CLK_GPU_PVTPLL 32 +#define CLK_NPU_SRC33 +#define CLK_NPU_PRE_NDFT 34 +#define CLK_NPU35 +#define CLK_NPU_NP536 +#define HCLK_NPU_PRE 37 +#define PCLK_NPU_PRE 38 +#define ACLK_NPU_PRE 39 +#define ACLK_NPU 40 +#define HCLK_NPU 41 +#define PCLK_NPU_PVTM 42 +#define CLK_NPU_PVTM 43 +#define CLK_NPU_PVTM_CORE 44 +#define CLK_NPU_PVTPLL 45 +#define CLK_DDRPHY1X_SRC 46 +#define CLK_DDRPHY1X_HWFFC_SRC 47 +#define CLK_DDR1X 48 +#define CLK_MSCH 49 +#define CLK24_DDRMON 50 +#define ACLK_GIC_AUDIO 51 +#define HCLK_GIC_AUDIO 52 +#define HCLK_SDMMC_BUFFER 53 +#define DCLK_SDMMC_BUFFER 54 +#define ACLK_GIC60055 +#define ACLK_SPINLOCK 56 +#define HCLK_I2S0_8CH 57 +#define HCLK_I2S1_8CH 58 +#define HCLK_I2S2_2CH 59 +#define HCLK_I2S3_2CH 60 +#define CLK_I2S0_8CH_TX_SRC61 +#define CLK_I2S0_8CH_TX_FRAC 62 +#define MCLK_I2S0_8CH_TX 63 +#define I2S0_MCLKOUT_TX64 +#define CLK_I2S0_8CH_RX_SRC65 +#define CLK_I2S0_8CH_RX_FRAC 66 +#define MCLK_I2S0_8CH_RX 67 +#define I2S0_MCLKOUT_RX68 +#define CLK_I2S1_8CH_TX_SRC69 +#define CLK_I2S1_8CH_TX_FRAC
[PATCH v4 0/4] clk: rockchip: add clock controller for rk3568
Add the clock tree definition for the new rk3568 SoC. Change in V4: [PATCH v4 1/4]: No change. [PATCH v4 2/4]: No change. [PATCH v4 3/4]: No change. [PATCH v4 4/4]: Drop parenthesis and module alias. Change in V3: [PATCH v3 1/4]: Fix some code styles. [PATCH v3 2/4]: No change. [PATCH v3 3/4]: No change. [PATCH v3 4/4]: No change. Change in V2: [PATCH v2 1/4]: Convert rockchip,rk3568-cru.txt to YAML, And update commit message. [PATCH v2 2/4]: No change. [PATCH v2 3/4]: Use arrays to support more core independent div settings. [PATCH v2 4/4]: Adapter [PATCH v2 3/4] changes. Elaine Zhang (4): dt-binding: clock: Document rockchip,rk3568-cru bindings clk: rockchip: add dt-binding header for rk3568 clk: rockchip: support more core div setting clk: rockchip: add clock controller for rk3568 .../bindings/clock/rockchip,rk3568-cru.yaml | 60 + drivers/clk/rockchip/Kconfig |7 + drivers/clk/rockchip/Makefile |1 + drivers/clk/rockchip/clk-cpu.c| 53 +- drivers/clk/rockchip/clk-px30.c |7 +- drivers/clk/rockchip/clk-rk3036.c |7 +- drivers/clk/rockchip/clk-rk3128.c |7 +- drivers/clk/rockchip/clk-rk3188.c |7 +- drivers/clk/rockchip/clk-rk3228.c |7 +- drivers/clk/rockchip/clk-rk3288.c |7 +- drivers/clk/rockchip/clk-rk3308.c |7 +- drivers/clk/rockchip/clk-rk3328.c |7 +- drivers/clk/rockchip/clk-rk3368.c | 14 +- drivers/clk/rockchip/clk-rk3399.c | 14 +- drivers/clk/rockchip/clk-rk3568.c | 1725 + drivers/clk/rockchip/clk-rv1108.c |7 +- drivers/clk/rockchip/clk.h| 54 +- include/dt-bindings/clock/rk3568-cru.h| 926 + 18 files changed, 2842 insertions(+), 75 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml create mode 100644 drivers/clk/rockchip/clk-rk3568.c create mode 100644 include/dt-bindings/clock/rk3568-cru.h -- 2.17.1
[PATCH v4 1/4] dt-binding: clock: Document rockchip,rk3568-cru bindings
Document the device tree bindings of the rockchip Rk3568 SoC
clock driver in
Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml.
Signed-off-by: Elaine Zhang
Reviewed-by: Kever Yang
Reviewed-by: Rob Herring
---
.../bindings/clock/rockchip,rk3568-cru.yaml | 60 +++
1 file changed, 60 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml
b/Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml
new file mode 100644
index ..b2c26097827f
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/rockchip,rk3568-cru.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ROCKCHIP rk3568 Family Clock Control Module Binding
+
+maintainers:
+ - Elaine Zhang
+ - Heiko Stuebner
+
+description: |
+ The RK3568 clock controller generates the clock and also implements a
+ reset controller for SoC peripherals.
+ (examples: provide SCLK_UART1\PCLK_UART1 and SRST_P_UART1\SRST_S_UART1 for
UART module)
+ Each clock is assigned an identifier and client nodes can use this identifier
+ to specify the clock which they consume. All available clocks are defined as
+ preprocessor macros in the dt-bindings/clock/rk3568-cru.h headers and can be
+ used in device tree sources.
+
+properties:
+ compatible:
+enum:
+ - rockchip,rk3568-cru
+ - rockchip,rk3568-pmucru
+
+ reg:
+maxItems: 1
+
+ "#clock-cells":
+const: 1
+
+ "#reset-cells":
+const: 1
+
+required:
+ - compatible
+ - reg
+ - "#clock-cells"
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ # Clock Control Module node:
+ - |
+pmucru: clock-controller@fdd0 {
+ compatible = "rockchip,rk3568-pmucru";
+ reg = <0xfdd0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+};
+ - |
+cru: clock-controller@fdd2 {
+ compatible = "rockchip,rk3568-cru";
+ reg = <0xfdd2 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+};
--
2.17.1
[PATCH v3 4/4] clk: rockchip: add clock controller for rk3568
Add the clock tree definition for the new rk3568 SoC.
Signed-off-by: Elaine Zhang
---
drivers/clk/rockchip/Kconfig |7 +
drivers/clk/rockchip/Makefile |1 +
drivers/clk/rockchip/clk-rk3568.c | 1726 +
drivers/clk/rockchip/clk.h| 30 +-
4 files changed, 1763 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/rockchip/clk-rk3568.c
diff --git a/drivers/clk/rockchip/Kconfig b/drivers/clk/rockchip/Kconfig
index effd05032e85..2e31901f4213 100644
--- a/drivers/clk/rockchip/Kconfig
+++ b/drivers/clk/rockchip/Kconfig
@@ -85,4 +85,11 @@ config CLK_RK3399
default y
help
Build the driver for RK3399 Clock Driver.
+
+config CLK_RK3568
+ tristate "Rockchip RK3568 clock controller support"
+ depends on (ARM64 || COMPILE_TEST)
+ default y
+ help
+ Build the driver for RK3568 Clock Driver.
endif
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index a99e4d9bbae1..2b78f1247372 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -26,3 +26,4 @@ obj-$(CONFIG_CLK_RK3308)+= clk-rk3308.o
obj-$(CONFIG_CLK_RK3328)+= clk-rk3328.o
obj-$(CONFIG_CLK_RK3368)+= clk-rk3368.o
obj-$(CONFIG_CLK_RK3399)+= clk-rk3399.o
+obj-$(CONFIG_CLK_RK3568) += clk-rk3568.o
diff --git a/drivers/clk/rockchip/clk-rk3568.c
b/drivers/clk/rockchip/clk-rk3568.c
new file mode 100644
index ..60913aa91897
--- /dev/null
+++ b/drivers/clk/rockchip/clk-rk3568.c
@@ -0,0 +1,1726 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
+ * Author: Elaine Zhang
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "clk.h"
+
+#define RK3568_GRF_SOC_STATUS0 0x580
+
+enum rk3568_pmu_plls {
+ ppll, hpll,
+};
+
+enum rk3568_plls {
+ apll, dpll, gpll, cpll, npll, vpll,
+};
+
+static struct rockchip_pll_rate_table rk3568_pll_rates[] = {
+ /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
+ RK3036_PLL_RATE(220800, 1, 92, 1, 1, 1, 0),
+ RK3036_PLL_RATE(218400, 1, 91, 1, 1, 1, 0),
+ RK3036_PLL_RATE(216000, 1, 90, 1, 1, 1, 0),
+ RK3036_PLL_RATE(208800, 1, 87, 1, 1, 1, 0),
+ RK3036_PLL_RATE(206400, 1, 86, 1, 1, 1, 0),
+ RK3036_PLL_RATE(204000, 1, 85, 1, 1, 1, 0),
+ RK3036_PLL_RATE(201600, 1, 84, 1, 1, 1, 0),
+ RK3036_PLL_RATE(199200, 1, 83, 1, 1, 1, 0),
+ RK3036_PLL_RATE(192000, 1, 80, 1, 1, 1, 0),
+ RK3036_PLL_RATE(189600, 1, 79, 1, 1, 1, 0),
+ RK3036_PLL_RATE(18, 1, 75, 1, 1, 1, 0),
+ RK3036_PLL_RATE(170400, 1, 71, 1, 1, 1, 0),
+ RK3036_PLL_RATE(160800, 1, 67, 1, 1, 1, 0),
+ RK3036_PLL_RATE(16, 3, 200, 1, 1, 1, 0),
+ RK3036_PLL_RATE(158400, 1, 132, 2, 1, 1, 0),
+ RK3036_PLL_RATE(156000, 1, 130, 2, 1, 1, 0),
+ RK3036_PLL_RATE(153600, 1, 128, 2, 1, 1, 0),
+ RK3036_PLL_RATE(151200, 1, 126, 2, 1, 1, 0),
+ RK3036_PLL_RATE(148800, 1, 124, 2, 1, 1, 0),
+ RK3036_PLL_RATE(146400, 1, 122, 2, 1, 1, 0),
+ RK3036_PLL_RATE(144000, 1, 120, 2, 1, 1, 0),
+ RK3036_PLL_RATE(141600, 1, 118, 2, 1, 1, 0),
+ RK3036_PLL_RATE(14, 3, 350, 2, 1, 1, 0),
+ RK3036_PLL_RATE(139200, 1, 116, 2, 1, 1, 0),
+ RK3036_PLL_RATE(136800, 1, 114, 2, 1, 1, 0),
+ RK3036_PLL_RATE(134400, 1, 112, 2, 1, 1, 0),
+ RK3036_PLL_RATE(132000, 1, 110, 2, 1, 1, 0),
+ RK3036_PLL_RATE(129600, 1, 108, 2, 1, 1, 0),
+ RK3036_PLL_RATE(127200, 1, 106, 2, 1, 1, 0),
+ RK3036_PLL_RATE(124800, 1, 104, 2, 1, 1, 0),
+ RK3036_PLL_RATE(12, 1, 100, 2, 1, 1, 0),
+ RK3036_PLL_RATE(118800, 1, 99, 2, 1, 1, 0),
+ RK3036_PLL_RATE(110400, 1, 92, 2, 1, 1, 0),
+ RK3036_PLL_RATE(11, 3, 275, 2, 1, 1, 0),
+ RK3036_PLL_RATE(100800, 1, 84, 2, 1, 1, 0),
+ RK3036_PLL_RATE(10, 3, 250, 2, 1, 1, 0),
+ RK3036_PLL_RATE(91200, 1, 76, 2, 1, 1, 0),
+ RK3036_PLL_RATE(81600, 1, 68, 2, 1, 1, 0),
+ RK3036_PLL_RATE(8, 3, 200, 2, 1, 1, 0),
+ RK3036_PLL_RATE(7, 3, 350, 4, 1, 1, 0),
+ RK3036_PLL_RATE(69600, 1, 116, 4, 1, 1, 0),
+ RK3036_PLL_RATE(6, 1, 100, 4, 1, 1, 0),
+ RK3036_PLL_RATE(59400, 1, 99, 4, 1, 1, 0),
+ RK3036_PLL_RATE(5, 1, 125, 6, 1, 1, 0),
+ RK3036_PLL_RATE(40800, 1, 68, 2, 2, 1, 0),
+ RK3036_PLL_RATE(31200, 1, 78, 6, 1, 1, 0),
+ RK3036_PLL_RATE(21600, 1, 72, 4, 2, 1, 0),
+ RK3036_PLL_RATE(2, 1, 100, 3, 4, 1, 0),
+ RK3036_PLL_RATE(14850, 1, 99, 4, 4, 1, 0),
+ RK3036_PLL_RATE(1, 1, 150, 6, 6, 1, 0),
+ RK3036_PLL_RATE(9600, 1, 96, 6, 4, 1, 0),
+ RK3036_
[PATCH v3 2/4] clk: rockchip: add dt-binding header for rk3568
Add the dt-bindings header for the rk3568, that gets shared between the clock controller and the clock references in the dts. Add softreset ID for rk3568. Signed-off-by: Elaine Zhang --- include/dt-bindings/clock/rk3568-cru.h | 926 + 1 file changed, 926 insertions(+) create mode 100644 include/dt-bindings/clock/rk3568-cru.h diff --git a/include/dt-bindings/clock/rk3568-cru.h b/include/dt-bindings/clock/rk3568-cru.h new file mode 100644 index ..d29890865150 --- /dev/null +++ b/include/dt-bindings/clock/rk3568-cru.h @@ -0,0 +1,926 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2021 Rockchip Electronics Co. Ltd. + * Author: Elaine Zhang + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H + +/* pmucru-clocks indices */ + +/* pmucru plls */ +#define PLL_PPLL 1 +#define PLL_HPLL 2 + +/* pmucru clocks */ +#define XIN_OSC0_DIV 4 +#define CLK_RTC_32K5 +#define CLK_PMU6 +#define CLK_I2C0 7 +#define CLK_RTC32K_FRAC8 +#define CLK_UART0_DIV 9 +#define CLK_UART0_FRAC 10 +#define SCLK_UART0 11 +#define DBCLK_GPIO012 +#define CLK_PWM0 13 +#define CLK_CAPTURE_PWM0_NDFT 14 +#define CLK_PMUPVTM15 +#define CLK_CORE_PMUPVTM 16 +#define CLK_REF24M 17 +#define XIN_OSC0_USBPHY0_G 18 +#define CLK_USBPHY0_REF19 +#define XIN_OSC0_USBPHY1_G 20 +#define CLK_USBPHY1_REF21 +#define XIN_OSC0_MIPIDSIPHY0_G 22 +#define CLK_MIPIDSIPHY0_REF23 +#define XIN_OSC0_MIPIDSIPHY1_G 24 +#define CLK_MIPIDSIPHY1_REF25 +#define CLK_WIFI_DIV 26 +#define CLK_WIFI_OSC0 27 +#define CLK_WIFI 28 +#define CLK_PCIEPHY0_DIV 29 +#define CLK_PCIEPHY0_OSC0 30 +#define CLK_PCIEPHY0_REF 31 +#define CLK_PCIEPHY1_DIV 32 +#define CLK_PCIEPHY1_OSC0 33 +#define CLK_PCIEPHY1_REF 34 +#define CLK_PCIEPHY2_DIV 35 +#define CLK_PCIEPHY2_OSC0 36 +#define CLK_PCIEPHY2_REF 37 +#define CLK_PCIE30PHY_REF_M38 +#define CLK_PCIE30PHY_REF_N39 +#define CLK_HDMI_REF 40 +#define XIN_OSC0_EDPPHY_G 41 +#define PCLK_PDPMU 42 +#define PCLK_PMU 43 +#define PCLK_UART0 44 +#define PCLK_I2C0 45 +#define PCLK_GPIO0 46 +#define PCLK_PMUPVTM 47 +#define PCLK_PWM0 48 +#define CLK_PDPMU 49 +#define SCLK_32K_IOE 50 + +#define CLKPMU_NR_CLKS (SCLK_32K_IOE + 1) + +/* cru-clocks indices */ + +/* cru plls */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_CPLL 3 +#define PLL_GPLL 4 +#define PLL_VPLL 5 +#define PLL_NPLL 6 + +/* cru clocks */ +#define CPLL_333M 9 +#define ARMCLK 10 +#define USB480M11 +#define ACLK_CORE_NIU2BUS 18 +#define CLK_CORE_PVTM 19 +#define CLK_CORE_PVTM_CORE 20 +#define CLK_CORE_PVTPLL21 +#define CLK_GPU_SRC22 +#define CLK_GPU_PRE_NDFT 23 +#define CLK_GPU_PRE_MUX24 +#define ACLK_GPU_PRE 25 +#define PCLK_GPU_PRE 26 +#define CLK_GPU27 +#define CLK_GPU_NP528 +#define PCLK_GPU_PVTM 29 +#define CLK_GPU_PVTM 30 +#define CLK_GPU_PVTM_CORE 31 +#define CLK_GPU_PVTPLL 32 +#define CLK_NPU_SRC33 +#define CLK_NPU_PRE_NDFT 34 +#define CLK_NPU35 +#define CLK_NPU_NP536 +#define HCLK_NPU_PRE 37 +#define PCLK_NPU_PRE 38 +#define ACLK_NPU_PRE 39 +#define ACLK_NPU 40 +#define HCLK_NPU 41 +#define PCLK_NPU_PVTM 42 +#define CLK_NPU_PVTM 43 +#define CLK_NPU_PVTM_CORE 44 +#define CLK_NPU_PVTPLL 45 +#define CLK_DDRPHY1X_SRC 46 +#define CLK_DDRPHY1X_HWFFC_SRC 47 +#define CLK_DDR1X 48 +#define CLK_MSCH 49 +#define CLK24_DDRMON 50 +#define ACLK_GIC_AUDIO 51 +#define HCLK_GIC_AUDIO 52 +#define HCLK_SDMMC_BUFFER 53 +#define DCLK_SDMMC_BUFFER 54 +#define ACLK_GIC60055 +#define ACLK_SPINLOCK 56 +#define HCLK_I2S0_8CH 57 +#define HCLK_I2S1_8CH 58 +#define HCLK_I2S2_2CH 59 +#define HCLK_I2S3_2CH 60 +#define CLK_I2S0_8CH_TX_SRC61 +#define CLK_I2S0_8CH_TX_FRAC 62 +#define MCLK_I2S0_8CH_TX 63 +#define I2S0_MCLKOUT_TX64 +#define CLK_I2S0_8CH_RX_SRC65 +#define CLK_I2S0_8CH_RX_FRAC 66 +#define MCLK_I2S0_8CH_RX 67 +#define I2S0_MCLKOUT_RX68 +#define CLK_I2S1_8CH_TX_SRC69 +#define CLK_I2S1_8CH_TX_FRAC 70 +#define MCLK_I2S1_8CH_TX 71 +#define
[PATCH v3 3/4] clk: rockchip: support more core div setting
Use arrays to support more core independent div settings.
A55 supports each core to work at different frequencies, and each core
has an independent divider control.
Signed-off-by: Elaine Zhang
---
drivers/clk/rockchip/clk-cpu.c| 53 +--
drivers/clk/rockchip/clk-px30.c | 7 ++--
drivers/clk/rockchip/clk-rk3036.c | 7 ++--
drivers/clk/rockchip/clk-rk3128.c | 7 ++--
drivers/clk/rockchip/clk-rk3188.c | 7 ++--
drivers/clk/rockchip/clk-rk3228.c | 7 ++--
drivers/clk/rockchip/clk-rk3288.c | 7 ++--
drivers/clk/rockchip/clk-rk3308.c | 7 ++--
drivers/clk/rockchip/clk-rk3328.c | 7 ++--
drivers/clk/rockchip/clk-rk3368.c | 14
drivers/clk/rockchip/clk-rk3399.c | 14
drivers/clk/rockchip/clk-rv1108.c | 7 ++--
drivers/clk/rockchip/clk.h| 24 +++---
13 files changed, 94 insertions(+), 74 deletions(-)
diff --git a/drivers/clk/rockchip/clk-cpu.c b/drivers/clk/rockchip/clk-cpu.c
index fa9027fb1920..47288197c9d7 100644
--- a/drivers/clk/rockchip/clk-cpu.c
+++ b/drivers/clk/rockchip/clk-cpu.c
@@ -84,10 +84,10 @@ static unsigned long rockchip_cpuclk_recalc_rate(struct
clk_hw *hw,
{
struct rockchip_cpuclk *cpuclk = to_rockchip_cpuclk_hw(hw);
const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data;
- u32 clksel0 = readl_relaxed(cpuclk->reg_base + reg_data->core_reg);
+ u32 clksel0 = readl_relaxed(cpuclk->reg_base + reg_data->core_reg[0]);
- clksel0 >>= reg_data->div_core_shift;
- clksel0 &= reg_data->div_core_mask;
+ clksel0 >>= reg_data->div_core_shift[0];
+ clksel0 &= reg_data->div_core_mask[0];
return parent_rate / (clksel0 + 1);
}
@@ -120,6 +120,7 @@ static int rockchip_cpuclk_pre_rate_change(struct
rockchip_cpuclk *cpuclk,
const struct rockchip_cpuclk_rate_table *rate;
unsigned long alt_prate, alt_div;
unsigned long flags;
+ int i = 0;
/* check validity of the new rate */
rate = rockchip_get_cpuclk_settings(cpuclk, ndata->new_rate);
@@ -142,10 +143,10 @@ static int rockchip_cpuclk_pre_rate_change(struct
rockchip_cpuclk *cpuclk,
if (alt_prate > ndata->old_rate) {
/* calculate dividers */
alt_div = DIV_ROUND_UP(alt_prate, ndata->old_rate) - 1;
- if (alt_div > reg_data->div_core_mask) {
+ if (alt_div > reg_data->div_core_mask[0]) {
pr_warn("%s: limiting alt-divider %lu to %d\n",
- __func__, alt_div, reg_data->div_core_mask);
- alt_div = reg_data->div_core_mask;
+ __func__, alt_div, reg_data->div_core_mask[0]);
+ alt_div = reg_data->div_core_mask[0];
}
/*
@@ -158,19 +159,17 @@ static int rockchip_cpuclk_pre_rate_change(struct
rockchip_cpuclk *cpuclk,
pr_debug("%s: setting div %lu as alt-rate %lu > old-rate %lu\n",
__func__, alt_div, alt_prate, ndata->old_rate);
- writel(HIWORD_UPDATE(alt_div, reg_data->div_core_mask,
- reg_data->div_core_shift) |
- HIWORD_UPDATE(reg_data->mux_core_alt,
-reg_data->mux_core_mask,
-reg_data->mux_core_shift),
- cpuclk->reg_base + reg_data->core_reg);
- } else {
- /* select alternate parent */
- writel(HIWORD_UPDATE(reg_data->mux_core_alt,
-reg_data->mux_core_mask,
-reg_data->mux_core_shift),
- cpuclk->reg_base + reg_data->core_reg);
+ for (i = 0; i < reg_data->num_cores; i++) {
+ writel(HIWORD_UPDATE(alt_div,
reg_data->div_core_mask[i],
+reg_data->div_core_shift[i]),
+ cpuclk->reg_base + reg_data->core_reg[i]);
+ }
}
+ /* select alternate parent */
+ writel(HIWORD_UPDATE(reg_data->mux_core_alt,
+reg_data->mux_core_mask,
+reg_data->mux_core_shift),
+ cpuclk->reg_base + reg_data->core_reg[0]);
spin_unlock_irqrestore(cpuclk->lock, flags);
return 0;
@@ -182,6 +181,7 @@ static int rockchip_cpuclk_post_rate_change(struct
rockchip_cpuclk *cpuclk,
const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data;
const struct rockchip_cpuclk_rate_table *rate;
unsigned long flags;
+ int i = 0;
rate = rockchip_get_cpuclk_settings(cpuclk, ndata->new_rate);
i
[PATCH v3 1/4] dt-binding: clock: Document rockchip,rk3568-cru bindings
Document the device tree bindings of the rockchip Rk3568 SoC
clock driver in
Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml.
Signed-off-by: Elaine Zhang
---
.../bindings/clock/rockchip,rk3568-cru.yaml | 60 +++
1 file changed, 60 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml
b/Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml
new file mode 100644
index ..b2c26097827f
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/rockchip,rk3568-cru.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ROCKCHIP rk3568 Family Clock Control Module Binding
+
+maintainers:
+ - Elaine Zhang
+ - Heiko Stuebner
+
+description: |
+ The RK3568 clock controller generates the clock and also implements a
+ reset controller for SoC peripherals.
+ (examples: provide SCLK_UART1\PCLK_UART1 and SRST_P_UART1\SRST_S_UART1 for
UART module)
+ Each clock is assigned an identifier and client nodes can use this identifier
+ to specify the clock which they consume. All available clocks are defined as
+ preprocessor macros in the dt-bindings/clock/rk3568-cru.h headers and can be
+ used in device tree sources.
+
+properties:
+ compatible:
+enum:
+ - rockchip,rk3568-cru
+ - rockchip,rk3568-pmucru
+
+ reg:
+maxItems: 1
+
+ "#clock-cells":
+const: 1
+
+ "#reset-cells":
+const: 1
+
+required:
+ - compatible
+ - reg
+ - "#clock-cells"
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ # Clock Control Module node:
+ - |
+pmucru: clock-controller@fdd0 {
+ compatible = "rockchip,rk3568-pmucru";
+ reg = <0xfdd0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+};
+ - |
+cru: clock-controller@fdd2 {
+ compatible = "rockchip,rk3568-cru";
+ reg = <0xfdd2 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+};
--
2.17.1
[PATCH v3 0/4] clk: rockchip: add clock controller for rk3568
Add the clock tree definition for the new rk3568 SoC. Change in V3: [PATCH v3 1/4]: Fix some code styles. [PATCH v3 2/4]: No change. [PATCH v3 3/4]: No change. [PATCH v3 4/4]: No change. Change in V2: [PATCH v2 1/4]: Convert rockchip,rk3568-cru.txt to YAML, And update commit message. [PATCH v2 2/4]: No change. [PATCH v2 3/4]: Use arrays to support more core independent div settings. [PATCH v2 4/4]: Adapter [PATCH v2 3/4] changes. Elaine Zhang (4): dt-binding: clock: Document rockchip,rk3568-cru bindings clk: rockchip: add dt-binding header for rk3568 clk: rockchip: support more core div setting clk: rockchip: add clock controller for rk3568 .../bindings/clock/rockchip,rk3568-cru.yaml | 60 + drivers/clk/rockchip/Kconfig |7 + drivers/clk/rockchip/Makefile |1 + drivers/clk/rockchip/clk-cpu.c| 53 +- drivers/clk/rockchip/clk-px30.c |7 +- drivers/clk/rockchip/clk-rk3036.c |7 +- drivers/clk/rockchip/clk-rk3128.c |7 +- drivers/clk/rockchip/clk-rk3188.c |7 +- drivers/clk/rockchip/clk-rk3228.c |7 +- drivers/clk/rockchip/clk-rk3288.c |7 +- drivers/clk/rockchip/clk-rk3308.c |7 +- drivers/clk/rockchip/clk-rk3328.c |7 +- drivers/clk/rockchip/clk-rk3368.c | 14 +- drivers/clk/rockchip/clk-rk3399.c | 14 +- drivers/clk/rockchip/clk-rk3568.c | 1726 + drivers/clk/rockchip/clk-rv1108.c |7 +- drivers/clk/rockchip/clk.h| 54 +- include/dt-bindings/clock/rk3568-cru.h| 926 + 18 files changed, 2843 insertions(+), 75 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml create mode 100644 drivers/clk/rockchip/clk-rk3568.c create mode 100644 include/dt-bindings/clock/rk3568-cru.h -- 2.17.1
[PATCH v2 1/4] dt-binding: clock: Document rockchip,rk3568-cru bindings
Document the device tree bindings of the rockchip Rk3568 SoC
clock driver in
Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml.
Signed-off-by: Elaine Zhang
---
.../bindings/clock/rockchip,rk3568-cru.yaml | 55 +++
1 file changed, 55 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml
b/Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml
new file mode 100644
index ..612da341ea67
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/rockchip,rk3568-cru.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ROCKCHIP rk3568 Family Clock Control Module Binding
+
+maintainers:
+ - Elaine Zhang
+
+description: |
+ The RK3568 clock controller generates and supplies clock to various
+ controllers within the SoC and also implements a reset controller for SoC
+ peripherals.
+
+properties:
+ compatible:
+enum:
+ - rockchip,rk3568-cru
+ - rockchip,rk3568-pmucru
+
+ reg:
+maxItems: 1
+
+ '#clock-cells':
+const: 1
+
+ '#reset-cells':
+const: 1
+
+required:
+ - compatible
+ - reg
+ - "#clock-cells"
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ # Clock Control Module node:
+ - |
+pmucru: clock-controller@fdd0 {
+ compatible = "rockchip,rk3568-pmucru";
+ reg = <0x0 0xfdd0 0x0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+};
+ - |
+cru: clock-controller@fdd2 {
+ compatible = "rockchip,rk3568-cru";
+ reg = <0x0 0xfdd2 0x0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+};
--
2.17.1
[PATCH v2 3/4] clk: rockchip: support more core div setting
Use arrays to support more core independent div settings.
A55 supports each core to work at different frequencies, and each core
has an independent divider control.
Signed-off-by: Elaine Zhang
---
drivers/clk/rockchip/clk-cpu.c| 53 +--
drivers/clk/rockchip/clk-px30.c | 7 ++--
drivers/clk/rockchip/clk-rk3036.c | 7 ++--
drivers/clk/rockchip/clk-rk3128.c | 7 ++--
drivers/clk/rockchip/clk-rk3188.c | 7 ++--
drivers/clk/rockchip/clk-rk3228.c | 7 ++--
drivers/clk/rockchip/clk-rk3288.c | 7 ++--
drivers/clk/rockchip/clk-rk3308.c | 7 ++--
drivers/clk/rockchip/clk-rk3328.c | 7 ++--
drivers/clk/rockchip/clk-rk3368.c | 14
drivers/clk/rockchip/clk-rk3399.c | 14
drivers/clk/rockchip/clk-rv1108.c | 7 ++--
drivers/clk/rockchip/clk.h| 24 +++---
13 files changed, 94 insertions(+), 74 deletions(-)
diff --git a/drivers/clk/rockchip/clk-cpu.c b/drivers/clk/rockchip/clk-cpu.c
index fa9027fb1920..47288197c9d7 100644
--- a/drivers/clk/rockchip/clk-cpu.c
+++ b/drivers/clk/rockchip/clk-cpu.c
@@ -84,10 +84,10 @@ static unsigned long rockchip_cpuclk_recalc_rate(struct
clk_hw *hw,
{
struct rockchip_cpuclk *cpuclk = to_rockchip_cpuclk_hw(hw);
const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data;
- u32 clksel0 = readl_relaxed(cpuclk->reg_base + reg_data->core_reg);
+ u32 clksel0 = readl_relaxed(cpuclk->reg_base + reg_data->core_reg[0]);
- clksel0 >>= reg_data->div_core_shift;
- clksel0 &= reg_data->div_core_mask;
+ clksel0 >>= reg_data->div_core_shift[0];
+ clksel0 &= reg_data->div_core_mask[0];
return parent_rate / (clksel0 + 1);
}
@@ -120,6 +120,7 @@ static int rockchip_cpuclk_pre_rate_change(struct
rockchip_cpuclk *cpuclk,
const struct rockchip_cpuclk_rate_table *rate;
unsigned long alt_prate, alt_div;
unsigned long flags;
+ int i = 0;
/* check validity of the new rate */
rate = rockchip_get_cpuclk_settings(cpuclk, ndata->new_rate);
@@ -142,10 +143,10 @@ static int rockchip_cpuclk_pre_rate_change(struct
rockchip_cpuclk *cpuclk,
if (alt_prate > ndata->old_rate) {
/* calculate dividers */
alt_div = DIV_ROUND_UP(alt_prate, ndata->old_rate) - 1;
- if (alt_div > reg_data->div_core_mask) {
+ if (alt_div > reg_data->div_core_mask[0]) {
pr_warn("%s: limiting alt-divider %lu to %d\n",
- __func__, alt_div, reg_data->div_core_mask);
- alt_div = reg_data->div_core_mask;
+ __func__, alt_div, reg_data->div_core_mask[0]);
+ alt_div = reg_data->div_core_mask[0];
}
/*
@@ -158,19 +159,17 @@ static int rockchip_cpuclk_pre_rate_change(struct
rockchip_cpuclk *cpuclk,
pr_debug("%s: setting div %lu as alt-rate %lu > old-rate %lu\n",
__func__, alt_div, alt_prate, ndata->old_rate);
- writel(HIWORD_UPDATE(alt_div, reg_data->div_core_mask,
- reg_data->div_core_shift) |
- HIWORD_UPDATE(reg_data->mux_core_alt,
-reg_data->mux_core_mask,
-reg_data->mux_core_shift),
- cpuclk->reg_base + reg_data->core_reg);
- } else {
- /* select alternate parent */
- writel(HIWORD_UPDATE(reg_data->mux_core_alt,
-reg_data->mux_core_mask,
-reg_data->mux_core_shift),
- cpuclk->reg_base + reg_data->core_reg);
+ for (i = 0; i < reg_data->num_cores; i++) {
+ writel(HIWORD_UPDATE(alt_div,
reg_data->div_core_mask[i],
+reg_data->div_core_shift[i]),
+ cpuclk->reg_base + reg_data->core_reg[i]);
+ }
}
+ /* select alternate parent */
+ writel(HIWORD_UPDATE(reg_data->mux_core_alt,
+reg_data->mux_core_mask,
+reg_data->mux_core_shift),
+ cpuclk->reg_base + reg_data->core_reg[0]);
spin_unlock_irqrestore(cpuclk->lock, flags);
return 0;
@@ -182,6 +181,7 @@ static int rockchip_cpuclk_post_rate_change(struct
rockchip_cpuclk *cpuclk,
const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data;
const struct rockchip_cpuclk_rate_table *rate;
unsigned long flags;
+ int i = 0;
rate = rockchip_get_cpuclk_settings(cpuclk, ndata->new_rate);
i
[PATCH v2 0/4] clk: rockchip: add clock controller for rk3568
Add the clock tree definition for the new rk3568 SoC. Change in V2: [PATCH v2 1/4]: Convert rockchip,rk3568-cru.txt to YAML, And update commit message. [PATCH v2 2/4]: No change. [PATCH v2 3/4]: Use arrays to support more core independent div settings. [PATCH v2 4/4]: Adapter [PATCH v2 3/4] changes. Elaine Zhang (4): dt-binding: clock: Document rockchip,rk3568-cru bindings clk: rockchip: add dt-binding header for rk3568 clk: rockchip: support more core div setting clk: rockchip: add clock controller for rk3568 .../bindings/clock/rockchip,rk3568-cru.yaml | 55 + drivers/clk/rockchip/Kconfig |7 + drivers/clk/rockchip/Makefile |1 + drivers/clk/rockchip/clk-cpu.c| 40 +- drivers/clk/rockchip/clk-px30.c |7 +- drivers/clk/rockchip/clk-rk3036.c |7 +- drivers/clk/rockchip/clk-rk3128.c |7 +- drivers/clk/rockchip/clk-rk3188.c |7 +- drivers/clk/rockchip/clk-rk3228.c |7 +- drivers/clk/rockchip/clk-rk3288.c |7 +- drivers/clk/rockchip/clk-rk3308.c |7 +- drivers/clk/rockchip/clk-rk3328.c |7 +- drivers/clk/rockchip/clk-rk3368.c | 14 +- drivers/clk/rockchip/clk-rk3399.c | 14 +- drivers/clk/rockchip/clk-rk3568.c | 1726 + drivers/clk/rockchip/clk-rv1108.c |7 +- drivers/clk/rockchip/clk.h| 54 +- include/dt-bindings/clock/rk3568-cru.h| 926 + 18 files changed, 2834 insertions(+), 66 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml create mode 100644 drivers/clk/rockchip/clk-rk3568.c create mode 100644 include/dt-bindings/clock/rk3568-cru.h -- 2.17.1
[PATCH v2 2/4] clk: rockchip: add dt-binding header for rk3568
Add the dt-bindings header for the rk3568, that gets shared between the clock controller and the clock references in the dts. Add softreset ID for rk3568. Signed-off-by: Elaine Zhang --- include/dt-bindings/clock/rk3568-cru.h | 926 + 1 file changed, 926 insertions(+) create mode 100644 include/dt-bindings/clock/rk3568-cru.h diff --git a/include/dt-bindings/clock/rk3568-cru.h b/include/dt-bindings/clock/rk3568-cru.h new file mode 100644 index ..d29890865150 --- /dev/null +++ b/include/dt-bindings/clock/rk3568-cru.h @@ -0,0 +1,926 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2021 Rockchip Electronics Co. Ltd. + * Author: Elaine Zhang + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H + +/* pmucru-clocks indices */ + +/* pmucru plls */ +#define PLL_PPLL 1 +#define PLL_HPLL 2 + +/* pmucru clocks */ +#define XIN_OSC0_DIV 4 +#define CLK_RTC_32K5 +#define CLK_PMU6 +#define CLK_I2C0 7 +#define CLK_RTC32K_FRAC8 +#define CLK_UART0_DIV 9 +#define CLK_UART0_FRAC 10 +#define SCLK_UART0 11 +#define DBCLK_GPIO012 +#define CLK_PWM0 13 +#define CLK_CAPTURE_PWM0_NDFT 14 +#define CLK_PMUPVTM15 +#define CLK_CORE_PMUPVTM 16 +#define CLK_REF24M 17 +#define XIN_OSC0_USBPHY0_G 18 +#define CLK_USBPHY0_REF19 +#define XIN_OSC0_USBPHY1_G 20 +#define CLK_USBPHY1_REF21 +#define XIN_OSC0_MIPIDSIPHY0_G 22 +#define CLK_MIPIDSIPHY0_REF23 +#define XIN_OSC0_MIPIDSIPHY1_G 24 +#define CLK_MIPIDSIPHY1_REF25 +#define CLK_WIFI_DIV 26 +#define CLK_WIFI_OSC0 27 +#define CLK_WIFI 28 +#define CLK_PCIEPHY0_DIV 29 +#define CLK_PCIEPHY0_OSC0 30 +#define CLK_PCIEPHY0_REF 31 +#define CLK_PCIEPHY1_DIV 32 +#define CLK_PCIEPHY1_OSC0 33 +#define CLK_PCIEPHY1_REF 34 +#define CLK_PCIEPHY2_DIV 35 +#define CLK_PCIEPHY2_OSC0 36 +#define CLK_PCIEPHY2_REF 37 +#define CLK_PCIE30PHY_REF_M38 +#define CLK_PCIE30PHY_REF_N39 +#define CLK_HDMI_REF 40 +#define XIN_OSC0_EDPPHY_G 41 +#define PCLK_PDPMU 42 +#define PCLK_PMU 43 +#define PCLK_UART0 44 +#define PCLK_I2C0 45 +#define PCLK_GPIO0 46 +#define PCLK_PMUPVTM 47 +#define PCLK_PWM0 48 +#define CLK_PDPMU 49 +#define SCLK_32K_IOE 50 + +#define CLKPMU_NR_CLKS (SCLK_32K_IOE + 1) + +/* cru-clocks indices */ + +/* cru plls */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_CPLL 3 +#define PLL_GPLL 4 +#define PLL_VPLL 5 +#define PLL_NPLL 6 + +/* cru clocks */ +#define CPLL_333M 9 +#define ARMCLK 10 +#define USB480M11 +#define ACLK_CORE_NIU2BUS 18 +#define CLK_CORE_PVTM 19 +#define CLK_CORE_PVTM_CORE 20 +#define CLK_CORE_PVTPLL21 +#define CLK_GPU_SRC22 +#define CLK_GPU_PRE_NDFT 23 +#define CLK_GPU_PRE_MUX24 +#define ACLK_GPU_PRE 25 +#define PCLK_GPU_PRE 26 +#define CLK_GPU27 +#define CLK_GPU_NP528 +#define PCLK_GPU_PVTM 29 +#define CLK_GPU_PVTM 30 +#define CLK_GPU_PVTM_CORE 31 +#define CLK_GPU_PVTPLL 32 +#define CLK_NPU_SRC33 +#define CLK_NPU_PRE_NDFT 34 +#define CLK_NPU35 +#define CLK_NPU_NP536 +#define HCLK_NPU_PRE 37 +#define PCLK_NPU_PRE 38 +#define ACLK_NPU_PRE 39 +#define ACLK_NPU 40 +#define HCLK_NPU 41 +#define PCLK_NPU_PVTM 42 +#define CLK_NPU_PVTM 43 +#define CLK_NPU_PVTM_CORE 44 +#define CLK_NPU_PVTPLL 45 +#define CLK_DDRPHY1X_SRC 46 +#define CLK_DDRPHY1X_HWFFC_SRC 47 +#define CLK_DDR1X 48 +#define CLK_MSCH 49 +#define CLK24_DDRMON 50 +#define ACLK_GIC_AUDIO 51 +#define HCLK_GIC_AUDIO 52 +#define HCLK_SDMMC_BUFFER 53 +#define DCLK_SDMMC_BUFFER 54 +#define ACLK_GIC60055 +#define ACLK_SPINLOCK 56 +#define HCLK_I2S0_8CH 57 +#define HCLK_I2S1_8CH 58 +#define HCLK_I2S2_2CH 59 +#define HCLK_I2S3_2CH 60 +#define CLK_I2S0_8CH_TX_SRC61 +#define CLK_I2S0_8CH_TX_FRAC 62 +#define MCLK_I2S0_8CH_TX 63 +#define I2S0_MCLKOUT_TX64 +#define CLK_I2S0_8CH_RX_SRC65 +#define CLK_I2S0_8CH_RX_FRAC 66 +#define MCLK_I2S0_8CH_RX 67 +#define I2S0_MCLKOUT_RX68 +#define CLK_I2S1_8CH_TX_SRC69 +#define CLK_I2S1_8CH_TX_FRAC 70 +#define MCLK_I2S1_8CH_TX 71 +#define
[PATCH v2 4/4] clk: rockchip: add clock controller for rk3568
Add the clock tree definition for the new rk3568 SoC.
Signed-off-by: Elaine Zhang
---
drivers/clk/rockchip/Kconfig |7 +
drivers/clk/rockchip/Makefile |1 +
drivers/clk/rockchip/clk-rk3568.c | 1726 +
drivers/clk/rockchip/clk.h| 30 +-
4 files changed, 1763 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/rockchip/clk-rk3568.c
diff --git a/drivers/clk/rockchip/Kconfig b/drivers/clk/rockchip/Kconfig
index effd05032e85..2e31901f4213 100644
--- a/drivers/clk/rockchip/Kconfig
+++ b/drivers/clk/rockchip/Kconfig
@@ -85,4 +85,11 @@ config CLK_RK3399
default y
help
Build the driver for RK3399 Clock Driver.
+
+config CLK_RK3568
+ tristate "Rockchip RK3568 clock controller support"
+ depends on (ARM64 || COMPILE_TEST)
+ default y
+ help
+ Build the driver for RK3568 Clock Driver.
endif
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index a99e4d9bbae1..2b78f1247372 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -26,3 +26,4 @@ obj-$(CONFIG_CLK_RK3308)+= clk-rk3308.o
obj-$(CONFIG_CLK_RK3328)+= clk-rk3328.o
obj-$(CONFIG_CLK_RK3368)+= clk-rk3368.o
obj-$(CONFIG_CLK_RK3399)+= clk-rk3399.o
+obj-$(CONFIG_CLK_RK3568) += clk-rk3568.o
diff --git a/drivers/clk/rockchip/clk-rk3568.c
b/drivers/clk/rockchip/clk-rk3568.c
new file mode 100644
index ..60913aa91897
--- /dev/null
+++ b/drivers/clk/rockchip/clk-rk3568.c
@@ -0,0 +1,1726 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
+ * Author: Elaine Zhang
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "clk.h"
+
+#define RK3568_GRF_SOC_STATUS0 0x580
+
+enum rk3568_pmu_plls {
+ ppll, hpll,
+};
+
+enum rk3568_plls {
+ apll, dpll, gpll, cpll, npll, vpll,
+};
+
+static struct rockchip_pll_rate_table rk3568_pll_rates[] = {
+ /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
+ RK3036_PLL_RATE(220800, 1, 92, 1, 1, 1, 0),
+ RK3036_PLL_RATE(218400, 1, 91, 1, 1, 1, 0),
+ RK3036_PLL_RATE(216000, 1, 90, 1, 1, 1, 0),
+ RK3036_PLL_RATE(208800, 1, 87, 1, 1, 1, 0),
+ RK3036_PLL_RATE(206400, 1, 86, 1, 1, 1, 0),
+ RK3036_PLL_RATE(204000, 1, 85, 1, 1, 1, 0),
+ RK3036_PLL_RATE(201600, 1, 84, 1, 1, 1, 0),
+ RK3036_PLL_RATE(199200, 1, 83, 1, 1, 1, 0),
+ RK3036_PLL_RATE(192000, 1, 80, 1, 1, 1, 0),
+ RK3036_PLL_RATE(189600, 1, 79, 1, 1, 1, 0),
+ RK3036_PLL_RATE(18, 1, 75, 1, 1, 1, 0),
+ RK3036_PLL_RATE(170400, 1, 71, 1, 1, 1, 0),
+ RK3036_PLL_RATE(160800, 1, 67, 1, 1, 1, 0),
+ RK3036_PLL_RATE(16, 3, 200, 1, 1, 1, 0),
+ RK3036_PLL_RATE(158400, 1, 132, 2, 1, 1, 0),
+ RK3036_PLL_RATE(156000, 1, 130, 2, 1, 1, 0),
+ RK3036_PLL_RATE(153600, 1, 128, 2, 1, 1, 0),
+ RK3036_PLL_RATE(151200, 1, 126, 2, 1, 1, 0),
+ RK3036_PLL_RATE(148800, 1, 124, 2, 1, 1, 0),
+ RK3036_PLL_RATE(146400, 1, 122, 2, 1, 1, 0),
+ RK3036_PLL_RATE(144000, 1, 120, 2, 1, 1, 0),
+ RK3036_PLL_RATE(141600, 1, 118, 2, 1, 1, 0),
+ RK3036_PLL_RATE(14, 3, 350, 2, 1, 1, 0),
+ RK3036_PLL_RATE(139200, 1, 116, 2, 1, 1, 0),
+ RK3036_PLL_RATE(136800, 1, 114, 2, 1, 1, 0),
+ RK3036_PLL_RATE(134400, 1, 112, 2, 1, 1, 0),
+ RK3036_PLL_RATE(132000, 1, 110, 2, 1, 1, 0),
+ RK3036_PLL_RATE(129600, 1, 108, 2, 1, 1, 0),
+ RK3036_PLL_RATE(127200, 1, 106, 2, 1, 1, 0),
+ RK3036_PLL_RATE(124800, 1, 104, 2, 1, 1, 0),
+ RK3036_PLL_RATE(12, 1, 100, 2, 1, 1, 0),
+ RK3036_PLL_RATE(118800, 1, 99, 2, 1, 1, 0),
+ RK3036_PLL_RATE(110400, 1, 92, 2, 1, 1, 0),
+ RK3036_PLL_RATE(11, 3, 275, 2, 1, 1, 0),
+ RK3036_PLL_RATE(100800, 1, 84, 2, 1, 1, 0),
+ RK3036_PLL_RATE(10, 3, 250, 2, 1, 1, 0),
+ RK3036_PLL_RATE(91200, 1, 76, 2, 1, 1, 0),
+ RK3036_PLL_RATE(81600, 1, 68, 2, 1, 1, 0),
+ RK3036_PLL_RATE(8, 3, 200, 2, 1, 1, 0),
+ RK3036_PLL_RATE(7, 3, 350, 4, 1, 1, 0),
+ RK3036_PLL_RATE(69600, 1, 116, 4, 1, 1, 0),
+ RK3036_PLL_RATE(6, 1, 100, 4, 1, 1, 0),
+ RK3036_PLL_RATE(59400, 1, 99, 4, 1, 1, 0),
+ RK3036_PLL_RATE(5, 1, 125, 6, 1, 1, 0),
+ RK3036_PLL_RATE(40800, 1, 68, 2, 2, 1, 0),
+ RK3036_PLL_RATE(31200, 1, 78, 6, 1, 1, 0),
+ RK3036_PLL_RATE(21600, 1, 72, 4, 2, 1, 0),
+ RK3036_PLL_RATE(2, 1, 100, 3, 4, 1, 0),
+ RK3036_PLL_RATE(14850, 1, 99, 4, 4, 1, 0),
+ RK3036_PLL_RATE(1, 1, 150, 6, 6, 1, 0),
+ RK3036_PLL_RATE(9600, 1, 96, 6, 4, 1, 0),
+ RK3036_
[PATCH v1 2/4] clk: rockchip: add dt-binding header for rk3568
Add the dt-bindings header for the rk3568, that gets shared between the clock controller and the clock references in the dts. Add softreset ID for rk3568. Signed-off-by: Elaine Zhang --- include/dt-bindings/clock/rk3568-cru.h | 926 + 1 file changed, 926 insertions(+) create mode 100644 include/dt-bindings/clock/rk3568-cru.h diff --git a/include/dt-bindings/clock/rk3568-cru.h b/include/dt-bindings/clock/rk3568-cru.h new file mode 100644 index ..22b0b8739b5d --- /dev/null +++ b/include/dt-bindings/clock/rk3568-cru.h @@ -0,0 +1,926 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2021 Rockchip Electronics Co. Ltd. + * Author: Elaine Zhang + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H + +/* pmucru-clocks indices */ + +/* pmucru plls */ +#define PLL_PPLL 1 +#define PLL_HPLL 2 + +/* pmucru clocks */ +#define XIN_OSC0_DIV 4 +#define CLK_RTC_32K5 +#define CLK_PMU6 +#define CLK_I2C0 7 +#define CLK_RTC32K_FRAC8 +#define CLK_UART0_DIV 9 +#define CLK_UART0_FRAC 10 +#define SCLK_UART0 11 +#define DBCLK_GPIO012 +#define CLK_PWM0 13 +#define CLK_CAPTURE_PWM0_NDFT 14 +#define CLK_PMUPVTM15 +#define CLK_CORE_PMUPVTM 16 +#define CLK_REF24M 17 +#define XIN_OSC0_USBPHY0_G 18 +#define CLK_USBPHY0_REF19 +#define XIN_OSC0_USBPHY1_G 20 +#define CLK_USBPHY1_REF21 +#define XIN_OSC0_MIPIDSIPHY0_G 22 +#define CLK_MIPIDSIPHY0_REF23 +#define XIN_OSC0_MIPIDSIPHY1_G 24 +#define CLK_MIPIDSIPHY1_REF25 +#define CLK_WIFI_DIV 26 +#define CLK_WIFI_OSC0 27 +#define CLK_WIFI 28 +#define CLK_PCIEPHY0_DIV 29 +#define CLK_PCIEPHY0_OSC0 30 +#define CLK_PCIEPHY0_REF 31 +#define CLK_PCIEPHY1_DIV 32 +#define CLK_PCIEPHY1_OSC0 33 +#define CLK_PCIEPHY1_REF 34 +#define CLK_PCIEPHY2_DIV 35 +#define CLK_PCIEPHY2_OSC0 36 +#define CLK_PCIEPHY2_REF 37 +#define CLK_PCIE30PHY_REF_M38 +#define CLK_PCIE30PHY_REF_N39 +#define CLK_HDMI_REF 40 +#define XIN_OSC0_EDPPHY_G 41 +#define PCLK_PDPMU 42 +#define PCLK_PMU 43 +#define PCLK_UART0 44 +#define PCLK_I2C0 45 +#define PCLK_GPIO0 46 +#define PCLK_PMUPVTM 47 +#define PCLK_PWM0 48 +#define CLK_PDPMU 49 +#define SCLK_32K_IOE 50 + +#define CLKPMU_NR_CLKS (SCLK_32K_IOE + 1) + +/* cru-clocks indices */ + +/* cru plls */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_CPLL 3 +#define PLL_GPLL 4 +#define PLL_VPLL 5 +#define PLL_NPLL 6 + +/* cru clocks */ +#define CPLL_333M 9 +#define ARMCLK 10 +#define USB480M11 +#define ACLK_CORE_NIU2BUS 18 +#define CLK_CORE_PVTM 19 +#define CLK_CORE_PVTM_CORE 20 +#define CLK_CORE_PVTPLL21 +#define CLK_GPU_SRC22 +#define CLK_GPU_PRE_NDFT 23 +#define CLK_GPU_PRE_MUX24 +#define ACLK_GPU_PRE 25 +#define PCLK_GPU_PRE 26 +#define CLK_GPU27 +#define CLK_GPU_NP528 +#define PCLK_GPU_PVTM 29 +#define CLK_GPU_PVTM 30 +#define CLK_GPU_PVTM_CORE 31 +#define CLK_GPU_PVTPLL 32 +#define CLK_NPU_SRC33 +#define CLK_NPU_PRE_NDFT 34 +#define CLK_NPU35 +#define CLK_NPU_NP536 +#define HCLK_NPU_PRE 37 +#define PCLK_NPU_PRE 38 +#define ACLK_NPU_PRE 39 +#define ACLK_NPU 40 +#define HCLK_NPU 41 +#define PCLK_NPU_PVTM 42 +#define CLK_NPU_PVTM 43 +#define CLK_NPU_PVTM_CORE 44 +#define CLK_NPU_PVTPLL 45 +#define CLK_DDRPHY1X_SRC 46 +#define CLK_DDRPHY1X_HWFFC_SRC 47 +#define CLK_DDR1X 48 +#define CLK_MSCH 49 +#define CLK24_DDRMON 50 +#define ACLK_GIC_AUDIO 51 +#define HCLK_GIC_AUDIO 52 +#define HCLK_SDMMC_BUFFER 53 +#define DCLK_SDMMC_BUFFER 54 +#define ACLK_GIC60055 +#define ACLK_SPINLOCK 56 +#define HCLK_I2S0_8CH 57 +#define HCLK_I2S1_8CH 58 +#define HCLK_I2S2_2CH 59 +#define HCLK_I2S3_2CH 60 +#define CLK_I2S0_8CH_TX_SRC61 +#define CLK_I2S0_8CH_TX_FRAC 62 +#define MCLK_I2S0_8CH_TX 63 +#define I2S0_MCLKOUT_TX64 +#define CLK_I2S0_8CH_RX_SRC65 +#define CLK_I2S0_8CH_RX_FRAC 66 +#define MCLK_I2S0_8CH_RX 67 +#define I2S0_MCLKOUT_RX68 +#define CLK_I2S1_8CH_TX_SRC69 +#define CLK_I2S1_8CH_TX_FRAC 70 +#define MCLK_I2S1_8CH_TX 71 +#define
[PATCH v1 4/4] clk: rockchip: add clock controller for rk3568
Add the clock tree definition for the new rk3568 SoC.
Signed-off-by: Elaine Zhang
---
drivers/clk/rockchip/Kconfig |7 +
drivers/clk/rockchip/Makefile |1 +
drivers/clk/rockchip/clk-rk3568.c | 1724 +
drivers/clk/rockchip/clk.h| 28 +
4 files changed, 1760 insertions(+)
create mode 100644 drivers/clk/rockchip/clk-rk3568.c
diff --git a/drivers/clk/rockchip/Kconfig b/drivers/clk/rockchip/Kconfig
index effd05032e85..2e31901f4213 100644
--- a/drivers/clk/rockchip/Kconfig
+++ b/drivers/clk/rockchip/Kconfig
@@ -85,4 +85,11 @@ config CLK_RK3399
default y
help
Build the driver for RK3399 Clock Driver.
+
+config CLK_RK3568
+ tristate "Rockchip RK3568 clock controller support"
+ depends on (ARM64 || COMPILE_TEST)
+ default y
+ help
+ Build the driver for RK3568 Clock Driver.
endif
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index a99e4d9bbae1..2b78f1247372 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -26,3 +26,4 @@ obj-$(CONFIG_CLK_RK3308)+= clk-rk3308.o
obj-$(CONFIG_CLK_RK3328)+= clk-rk3328.o
obj-$(CONFIG_CLK_RK3368)+= clk-rk3368.o
obj-$(CONFIG_CLK_RK3399)+= clk-rk3399.o
+obj-$(CONFIG_CLK_RK3568) += clk-rk3568.o
diff --git a/drivers/clk/rockchip/clk-rk3568.c
b/drivers/clk/rockchip/clk-rk3568.c
new file mode 100644
index ..f498be1ab7c8
--- /dev/null
+++ b/drivers/clk/rockchip/clk-rk3568.c
@@ -0,0 +1,1724 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
+ * Author: Elaine Zhang
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "clk.h"
+
+#define RK3568_GRF_SOC_STATUS0 0x580
+
+enum rk3568_pmu_plls {
+ ppll, hpll,
+};
+
+enum rk3568_plls {
+ apll, dpll, gpll, cpll, npll, vpll,
+};
+
+static struct rockchip_pll_rate_table rk3568_pll_rates[] = {
+ /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
+ RK3036_PLL_RATE(220800, 1, 92, 1, 1, 1, 0),
+ RK3036_PLL_RATE(218400, 1, 91, 1, 1, 1, 0),
+ RK3036_PLL_RATE(216000, 1, 90, 1, 1, 1, 0),
+ RK3036_PLL_RATE(208800, 1, 87, 1, 1, 1, 0),
+ RK3036_PLL_RATE(206400, 1, 86, 1, 1, 1, 0),
+ RK3036_PLL_RATE(204000, 1, 85, 1, 1, 1, 0),
+ RK3036_PLL_RATE(201600, 1, 84, 1, 1, 1, 0),
+ RK3036_PLL_RATE(199200, 1, 83, 1, 1, 1, 0),
+ RK3036_PLL_RATE(192000, 1, 80, 1, 1, 1, 0),
+ RK3036_PLL_RATE(189600, 1, 79, 1, 1, 1, 0),
+ RK3036_PLL_RATE(18, 1, 75, 1, 1, 1, 0),
+ RK3036_PLL_RATE(170400, 1, 71, 1, 1, 1, 0),
+ RK3036_PLL_RATE(160800, 1, 67, 1, 1, 1, 0),
+ RK3036_PLL_RATE(16, 3, 200, 1, 1, 1, 0),
+ RK3036_PLL_RATE(158400, 1, 132, 2, 1, 1, 0),
+ RK3036_PLL_RATE(156000, 1, 130, 2, 1, 1, 0),
+ RK3036_PLL_RATE(153600, 1, 128, 2, 1, 1, 0),
+ RK3036_PLL_RATE(151200, 1, 126, 2, 1, 1, 0),
+ RK3036_PLL_RATE(148800, 1, 124, 2, 1, 1, 0),
+ RK3036_PLL_RATE(146400, 1, 122, 2, 1, 1, 0),
+ RK3036_PLL_RATE(144000, 1, 120, 2, 1, 1, 0),
+ RK3036_PLL_RATE(141600, 1, 118, 2, 1, 1, 0),
+ RK3036_PLL_RATE(14, 3, 350, 2, 1, 1, 0),
+ RK3036_PLL_RATE(139200, 1, 116, 2, 1, 1, 0),
+ RK3036_PLL_RATE(136800, 1, 114, 2, 1, 1, 0),
+ RK3036_PLL_RATE(134400, 1, 112, 2, 1, 1, 0),
+ RK3036_PLL_RATE(132000, 1, 110, 2, 1, 1, 0),
+ RK3036_PLL_RATE(129600, 1, 108, 2, 1, 1, 0),
+ RK3036_PLL_RATE(127200, 1, 106, 2, 1, 1, 0),
+ RK3036_PLL_RATE(124800, 1, 104, 2, 1, 1, 0),
+ RK3036_PLL_RATE(12, 1, 100, 2, 1, 1, 0),
+ RK3036_PLL_RATE(118800, 1, 99, 2, 1, 1, 0),
+ RK3036_PLL_RATE(110400, 1, 92, 2, 1, 1, 0),
+ RK3036_PLL_RATE(11, 3, 275, 2, 1, 1, 0),
+ RK3036_PLL_RATE(100800, 1, 84, 2, 1, 1, 0),
+ RK3036_PLL_RATE(10, 3, 250, 2, 1, 1, 0),
+ RK3036_PLL_RATE(91200, 1, 76, 2, 1, 1, 0),
+ RK3036_PLL_RATE(81600, 1, 68, 2, 1, 1, 0),
+ RK3036_PLL_RATE(8, 3, 200, 2, 1, 1, 0),
+ RK3036_PLL_RATE(7, 3, 350, 4, 1, 1, 0),
+ RK3036_PLL_RATE(69600, 1, 116, 4, 1, 1, 0),
+ RK3036_PLL_RATE(6, 1, 100, 4, 1, 1, 0),
+ RK3036_PLL_RATE(59400, 1, 99, 4, 1, 1, 0),
+ RK3036_PLL_RATE(5, 1, 125, 6, 1, 1, 0),
+ RK3036_PLL_RATE(40800, 1, 68, 2, 2, 1, 0),
+ RK3036_PLL_RATE(31200, 1, 78, 6, 1, 1, 0),
+ RK3036_PLL_RATE(21600, 1, 72, 4, 2, 1, 0),
+ RK3036_PLL_RATE(2, 1, 100, 3, 4, 1, 0),
+ RK3036_PLL_RATE(14850, 1, 99, 4, 4, 1, 0),
+ RK3036_PLL_RATE(1, 1, 150, 6, 6, 1, 0),
+ RK3036_PLL_RATE(9600, 1, 96, 6, 4, 1, 0),
+ RK3036_PLL_RATE(7425000
[PATCH v1 3/4] clk: rockchip: support more core div setting
A55 supports each core to work at different frequencies, and each core
has an independent divider control.
Signed-off-by: Elaine Zhang
---
drivers/clk/rockchip/clk-cpu.c | 25 +
drivers/clk/rockchip/clk.h | 17 -
2 files changed, 41 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-cpu.c b/drivers/clk/rockchip/clk-cpu.c
index fa9027fb1920..cac06f4f7573 100644
--- a/drivers/clk/rockchip/clk-cpu.c
+++ b/drivers/clk/rockchip/clk-cpu.c
@@ -164,6 +164,18 @@ static int rockchip_cpuclk_pre_rate_change(struct
rockchip_cpuclk *cpuclk,
reg_data->mux_core_mask,
reg_data->mux_core_shift),
cpuclk->reg_base + reg_data->core_reg);
+ if (reg_data->core1_reg)
+ writel(HIWORD_UPDATE(alt_div, reg_data->div_core1_mask,
+reg_data->div_core1_shift),
+ cpuclk->reg_base + reg_data->core1_reg);
+ if (reg_data->core2_reg)
+ writel(HIWORD_UPDATE(alt_div, reg_data->div_core2_mask,
+reg_data->div_core2_shift),
+ cpuclk->reg_base + reg_data->core2_reg);
+ if (reg_data->core3_reg)
+ writel(HIWORD_UPDATE(alt_div, reg_data->div_core3_mask,
+reg_data->div_core3_shift),
+ cpuclk->reg_base + reg_data->core3_reg);
} else {
/* select alternate parent */
writel(HIWORD_UPDATE(reg_data->mux_core_alt,
@@ -209,6 +221,19 @@ static int rockchip_cpuclk_post_rate_change(struct
rockchip_cpuclk *cpuclk,
reg_data->mux_core_shift),
cpuclk->reg_base + reg_data->core_reg);
+ if (reg_data->core1_reg)
+ writel(HIWORD_UPDATE(0, reg_data->div_core1_mask,
+reg_data->div_core1_shift),
+ cpuclk->reg_base + reg_data->core1_reg);
+ if (reg_data->core2_reg)
+ writel(HIWORD_UPDATE(0, reg_data->div_core2_mask,
+reg_data->div_core2_shift),
+ cpuclk->reg_base + reg_data->core2_reg);
+ if (reg_data->core3_reg)
+ writel(HIWORD_UPDATE(0, reg_data->div_core3_mask,
+reg_data->div_core3_shift),
+ cpuclk->reg_base + reg_data->core3_reg);
+
if (ndata->old_rate > ndata->new_rate)
rockchip_cpuclk_set_dividers(cpuclk, rate);
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index 2271a84124b0..b46c93fd0cb5 100644
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -322,7 +322,7 @@ struct rockchip_cpuclk_clksel {
u32 val;
};
-#define ROCKCHIP_CPUCLK_NUM_DIVIDERS 2
+#define ROCKCHIP_CPUCLK_NUM_DIVIDERS 5
struct rockchip_cpuclk_rate_table {
unsigned long prate;
struct rockchip_cpuclk_clksel divs[ROCKCHIP_CPUCLK_NUM_DIVIDERS];
@@ -333,6 +333,12 @@ struct rockchip_cpuclk_rate_table {
* @core_reg: register offset of the core settings register
* @div_core_shift:core divider offset used to divide the pll value
* @div_core_mask: core divider mask
+ * @div_core1_shift: core1 divider offset used to divide the pll value
+ * @div_core1_mask:core1 divider mask
+ * @div_core2_shift: core2 divider offset used to divide the pll value
+ * @div_core2_mask:core2 divider mask
+ * @div_core3_shift: core3 divider offset used to divide the pll value
+ * @div_core3_mask:core3 divider mask
* @mux_core_alt: mux value to select alternate parent
* @mux_core_main: mux value to select main parent of core
* @mux_core_shift:offset of the core multiplexer
@@ -342,6 +348,15 @@ struct rockchip_cpuclk_reg_data {
int core_reg;
u8 div_core_shift;
u32 div_core_mask;
+ int core1_reg;
+ u8 div_core1_shift;
+ u32 div_core1_mask;
+ int core2_reg;
+ u8 div_core2_shift;
+ u32 div_core2_mask;
+ int core3_reg;
+ u8 div_core3_shift;
+ u32 div_core3_mask;
u8 mux_core_alt;
u8 mux_core_main;
u8 mux_core_shift;
--
2.17.1
[PATCH v1 0/4] clk: rockchip: add clock controller for rk3568
Add the clock tree definition for the new rk3568 SoC Elaine Zhang (4): dt-bindings: add bindings for rk3568 clock controller clk: rockchip: add dt-binding header for rk3568 clk: rockchip: support more core div setting clk: rockchip: add clock controller for rk3568 .../bindings/clock/rockchip,rk3568-cru.txt| 66 + drivers/clk/rockchip/Kconfig |7 + drivers/clk/rockchip/Makefile |1 + drivers/clk/rockchip/clk-cpu.c| 25 + drivers/clk/rockchip/clk-rk3568.c | 1724 + drivers/clk/rockchip/clk.h| 45 +- include/dt-bindings/clock/rk3568-cru.h| 926 + 7 files changed, 2793 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.txt create mode 100644 drivers/clk/rockchip/clk-rk3568.c create mode 100644 include/dt-bindings/clock/rk3568-cru.h -- 2.17.1
[PATCH v1 1/4] dt-bindings: add bindings for rk3568 clock controller
Add devicetree bindings for Rockchip cru which found on
Rockchip SoCs.
Signed-off-by: Elaine Zhang
---
.../bindings/clock/rockchip,rk3568-cru.txt| 66 +++
1 file changed, 66 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.txt
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.txt
b/Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.txt
new file mode 100644
index ..b1119aecb7c7
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.txt
@@ -0,0 +1,66 @@
+* Rockchip RK3568 Clock and Reset Unit
+
+The RK3568 clock controller generates and supplies clock to various
+controllers within the SoC and also implements a reset controller for SoC
+peripherals.
+
+Required Properties:
+
+- compatible: PMU for CRU should be "rockchip,rk3568-pmucru"
+- compatible: CRU should be "rockchip,rk3568-cru"
+- reg: physical base address of the controller and length of memory mapped
+ region.
+- #clock-cells: should be 1.
+- #reset-cells: should be 1.
+
+Optional Properties:
+
+- rockchip,grf: phandle to the syscon managing the "general register files"
+ If missing, pll rates are not changeable, due to the missing pll lock status.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume. All available clocks are defined as
+preprocessor macros in the dt-bindings/clock/rk3568-cru.h headers and can be
+used in device tree sources. Similar macros exist for the reset sources in
+these files.
+
+External clocks:
+
+There are several clocks that are generated outside the SoC. It is expected
+that they are defined using standard clock bindings with following
+clock-output-names:
+ - "xin24m" - crystal input - required,
+ - "xin32k" - rtc clock - optional,
+ - "i2sx_mclkin" - external I2S clock - optional,
+ - "xin_osc0_usbphyx_g" - external USBPHY clock - optional,
+ - "xin_osc0_mipidsiphyx_g" - external MIPIDSIPHY clock - optional,
+
+Example: Clock controller node:
+
+ pmucru: clock-controller@fdd0 {
+ compatible = "rockchip,rK3568-pmucru";
+ reg = <0x0 0xfdd0 0x0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ cru: clock-controller@fdd2 {
+ compatible = "rockchip,rK3568-cru";
+ reg = <0x0 0xfdd2 0x0 0x1000>;
+ rockchip,grf = <>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+Example: UART controller node that consumes the clock generated by the clock
+ controller:
+
+ uart1: serial@fe65 {
+ compatible = "rockchip,rK3568-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xfe65 0x0 0x100>;
+ interrupts = ;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = < SCLK_UART1>, < PCLK_UART1>;
+ clock-names = "baudclk", "apb_pclk";
+ };
--
2.17.1
[PATCH v4 0/5] clk: rockchip: Support for some new features
1. Support for some new features 2. fix up some error Chang in V4: [PATCH v3 1/5] : Update the commit message. [PATCH v3 2/5] : Update the commit message. Chang in V3: [PATCH v2 3/6] : It's been merged So rebased and resubmit. Chang in V2: [PATCH v2 5/6] : fix up the Register error, and add delay. Elaine Zhang (5): clk: rockchip: Add supprot to limit input rate for fractional divider clk: rockchip: fix up the frac clk get rate error clk: rockchip: add a clock-type for muxes based in the pmugrf clk: rockchip: add pll up and down when change pll freq clk: rockchip: support pll setting by auto drivers/clk/rockchip/clk-pll.c| 236 -- drivers/clk/rockchip/clk-px30.c | 29 ++-- drivers/clk/rockchip/clk-rk3036.c | 13 +- drivers/clk/rockchip/clk-rk3128.c | 15 +- drivers/clk/rockchip/clk-rk3188.c | 24 +-- drivers/clk/rockchip/clk-rk3228.c | 18 ++- drivers/clk/rockchip/clk-rk3288.c | 19 ++- drivers/clk/rockchip/clk-rk3308.c | 46 +++--- drivers/clk/rockchip/clk-rk3328.c | 17 ++- drivers/clk/rockchip/clk-rk3368.c | 17 ++- drivers/clk/rockchip/clk-rk3399.c | 32 ++-- drivers/clk/rockchip/clk-rv1108.c | 14 +- drivers/clk/rockchip/clk.c| 39 - drivers/clk/rockchip/clk.h| 27 +++- include/linux/clk-provider.h | 2 + 15 files changed, 422 insertions(+), 126 deletions(-) -- 2.17.1
[PATCH v4 2/5] clk: rockchip: fix up the frac clk get rate error
support fractional divider with one level and two level parent clock
.i.e:
normal fractional divider is:
|--\
---[GPLL]---| \ |--\
---[CPLL]---|mux|--[GATE]--[DIV]---| \
---[NPLL]---| /|
|mux|--[GATE]--[UART0]
|--/ |--[GATE]--[FRACDIV]--| /
|--/
but rk3399 uart is special:
|--\
---[GPLL]---| \ |--\
---[CPLL]---|mux|--|--[GATE]--[DIV]---| \
---[NPLL]---| / ||
|mux|--[GATE]--[UART1]
|--/ ||--[GATE]--[FRACDIV]--| /
| |--/
|
| |--\
|--[GATE]--[DIV]---| \
||
|mux|--[GATE]--[UART2]
||--[GATE]--[FRACDIV]--| /
| |--/
|
| |--\
|--[GATE]--[DIV]---| \
|
|mux|--[GATE]--[UART3]
|--[GATE]--[FRACDIV]--| /
|--/
The special fractional divider, there are two levels of clock between FRACDIV
and PLL.
Signed-off-by: Elaine Zhang
---
drivers/clk/rockchip/clk.c | 19 ---
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index fac5a4a3f5c3..8f77c3f9fab7 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -190,16 +190,21 @@ static void rockchip_fractional_approximation(struct
clk_hw *hw,
if (((rate * 20 > p_rate) && (p_rate % rate != 0)) ||
(fd->max_prate && fd->max_prate < p_rate)) {
p_parent = clk_hw_get_parent(clk_hw_get_parent(hw));
- p_parent_rate = clk_hw_get_rate(p_parent);
- *parent_rate = p_parent_rate;
- if (fd->max_prate && p_parent_rate > fd->max_prate) {
- div = DIV_ROUND_UP(p_parent_rate, fd->max_prate);
- *parent_rate = p_parent_rate / div;
+ if (!p_parent) {
+ *parent_rate = p_rate;
+ } else {
+ p_parent_rate = clk_hw_get_rate(p_parent);
+ *parent_rate = p_parent_rate;
+ if (fd->max_prate && p_parent_rate > fd->max_prate) {
+ div = DIV_ROUND_UP(p_parent_rate,
+ fd->max_prate);
+ *parent_rate = p_parent_rate / div;
+ }
}
if (*parent_rate < rate * 20) {
- pr_err("%s parent_rate(%ld) is low than rate(%ld)*20,
fractional div is not allowed\n",
- clk_hw_get_name(hw), *parent_rate, rate);
+ pr_warn("%s p_rate(%ld) is low than rate(%ld)*20, use
integer or half-div\n",
+ clk_hw_get_name(hw), *parent_rate, rate);
*m = 0;
*n = 1;
return;
--
2.17.1
[PATCH v4 5/5] clk: rockchip: support pll setting by auto
If setting freq is not support in rockchip_pll_rate_table,
It can calculate and set pll params by auto.
Signed-off-by: Elaine Zhang
---
drivers/clk/rockchip/clk-pll.c | 215 ++---
1 file changed, 200 insertions(+), 15 deletions(-)
diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index 8adc6f54a605..e8ca86f5b7d1 100644
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -15,6 +15,7 @@
#include
#include
#include
+#include
#include "clk.h"
#define PLL_MODE_MASK 0x3
@@ -47,6 +48,198 @@ struct rockchip_clk_pll {
#define to_rockchip_clk_pll_nb(nb) \
container_of(nb, struct rockchip_clk_pll, clk_nb)
+#define MHZ(1000UL * 1000UL)
+#define KHZ(1000UL)
+
+/* CLK_PLL_TYPE_RK3066_AUTO type ops */
+#define PLL_FREF_MIN (269 * KHZ)
+#define PLL_FREF_MAX (2200 * MHZ)
+
+#define PLL_FVCO_MIN (440 * MHZ)
+#define PLL_FVCO_MAX (2200 * MHZ)
+
+#define PLL_FOUT_MIN (27500 * KHZ)
+#define PLL_FOUT_MAX (2200 * MHZ)
+
+#define PLL_NF_MAX (4096)
+#define PLL_NR_MAX (64)
+#define PLL_NO_MAX (16)
+
+/* CLK_PLL_TYPE_RK3036/3366/3399_AUTO type ops */
+#define MIN_FOUTVCO_FREQ (800 * MHZ)
+#define MAX_FOUTVCO_FREQ (2000 * MHZ)
+
+static struct rockchip_pll_rate_table auto_table;
+
+static struct rockchip_pll_rate_table *rk_pll_rate_table_get(void)
+{
+ return _table;
+}
+
+static int rockchip_pll_clk_set_postdiv(unsigned long fout_hz,
+ u32 *postdiv1,
+ u32 *postdiv2,
+ u32 *foutvco)
+{
+ unsigned long freq;
+
+ if (fout_hz < MIN_FOUTVCO_FREQ) {
+ for (*postdiv1 = 1; *postdiv1 <= 7; (*postdiv1)++) {
+ for (*postdiv2 = 1; *postdiv2 <= 7; (*postdiv2)++) {
+ freq = fout_hz * (*postdiv1) * (*postdiv2);
+ if (freq >= MIN_FOUTVCO_FREQ &&
+ freq <= MAX_FOUTVCO_FREQ) {
+ *foutvco = freq;
+ return 0;
+ }
+ }
+ }
+ pr_err("CANNOT FIND postdiv1/2 to make fout in range from 800M
to 2000M,fout = %lu\n",
+ fout_hz);
+ } else {
+ *postdiv1 = 1;
+ *postdiv2 = 1;
+ }
+ return 0;
+}
+
+static struct rockchip_pll_rate_table *
+rockchip_pll_clk_set_by_auto(struct rockchip_clk_pll *pll,
+unsigned long fin_hz,
+unsigned long fout_hz)
+{
+ struct rockchip_pll_rate_table *rate_table = rk_pll_rate_table_get();
+ /* FIXME set postdiv1/2 always 1*/
+ u32 foutvco = fout_hz;
+ u64 fin_64, frac_64;
+ u32 f_frac, postdiv1, postdiv2;
+ unsigned long clk_gcd = 0;
+
+ if (fin_hz == 0 || fout_hz == 0 || fout_hz == fin_hz)
+ return NULL;
+
+ rockchip_pll_clk_set_postdiv(fout_hz, , , );
+ rate_table->postdiv1 = postdiv1;
+ rate_table->postdiv2 = postdiv2;
+ rate_table->dsmpd = 1;
+
+ if (fin_hz / MHZ * MHZ == fin_hz && fout_hz / MHZ * MHZ == fout_hz) {
+ fin_hz /= MHZ;
+ foutvco /= MHZ;
+ clk_gcd = gcd(fin_hz, foutvco);
+ rate_table->refdiv = fin_hz / clk_gcd;
+ rate_table->fbdiv = foutvco / clk_gcd;
+
+ rate_table->frac = 0;
+
+ pr_debug("fin = %lu, fout = %lu, clk_gcd = %lu, refdiv = %u,
fbdiv = %u, postdiv1 = %u, postdiv2 = %u, frac = %u\n",
+fin_hz, fout_hz, clk_gcd, rate_table->refdiv,
+rate_table->fbdiv, rate_table->postdiv1,
+rate_table->postdiv2, rate_table->frac);
+ } else {
+ pr_debug("frac div running, fin_hz = %lu, fout_hz = %lu,
fin_INT_mhz = %lu, fout_INT_mhz = %lu\n",
+fin_hz, fout_hz,
+fin_hz / MHZ * MHZ,
+fout_hz / MHZ * MHZ);
+ pr_debug("frac get postdiv1 = %u, postdiv2 = %u, foutvco =
%u\n",
+rate_table->postdiv1, rate_table->postdiv2, foutvco);
+ clk_gcd = gcd(fin_hz / MHZ, foutvco / MHZ);
+ rate_table->refdiv = fin_hz / MHZ / clk_gcd;
+ rate_table->fbdiv = foutvco / MHZ / clk_gcd;
+ pr_debug("frac get refdiv = %u, fbdiv = %u\n",
+rate_table->refdiv, rate_table->fbdiv);
+
+ rate_table->frac = 0;
+
+ f_frac =
[PATCH v4 3/5] clk: rockchip: add a clock-type for muxes based in the pmugrf
Rockchip socs often have some tiny number of muxes not controlled from
the core clock controller but through bits set in the pmugrf.
Use MUXPMUGRF() to cover this special clock-type.
Signed-off-by: Elaine Zhang
---
drivers/clk/rockchip/clk.c | 9 +
drivers/clk/rockchip/clk.h | 17 +
2 files changed, 26 insertions(+)
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index 8f77c3f9fab7..4f238f2851ac 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -407,6 +407,8 @@ struct rockchip_clk_provider * __init
rockchip_clk_init(struct device_node *np,
ctx->grf = syscon_regmap_lookup_by_phandle(ctx->cru_node,
"rockchip,grf");
+ ctx->pmugrf = syscon_regmap_lookup_by_phandle(ctx->cru_node,
+ "rockchip,pmugrf");
return ctx;
@@ -482,6 +484,13 @@ void __init rockchip_clk_register_branches(
list->mux_shift, list->mux_width,
list->mux_flags);
break;
+ case branch_muxpmugrf:
+ clk = rockchip_clk_register_muxgrf(list->name,
+ list->parent_names, list->num_parents,
+ flags, ctx->pmugrf, list->muxdiv_offset,
+ list->mux_shift, list->mux_width,
+ list->mux_flags);
+ break;
case branch_divider:
if (list->div_table)
clk = clk_register_divider_table(NULL,
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index 0d401ce09a54..ae059b7744f9 100644
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -238,6 +238,7 @@ struct rockchip_clk_provider {
struct clk_onecell_data clk_data;
struct device_node *cru_node;
struct regmap *grf;
+ struct regmap *pmugrf;
spinlock_t lock;
};
@@ -390,6 +391,7 @@ enum rockchip_clk_branch_type {
branch_composite,
branch_mux,
branch_muxgrf,
+ branch_muxpmugrf,
branch_divider,
branch_fraction_divider,
branch_gate,
@@ -662,6 +664,21 @@ struct rockchip_clk_branch {
.gate_offset= -1, \
}
+#define MUXPMUGRF(_id, cname, pnames, f, o, s, w, mf) \
+ { \
+ .id = _id, \
+ .branch_type= branch_muxpmugrf, \
+ .name = cname,\
+ .parent_names = pnames, \
+ .num_parents= ARRAY_SIZE(pnames), \
+ .flags = f,\
+ .muxdiv_offset = o,\
+ .mux_shift = s,\
+ .mux_width = w,\
+ .mux_flags = mf, \
+ .gate_offset= -1, \
+ }
+
#define DIV(_id, cname, pname, f, o, s, w, df) \
{ \
.id = _id, \
--
2.17.1
[PATCH v4 4/5] clk: rockchip: add pll up and down when change pll freq
set pll sequence:
->set pll to slow mode or other plls
->set pll down
->set pll params
->set pll up
->wait pll lock status
->set pll to normal mode
To slove the system error:
wait_pll_lock: timeout waiting for pll to lock
pll_set_params: pll update unsucessful,
trying to restore old params
Signed-off-by: Elaine Zhang
---
drivers/clk/rockchip/clk-pll.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index 4c6c9167ef50..8adc6f54a605 100644
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -210,6 +210,11 @@ static int rockchip_rk3036_pll_set_params(struct
rockchip_clk_pll *pll,
rate_change_remuxed = 1;
}
+ /* set pll power down */
+ writel(HIWORD_UPDATE(RK3036_PLLCON1_PWRDOWN,
+RK3036_PLLCON1_PWRDOWN, 0),
+ pll->reg_base + RK3036_PLLCON(1));
+
/* update pll values */
writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3036_PLLCON0_FBDIV_MASK,
RK3036_PLLCON0_FBDIV_SHIFT) |
@@ -231,6 +236,11 @@ static int rockchip_rk3036_pll_set_params(struct
rockchip_clk_pll *pll,
pllcon |= rate->frac << RK3036_PLLCON2_FRAC_SHIFT;
writel_relaxed(pllcon, pll->reg_base + RK3036_PLLCON(2));
+ /* set pll power up */
+ writel(HIWORD_UPDATE(0, RK3036_PLLCON1_PWRDOWN, 0),
+ pll->reg_base + RK3036_PLLCON(1));
+ udelay(1);
+
/* wait for the pll to lock */
ret = rockchip_rk3036_pll_wait_lock(pll);
if (ret) {
@@ -692,6 +702,11 @@ static int rockchip_rk3399_pll_set_params(struct
rockchip_clk_pll *pll,
rate_change_remuxed = 1;
}
+ /* set pll power down */
+ writel(HIWORD_UPDATE(RK3399_PLLCON3_PWRDOWN,
+RK3399_PLLCON3_PWRDOWN, 0),
+ pll->reg_base + RK3399_PLLCON(3));
+
/* update pll values */
writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3399_PLLCON0_FBDIV_MASK,
RK3399_PLLCON0_FBDIV_SHIFT),
@@ -715,6 +730,12 @@ static int rockchip_rk3399_pll_set_params(struct
rockchip_clk_pll *pll,
RK3399_PLLCON3_DSMPD_SHIFT),
pll->reg_base + RK3399_PLLCON(3));
+ /* set pll power up */
+ writel(HIWORD_UPDATE(0,
+RK3399_PLLCON3_PWRDOWN, 0),
+ pll->reg_base + RK3399_PLLCON(3));
+ udelay(1);
+
/* wait for the pll to lock */
ret = rockchip_rk3399_pll_wait_lock(pll);
if (ret) {
--
2.17.1
[PATCH v4 1/5] clk: rockchip: Add supprot to limit input rate for fractional divider
>From Rockchips fractional divider usage, some clocks can be generated
by fractional divider, but the input clock frequency of fractional
divider should be less than a specified value.
.i.e:
|--\
---[GPLL]---| \ |--\
---[CPLL]---|mux|--[GATE]--[DIV]---| \
---[NPLL]---| /| |mux|--[GATE]--
|--/ |--[GATE]--[FRACDIV]--| /
|--/
The FRACDIV frequency is designed to be only 300M(Different SOC
implementations are different).But the GPLL or CPLL may be 1200M.
Must be added to limit to ensure that the design is not exceeded.
Signed-off-by: Finley Xiao
Signed-off-by: Elaine Zhang
---
drivers/clk/rockchip/clk-px30.c | 29 +--
drivers/clk/rockchip/clk-rk3036.c | 13 +
drivers/clk/rockchip/clk-rk3128.c | 15 ++
drivers/clk/rockchip/clk-rk3188.c | 24 +---
drivers/clk/rockchip/clk-rk3228.c | 18 +++-
drivers/clk/rockchip/clk-rk3288.c | 19 +++--
drivers/clk/rockchip/clk-rk3308.c | 46 +--
drivers/clk/rockchip/clk-rk3328.c | 17 +++-
drivers/clk/rockchip/clk-rk3368.c | 17 +++-
drivers/clk/rockchip/clk-rk3399.c | 32 -
drivers/clk/rockchip/clk-rv1108.c | 14 ++
drivers/clk/rockchip/clk.c| 21 --
drivers/clk/rockchip/clk.h| 10 +--
include/linux/clk-provider.h | 2 ++
14 files changed, 168 insertions(+), 109 deletions(-)
diff --git a/drivers/clk/rockchip/clk-px30.c b/drivers/clk/rockchip/clk-px30.c
index 6fb9c98b7d24..f075eb922bab 100644
--- a/drivers/clk/rockchip/clk-px30.c
+++ b/drivers/clk/rockchip/clk-px30.c
@@ -13,6 +13,7 @@
#include "clk.h"
#define PX30_GRF_SOC_STATUS0 0x480
+#define PX30_FRAC_MAX_PRATE6
enum px30_plls {
apll, dpll, cpll, npll, apll_b_h, apll_b_l,
@@ -424,7 +425,7 @@ static struct rockchip_clk_branch px30_clk_branches[]
__initdata = {
COMPOSITE_FRACMUX(0, "dclk_vopb_frac", "dclk_vopb_src",
CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(6), 0,
PX30_CLKGATE_CON(2), 3, GFLAGS,
- _dclk_vopb_fracmux),
+ _dclk_vopb_fracmux, 0),
GATE(DCLK_VOPB, "dclk_vopb", "dclk_vopb_mux", CLK_SET_RATE_PARENT,
PX30_CLKGATE_CON(2), 4, GFLAGS),
COMPOSITE(0, "dclk_vopl_src", mux_npll_cpll_p, 0,
@@ -433,7 +434,7 @@ static struct rockchip_clk_branch px30_clk_branches[]
__initdata = {
COMPOSITE_FRACMUX(0, "dclk_vopl_frac", "dclk_vopl_src",
CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(9), 0,
PX30_CLKGATE_CON(2), 7, GFLAGS,
- _dclk_vopl_fracmux),
+ _dclk_vopl_fracmux, 0),
GATE(DCLK_VOPL, "dclk_vopl", "dclk_vopl_mux", CLK_SET_RATE_PARENT,
PX30_CLKGATE_CON(2), 8, GFLAGS),
@@ -591,7 +592,7 @@ static struct rockchip_clk_branch px30_clk_branches[]
__initdata = {
COMPOSITE_FRACMUX(0, "clk_pdm_frac", "clk_pdm_src", CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(27), 0,
PX30_CLKGATE_CON(9), 10, GFLAGS,
- _pdm_fracmux),
+ _pdm_fracmux, PX30_FRAC_MAX_PRATE),
GATE(SCLK_PDM, "clk_pdm", "clk_pdm_mux", CLK_SET_RATE_PARENT,
PX30_CLKGATE_CON(9), 11, GFLAGS),
@@ -601,7 +602,7 @@ static struct rockchip_clk_branch px30_clk_branches[]
__initdata = {
COMPOSITE_FRACMUX(0, "clk_i2s0_tx_frac", "clk_i2s0_tx_src",
CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(29), 0,
PX30_CLKGATE_CON(9), 13, GFLAGS,
- _i2s0_tx_fracmux),
+ _i2s0_tx_fracmux, PX30_FRAC_MAX_PRATE),
COMPOSITE_NODIV(SCLK_I2S0_TX, "clk_i2s0_tx", mux_i2s0_tx_rx_p,
CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(28), 12, 1, MFLAGS,
PX30_CLKGATE_CON(9), 14, GFLAGS),
@@ -617,7 +618,7 @@ static struct rockchip_clk_branch px30_clk_branches[]
__initdata = {
COMPOSITE_FRACMUX(0, "clk_i2s0_rx_frac", "clk_i2s0_rx_src",
CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(59), 0,
PX30_CLKGATE_CON(17), 1, GFLAGS,
- _i2s0_rx_fracmux),
+ _i2s0_rx_fracmux, PX30_FRAC_MAX_PRATE),
COMPOSITE_NODIV(SCLK_I2S0_RX, "clk_i2s0_rx", mux_i2s0_rx_tx_p,
CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(58), 12, 1, MFLAGS,
PX30_CLKGATE_CON(17), 2, GFLAGS),
@@ -633,7 +634,7
[PATCH v4 6/6] clk: rockchip: rk3399: Support module build
support CLK_OF_DECLARE and builtin_platform_driver_probe
double clk init method.
add module author, description and license to support building
Soc Rk3399 clock driver as module.
Signed-off-by: Elaine Zhang
Reviewed-by: Kever Yang
---
drivers/clk/rockchip/clk-rk3399.c | 56 +++
1 file changed, 56 insertions(+)
diff --git a/drivers/clk/rockchip/clk-rk3399.c
b/drivers/clk/rockchip/clk-rk3399.c
index ce1d2446f142..7df2f1e00347 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -5,9 +5,11 @@
*/
#include
+#include
#include
#include
#include
+#include
#include
#include
#include
@@ -1600,3 +1602,57 @@ static void __init rk3399_pmu_clk_init(struct
device_node *np)
rockchip_clk_of_add_provider(np, ctx);
}
CLK_OF_DECLARE(rk3399_cru_pmu, "rockchip,rk3399-pmucru", rk3399_pmu_clk_init);
+
+struct clk_rk3399_inits {
+ void (*inits)(struct device_node *np);
+};
+
+static const struct clk_rk3399_inits clk_rk3399_pmucru_init = {
+ .inits = rk3399_pmu_clk_init,
+};
+
+static const struct clk_rk3399_inits clk_rk3399_cru_init = {
+ .inits = rk3399_clk_init,
+};
+
+static const struct of_device_id clk_rk3399_match_table[] = {
+ {
+ .compatible = "rockchip,rk3399-cru",
+ .data = _rk3399_cru_init,
+ }, {
+ .compatible = "rockchip,rk3399-pmucru",
+ .data = _rk3399_pmucru_init,
+ },
+ { }
+};
+MODULE_DEVICE_TABLE(of, clk_rk3399_match_table);
+
+static int __init clk_rk3399_probe(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ const struct of_device_id *match;
+ const struct clk_rk3399_inits *init_data;
+
+ match = of_match_device(clk_rk3399_match_table, >dev);
+ if (!match || !match->data)
+ return -EINVAL;
+
+ init_data = match->data;
+ if (init_data->inits)
+ init_data->inits(np);
+
+ return 0;
+}
+
+static struct platform_driver clk_rk3399_driver = {
+ .driver = {
+ .name = "clk-rk3399",
+ .of_match_table = clk_rk3399_match_table,
+ .suppress_bind_attrs = true,
+ },
+};
+builtin_platform_driver_probe(clk_rk3399_driver, clk_rk3399_probe);
+
+MODULE_DESCRIPTION("Rockchip RK3399 Clock Driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:clk-rk3399");
--
2.17.1
[PATCH v4 0/6] clk: rockchip: Support module build
Export some APIs for module drivers. Fix the clock config to support module build. Fix the clk driver init, add module author, description and license to support building RK3399 SoC clock driver as module. Change in V2: [PATCH v2 1/6]: remove "clk",and check "hw" isn't an error value. [PATCH v2 6/6]: store a function pointer in the match data. Change in V3: [PATCH v3 1/6]: fix up the compiler warning. drivers/clk/rockchip/clk.c: In function 'rockchip_clk_register_branch': >> drivers/clk/rockchip/clk.c:52:6: warning: variable 'ret' set but not >> used [-Wunused-but-set-variable] 52 | int ret; | ^~~ Change in V4: [PATCH v4 2/6]: Use EXPORT_SYMBOL_GPL instead of EXPORT_SYMBOL. [PATCH v4 3/6]: Use EXPORT_SYMBOL_GPL instead of EXPORT_SYMBOL. [PATCH v4 4/6]: Use EXPORT_SYMBOL_GPL instead of EXPORT_SYMBOL. [PATCH v4 5/6]: Mark CONFIG_CLK_xxx to "bool". [PATCH v4 6/6]: add .suppress_bind_attrs = true Elaine Zhang (6): clk: rockchip: Use clk_hw_register_composite instead of clk_register_composite calls clk: rockchip: Export rockchip_clk_register_ddrclk() clk: rockchip: Export rockchip_register_softrst() clk: rockchip: Export some clock common APIs for module drivers clk: rockchip: fix the clk config to support module build clk: rockchip: rk3399: Support module build drivers/clk/Kconfig | 1 + drivers/clk/rockchip/Kconfig| 78 drivers/clk/rockchip/Makefile | 42 - drivers/clk/rockchip/clk-ddr.c | 1 + drivers/clk/rockchip/clk-half-divider.c | 18 ++-- drivers/clk/rockchip/clk-rk3399.c | 56 drivers/clk/rockchip/clk.c | 113 +--- drivers/clk/rockchip/softrst.c | 7 +- 8 files changed, 232 insertions(+), 84 deletions(-) create mode 100644 drivers/clk/rockchip/Kconfig base-commit: b36c969764ab12faebb74711c942fa3e6eaf1e96 -- 2.17.1
[PATCH v4 5/6] clk: rockchip: fix the clk config to support module build
use CONFIG_COMMON_CLK_ROCKCHIP for Rk common clk drivers. use CONFIG_CLK_RKXX for Rk soc clk driver. Mark CONFIG_CLK_RK3399 to "tristate", to support building Rk3399 SoC clock driver as module. Signed-off-by: Elaine Zhang Reviewed-by: Kever Yang --- drivers/clk/Kconfig | 1 + drivers/clk/rockchip/Kconfig | 78 +++ drivers/clk/rockchip/Makefile | 42 ++- 3 files changed, 101 insertions(+), 20 deletions(-) create mode 100644 drivers/clk/rockchip/Kconfig diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 4026fac9fac3..b41aaed9bd51 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -373,6 +373,7 @@ source "drivers/clk/meson/Kconfig" source "drivers/clk/mvebu/Kconfig" source "drivers/clk/qcom/Kconfig" source "drivers/clk/renesas/Kconfig" +source "drivers/clk/rockchip/Kconfig" source "drivers/clk/samsung/Kconfig" source "drivers/clk/sifive/Kconfig" source "drivers/clk/sprd/Kconfig" diff --git a/drivers/clk/rockchip/Kconfig b/drivers/clk/rockchip/Kconfig new file mode 100644 index ..a1a21c99d388 --- /dev/null +++ b/drivers/clk/rockchip/Kconfig @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: GPL-2.0 +# common clock support for ROCKCHIP SoC family. + +config COMMON_CLK_ROCKCHIP + bool "Rockchip clock controller common support" + depends on ARCH_ROCKCHIP + default ARCH_ROCKCHIP + help + Say y here to enable common clock controller for Rockchip platforms. + +if COMMON_CLK_ROCKCHIP +config CLK_PX30 + bool "Rockchip Px30 clock controller support" + default y + help + Build the driver for Px30 Clock Driver. + +config CLK_RV110X + bool "Rockchip Rv110x clock controller support" + default y + help + Build the driver for Rv110x Clock Driver. + +config CLK_RK3036 + bool "Rockchip Rk3036 clock controller support" + default y + help + Build the driver for Rk3036 Clock Driver. + +config CLK_RK312X + bool "Rockchip Rk312x clock controller support" + default y + help + Build the driver for Rk312x Clock Driver. + +config CLK_RK3188 + bool "Rockchip Rk3188 clock controller support" + default y + help + Build the driver for Rk3188 Clock Driver. + +config CLK_RK322X + bool "Rockchip Rk322x clock controller support" + default y + help + Build the driver for Rk322x Clock Driver. + +config CLK_RK3288 + bool "Rockchip Rk3288 clock controller support" + depends on ARM + default y + help + Build the driver for Rk3288 Clock Driver. + +config CLK_RK3308 + bool "Rockchip Rk3308 clock controller support" + default y + help + Build the driver for Rk3308 Clock Driver. + +config CLK_RK3328 + bool "Rockchip Rk3328 clock controller support" + default y + help + Build the driver for Rk3328 Clock Driver. + +config CLK_RK3368 + bool "Rockchip Rk3368 clock controller support" + default y + help + Build the driver for Rk3368 Clock Driver. + +config CLK_RK3399 + tristate "Rockchip Rk3399 clock controller support" + default y + help + Build the driver for Rk3399 Clock Driver. +endif diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile index 7c5b5813a87c..a99e4d9bbae1 100644 --- a/drivers/clk/rockchip/Makefile +++ b/drivers/clk/rockchip/Makefile @@ -3,24 +3,26 @@ # Rockchip Clock specific Makefile # -obj-y += clk.o -obj-y += clk-pll.o -obj-y += clk-cpu.o -obj-y += clk-half-divider.o -obj-y += clk-inverter.o -obj-y += clk-mmc-phase.o -obj-y += clk-muxgrf.o -obj-y += clk-ddr.o -obj-$(CONFIG_RESET_CONTROLLER) += softrst.o +obj-$(CONFIG_COMMON_CLK_ROCKCHIP) += clk-rockchip.o -obj-y += clk-px30.o -obj-y += clk-rv1108.o -obj-y += clk-rk3036.o -obj-y += clk-rk3128.o -obj-y += clk-rk3188.o -obj-y += clk-rk3228.o -obj-y += clk-rk3288.o -obj-y += clk-rk3308.o -obj-y += clk-rk3328.o -obj-y += clk-rk3368.o -obj-y += clk-rk3399.o +clk-rockchip-y += clk.o +clk-rockchip-y += clk-pll.o +clk-rockchip-y += clk-cpu.o +clk-rockchip-y += clk-half-divider.o +clk-rockchip-y += clk-inverter.o +clk-rockchip-y += clk-mmc-phase.o +clk-rockchip-y += clk-muxgrf.o +clk-rockchip-y += clk-ddr.o +clk-rockchip-$(CONFIG_RESET_CONTROLLER) += softrst.o + +obj-$(CONFIG_CLK_PX30) += clk-px30.o +obj-$(CONFIG_CLK_RV110X)+= clk-rv1108.o +obj-$(CONFIG_CLK_RK3036)+= clk-rk3036.o +obj-$(CONFIG_CLK_RK312X)+= clk-rk3128.o +obj-$(CONFIG_CLK_RK3188)+= clk-rk3188.o +obj-$(CONFIG_CLK_RK322X)+= clk-rk3228.o +obj-$(CONFIG_CLK_RK3288)+= clk-rk3288.o +obj-$(CONFIG_CLK_RK3308)+= clk-rk3308.o +obj-$(CONFIG_CLK_RK3328)+= clk-rk3328.o +obj-$(CONFIG_CLK_RK3368)+= clk-rk3368.o +obj-$(CONFIG_CLK_RK3399)+= clk-rk3399.o -- 2.17.1
[PATCH v4 2/6] clk: rockchip: Export rockchip_clk_register_ddrclk()
This is used by the Rockchip clk driver, export it to allow that driver to be compiled as a module.. Signed-off-by: Elaine Zhang Reviewed-by: Kever Yang --- drivers/clk/rockchip/clk-ddr.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/rockchip/clk-ddr.c b/drivers/clk/rockchip/clk-ddr.c index 9273bce4d7b6..86718c54e56b 100644 --- a/drivers/clk/rockchip/clk-ddr.c +++ b/drivers/clk/rockchip/clk-ddr.c @@ -136,3 +136,4 @@ struct clk *rockchip_clk_register_ddrclk(const char *name, int flags, return clk; } +EXPORT_SYMBOL_GPL(rockchip_clk_register_ddrclk); -- 2.17.1
[PATCH v4 1/6] clk: rockchip: Use clk_hw_register_composite instead of clk_register_composite calls
clk_hw_register_composite it's already exported.
Preparation for compilation of rK common clock drivers into modules.
Signed-off-by: Elaine Zhang
Reported-by: kernel test robot
Reviewed-by: Kever Yang
Reviewed-by: Heiko Stuebner
---
drivers/clk/rockchip/clk-half-divider.c | 18
drivers/clk/rockchip/clk.c | 61 -
2 files changed, 40 insertions(+), 39 deletions(-)
diff --git a/drivers/clk/rockchip/clk-half-divider.c
b/drivers/clk/rockchip/clk-half-divider.c
index b333fc28c94b..e97fd3dfbae7 100644
--- a/drivers/clk/rockchip/clk-half-divider.c
+++ b/drivers/clk/rockchip/clk-half-divider.c
@@ -166,7 +166,7 @@ struct clk *rockchip_clk_register_halfdiv(const char *name,
unsigned long flags,
spinlock_t *lock)
{
- struct clk *clk;
+ struct clk_hw *hw;
struct clk_mux *mux = NULL;
struct clk_gate *gate = NULL;
struct clk_divider *div = NULL;
@@ -212,16 +212,18 @@ struct clk *rockchip_clk_register_halfdiv(const char
*name,
div_ops = _half_divider_ops;
}
- clk = clk_register_composite(NULL, name, parent_names, num_parents,
-mux ? >hw : NULL, mux_ops,
-div ? >hw : NULL, div_ops,
-gate ? >hw : NULL, gate_ops,
-flags);
+ hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
+ mux ? >hw : NULL, mux_ops,
+ div ? >hw : NULL, div_ops,
+ gate ? >hw : NULL, gate_ops,
+ flags);
+ if (IS_ERR(hw))
+ goto err_div;
- return clk;
+ return hw->clk;
err_div:
kfree(gate);
err_gate:
kfree(mux);
- return ERR_PTR(-ENOMEM);
+ return ERR_CAST(hw);
}
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index 546e810c3560..46409972983e 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -43,7 +43,7 @@ static struct clk *rockchip_clk_register_branch(const char
*name,
u8 gate_shift, u8 gate_flags, unsigned long flags,
spinlock_t *lock)
{
- struct clk *clk;
+ struct clk_hw *hw;
struct clk_mux *mux = NULL;
struct clk_gate *gate = NULL;
struct clk_divider *div = NULL;
@@ -100,20 +100,18 @@ static struct clk *rockchip_clk_register_branch(const
char *name,
: _divider_ops;
}
- clk = clk_register_composite(NULL, name, parent_names, num_parents,
-mux ? >hw : NULL, mux_ops,
-div ? >hw : NULL, div_ops,
-gate ? >hw : NULL, gate_ops,
-flags);
-
- if (IS_ERR(clk)) {
- ret = PTR_ERR(clk);
- goto err_composite;
+ hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
+ mux ? >hw : NULL, mux_ops,
+ div ? >hw : NULL, div_ops,
+ gate ? >hw : NULL, gate_ops,
+ flags);
+ if (IS_ERR(hw)) {
+ kfree(div);
+ kfree(gate);
+ return ERR_CAST(hw);
}
- return clk;
-err_composite:
- kfree(div);
+ return hw->clk;
err_div:
kfree(gate);
err_gate:
@@ -214,8 +212,8 @@ static struct clk *rockchip_clk_register_frac_branch(
unsigned long flags, struct rockchip_clk_branch *child,
spinlock_t *lock)
{
+ struct clk_hw *hw;
struct rockchip_clk_frac *frac;
- struct clk *clk;
struct clk_gate *gate = NULL;
struct clk_fractional_divider *div = NULL;
const struct clk_ops *div_ops = NULL, *gate_ops = NULL;
@@ -255,14 +253,14 @@ static struct clk *rockchip_clk_register_frac_branch(
div->approximation = rockchip_fractional_approximation;
div_ops = _fractional_divider_ops;
- clk = clk_register_composite(NULL, name, parent_names, num_parents,
-NULL, NULL,
->hw, div_ops,
-gate ? >hw : NULL, gate_ops,
-flags | CLK_SET_RATE_UNGATE);
- if (IS_ERR(clk)) {
+ hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
+ NULL, NULL,
+ >hw, div_ops,
+ gate ? >hw : NULL, gate_ops,
+
[PATCH v4 4/6] clk: rockchip: Export some clock common APIs for module drivers
This is used by the Rockchip clk driver, export it to allow that
driver to be compiled as a module.
Signed-off-by: Elaine Zhang
Reviewed-by: Kever Yang
---
drivers/clk/rockchip/clk.c | 52 ++
1 file changed, 30 insertions(+), 22 deletions(-)
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index 46409972983e..b443169dd408 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -360,8 +360,9 @@ static struct clk
*rockchip_clk_register_factor_branch(const char *name,
return hw->clk;
}
-struct rockchip_clk_provider * __init rockchip_clk_init(struct device_node *np,
- void __iomem *base, unsigned long nr_clks)
+struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np,
+ void __iomem *base,
+ unsigned long nr_clks)
{
struct rockchip_clk_provider *ctx;
struct clk **clk_table;
@@ -393,14 +394,16 @@ struct rockchip_clk_provider * __init
rockchip_clk_init(struct device_node *np,
kfree(ctx);
return ERR_PTR(-ENOMEM);
}
+EXPORT_SYMBOL_GPL(rockchip_clk_init);
-void __init rockchip_clk_of_add_provider(struct device_node *np,
- struct rockchip_clk_provider *ctx)
+void rockchip_clk_of_add_provider(struct device_node *np,
+ struct rockchip_clk_provider *ctx)
{
if (of_clk_add_provider(np, of_clk_src_onecell_get,
>clk_data))
pr_err("%s: could not register clk provider\n", __func__);
}
+EXPORT_SYMBOL_GPL(rockchip_clk_of_add_provider);
void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx,
struct clk *clk, unsigned int id)
@@ -408,8 +411,9 @@ void rockchip_clk_add_lookup(struct rockchip_clk_provider
*ctx,
if (ctx->clk_data.clks && id)
ctx->clk_data.clks[id] = clk;
}
+EXPORT_SYMBOL_GPL(rockchip_clk_add_lookup);
-void __init rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
+void rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
struct rockchip_pll_clock *list,
unsigned int nr_pll, int grf_lock_offset)
{
@@ -432,11 +436,11 @@ void __init rockchip_clk_register_plls(struct
rockchip_clk_provider *ctx,
rockchip_clk_add_lookup(ctx, clk, list->id);
}
}
+EXPORT_SYMBOL_GPL(rockchip_clk_register_plls);
-void __init rockchip_clk_register_branches(
- struct rockchip_clk_provider *ctx,
- struct rockchip_clk_branch *list,
- unsigned int nr_clk)
+void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
+ struct rockchip_clk_branch *list,
+ unsigned int nr_clk)
{
struct clk *clk = NULL;
unsigned int idx;
@@ -565,14 +569,15 @@ void __init rockchip_clk_register_branches(
rockchip_clk_add_lookup(ctx, clk, list->id);
}
}
-
-void __init rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
- unsigned int lookup_id,
- const char *name, const char *const *parent_names,
- u8 num_parents,
- const struct rockchip_cpuclk_reg_data *reg_data,
- const struct rockchip_cpuclk_rate_table *rates,
- int nrates)
+EXPORT_SYMBOL_GPL(rockchip_clk_register_branches);
+
+void rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
+ unsigned int lookup_id,
+ const char *name, const char *const
*parent_names,
+ u8 num_parents,
+ const struct rockchip_cpuclk_reg_data
*reg_data,
+ const struct rockchip_cpuclk_rate_table
*rates,
+ int nrates)
{
struct clk *clk;
@@ -587,9 +592,10 @@ void __init rockchip_clk_register_armclk(struct
rockchip_clk_provider *ctx,
rockchip_clk_add_lookup(ctx, clk, lookup_id);
}
+EXPORT_SYMBOL_GPL(rockchip_clk_register_armclk);
-void __init rockchip_clk_protect_critical(const char *const clocks[],
- int nclocks)
+void rockchip_clk_protect_critical(const char *const clocks[],
+ int nclocks)
{
int i;
@@ -601,6 +607,7 @@ void __init rockchip_clk_protect_critical(const char *const
clocks[],
clk_prepare_enable(clk);
}
}
+EXPORT_SYMBOL_GPL(rockchip_clk_protect_critical);
static void __iomem *rst_base;
static unsigned int reg_restart;
@@ -620,10 +62
[PATCH v4 3/6] clk: rockchip: Export rockchip_register_softrst()
This is used by the Rockchip clk driver, export it to allow that
driver to be compiled as a module..
Signed-off-by: Elaine Zhang
Reviewed-by: Kever Yang
---
drivers/clk/rockchip/softrst.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/rockchip/softrst.c b/drivers/clk/rockchip/softrst.c
index 5f1ff5e47c4f..5d07266745b8 100644
--- a/drivers/clk/rockchip/softrst.c
+++ b/drivers/clk/rockchip/softrst.c
@@ -77,9 +77,9 @@ static const struct reset_control_ops rockchip_softrst_ops = {
.deassert = rockchip_softrst_deassert,
};
-void __init rockchip_register_softrst(struct device_node *np,
- unsigned int num_regs,
- void __iomem *base, u8 flags)
+void rockchip_register_softrst(struct device_node *np,
+ unsigned int num_regs,
+ void __iomem *base, u8 flags)
{
struct rockchip_softrst *softrst;
int ret;
@@ -107,3 +107,4 @@ void __init rockchip_register_softrst(struct device_node
*np,
kfree(softrst);
}
};
+EXPORT_SYMBOL_GPL(rockchip_register_softrst);
--
2.17.1
[PATCH v3 6/6] clk: rockchip: rk3399: Support module build
support CLK_OF_DECLARE and builtin_platform_driver_probe
double clk init method.
add module author, description and license to support building
Soc Rk3399 clock driver as module.
Signed-off-by: Elaine Zhang
Reviewed-by: Kever Yang
---
drivers/clk/rockchip/clk-rk3399.c | 55 +++
1 file changed, 55 insertions(+)
diff --git a/drivers/clk/rockchip/clk-rk3399.c
b/drivers/clk/rockchip/clk-rk3399.c
index ce1d2446f142..40ff17aee5b6 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -5,9 +5,11 @@
*/
#include
+#include
#include
#include
#include
+#include
#include
#include
#include
@@ -1600,3 +1602,56 @@ static void __init rk3399_pmu_clk_init(struct
device_node *np)
rockchip_clk_of_add_provider(np, ctx);
}
CLK_OF_DECLARE(rk3399_cru_pmu, "rockchip,rk3399-pmucru", rk3399_pmu_clk_init);
+
+struct clk_rk3399_inits {
+ void (*inits)(struct device_node *np);
+};
+
+static const struct clk_rk3399_inits clk_rk3399_pmucru_init = {
+ .inits = rk3399_pmu_clk_init,
+};
+
+static const struct clk_rk3399_inits clk_rk3399_cru_init = {
+ .inits = rk3399_clk_init,
+};
+
+static const struct of_device_id clk_rk3399_match_table[] = {
+ {
+ .compatible = "rockchip,rk3399-cru",
+ .data = _rk3399_cru_init,
+ }, {
+ .compatible = "rockchip,rk3399-pmucru",
+ .data = _rk3399_pmucru_init,
+ },
+ { }
+};
+MODULE_DEVICE_TABLE(of, clk_rk3399_match_table);
+
+static int __init clk_rk3399_probe(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ const struct of_device_id *match;
+ const struct clk_rk3399_inits *init_data;
+
+ match = of_match_device(clk_rk3399_match_table, >dev);
+ if (!match || !match->data)
+ return -EINVAL;
+
+ init_data = match->data;
+ if (init_data->inits)
+ init_data->inits(np);
+
+ return 0;
+}
+
+static struct platform_driver clk_rk3399_driver = {
+ .driver = {
+ .name = "clk-rk3399",
+ .of_match_table = clk_rk3399_match_table,
+ },
+};
+builtin_platform_driver_probe(clk_rk3399_driver, clk_rk3399_probe);
+
+MODULE_DESCRIPTION("Rockchip RK3399 Clock Driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:clk-rk3399");
--
2.17.1
[PATCH v3 1/6] clk: rockchip: Use clk_hw_register_composite instead of clk_register_composite calls
clk_hw_register_composite it's already exported.
Preparation for compilation of rK common clock drivers into modules.
Signed-off-by: Elaine Zhang
Reported-by: kernel test robot
Reviewed-by: Kever Yang
---
drivers/clk/rockchip/clk-half-divider.c | 18
drivers/clk/rockchip/clk.c | 61 -
2 files changed, 40 insertions(+), 39 deletions(-)
diff --git a/drivers/clk/rockchip/clk-half-divider.c
b/drivers/clk/rockchip/clk-half-divider.c
index b333fc28c94b..e97fd3dfbae7 100644
--- a/drivers/clk/rockchip/clk-half-divider.c
+++ b/drivers/clk/rockchip/clk-half-divider.c
@@ -166,7 +166,7 @@ struct clk *rockchip_clk_register_halfdiv(const char *name,
unsigned long flags,
spinlock_t *lock)
{
- struct clk *clk;
+ struct clk_hw *hw;
struct clk_mux *mux = NULL;
struct clk_gate *gate = NULL;
struct clk_divider *div = NULL;
@@ -212,16 +212,18 @@ struct clk *rockchip_clk_register_halfdiv(const char
*name,
div_ops = _half_divider_ops;
}
- clk = clk_register_composite(NULL, name, parent_names, num_parents,
-mux ? >hw : NULL, mux_ops,
-div ? >hw : NULL, div_ops,
-gate ? >hw : NULL, gate_ops,
-flags);
+ hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
+ mux ? >hw : NULL, mux_ops,
+ div ? >hw : NULL, div_ops,
+ gate ? >hw : NULL, gate_ops,
+ flags);
+ if (IS_ERR(hw))
+ goto err_div;
- return clk;
+ return hw->clk;
err_div:
kfree(gate);
err_gate:
kfree(mux);
- return ERR_PTR(-ENOMEM);
+ return ERR_CAST(hw);
}
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index 546e810c3560..46409972983e 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -43,7 +43,7 @@ static struct clk *rockchip_clk_register_branch(const char
*name,
u8 gate_shift, u8 gate_flags, unsigned long flags,
spinlock_t *lock)
{
- struct clk *clk;
+ struct clk_hw *hw;
struct clk_mux *mux = NULL;
struct clk_gate *gate = NULL;
struct clk_divider *div = NULL;
@@ -100,20 +100,18 @@ static struct clk *rockchip_clk_register_branch(const
char *name,
: _divider_ops;
}
- clk = clk_register_composite(NULL, name, parent_names, num_parents,
-mux ? >hw : NULL, mux_ops,
-div ? >hw : NULL, div_ops,
-gate ? >hw : NULL, gate_ops,
-flags);
-
- if (IS_ERR(clk)) {
- ret = PTR_ERR(clk);
- goto err_composite;
+ hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
+ mux ? >hw : NULL, mux_ops,
+ div ? >hw : NULL, div_ops,
+ gate ? >hw : NULL, gate_ops,
+ flags);
+ if (IS_ERR(hw)) {
+ kfree(div);
+ kfree(gate);
+ return ERR_CAST(hw);
}
- return clk;
-err_composite:
- kfree(div);
+ return hw->clk;
err_div:
kfree(gate);
err_gate:
@@ -214,8 +212,8 @@ static struct clk *rockchip_clk_register_frac_branch(
unsigned long flags, struct rockchip_clk_branch *child,
spinlock_t *lock)
{
+ struct clk_hw *hw;
struct rockchip_clk_frac *frac;
- struct clk *clk;
struct clk_gate *gate = NULL;
struct clk_fractional_divider *div = NULL;
const struct clk_ops *div_ops = NULL, *gate_ops = NULL;
@@ -255,14 +253,14 @@ static struct clk *rockchip_clk_register_frac_branch(
div->approximation = rockchip_fractional_approximation;
div_ops = _fractional_divider_ops;
- clk = clk_register_composite(NULL, name, parent_names, num_parents,
-NULL, NULL,
->hw, div_ops,
-gate ? >hw : NULL, gate_ops,
-flags | CLK_SET_RATE_UNGATE);
- if (IS_ERR(clk)) {
+ hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
+ NULL, NULL,
+ >hw, div_ops,
+ gate ? >hw : NULL, gate_ops,
+
[PATCH v3 4/6] clk: rockchip: Export some clock common APIs for module drivers
This is used by the Rockchip clk driver, export it to allow that
driver to be compiled as a module.
Signed-off-by: Elaine Zhang
Reviewed-by: Kever Yang
---
drivers/clk/rockchip/clk.c | 52 ++
1 file changed, 30 insertions(+), 22 deletions(-)
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index 46409972983e..fd3aff2a599d 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -360,8 +360,9 @@ static struct clk
*rockchip_clk_register_factor_branch(const char *name,
return hw->clk;
}
-struct rockchip_clk_provider * __init rockchip_clk_init(struct device_node *np,
- void __iomem *base, unsigned long nr_clks)
+struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np,
+ void __iomem *base,
+ unsigned long nr_clks)
{
struct rockchip_clk_provider *ctx;
struct clk **clk_table;
@@ -393,14 +394,16 @@ struct rockchip_clk_provider * __init
rockchip_clk_init(struct device_node *np,
kfree(ctx);
return ERR_PTR(-ENOMEM);
}
+EXPORT_SYMBOL(rockchip_clk_init);
-void __init rockchip_clk_of_add_provider(struct device_node *np,
- struct rockchip_clk_provider *ctx)
+void rockchip_clk_of_add_provider(struct device_node *np,
+ struct rockchip_clk_provider *ctx)
{
if (of_clk_add_provider(np, of_clk_src_onecell_get,
>clk_data))
pr_err("%s: could not register clk provider\n", __func__);
}
+EXPORT_SYMBOL(rockchip_clk_of_add_provider);
void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx,
struct clk *clk, unsigned int id)
@@ -408,8 +411,9 @@ void rockchip_clk_add_lookup(struct rockchip_clk_provider
*ctx,
if (ctx->clk_data.clks && id)
ctx->clk_data.clks[id] = clk;
}
+EXPORT_SYMBOL(rockchip_clk_add_lookup);
-void __init rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
+void rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
struct rockchip_pll_clock *list,
unsigned int nr_pll, int grf_lock_offset)
{
@@ -432,11 +436,11 @@ void __init rockchip_clk_register_plls(struct
rockchip_clk_provider *ctx,
rockchip_clk_add_lookup(ctx, clk, list->id);
}
}
+EXPORT_SYMBOL(rockchip_clk_register_plls);
-void __init rockchip_clk_register_branches(
- struct rockchip_clk_provider *ctx,
- struct rockchip_clk_branch *list,
- unsigned int nr_clk)
+void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
+ struct rockchip_clk_branch *list,
+ unsigned int nr_clk)
{
struct clk *clk = NULL;
unsigned int idx;
@@ -565,14 +569,15 @@ void __init rockchip_clk_register_branches(
rockchip_clk_add_lookup(ctx, clk, list->id);
}
}
-
-void __init rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
- unsigned int lookup_id,
- const char *name, const char *const *parent_names,
- u8 num_parents,
- const struct rockchip_cpuclk_reg_data *reg_data,
- const struct rockchip_cpuclk_rate_table *rates,
- int nrates)
+EXPORT_SYMBOL(rockchip_clk_register_branches);
+
+void rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
+ unsigned int lookup_id,
+ const char *name, const char *const
*parent_names,
+ u8 num_parents,
+ const struct rockchip_cpuclk_reg_data
*reg_data,
+ const struct rockchip_cpuclk_rate_table
*rates,
+ int nrates)
{
struct clk *clk;
@@ -587,9 +592,10 @@ void __init rockchip_clk_register_armclk(struct
rockchip_clk_provider *ctx,
rockchip_clk_add_lookup(ctx, clk, lookup_id);
}
+EXPORT_SYMBOL(rockchip_clk_register_armclk);
-void __init rockchip_clk_protect_critical(const char *const clocks[],
- int nclocks)
+void rockchip_clk_protect_critical(const char *const clocks[],
+ int nclocks)
{
int i;
@@ -601,6 +607,7 @@ void __init rockchip_clk_protect_critical(const char *const
clocks[],
clk_prepare_enable(clk);
}
}
+EXPORT_SYMBOL(rockchip_clk_protect_critical);
static void __iomem *rst_base;
static unsigned int reg_restart;
@@ -620,10 +627,10 @@ static struct not
[PATCH v3 5/6] clk: rockchip: fix the clk config to support module build
use CONFIG_COMMON_CLK_ROCKCHIP for Rk common clk drivers. use CONFIG_CLK_RKXX for Rk soc clk driver. Mark configuration to "tristate", to support building Rk SoCs clock driver as module. Signed-off-by: Elaine Zhang Reviewed-by: Kever Yang --- drivers/clk/Kconfig | 1 + drivers/clk/rockchip/Kconfig | 78 +++ drivers/clk/rockchip/Makefile | 42 ++- 3 files changed, 101 insertions(+), 20 deletions(-) create mode 100644 drivers/clk/rockchip/Kconfig diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 4026fac9fac3..b41aaed9bd51 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -373,6 +373,7 @@ source "drivers/clk/meson/Kconfig" source "drivers/clk/mvebu/Kconfig" source "drivers/clk/qcom/Kconfig" source "drivers/clk/renesas/Kconfig" +source "drivers/clk/rockchip/Kconfig" source "drivers/clk/samsung/Kconfig" source "drivers/clk/sifive/Kconfig" source "drivers/clk/sprd/Kconfig" diff --git a/drivers/clk/rockchip/Kconfig b/drivers/clk/rockchip/Kconfig new file mode 100644 index ..53a44396bc35 --- /dev/null +++ b/drivers/clk/rockchip/Kconfig @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: GPL-2.0 +# common clock support for ROCKCHIP SoC family. + +config COMMON_CLK_ROCKCHIP + tristate "Rockchip clock controller common support" + depends on ARCH_ROCKCHIP + default ARCH_ROCKCHIP + help + Say y here to enable common clock controller. + +if COMMON_CLK_ROCKCHIP +config CLK_PX30 + tristate "Rockchip Px30 clock controller support" + default y + help + Build the driver for Px30 Clock Driver. + +config CLK_RV110X + tristate "Rockchip Rv110x clock controller support" + default y + help + Build the driver for Rv110x Clock Driver. + +config CLK_RK3036 + tristate "Rockchip Rk3036 clock controller support" + default y + help + Build the driver for Rk3036 Clock Driver. + +config CLK_RK312X + tristate "Rockchip Rk312x clock controller support" + default y + help + Build the driver for Rk312x Clock Driver. + +config CLK_RK3188 + tristate "Rockchip Rk3188 clock controller support" + default y + help + Build the driver for Rk3188 Clock Driver. + +config CLK_RK322X + tristate "Rockchip Rk322x clock controller support" + default y + help + Build the driver for Rk322x Clock Driver. + +config CLK_RK3288 + tristate "Rockchip Rk3288 clock controller support" + depends on ARM + default y + help + Build the driver for Rk3288 Clock Driver. + +config CLK_RK3308 + tristate "Rockchip Rk3308 clock controller support" + default y + help + Build the driver for Rk3308 Clock Driver. + +config CLK_RK3328 + tristate "Rockchip Rk3328 clock controller support" + default y + help + Build the driver for Rk3328 Clock Driver. + +config CLK_RK3368 + tristate "Rockchip Rk3368 clock controller support" + default y + help + Build the driver for Rk3368 Clock Driver. + +config CLK_RK3399 + tristate "Rockchip Rk3399 clock controller support" + default y + help + Build the driver for Rk3399 Clock Driver. +endif diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile index 7c5b5813a87c..a99e4d9bbae1 100644 --- a/drivers/clk/rockchip/Makefile +++ b/drivers/clk/rockchip/Makefile @@ -3,24 +3,26 @@ # Rockchip Clock specific Makefile # -obj-y += clk.o -obj-y += clk-pll.o -obj-y += clk-cpu.o -obj-y += clk-half-divider.o -obj-y += clk-inverter.o -obj-y += clk-mmc-phase.o -obj-y += clk-muxgrf.o -obj-y += clk-ddr.o -obj-$(CONFIG_RESET_CONTROLLER) += softrst.o +obj-$(CONFIG_COMMON_CLK_ROCKCHIP) += clk-rockchip.o -obj-y += clk-px30.o -obj-y += clk-rv1108.o -obj-y += clk-rk3036.o -obj-y += clk-rk3128.o -obj-y += clk-rk3188.o -obj-y += clk-rk3228.o -obj-y += clk-rk3288.o -obj-y += clk-rk3308.o -obj-y += clk-rk3328.o -obj-y += clk-rk3368.o -obj-y += clk-rk3399.o +clk-rockchip-y += clk.o +clk-rockchip-y += clk-pll.o +clk-rockchip-y += clk-cpu.o +clk-rockchip-y += clk-half-divider.o +clk-rockchip-y += clk-inverter.o +clk-rockchip-y += clk-mmc-phase.o +clk-rockchip-y += clk-muxgrf.o +clk-rockchip-y += clk-ddr.o +clk-rockchip-$(CONFIG_RESET_CONTROLLER) += softrst.o + +obj-$(CONFIG_CLK_PX30) += clk-px30.o +obj-$(CONFIG_CLK_RV110X)+= clk-rv1108.o +obj-$(CONFIG_CLK_RK3036)+= clk-rk3036.o +obj-$(CONFIG_CLK_RK312X)+= clk-rk3128.o +obj-$(CONFIG_CLK_RK3188)+= clk-rk3188.o +obj-$(CONFIG_CLK_RK322X)+= clk-rk3228.o +obj-$(CONFIG_CLK_RK3288)+= clk-rk3288.o +obj-$(CONFIG_CLK_RK3308)+= clk-rk3308.o +obj-$(CONFIG_CLK_RK3328)+= clk-rk3328.o +obj-$(CONFIG_CLK_RK3368)+= clk-rk3368.o +obj-$(CONFIG_CLK_RK3399)+= clk-rk3399.o -- 2.17.1
[PATCH v3 3/6] clk: rockchip: Export rockchip_register_softrst()
This is used by the Rockchip clk driver, export it to allow that
driver to be compiled as a module..
Signed-off-by: Elaine Zhang
Reviewed-by: Kever Yang
---
drivers/clk/rockchip/softrst.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/rockchip/softrst.c b/drivers/clk/rockchip/softrst.c
index 5f1ff5e47c4f..caba9055090b 100644
--- a/drivers/clk/rockchip/softrst.c
+++ b/drivers/clk/rockchip/softrst.c
@@ -77,9 +77,9 @@ static const struct reset_control_ops rockchip_softrst_ops = {
.deassert = rockchip_softrst_deassert,
};
-void __init rockchip_register_softrst(struct device_node *np,
- unsigned int num_regs,
- void __iomem *base, u8 flags)
+void rockchip_register_softrst(struct device_node *np,
+ unsigned int num_regs,
+ void __iomem *base, u8 flags)
{
struct rockchip_softrst *softrst;
int ret;
@@ -107,3 +107,4 @@ void __init rockchip_register_softrst(struct device_node
*np,
kfree(softrst);
}
};
+EXPORT_SYMBOL(rockchip_register_softrst);
--
2.17.1
[PATCH v3 2/6] clk: rockchip: Export rockchip_clk_register_ddrclk()
This is used by the Rockchip clk driver, export it to allow that driver to be compiled as a module.. Signed-off-by: Elaine Zhang Reviewed-by: Kever Yang --- drivers/clk/rockchip/clk-ddr.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/rockchip/clk-ddr.c b/drivers/clk/rockchip/clk-ddr.c index 9273bce4d7b6..282b6f22eb22 100644 --- a/drivers/clk/rockchip/clk-ddr.c +++ b/drivers/clk/rockchip/clk-ddr.c @@ -136,3 +136,4 @@ struct clk *rockchip_clk_register_ddrclk(const char *name, int flags, return clk; } +EXPORT_SYMBOL(rockchip_clk_register_ddrclk); -- 2.17.1
[PATCH v3 0/6] clk: rockchip: Support module build
Export some APIs for module drivers. Fix the clock config to support module build. Fix the clk driver init, add module author, description and license to support building RK3399 SoC clock driver as module. Change in V2: [PATCH v2 1/6]: remove "clk",and check "hw" isn't an error value. [PATCH v2 6/6]: store a function pointer in the match data. Change in V3: [PATCH v3 1/6]: fix up the compiler warning. drivers/clk/rockchip/clk.c: In function 'rockchip_clk_register_branch': >> drivers/clk/rockchip/clk.c:52:6: warning: variable 'ret' set but not >> used [-Wunused-but-set-variable] 52 | int ret; | ^~~ Elaine Zhang (6): clk: rockchip: Use clk_hw_register_composite instead of clk_register_composite calls clk: rockchip: Export rockchip_clk_register_ddrclk() clk: rockchip: Export rockchip_register_softrst() clk: rockchip: Export some clock common APIs for module drivers clk: rockchip: fix the clk config to support module build clk: rockchip: rk3399: Support module build drivers/clk/Kconfig | 1 + drivers/clk/rockchip/Kconfig| 78 drivers/clk/rockchip/Makefile | 42 - drivers/clk/rockchip/clk-ddr.c | 1 + drivers/clk/rockchip/clk-half-divider.c | 18 ++-- drivers/clk/rockchip/clk-rk3399.c | 55 drivers/clk/rockchip/clk.c | 113 +--- drivers/clk/rockchip/softrst.c | 7 +- 8 files changed, 231 insertions(+), 84 deletions(-) create mode 100644 drivers/clk/rockchip/Kconfig base-commit: b36c969764ab12faebb74711c942fa3e6eaf1e96 -- 2.17.1
[PATCH v2 3/6] clk: rockchip: Export rockchip_register_softrst()
This is used by the Rockchip clk driver, export it to allow that
driver to be compiled as a module..
Signed-off-by: Elaine Zhang
---
drivers/clk/rockchip/softrst.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/rockchip/softrst.c b/drivers/clk/rockchip/softrst.c
index 5f1ff5e47c4f..caba9055090b 100644
--- a/drivers/clk/rockchip/softrst.c
+++ b/drivers/clk/rockchip/softrst.c
@@ -77,9 +77,9 @@ static const struct reset_control_ops rockchip_softrst_ops = {
.deassert = rockchip_softrst_deassert,
};
-void __init rockchip_register_softrst(struct device_node *np,
- unsigned int num_regs,
- void __iomem *base, u8 flags)
+void rockchip_register_softrst(struct device_node *np,
+ unsigned int num_regs,
+ void __iomem *base, u8 flags)
{
struct rockchip_softrst *softrst;
int ret;
@@ -107,3 +107,4 @@ void __init rockchip_register_softrst(struct device_node
*np,
kfree(softrst);
}
};
+EXPORT_SYMBOL(rockchip_register_softrst);
--
2.17.1
[PATCH v2 4/6] clk: rockchip: Export some clock common APIs for module drivers
This is used by the Rockchip clk driver, export it to allow that
driver to be compiled as a module.
Signed-off-by: Elaine Zhang
---
drivers/clk/rockchip/clk.c | 52 ++
1 file changed, 30 insertions(+), 22 deletions(-)
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index b51f320e5733..b7664224e64a 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -359,8 +359,9 @@ static struct clk
*rockchip_clk_register_factor_branch(const char *name,
return hw->clk;
}
-struct rockchip_clk_provider * __init rockchip_clk_init(struct device_node *np,
- void __iomem *base, unsigned long nr_clks)
+struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np,
+ void __iomem *base,
+ unsigned long nr_clks)
{
struct rockchip_clk_provider *ctx;
struct clk **clk_table;
@@ -392,14 +393,16 @@ struct rockchip_clk_provider * __init
rockchip_clk_init(struct device_node *np,
kfree(ctx);
return ERR_PTR(-ENOMEM);
}
+EXPORT_SYMBOL(rockchip_clk_init);
-void __init rockchip_clk_of_add_provider(struct device_node *np,
- struct rockchip_clk_provider *ctx)
+void rockchip_clk_of_add_provider(struct device_node *np,
+ struct rockchip_clk_provider *ctx)
{
if (of_clk_add_provider(np, of_clk_src_onecell_get,
>clk_data))
pr_err("%s: could not register clk provider\n", __func__);
}
+EXPORT_SYMBOL(rockchip_clk_of_add_provider);
void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx,
struct clk *clk, unsigned int id)
@@ -407,8 +410,9 @@ void rockchip_clk_add_lookup(struct rockchip_clk_provider
*ctx,
if (ctx->clk_data.clks && id)
ctx->clk_data.clks[id] = clk;
}
+EXPORT_SYMBOL(rockchip_clk_add_lookup);
-void __init rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
+void rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
struct rockchip_pll_clock *list,
unsigned int nr_pll, int grf_lock_offset)
{
@@ -431,11 +435,11 @@ void __init rockchip_clk_register_plls(struct
rockchip_clk_provider *ctx,
rockchip_clk_add_lookup(ctx, clk, list->id);
}
}
+EXPORT_SYMBOL(rockchip_clk_register_plls);
-void __init rockchip_clk_register_branches(
- struct rockchip_clk_provider *ctx,
- struct rockchip_clk_branch *list,
- unsigned int nr_clk)
+void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
+ struct rockchip_clk_branch *list,
+ unsigned int nr_clk)
{
struct clk *clk = NULL;
unsigned int idx;
@@ -564,14 +568,15 @@ void __init rockchip_clk_register_branches(
rockchip_clk_add_lookup(ctx, clk, list->id);
}
}
-
-void __init rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
- unsigned int lookup_id,
- const char *name, const char *const *parent_names,
- u8 num_parents,
- const struct rockchip_cpuclk_reg_data *reg_data,
- const struct rockchip_cpuclk_rate_table *rates,
- int nrates)
+EXPORT_SYMBOL(rockchip_clk_register_branches);
+
+void rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
+ unsigned int lookup_id,
+ const char *name, const char *const
*parent_names,
+ u8 num_parents,
+ const struct rockchip_cpuclk_reg_data
*reg_data,
+ const struct rockchip_cpuclk_rate_table
*rates,
+ int nrates)
{
struct clk *clk;
@@ -586,9 +591,10 @@ void __init rockchip_clk_register_armclk(struct
rockchip_clk_provider *ctx,
rockchip_clk_add_lookup(ctx, clk, lookup_id);
}
+EXPORT_SYMBOL(rockchip_clk_register_armclk);
-void __init rockchip_clk_protect_critical(const char *const clocks[],
- int nclocks)
+void rockchip_clk_protect_critical(const char *const clocks[],
+ int nclocks)
{
int i;
@@ -600,6 +606,7 @@ void __init rockchip_clk_protect_critical(const char *const
clocks[],
clk_prepare_enable(clk);
}
}
+EXPORT_SYMBOL(rockchip_clk_protect_critical);
static void __iomem *rst_base;
static unsigned int reg_restart;
@@ -619,10 +626,10 @@ static struct notifier_block rockchip_restart
[PATCH v2 1/6] clk: rockchip: Use clk_hw_register_composite instead of clk_register_composite calls
clk_hw_register_composite it's already exported.
Preparation for compilation of rK common clock drivers into modules.
Signed-off-by: Elaine Zhang
---
drivers/clk/rockchip/clk-half-divider.c | 18
drivers/clk/rockchip/clk.c | 58 -
2 files changed, 38 insertions(+), 38 deletions(-)
diff --git a/drivers/clk/rockchip/clk-half-divider.c
b/drivers/clk/rockchip/clk-half-divider.c
index b333fc28c94b..e97fd3dfbae7 100644
--- a/drivers/clk/rockchip/clk-half-divider.c
+++ b/drivers/clk/rockchip/clk-half-divider.c
@@ -166,7 +166,7 @@ struct clk *rockchip_clk_register_halfdiv(const char *name,
unsigned long flags,
spinlock_t *lock)
{
- struct clk *clk;
+ struct clk_hw *hw;
struct clk_mux *mux = NULL;
struct clk_gate *gate = NULL;
struct clk_divider *div = NULL;
@@ -212,16 +212,18 @@ struct clk *rockchip_clk_register_halfdiv(const char
*name,
div_ops = _half_divider_ops;
}
- clk = clk_register_composite(NULL, name, parent_names, num_parents,
-mux ? >hw : NULL, mux_ops,
-div ? >hw : NULL, div_ops,
-gate ? >hw : NULL, gate_ops,
-flags);
+ hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
+ mux ? >hw : NULL, mux_ops,
+ div ? >hw : NULL, div_ops,
+ gate ? >hw : NULL, gate_ops,
+ flags);
+ if (IS_ERR(hw))
+ goto err_div;
- return clk;
+ return hw->clk;
err_div:
kfree(gate);
err_gate:
kfree(mux);
- return ERR_PTR(-ENOMEM);
+ return ERR_CAST(hw);
}
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index 546e810c3560..b51f320e5733 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -43,7 +43,7 @@ static struct clk *rockchip_clk_register_branch(const char
*name,
u8 gate_shift, u8 gate_flags, unsigned long flags,
spinlock_t *lock)
{
- struct clk *clk;
+ struct clk_hw *hw;
struct clk_mux *mux = NULL;
struct clk_gate *gate = NULL;
struct clk_divider *div = NULL;
@@ -100,25 +100,22 @@ static struct clk *rockchip_clk_register_branch(const
char *name,
: _divider_ops;
}
- clk = clk_register_composite(NULL, name, parent_names, num_parents,
-mux ? >hw : NULL, mux_ops,
-div ? >hw : NULL, div_ops,
-gate ? >hw : NULL, gate_ops,
-flags);
-
- if (IS_ERR(clk)) {
- ret = PTR_ERR(clk);
+ hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
+ mux ? >hw : NULL, mux_ops,
+ div ? >hw : NULL, div_ops,
+ gate ? >hw : NULL, gate_ops,
+ flags);
+ if (IS_ERR(hw))
goto err_composite;
- }
- return clk;
+ return hw->clk;
err_composite:
kfree(div);
err_div:
kfree(gate);
err_gate:
kfree(mux);
- return ERR_PTR(ret);
+ return ERR_CAST(hw);
}
struct rockchip_clk_frac {
@@ -214,8 +211,8 @@ static struct clk *rockchip_clk_register_frac_branch(
unsigned long flags, struct rockchip_clk_branch *child,
spinlock_t *lock)
{
+ struct clk_hw *hw;
struct rockchip_clk_frac *frac;
- struct clk *clk;
struct clk_gate *gate = NULL;
struct clk_fractional_divider *div = NULL;
const struct clk_ops *div_ops = NULL, *gate_ops = NULL;
@@ -255,14 +252,14 @@ static struct clk *rockchip_clk_register_frac_branch(
div->approximation = rockchip_fractional_approximation;
div_ops = _fractional_divider_ops;
- clk = clk_register_composite(NULL, name, parent_names, num_parents,
-NULL, NULL,
->hw, div_ops,
-gate ? >hw : NULL, gate_ops,
-flags | CLK_SET_RATE_UNGATE);
- if (IS_ERR(clk)) {
+ hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
+ NULL, NULL,
+ >hw, div_ops,
+ gate ? >hw : NULL, gate_ops,
+ flags | CLK_SET_RATE_UNGATE);
+ if (IS_ERR(hw))
[PATCH v2 6/6] clk: rockchip: rk3399: Support module build
support CLK_OF_DECLARE and builtin_platform_driver_probe
double clk init method.
add module author, description and license to support building
Soc Rk3399 clock driver as module.
Signed-off-by: Elaine Zhang
---
drivers/clk/rockchip/clk-rk3399.c | 55 +++
1 file changed, 55 insertions(+)
diff --git a/drivers/clk/rockchip/clk-rk3399.c
b/drivers/clk/rockchip/clk-rk3399.c
index ce1d2446f142..40ff17aee5b6 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -5,9 +5,11 @@
*/
#include
+#include
#include
#include
#include
+#include
#include
#include
#include
@@ -1600,3 +1602,56 @@ static void __init rk3399_pmu_clk_init(struct
device_node *np)
rockchip_clk_of_add_provider(np, ctx);
}
CLK_OF_DECLARE(rk3399_cru_pmu, "rockchip,rk3399-pmucru", rk3399_pmu_clk_init);
+
+struct clk_rk3399_inits {
+ void (*inits)(struct device_node *np);
+};
+
+static const struct clk_rk3399_inits clk_rk3399_pmucru_init = {
+ .inits = rk3399_pmu_clk_init,
+};
+
+static const struct clk_rk3399_inits clk_rk3399_cru_init = {
+ .inits = rk3399_clk_init,
+};
+
+static const struct of_device_id clk_rk3399_match_table[] = {
+ {
+ .compatible = "rockchip,rk3399-cru",
+ .data = _rk3399_cru_init,
+ }, {
+ .compatible = "rockchip,rk3399-pmucru",
+ .data = _rk3399_pmucru_init,
+ },
+ { }
+};
+MODULE_DEVICE_TABLE(of, clk_rk3399_match_table);
+
+static int __init clk_rk3399_probe(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ const struct of_device_id *match;
+ const struct clk_rk3399_inits *init_data;
+
+ match = of_match_device(clk_rk3399_match_table, >dev);
+ if (!match || !match->data)
+ return -EINVAL;
+
+ init_data = match->data;
+ if (init_data->inits)
+ init_data->inits(np);
+
+ return 0;
+}
+
+static struct platform_driver clk_rk3399_driver = {
+ .driver = {
+ .name = "clk-rk3399",
+ .of_match_table = clk_rk3399_match_table,
+ },
+};
+builtin_platform_driver_probe(clk_rk3399_driver, clk_rk3399_probe);
+
+MODULE_DESCRIPTION("Rockchip RK3399 Clock Driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:clk-rk3399");
--
2.17.1
[PATCH v2 2/6] clk: rockchip: Export rockchip_clk_register_ddrclk()
This is used by the Rockchip clk driver, export it to allow that driver to be compiled as a module.. Signed-off-by: Elaine Zhang --- drivers/clk/rockchip/clk-ddr.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/rockchip/clk-ddr.c b/drivers/clk/rockchip/clk-ddr.c index 9273bce4d7b6..282b6f22eb22 100644 --- a/drivers/clk/rockchip/clk-ddr.c +++ b/drivers/clk/rockchip/clk-ddr.c @@ -136,3 +136,4 @@ struct clk *rockchip_clk_register_ddrclk(const char *name, int flags, return clk; } +EXPORT_SYMBOL(rockchip_clk_register_ddrclk); -- 2.17.1
[PATCH v2 0/6] clk: rockchip: Support module build
Export some APIs for module drivers. Fix the clock config to support module build. Fix the clk driver init, add module author, description and license to support building RK3399 SoC clock driver as module. Change in V2: [PATCH v2 1/6]: remove "clk",and check "hw" isn't an error value. [PATCH v2 6/6]: store a function pointer in the match data. Elaine Zhang (6): clk: rockchip: Use clk_hw_register_composite instead of clk_register_composite calls clk: rockchip: Export rockchip_clk_register_ddrclk() clk: rockchip: Export rockchip_register_softrst() clk: rockchip: Export some clock common APIs for module drivers clk: rockchip: fix the clk config to support module build clk: rockchip: rk3399: Support module build drivers/clk/Kconfig | 1 + drivers/clk/rockchip/Kconfig| 78 + drivers/clk/rockchip/Makefile | 42 - drivers/clk/rockchip/clk-ddr.c | 1 + drivers/clk/rockchip/clk-half-divider.c | 18 ++-- drivers/clk/rockchip/clk-rk3399.c | 55 drivers/clk/rockchip/clk.c | 110 +--- drivers/clk/rockchip/softrst.c | 7 +- 8 files changed, 229 insertions(+), 83 deletions(-) create mode 100644 drivers/clk/rockchip/Kconfig -- 2.17.1
[PATCH v2 5/6] clk: rockchip: fix the clk config to support module build
use CONFIG_COMMON_CLK_ROCKCHIP for Rk common clk drivers. use CONFIG_CLK_RKXX for Rk soc clk driver. Mark configuration to "tristate", to support building Rk SoCs clock driver as module. Signed-off-by: Elaine Zhang --- drivers/clk/Kconfig | 1 + drivers/clk/rockchip/Kconfig | 78 +++ drivers/clk/rockchip/Makefile | 42 ++- 3 files changed, 101 insertions(+), 20 deletions(-) create mode 100644 drivers/clk/rockchip/Kconfig diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 4026fac9fac3..b41aaed9bd51 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -373,6 +373,7 @@ source "drivers/clk/meson/Kconfig" source "drivers/clk/mvebu/Kconfig" source "drivers/clk/qcom/Kconfig" source "drivers/clk/renesas/Kconfig" +source "drivers/clk/rockchip/Kconfig" source "drivers/clk/samsung/Kconfig" source "drivers/clk/sifive/Kconfig" source "drivers/clk/sprd/Kconfig" diff --git a/drivers/clk/rockchip/Kconfig b/drivers/clk/rockchip/Kconfig new file mode 100644 index ..53a44396bc35 --- /dev/null +++ b/drivers/clk/rockchip/Kconfig @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: GPL-2.0 +# common clock support for ROCKCHIP SoC family. + +config COMMON_CLK_ROCKCHIP + tristate "Rockchip clock controller common support" + depends on ARCH_ROCKCHIP + default ARCH_ROCKCHIP + help + Say y here to enable common clock controller. + +if COMMON_CLK_ROCKCHIP +config CLK_PX30 + tristate "Rockchip Px30 clock controller support" + default y + help + Build the driver for Px30 Clock Driver. + +config CLK_RV110X + tristate "Rockchip Rv110x clock controller support" + default y + help + Build the driver for Rv110x Clock Driver. + +config CLK_RK3036 + tristate "Rockchip Rk3036 clock controller support" + default y + help + Build the driver for Rk3036 Clock Driver. + +config CLK_RK312X + tristate "Rockchip Rk312x clock controller support" + default y + help + Build the driver for Rk312x Clock Driver. + +config CLK_RK3188 + tristate "Rockchip Rk3188 clock controller support" + default y + help + Build the driver for Rk3188 Clock Driver. + +config CLK_RK322X + tristate "Rockchip Rk322x clock controller support" + default y + help + Build the driver for Rk322x Clock Driver. + +config CLK_RK3288 + tristate "Rockchip Rk3288 clock controller support" + depends on ARM + default y + help + Build the driver for Rk3288 Clock Driver. + +config CLK_RK3308 + tristate "Rockchip Rk3308 clock controller support" + default y + help + Build the driver for Rk3308 Clock Driver. + +config CLK_RK3328 + tristate "Rockchip Rk3328 clock controller support" + default y + help + Build the driver for Rk3328 Clock Driver. + +config CLK_RK3368 + tristate "Rockchip Rk3368 clock controller support" + default y + help + Build the driver for Rk3368 Clock Driver. + +config CLK_RK3399 + tristate "Rockchip Rk3399 clock controller support" + default y + help + Build the driver for Rk3399 Clock Driver. +endif diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile index 7c5b5813a87c..a99e4d9bbae1 100644 --- a/drivers/clk/rockchip/Makefile +++ b/drivers/clk/rockchip/Makefile @@ -3,24 +3,26 @@ # Rockchip Clock specific Makefile # -obj-y += clk.o -obj-y += clk-pll.o -obj-y += clk-cpu.o -obj-y += clk-half-divider.o -obj-y += clk-inverter.o -obj-y += clk-mmc-phase.o -obj-y += clk-muxgrf.o -obj-y += clk-ddr.o -obj-$(CONFIG_RESET_CONTROLLER) += softrst.o +obj-$(CONFIG_COMMON_CLK_ROCKCHIP) += clk-rockchip.o -obj-y += clk-px30.o -obj-y += clk-rv1108.o -obj-y += clk-rk3036.o -obj-y += clk-rk3128.o -obj-y += clk-rk3188.o -obj-y += clk-rk3228.o -obj-y += clk-rk3288.o -obj-y += clk-rk3308.o -obj-y += clk-rk3328.o -obj-y += clk-rk3368.o -obj-y += clk-rk3399.o +clk-rockchip-y += clk.o +clk-rockchip-y += clk-pll.o +clk-rockchip-y += clk-cpu.o +clk-rockchip-y += clk-half-divider.o +clk-rockchip-y += clk-inverter.o +clk-rockchip-y += clk-mmc-phase.o +clk-rockchip-y += clk-muxgrf.o +clk-rockchip-y += clk-ddr.o +clk-rockchip-$(CONFIG_RESET_CONTROLLER) += softrst.o + +obj-$(CONFIG_CLK_PX30) += clk-px30.o +obj-$(CONFIG_CLK_RV110X)+= clk-rv1108.o +obj-$(CONFIG_CLK_RK3036)+= clk-rk3036.o +obj-$(CONFIG_CLK_RK312X)+= clk-rk3128.o +obj-$(CONFIG_CLK_RK3188)+= clk-rk3188.o +obj-$(CONFIG_CLK_RK322X)+= clk-rk3228.o +obj-$(CONFIG_CLK_RK3288)+= clk-rk3288.o +obj-$(CONFIG_CLK_RK3308)+= clk-rk3308.o +obj-$(CONFIG_CLK_RK3328)+= clk-rk3328.o +obj-$(CONFIG_CLK_RK3368)+= clk-rk3368.o +obj-$(CONFIG_CLK_RK3399)+= clk-rk3399.o -- 2.17.1
[PATCH v1 0/6] clk: rockchip: Support module build
Export some APIs for module drivers. Fix the clock config to support module build. Fix the clk driver init, add module author, description and license to support building RK3399 SoC clock driver as module. Elaine Zhang (6): clk: rockchip: Use clk_hw_register_composite instead of clk_register_composite calls clk: rockchip: Export rockchip_clk_register_ddrclk() clk: rockchip: Export rockchip_register_softrst() clk: rockchip: Export some clock common APIs for module drivers clk: rockchip: fix the clk config to support module build clk: rockchip: rk3399: Support module build drivers/clk/Kconfig | 1 + drivers/clk/rockchip/Kconfig| 78 ++ drivers/clk/rockchip/Makefile | 42 ++-- drivers/clk/rockchip/clk-ddr.c | 1 + drivers/clk/rockchip/clk-half-divider.c | 12 ++-- drivers/clk/rockchip/clk-rk3399.c | 40 drivers/clk/rockchip/clk.c | 87 ++--- drivers/clk/rockchip/softrst.c | 7 +- 8 files changed, 203 insertions(+), 65 deletions(-) create mode 100644 drivers/clk/rockchip/Kconfig -- 2.17.1
[PATCH v1 5/6] clk: rockchip: fix the clk config to support module build
use CONFIG_COMMON_CLK_ROCKCHIP for Rk common clk drivers. use CONFIG_CLK_RKXX for Rk soc clk driver. Mark configuration to "tristate", to support building Rk SoCs clock driver as module. Signed-off-by: Elaine Zhang --- drivers/clk/Kconfig | 1 + drivers/clk/rockchip/Kconfig | 78 +++ drivers/clk/rockchip/Makefile | 42 ++- 3 files changed, 101 insertions(+), 20 deletions(-) create mode 100644 drivers/clk/rockchip/Kconfig diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 4026fac9fac3..b41aaed9bd51 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -373,6 +373,7 @@ source "drivers/clk/meson/Kconfig" source "drivers/clk/mvebu/Kconfig" source "drivers/clk/qcom/Kconfig" source "drivers/clk/renesas/Kconfig" +source "drivers/clk/rockchip/Kconfig" source "drivers/clk/samsung/Kconfig" source "drivers/clk/sifive/Kconfig" source "drivers/clk/sprd/Kconfig" diff --git a/drivers/clk/rockchip/Kconfig b/drivers/clk/rockchip/Kconfig new file mode 100644 index ..53a44396bc35 --- /dev/null +++ b/drivers/clk/rockchip/Kconfig @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: GPL-2.0 +# common clock support for ROCKCHIP SoC family. + +config COMMON_CLK_ROCKCHIP + tristate "Rockchip clock controller common support" + depends on ARCH_ROCKCHIP + default ARCH_ROCKCHIP + help + Say y here to enable common clock controller. + +if COMMON_CLK_ROCKCHIP +config CLK_PX30 + tristate "Rockchip Px30 clock controller support" + default y + help + Build the driver for Px30 Clock Driver. + +config CLK_RV110X + tristate "Rockchip Rv110x clock controller support" + default y + help + Build the driver for Rv110x Clock Driver. + +config CLK_RK3036 + tristate "Rockchip Rk3036 clock controller support" + default y + help + Build the driver for Rk3036 Clock Driver. + +config CLK_RK312X + tristate "Rockchip Rk312x clock controller support" + default y + help + Build the driver for Rk312x Clock Driver. + +config CLK_RK3188 + tristate "Rockchip Rk3188 clock controller support" + default y + help + Build the driver for Rk3188 Clock Driver. + +config CLK_RK322X + tristate "Rockchip Rk322x clock controller support" + default y + help + Build the driver for Rk322x Clock Driver. + +config CLK_RK3288 + tristate "Rockchip Rk3288 clock controller support" + depends on ARM + default y + help + Build the driver for Rk3288 Clock Driver. + +config CLK_RK3308 + tristate "Rockchip Rk3308 clock controller support" + default y + help + Build the driver for Rk3308 Clock Driver. + +config CLK_RK3328 + tristate "Rockchip Rk3328 clock controller support" + default y + help + Build the driver for Rk3328 Clock Driver. + +config CLK_RK3368 + tristate "Rockchip Rk3368 clock controller support" + default y + help + Build the driver for Rk3368 Clock Driver. + +config CLK_RK3399 + tristate "Rockchip Rk3399 clock controller support" + default y + help + Build the driver for Rk3399 Clock Driver. +endif diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile index 7c5b5813a87c..a99e4d9bbae1 100644 --- a/drivers/clk/rockchip/Makefile +++ b/drivers/clk/rockchip/Makefile @@ -3,24 +3,26 @@ # Rockchip Clock specific Makefile # -obj-y += clk.o -obj-y += clk-pll.o -obj-y += clk-cpu.o -obj-y += clk-half-divider.o -obj-y += clk-inverter.o -obj-y += clk-mmc-phase.o -obj-y += clk-muxgrf.o -obj-y += clk-ddr.o -obj-$(CONFIG_RESET_CONTROLLER) += softrst.o +obj-$(CONFIG_COMMON_CLK_ROCKCHIP) += clk-rockchip.o -obj-y += clk-px30.o -obj-y += clk-rv1108.o -obj-y += clk-rk3036.o -obj-y += clk-rk3128.o -obj-y += clk-rk3188.o -obj-y += clk-rk3228.o -obj-y += clk-rk3288.o -obj-y += clk-rk3308.o -obj-y += clk-rk3328.o -obj-y += clk-rk3368.o -obj-y += clk-rk3399.o +clk-rockchip-y += clk.o +clk-rockchip-y += clk-pll.o +clk-rockchip-y += clk-cpu.o +clk-rockchip-y += clk-half-divider.o +clk-rockchip-y += clk-inverter.o +clk-rockchip-y += clk-mmc-phase.o +clk-rockchip-y += clk-muxgrf.o +clk-rockchip-y += clk-ddr.o +clk-rockchip-$(CONFIG_RESET_CONTROLLER) += softrst.o + +obj-$(CONFIG_CLK_PX30) += clk-px30.o +obj-$(CONFIG_CLK_RV110X)+= clk-rv1108.o +obj-$(CONFIG_CLK_RK3036)+= clk-rk3036.o +obj-$(CONFIG_CLK_RK312X)+= clk-rk3128.o +obj-$(CONFIG_CLK_RK3188)+= clk-rk3188.o +obj-$(CONFIG_CLK_RK322X)+= clk-rk3228.o +obj-$(CONFIG_CLK_RK3288)+= clk-rk3288.o +obj-$(CONFIG_CLK_RK3308)+= clk-rk3308.o +obj-$(CONFIG_CLK_RK3328)+= clk-rk3328.o +obj-$(CONFIG_CLK_RK3368)+= clk-rk3368.o +obj-$(CONFIG_CLK_RK3399)+= clk-rk3399.o -- 2.17.1
[PATCH v1 6/6] clk: rockchip: rk3399: Support module build
support CLK_OF_DECLARE and builtin_platform_driver_probe
double clk init method.
add module author, description and license to support building
Soc Rk3399 clock driver as module.
Signed-off-by: Elaine Zhang
---
drivers/clk/rockchip/clk-rk3399.c | 40 +++
1 file changed, 40 insertions(+)
diff --git a/drivers/clk/rockchip/clk-rk3399.c
b/drivers/clk/rockchip/clk-rk3399.c
index ce1d2446f142..a1d5704b9ba2 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -5,9 +5,11 @@
*/
#include
+#include
#include
#include
#include
+#include
#include
#include
#include
@@ -1600,3 +1602,41 @@ static void __init rk3399_pmu_clk_init(struct
device_node *np)
rockchip_clk_of_add_provider(np, ctx);
}
CLK_OF_DECLARE(rk3399_cru_pmu, "rockchip,rk3399-pmucru", rk3399_pmu_clk_init);
+
+static int __init clk_rk3399_probe(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ unsigned long data;
+
+ data = (unsigned long)of_device_get_match_data(>dev);
+ if (data)
+ rk3399_pmu_clk_init(np);
+ else
+ rk3399_clk_init(np);
+
+ return 0;
+}
+
+static const struct of_device_id clk_rk3399_match_table[] = {
+ {
+ .compatible = "rockchip,rk3399-cru",
+ .data = (void *)0
+ }, {
+ .compatible = "rockchip,rk3399-pmucru",
+ .data = (void *)1,
+ },
+ { }
+};
+MODULE_DEVICE_TABLE(of, clk_rk3399_match_table);
+
+static struct platform_driver clk_rk3399_driver = {
+ .driver = {
+ .name = "clk-rk3399",
+ .of_match_table = clk_rk3399_match_table,
+ },
+};
+builtin_platform_driver_probe(clk_rk3399_driver, clk_rk3399_probe);
+
+MODULE_DESCRIPTION("Rockchip RK3399 Clock Driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:clk-rk3399");
--
2.17.1
[PATCH v1 2/6] clk: rockchip: Export rockchip_clk_register_ddrclk()
This is used by the Rockchip clk driver, export it to allow that driver to be compiled as a module.. Signed-off-by: Elaine Zhang --- drivers/clk/rockchip/clk-ddr.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/rockchip/clk-ddr.c b/drivers/clk/rockchip/clk-ddr.c index 9273bce4d7b6..282b6f22eb22 100644 --- a/drivers/clk/rockchip/clk-ddr.c +++ b/drivers/clk/rockchip/clk-ddr.c @@ -136,3 +136,4 @@ struct clk *rockchip_clk_register_ddrclk(const char *name, int flags, return clk; } +EXPORT_SYMBOL(rockchip_clk_register_ddrclk); -- 2.17.1
[PATCH v1 3/6] clk: rockchip: Export rockchip_register_softrst()
This is used by the Rockchip clk driver, export it to allow that
driver to be compiled as a module..
Signed-off-by: Elaine Zhang
---
drivers/clk/rockchip/softrst.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/rockchip/softrst.c b/drivers/clk/rockchip/softrst.c
index 5f1ff5e47c4f..caba9055090b 100644
--- a/drivers/clk/rockchip/softrst.c
+++ b/drivers/clk/rockchip/softrst.c
@@ -77,9 +77,9 @@ static const struct reset_control_ops rockchip_softrst_ops = {
.deassert = rockchip_softrst_deassert,
};
-void __init rockchip_register_softrst(struct device_node *np,
- unsigned int num_regs,
- void __iomem *base, u8 flags)
+void rockchip_register_softrst(struct device_node *np,
+ unsigned int num_regs,
+ void __iomem *base, u8 flags)
{
struct rockchip_softrst *softrst;
int ret;
@@ -107,3 +107,4 @@ void __init rockchip_register_softrst(struct device_node
*np,
kfree(softrst);
}
};
+EXPORT_SYMBOL(rockchip_register_softrst);
--
2.17.1
[PATCH v1 1/6] clk: rockchip: Use clk_hw_register_composite instead of clk_register_composite calls
clk_hw_register_composite it's already exported.
Preparation for compilation of rK common clock drivers into modules.
Signed-off-by: Elaine Zhang
---
drivers/clk/rockchip/clk-half-divider.c | 12 +
drivers/clk/rockchip/clk.c | 35 ++---
2 files changed, 27 insertions(+), 20 deletions(-)
diff --git a/drivers/clk/rockchip/clk-half-divider.c
b/drivers/clk/rockchip/clk-half-divider.c
index b333fc28c94b..35db0651ea1d 100644
--- a/drivers/clk/rockchip/clk-half-divider.c
+++ b/drivers/clk/rockchip/clk-half-divider.c
@@ -166,6 +166,7 @@ struct clk *rockchip_clk_register_halfdiv(const char *name,
unsigned long flags,
spinlock_t *lock)
{
+ struct clk_hw *hw;
struct clk *clk;
struct clk_mux *mux = NULL;
struct clk_gate *gate = NULL;
@@ -212,12 +213,13 @@ struct clk *rockchip_clk_register_halfdiv(const char
*name,
div_ops = _half_divider_ops;
}
- clk = clk_register_composite(NULL, name, parent_names, num_parents,
-mux ? >hw : NULL, mux_ops,
-div ? >hw : NULL, div_ops,
-gate ? >hw : NULL, gate_ops,
-flags);
+ hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
+ mux ? >hw : NULL, mux_ops,
+ div ? >hw : NULL, div_ops,
+ gate ? >hw : NULL, gate_ops,
+ flags);
+ clk = hw->clk;
return clk;
err_div:
kfree(gate);
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index 546e810c3560..2cfebfb61814 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -43,6 +43,7 @@ static struct clk *rockchip_clk_register_branch(const char
*name,
u8 gate_shift, u8 gate_flags, unsigned long flags,
spinlock_t *lock)
{
+ struct clk_hw *hw;
struct clk *clk;
struct clk_mux *mux = NULL;
struct clk_gate *gate = NULL;
@@ -100,12 +101,12 @@ static struct clk *rockchip_clk_register_branch(const
char *name,
: _divider_ops;
}
- clk = clk_register_composite(NULL, name, parent_names, num_parents,
-mux ? >hw : NULL, mux_ops,
-div ? >hw : NULL, div_ops,
-gate ? >hw : NULL, gate_ops,
-flags);
-
+ hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
+ mux ? >hw : NULL, mux_ops,
+ div ? >hw : NULL, div_ops,
+ gate ? >hw : NULL, gate_ops,
+ flags);
+ clk = hw->clk;
if (IS_ERR(clk)) {
ret = PTR_ERR(clk);
goto err_composite;
@@ -214,6 +215,7 @@ static struct clk *rockchip_clk_register_frac_branch(
unsigned long flags, struct rockchip_clk_branch *child,
spinlock_t *lock)
{
+ struct clk_hw *hw;
struct rockchip_clk_frac *frac;
struct clk *clk;
struct clk_gate *gate = NULL;
@@ -255,11 +257,12 @@ static struct clk *rockchip_clk_register_frac_branch(
div->approximation = rockchip_fractional_approximation;
div_ops = _fractional_divider_ops;
- clk = clk_register_composite(NULL, name, parent_names, num_parents,
-NULL, NULL,
->hw, div_ops,
-gate ? >hw : NULL, gate_ops,
-flags | CLK_SET_RATE_UNGATE);
+ hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
+ NULL, NULL,
+ >hw, div_ops,
+ gate ? >hw : NULL, gate_ops,
+ flags | CLK_SET_RATE_UNGATE);
+ clk = hw->clk;
if (IS_ERR(clk)) {
kfree(frac);
return clk;
@@ -320,6 +323,7 @@ static struct clk
*rockchip_clk_register_factor_branch(const char *name,
int gate_offset, u8 gate_shift, u8 gate_flags,
unsigned long flags, spinlock_t *lock)
{
+ struct clk_hw *hw;
struct clk *clk;
struct clk_gate *gate = NULL;
struct clk_fixed_factor *fix = NULL;
@@ -349,10 +353,11 @@ static struct clk
*rockchip_clk_register_factor_branch(const char *name,
fix->mult = mult;
fix->div = div;
-
