Re: [PATCH v3 1/2] dt-bindings: PCI: intel: Add YAML schemas for the PCIe RC controller
On Fri, Sep 06, 2019 at 08:48:15PM +0300, Andy Shevchenko wrote: > On Fri, Sep 06, 2019 at 07:17:11PM +0200, Martin Blumenstingl wrote: > > On Fri, Sep 6, 2019 at 5:22 AM Chuan Hua, Lei > > wrote: > > > > type_index = fwspec->param[1]; // index. > > > if (type_index >= ARRAY_SIZE(of_ioapic_type)) > > > return -EINVAL; > > > > > > I would not see this definition is user-friendly. But it is how x86 > > > handles at the moment. > > thank you for explaining this - I had no idea x86 is different from > > all other platforms I know > > the only upstream x86 .dts I could find > > (arch/x86/platform/ce4100/falconfalls.dts) also uses the magic x86 > > numbers > > so I'm fine with this until someone else knows a better solution > > Ivan, Cc'ed, had done few amendments to x86 DT support. Perhaps he may add > something to the discussion. I just fixed broken interrupt support in x86-specific DT implementation. In CE4100, PCI devices are directly connected to I/O APIC input lines. Conventional PCI devices other than bridges don't need to be described in Device Tree or if they use standard PCI routing. Mapping INTA .. INTD pins to inputs of the bridge's interrupt parent depends on device number on the bus. In Device Tree, this mapping is described by "interrupt-map-mask" and "interrupt-map" properties of the bridge device node. Possible interrupt types described by Open Firmware Recomended Practice: 0 - Rising Edge 1 - Level triggered, active low
[tip:x86/platform] x86/devicetree: Use CPU description from Device Tree
Commit-ID: 4e07db9c8db87e3b71be4c3cd626ddc9bacd5a1e
Gitweb: https://git.kernel.org/tip/4e07db9c8db87e3b71be4c3cd626ddc9bacd5a1e
Author: Ivan Gorinov <ivan.gori...@intel.com>
AuthorDate: Thu, 22 Mar 2018 14:35:47 -0700
Committer: Thomas Gleixner <t...@linutronix.de>
CommitDate: Mon, 26 Mar 2018 15:13:32 +0200
x86/devicetree: Use CPU description from Device Tree
Current x86 Device Tree implementation does not support multiprocessing.
Use new DT bindings to describe the processors.
Signed-off-by: Ivan Gorinov <ivan.gori...@intel.com>
Signed-off-by: Thomas Gleixner <t...@linutronix.de>
Reviewed-by: Andy Shevchenko <andy.shevche...@gmail.com>
Cc: Mark Rutland <mark.rutl...@arm.com>
Cc: Rob Herring <robh...@kernel.org>
Cc: Frank Rowand <frowand.l...@gmail.com>
Link:
https://lkml.kernel.org/r/c291fb2cef51b730b59916d7745be0eaa4378c6c.1521753738.git.ivan.gori...@intel.com
---
arch/x86/kernel/devicetree.c | 45
1 file changed, 33 insertions(+), 12 deletions(-)
diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c
index 5cd387fcc777..c9d2b19749b8 100644
--- a/arch/x86/kernel/devicetree.c
+++ b/arch/x86/kernel/devicetree.c
@@ -131,34 +131,52 @@ static void __init dtb_setup_hpet(void)
#endif
}
+#ifdef CONFIG_X86_LOCAL_APIC
+
+static void __init dtb_cpu_setup(void)
+{
+ struct device_node *dn;
+ u32 apic_id, version;
+ int ret;
+
+ version = GET_APIC_VERSION(apic_read(APIC_LVR));
+ for_each_node_by_type(dn, "cpu") {
+ ret = of_property_read_u32(dn, "reg", _id);
+ if (ret < 0) {
+ pr_warn("%pOF: missing local APIC ID\n", dn);
+ continue;
+ }
+ generic_processor_info(apic_id, version);
+ }
+}
+
static void __init dtb_lapic_setup(void)
{
-#ifdef CONFIG_X86_LOCAL_APIC
struct device_node *dn;
struct resource r;
+ unsigned long lapic_addr = APIC_DEFAULT_PHYS_BASE;
int ret;
dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-lapic");
- if (!dn)
- return;
-
- ret = of_address_to_resource(dn, 0, );
- if (WARN_ON(ret))
- return;
+ if (dn) {
+ ret = of_address_to_resource(dn, 0, );
+ if (WARN_ON(ret))
+ return;
+ lapic_addr = r.start;
+ }
/* Did the boot loader setup the local APIC ? */
if (!boot_cpu_has(X86_FEATURE_APIC)) {
- if (apic_force_enable(r.start))
+ if (apic_force_enable(lapic_addr))
return;
}
smp_found_config = 1;
pic_mode = 1;
- register_lapic_address(r.start);
- generic_processor_info(boot_cpu_physical_apicid,
- GET_APIC_VERSION(apic_read(APIC_LVR)));
-#endif
+ register_lapic_address(lapic_addr);
}
+#endif /* CONFIG_X86_LOCAL_APIC */
+
#ifdef CONFIG_X86_IO_APIC
static unsigned int ioapic_id;
@@ -259,7 +277,10 @@ static void __init dtb_ioapic_setup(void) {}
static void __init dtb_apic_setup(void)
{
+#ifdef CONFIG_X86_LOCAL_APIC
dtb_lapic_setup();
+ dtb_cpu_setup();
+#endif
dtb_ioapic_setup();
}
[tip:x86/platform] x86/devicetree: Use CPU description from Device Tree
Commit-ID: 4e07db9c8db87e3b71be4c3cd626ddc9bacd5a1e
Gitweb: https://git.kernel.org/tip/4e07db9c8db87e3b71be4c3cd626ddc9bacd5a1e
Author: Ivan Gorinov
AuthorDate: Thu, 22 Mar 2018 14:35:47 -0700
Committer: Thomas Gleixner
CommitDate: Mon, 26 Mar 2018 15:13:32 +0200
x86/devicetree: Use CPU description from Device Tree
Current x86 Device Tree implementation does not support multiprocessing.
Use new DT bindings to describe the processors.
Signed-off-by: Ivan Gorinov
Signed-off-by: Thomas Gleixner
Reviewed-by: Andy Shevchenko
Cc: Mark Rutland
Cc: Rob Herring
Cc: Frank Rowand
Link:
https://lkml.kernel.org/r/c291fb2cef51b730b59916d7745be0eaa4378c6c.1521753738.git.ivan.gori...@intel.com
---
arch/x86/kernel/devicetree.c | 45
1 file changed, 33 insertions(+), 12 deletions(-)
diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c
index 5cd387fcc777..c9d2b19749b8 100644
--- a/arch/x86/kernel/devicetree.c
+++ b/arch/x86/kernel/devicetree.c
@@ -131,34 +131,52 @@ static void __init dtb_setup_hpet(void)
#endif
}
+#ifdef CONFIG_X86_LOCAL_APIC
+
+static void __init dtb_cpu_setup(void)
+{
+ struct device_node *dn;
+ u32 apic_id, version;
+ int ret;
+
+ version = GET_APIC_VERSION(apic_read(APIC_LVR));
+ for_each_node_by_type(dn, "cpu") {
+ ret = of_property_read_u32(dn, "reg", _id);
+ if (ret < 0) {
+ pr_warn("%pOF: missing local APIC ID\n", dn);
+ continue;
+ }
+ generic_processor_info(apic_id, version);
+ }
+}
+
static void __init dtb_lapic_setup(void)
{
-#ifdef CONFIG_X86_LOCAL_APIC
struct device_node *dn;
struct resource r;
+ unsigned long lapic_addr = APIC_DEFAULT_PHYS_BASE;
int ret;
dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-lapic");
- if (!dn)
- return;
-
- ret = of_address_to_resource(dn, 0, );
- if (WARN_ON(ret))
- return;
+ if (dn) {
+ ret = of_address_to_resource(dn, 0, );
+ if (WARN_ON(ret))
+ return;
+ lapic_addr = r.start;
+ }
/* Did the boot loader setup the local APIC ? */
if (!boot_cpu_has(X86_FEATURE_APIC)) {
- if (apic_force_enable(r.start))
+ if (apic_force_enable(lapic_addr))
return;
}
smp_found_config = 1;
pic_mode = 1;
- register_lapic_address(r.start);
- generic_processor_info(boot_cpu_physical_apicid,
- GET_APIC_VERSION(apic_read(APIC_LVR)));
-#endif
+ register_lapic_address(lapic_addr);
}
+#endif /* CONFIG_X86_LOCAL_APIC */
+
#ifdef CONFIG_X86_IO_APIC
static unsigned int ioapic_id;
@@ -259,7 +277,10 @@ static void __init dtb_ioapic_setup(void) {}
static void __init dtb_apic_setup(void)
{
+#ifdef CONFIG_X86_LOCAL_APIC
dtb_lapic_setup();
+ dtb_cpu_setup();
+#endif
dtb_ioapic_setup();
}
[tip:x86/platform] of/Documentation: Specify local APIC ID in "reg"
Commit-ID: 7f2e85840871f199057e65232ebde846192ed989
Gitweb: https://git.kernel.org/tip/7f2e85840871f199057e65232ebde846192ed989
Author: Ivan Gorinov <ivan.gori...@intel.com>
AuthorDate: Thu, 22 Mar 2018 14:35:33 -0700
Committer: Thomas Gleixner <t...@linutronix.de>
CommitDate: Mon, 26 Mar 2018 15:13:32 +0200
of/Documentation: Specify local APIC ID in "reg"
Use the "reg" property to specify the processor's local APIC ID instead of
setting it to the CPU node index in Device Tree.
Local APIC ID is assigned by hardware and visible in the APIC ID register.
Some processor models allow APIC ID to be changed by software, but CPUID
instruction executed with %eax = 0x0b always returns the initial ID in %edx.
Local APIC ID does not match the node index in many systems.
Signed-off-by: Ivan Gorinov <ivan.gori...@intel.com>
Signed-off-by: Thomas Gleixner <t...@linutronix.de>
Reviewed-by: Andy Shevchenko <andy.shevche...@gmail.com>
Reviewed-by: Rob Herring <r...@kernel.org>
Cc: Mark Rutland <mark.rutl...@arm.com>
Cc: Rob Herring <robh...@kernel.org>
Cc: Frank Rowand <frowand.l...@gmail.com>
Link:
https://lkml.kernel.org/r/4b1a471a56ac0ebd7510f4759afce9104595d6da.1521753738.git.ivan.gori...@intel.com
---
Documentation/devicetree/bindings/x86/ce4100.txt | 37 ++--
1 file changed, 28 insertions(+), 9 deletions(-)
diff --git a/Documentation/devicetree/bindings/x86/ce4100.txt
b/Documentation/devicetree/bindings/x86/ce4100.txt
index b49ae593a60b..cd1221bfb539 100644
--- a/Documentation/devicetree/bindings/x86/ce4100.txt
+++ b/Documentation/devicetree/bindings/x86/ce4100.txt
@@ -7,17 +7,36 @@ Many of the "generic" devices like HPET or IO APIC have the
ce4100
name in their compatible property because they first appeared in this
SoC.
-The CPU node
-
- cpu@0 {
- device_type = "cpu";
- compatible = "intel,ce4100";
- reg = <0>;
- lapic = <>;
+The CPU nodes
+-
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "intel,ce4100";
+ reg = <0x00>;
+ };
+
+ cpu@2 {
+ device_type = "cpu";
+ compatible = "intel,ce4100";
+ reg = <0x02>;
+ };
};
-The reg property describes the CPU number. The lapic property points to
-the local APIC timer.
+A "cpu" node describes one logical processor (hardware thread).
+
+Required properties:
+
+- device_type
+ Device type, must be "cpu".
+
+- reg
+ Local APIC ID, the unique number assigned to each processor by
+ system hardware.
The SoC node
[tip:x86/platform] of/Documentation: Specify local APIC ID in "reg"
Commit-ID: 7f2e85840871f199057e65232ebde846192ed989
Gitweb: https://git.kernel.org/tip/7f2e85840871f199057e65232ebde846192ed989
Author: Ivan Gorinov
AuthorDate: Thu, 22 Mar 2018 14:35:33 -0700
Committer: Thomas Gleixner
CommitDate: Mon, 26 Mar 2018 15:13:32 +0200
of/Documentation: Specify local APIC ID in "reg"
Use the "reg" property to specify the processor's local APIC ID instead of
setting it to the CPU node index in Device Tree.
Local APIC ID is assigned by hardware and visible in the APIC ID register.
Some processor models allow APIC ID to be changed by software, but CPUID
instruction executed with %eax = 0x0b always returns the initial ID in %edx.
Local APIC ID does not match the node index in many systems.
Signed-off-by: Ivan Gorinov
Signed-off-by: Thomas Gleixner
Reviewed-by: Andy Shevchenko
Reviewed-by: Rob Herring
Cc: Mark Rutland
Cc: Rob Herring
Cc: Frank Rowand
Link:
https://lkml.kernel.org/r/4b1a471a56ac0ebd7510f4759afce9104595d6da.1521753738.git.ivan.gori...@intel.com
---
Documentation/devicetree/bindings/x86/ce4100.txt | 37 ++--
1 file changed, 28 insertions(+), 9 deletions(-)
diff --git a/Documentation/devicetree/bindings/x86/ce4100.txt
b/Documentation/devicetree/bindings/x86/ce4100.txt
index b49ae593a60b..cd1221bfb539 100644
--- a/Documentation/devicetree/bindings/x86/ce4100.txt
+++ b/Documentation/devicetree/bindings/x86/ce4100.txt
@@ -7,17 +7,36 @@ Many of the "generic" devices like HPET or IO APIC have the
ce4100
name in their compatible property because they first appeared in this
SoC.
-The CPU node
-
- cpu@0 {
- device_type = "cpu";
- compatible = "intel,ce4100";
- reg = <0>;
- lapic = <>;
+The CPU nodes
+-
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "intel,ce4100";
+ reg = <0x00>;
+ };
+
+ cpu@2 {
+ device_type = "cpu";
+ compatible = "intel,ce4100";
+ reg = <0x02>;
+ };
};
-The reg property describes the CPU number. The lapic property points to
-the local APIC timer.
+A "cpu" node describes one logical processor (hardware thread).
+
+Required properties:
+
+- device_type
+ Device type, must be "cpu".
+
+- reg
+ Local APIC ID, the unique number assigned to each processor by
+ system hardware.
The SoC node
[PATCH v8 2/2] x86/devicetree: Use CPU description from Device Tree
Current x86 Device Tree implementation does not support multiprocessing.
Use new DT bindings to describe the processors.
Signed-off-by: Ivan Gorinov <ivan.gori...@intel.com>
---
arch/x86/kernel/devicetree.c | 45
1 file changed, 33 insertions(+), 12 deletions(-)
diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c
index 25de5f6..cca6742 100644
--- a/arch/x86/kernel/devicetree.c
+++ b/arch/x86/kernel/devicetree.c
@@ -130,34 +130,52 @@ static void __init dtb_setup_hpet(void)
#endif
}
+#ifdef CONFIG_X86_LOCAL_APIC
+
+static void __init dtb_cpu_setup(void)
+{
+ struct device_node *dn;
+ u32 apic_id, version;
+ int ret;
+
+ version = GET_APIC_VERSION(apic_read(APIC_LVR));
+ for_each_node_by_type(dn, "cpu") {
+ ret = of_property_read_u32(dn, "reg", _id);
+ if (ret < 0) {
+ pr_warn("%pOF: missing local APIC ID\n", dn);
+ continue;
+ }
+ generic_processor_info(apic_id, version);
+ }
+}
+
static void __init dtb_lapic_setup(void)
{
-#ifdef CONFIG_X86_LOCAL_APIC
struct device_node *dn;
struct resource r;
+ unsigned long lapic_addr = APIC_DEFAULT_PHYS_BASE;
int ret;
dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-lapic");
- if (!dn)
- return;
-
- ret = of_address_to_resource(dn, 0, );
- if (WARN_ON(ret))
- return;
+ if (dn) {
+ ret = of_address_to_resource(dn, 0, );
+ if (WARN_ON(ret))
+ return;
+ lapic_addr = r.start;
+ }
/* Did the boot loader setup the local APIC ? */
if (!boot_cpu_has(X86_FEATURE_APIC)) {
- if (apic_force_enable(r.start))
+ if (apic_force_enable(lapic_addr))
return;
}
smp_found_config = 1;
pic_mode = 1;
- register_lapic_address(r.start);
- generic_processor_info(boot_cpu_physical_apicid,
- GET_APIC_VERSION(apic_read(APIC_LVR)));
-#endif
+ register_lapic_address(lapic_addr);
}
+#endif /* CONFIG_X86_LOCAL_APIC */
+
#ifdef CONFIG_X86_IO_APIC
static unsigned int ioapic_id;
@@ -255,7 +273,10 @@ static void __init dtb_ioapic_setup(void) {}
static void __init dtb_apic_setup(void)
{
+#ifdef CONFIG_X86_LOCAL_APIC
dtb_lapic_setup();
+ dtb_cpu_setup();
+#endif
dtb_ioapic_setup();
}
--
2.7.4
[PATCH v8 2/2] x86/devicetree: Use CPU description from Device Tree
Current x86 Device Tree implementation does not support multiprocessing.
Use new DT bindings to describe the processors.
Signed-off-by: Ivan Gorinov
---
arch/x86/kernel/devicetree.c | 45
1 file changed, 33 insertions(+), 12 deletions(-)
diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c
index 25de5f6..cca6742 100644
--- a/arch/x86/kernel/devicetree.c
+++ b/arch/x86/kernel/devicetree.c
@@ -130,34 +130,52 @@ static void __init dtb_setup_hpet(void)
#endif
}
+#ifdef CONFIG_X86_LOCAL_APIC
+
+static void __init dtb_cpu_setup(void)
+{
+ struct device_node *dn;
+ u32 apic_id, version;
+ int ret;
+
+ version = GET_APIC_VERSION(apic_read(APIC_LVR));
+ for_each_node_by_type(dn, "cpu") {
+ ret = of_property_read_u32(dn, "reg", _id);
+ if (ret < 0) {
+ pr_warn("%pOF: missing local APIC ID\n", dn);
+ continue;
+ }
+ generic_processor_info(apic_id, version);
+ }
+}
+
static void __init dtb_lapic_setup(void)
{
-#ifdef CONFIG_X86_LOCAL_APIC
struct device_node *dn;
struct resource r;
+ unsigned long lapic_addr = APIC_DEFAULT_PHYS_BASE;
int ret;
dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-lapic");
- if (!dn)
- return;
-
- ret = of_address_to_resource(dn, 0, );
- if (WARN_ON(ret))
- return;
+ if (dn) {
+ ret = of_address_to_resource(dn, 0, );
+ if (WARN_ON(ret))
+ return;
+ lapic_addr = r.start;
+ }
/* Did the boot loader setup the local APIC ? */
if (!boot_cpu_has(X86_FEATURE_APIC)) {
- if (apic_force_enable(r.start))
+ if (apic_force_enable(lapic_addr))
return;
}
smp_found_config = 1;
pic_mode = 1;
- register_lapic_address(r.start);
- generic_processor_info(boot_cpu_physical_apicid,
- GET_APIC_VERSION(apic_read(APIC_LVR)));
-#endif
+ register_lapic_address(lapic_addr);
}
+#endif /* CONFIG_X86_LOCAL_APIC */
+
#ifdef CONFIG_X86_IO_APIC
static unsigned int ioapic_id;
@@ -255,7 +273,10 @@ static void __init dtb_ioapic_setup(void) {}
static void __init dtb_apic_setup(void)
{
+#ifdef CONFIG_X86_LOCAL_APIC
dtb_lapic_setup();
+ dtb_cpu_setup();
+#endif
dtb_ioapic_setup();
}
--
2.7.4
[PATCH v8 1/2] of: Documentation: Specify local APIC ID in "reg"
Use the "reg" property to specify the processor's local APIC ID instead of
setting it to the CPU node index in Device Tree.
Local APIC ID is assigned by hardware and visible in the APIC ID register.
Some processor models allow APIC ID to be changed by software, but CPUID
instruction executed with %eax = 0x0b always returns the initial ID in %edx.
Local APIC ID does not match the node index in many systems.
Signed-off-by: Ivan Gorinov <ivan.gori...@intel.com>
---
Documentation/devicetree/bindings/x86/ce4100.txt | 37 ++--
1 file changed, 28 insertions(+), 9 deletions(-)
diff --git a/Documentation/devicetree/bindings/x86/ce4100.txt
b/Documentation/devicetree/bindings/x86/ce4100.txt
index b49ae59..4bbfed1 100644
--- a/Documentation/devicetree/bindings/x86/ce4100.txt
+++ b/Documentation/devicetree/bindings/x86/ce4100.txt
@@ -7,17 +7,36 @@ Many of the "generic" devices like HPET or IO APIC have the
ce4100
name in their compatible property because they first appeared in this
SoC.
-The CPU node
-
- cpu@0 {
- device_type = "cpu";
- compatible = "intel,ce4100";
- reg = <0>;
- lapic = <>;
+The CPU nodes
+-
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0x00 {
+ device_type = "cpu";
+ compatible = "intel,ce4100";
+ reg = <0x00>;
+ };
+
+ cpu@0x02 {
+ device_type = "cpu";
+ compatible = "intel,ce4100";
+ reg = <0x02>;
+ };
};
-The reg property describes the CPU number. The lapic property points to
-the local APIC timer.
+A "cpu" node describes one logical processor (hardware thread).
+
+Required properties:
+
+- device_type
+ Device type, must be "cpu".
+
+- reg
+ Local APIC ID, the unique number assigned to each processor by
+ system hardware.
The SoC node
--
2.7.4
[PATCH v8 1/2] of: Documentation: Specify local APIC ID in "reg"
Use the "reg" property to specify the processor's local APIC ID instead of
setting it to the CPU node index in Device Tree.
Local APIC ID is assigned by hardware and visible in the APIC ID register.
Some processor models allow APIC ID to be changed by software, but CPUID
instruction executed with %eax = 0x0b always returns the initial ID in %edx.
Local APIC ID does not match the node index in many systems.
Signed-off-by: Ivan Gorinov
---
Documentation/devicetree/bindings/x86/ce4100.txt | 37 ++--
1 file changed, 28 insertions(+), 9 deletions(-)
diff --git a/Documentation/devicetree/bindings/x86/ce4100.txt
b/Documentation/devicetree/bindings/x86/ce4100.txt
index b49ae59..4bbfed1 100644
--- a/Documentation/devicetree/bindings/x86/ce4100.txt
+++ b/Documentation/devicetree/bindings/x86/ce4100.txt
@@ -7,17 +7,36 @@ Many of the "generic" devices like HPET or IO APIC have the
ce4100
name in their compatible property because they first appeared in this
SoC.
-The CPU node
-
- cpu@0 {
- device_type = "cpu";
- compatible = "intel,ce4100";
- reg = <0>;
- lapic = <>;
+The CPU nodes
+-
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0x00 {
+ device_type = "cpu";
+ compatible = "intel,ce4100";
+ reg = <0x00>;
+ };
+
+ cpu@0x02 {
+ device_type = "cpu";
+ compatible = "intel,ce4100";
+ reg = <0x02>;
+ };
};
-The reg property describes the CPU number. The lapic property points to
-the local APIC timer.
+A "cpu" node describes one logical processor (hardware thread).
+
+Required properties:
+
+- device_type
+ Device type, must be "cpu".
+
+- reg
+ Local APIC ID, the unique number assigned to each processor by
+ system hardware.
The SoC node
--
2.7.4
[PATCH v8 0/2] x86/devicetree: Enable multiprocessing
Current x86 implementation of Device Tree does not support multiprocessing, and the bindings documentation describes the "reg" property of "cpu" nodes as "CPU number" instead of hardware-assigned local APIC ID. v8: * Fixed build error with CONFIG_X86_LOCAL_APIC=n reported by kbuild. v7: * Change log update. v6: * Calling of_property_read_u32() to get Local APIC ID from "reg". * DT documentation changes: corrected CPU node example and changed the "reg" property description. v5: * Using the "reg" property to specify Local APIC ID. Ivan Gorinov (2): of: Documentation: Specify local APIC ID in "reg" x86/devicetree: Use CPU description from Device Tree Documentation/devicetree/bindings/x86/ce4100.txt | 37 ++- arch/x86/kernel/devicetree.c | 45 +--- 2 files changed, 61 insertions(+), 21 deletions(-) -- 2.7.4
[PATCH v8 0/2] x86/devicetree: Enable multiprocessing
Current x86 implementation of Device Tree does not support multiprocessing, and the bindings documentation describes the "reg" property of "cpu" nodes as "CPU number" instead of hardware-assigned local APIC ID. v8: * Fixed build error with CONFIG_X86_LOCAL_APIC=n reported by kbuild. v7: * Change log update. v6: * Calling of_property_read_u32() to get Local APIC ID from "reg". * DT documentation changes: corrected CPU node example and changed the "reg" property description. v5: * Using the "reg" property to specify Local APIC ID. Ivan Gorinov (2): of: Documentation: Specify local APIC ID in "reg" x86/devicetree: Use CPU description from Device Tree Documentation/devicetree/bindings/x86/ce4100.txt | 37 ++- arch/x86/kernel/devicetree.c | 45 +--- 2 files changed, 61 insertions(+), 21 deletions(-) -- 2.7.4
[PATCH v7 2/2] x86/devicetree: Use CPU description from Device Tree
Current x86 Device Tree implementation does not support multiprocessing.
Use new DT bindings to describe the processors.
Signed-off-by: Ivan Gorinov <ivan.gori...@intel.com>
---
arch/x86/kernel/devicetree.c | 39 ---
1 file changed, 28 insertions(+), 11 deletions(-)
diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c
index 25de5f6..62fd5c9 100644
--- a/arch/x86/kernel/devicetree.c
+++ b/arch/x86/kernel/devicetree.c
@@ -130,31 +130,46 @@ static void __init dtb_setup_hpet(void)
#endif
}
+static void __init dtb_cpu_setup(void)
+{
+ struct device_node *dn;
+ u32 apic_id, version;
+ int ret;
+
+ version = GET_APIC_VERSION(apic_read(APIC_LVR));
+ for_each_node_by_type(dn, "cpu") {
+ ret = of_property_read_u32(dn, "reg", _id);
+ if (ret < 0) {
+ pr_warn("%pOF: missing local APIC ID\n", dn);
+ continue;
+ }
+ generic_processor_info(apic_id, version);
+ }
+}
+
static void __init dtb_lapic_setup(void)
{
#ifdef CONFIG_X86_LOCAL_APIC
struct device_node *dn;
struct resource r;
+ unsigned long lapic_addr = APIC_DEFAULT_PHYS_BASE;
int ret;
dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-lapic");
- if (!dn)
- return;
-
- ret = of_address_to_resource(dn, 0, );
- if (WARN_ON(ret))
- return;
+ if (dn) {
+ ret = of_address_to_resource(dn, 0, );
+ if (WARN_ON(ret))
+ return;
+ lapic_addr = r.start;
+ }
/* Did the boot loader setup the local APIC ? */
if (!boot_cpu_has(X86_FEATURE_APIC)) {
- if (apic_force_enable(r.start))
+ if (apic_force_enable(lapic_addr))
return;
}
- smp_found_config = 1;
pic_mode = 1;
- register_lapic_address(r.start);
- generic_processor_info(boot_cpu_physical_apicid,
- GET_APIC_VERSION(apic_read(APIC_LVR)));
+ register_lapic_address(lapic_addr);
#endif
}
@@ -256,6 +271,7 @@ static void __init dtb_ioapic_setup(void) {}
static void __init dtb_apic_setup(void)
{
dtb_lapic_setup();
+ dtb_cpu_setup();
dtb_ioapic_setup();
}
@@ -292,6 +308,7 @@ void __init x86_dtb_init(void)
if (!of_have_populated_dt())
return;
+ smp_found_config = 1;
dtb_setup_hpet();
dtb_apic_setup();
}
--
2.7.4
[PATCH v7 2/2] x86/devicetree: Use CPU description from Device Tree
Current x86 Device Tree implementation does not support multiprocessing.
Use new DT bindings to describe the processors.
Signed-off-by: Ivan Gorinov
---
arch/x86/kernel/devicetree.c | 39 ---
1 file changed, 28 insertions(+), 11 deletions(-)
diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c
index 25de5f6..62fd5c9 100644
--- a/arch/x86/kernel/devicetree.c
+++ b/arch/x86/kernel/devicetree.c
@@ -130,31 +130,46 @@ static void __init dtb_setup_hpet(void)
#endif
}
+static void __init dtb_cpu_setup(void)
+{
+ struct device_node *dn;
+ u32 apic_id, version;
+ int ret;
+
+ version = GET_APIC_VERSION(apic_read(APIC_LVR));
+ for_each_node_by_type(dn, "cpu") {
+ ret = of_property_read_u32(dn, "reg", _id);
+ if (ret < 0) {
+ pr_warn("%pOF: missing local APIC ID\n", dn);
+ continue;
+ }
+ generic_processor_info(apic_id, version);
+ }
+}
+
static void __init dtb_lapic_setup(void)
{
#ifdef CONFIG_X86_LOCAL_APIC
struct device_node *dn;
struct resource r;
+ unsigned long lapic_addr = APIC_DEFAULT_PHYS_BASE;
int ret;
dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-lapic");
- if (!dn)
- return;
-
- ret = of_address_to_resource(dn, 0, );
- if (WARN_ON(ret))
- return;
+ if (dn) {
+ ret = of_address_to_resource(dn, 0, );
+ if (WARN_ON(ret))
+ return;
+ lapic_addr = r.start;
+ }
/* Did the boot loader setup the local APIC ? */
if (!boot_cpu_has(X86_FEATURE_APIC)) {
- if (apic_force_enable(r.start))
+ if (apic_force_enable(lapic_addr))
return;
}
- smp_found_config = 1;
pic_mode = 1;
- register_lapic_address(r.start);
- generic_processor_info(boot_cpu_physical_apicid,
- GET_APIC_VERSION(apic_read(APIC_LVR)));
+ register_lapic_address(lapic_addr);
#endif
}
@@ -256,6 +271,7 @@ static void __init dtb_ioapic_setup(void) {}
static void __init dtb_apic_setup(void)
{
dtb_lapic_setup();
+ dtb_cpu_setup();
dtb_ioapic_setup();
}
@@ -292,6 +308,7 @@ void __init x86_dtb_init(void)
if (!of_have_populated_dt())
return;
+ smp_found_config = 1;
dtb_setup_hpet();
dtb_apic_setup();
}
--
2.7.4
[PATCH v7 1/2] of: Documentation: Specify local APIC ID in "reg"
Use the "reg" property to specify the processor's local APIC ID instead of
setting it to the "cpu" node index in Device Tree.
Local APIC ID is assigned by hardware and visible in the APIC ID register.
Some processor models allow APIC ID to be changed by software, but CPUID
instruction executed with %eax = 0x0b always returns the initial ID in %edx.
Local APIC ID does not match the DT "cpu" node index in many systems.
Signed-off-by: Ivan Gorinov <ivan.gori...@intel.com>
---
Documentation/devicetree/bindings/x86/ce4100.txt | 37 ++--
1 file changed, 28 insertions(+), 9 deletions(-)
diff --git a/Documentation/devicetree/bindings/x86/ce4100.txt
b/Documentation/devicetree/bindings/x86/ce4100.txt
index b49ae59..4bbfed1 100644
--- a/Documentation/devicetree/bindings/x86/ce4100.txt
+++ b/Documentation/devicetree/bindings/x86/ce4100.txt
@@ -7,17 +7,36 @@ Many of the "generic" devices like HPET or IO APIC have the
ce4100
name in their compatible property because they first appeared in this
SoC.
-The CPU node
-
- cpu@0 {
- device_type = "cpu";
- compatible = "intel,ce4100";
- reg = <0>;
- lapic = <>;
+The CPU nodes
+-
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0x00 {
+ device_type = "cpu";
+ compatible = "intel,ce4100";
+ reg = <0x00>;
+ };
+
+ cpu@0x02 {
+ device_type = "cpu";
+ compatible = "intel,ce4100";
+ reg = <0x02>;
+ };
};
-The reg property describes the CPU number. The lapic property points to
-the local APIC timer.
+A "cpu" node describes one logical processor (hardware thread).
+
+Required properties:
+
+- device_type
+ Device type, must be "cpu".
+
+- reg
+ Local APIC ID, the unique number assigned to each processor by
+ system hardware.
The SoC node
--
2.7.4
[PATCH v7 1/2] of: Documentation: Specify local APIC ID in "reg"
Use the "reg" property to specify the processor's local APIC ID instead of
setting it to the "cpu" node index in Device Tree.
Local APIC ID is assigned by hardware and visible in the APIC ID register.
Some processor models allow APIC ID to be changed by software, but CPUID
instruction executed with %eax = 0x0b always returns the initial ID in %edx.
Local APIC ID does not match the DT "cpu" node index in many systems.
Signed-off-by: Ivan Gorinov
---
Documentation/devicetree/bindings/x86/ce4100.txt | 37 ++--
1 file changed, 28 insertions(+), 9 deletions(-)
diff --git a/Documentation/devicetree/bindings/x86/ce4100.txt
b/Documentation/devicetree/bindings/x86/ce4100.txt
index b49ae59..4bbfed1 100644
--- a/Documentation/devicetree/bindings/x86/ce4100.txt
+++ b/Documentation/devicetree/bindings/x86/ce4100.txt
@@ -7,17 +7,36 @@ Many of the "generic" devices like HPET or IO APIC have the
ce4100
name in their compatible property because they first appeared in this
SoC.
-The CPU node
-
- cpu@0 {
- device_type = "cpu";
- compatible = "intel,ce4100";
- reg = <0>;
- lapic = <>;
+The CPU nodes
+-
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0x00 {
+ device_type = "cpu";
+ compatible = "intel,ce4100";
+ reg = <0x00>;
+ };
+
+ cpu@0x02 {
+ device_type = "cpu";
+ compatible = "intel,ce4100";
+ reg = <0x02>;
+ };
};
-The reg property describes the CPU number. The lapic property points to
-the local APIC timer.
+A "cpu" node describes one logical processor (hardware thread).
+
+Required properties:
+
+- device_type
+ Device type, must be "cpu".
+
+- reg
+ Local APIC ID, the unique number assigned to each processor by
+ system hardware.
The SoC node
--
2.7.4
[PATCH v7 0/2] x86/devicetree: Enable multiprocessing
Current x86 implementation of Device Tree does not support multiprocessing, and the bindings documentation describes the "reg" property as CPU number instead of hardware-assigned local APIC ID. v7: * Change log update v6: * Calling of_property_read_u32() to get Local APIC ID from "reg" * DT documentation changes: corrected CPU node example and changed the "reg" property description v5: * Using the "reg" property to specify Local APIC ID Ivan Gorinov (2): of: Documentation: Specify local APIC ID in "reg" x86/devicetree: Use CPU description from Device Tree Documentation/devicetree/bindings/x86/ce4100.txt | 37 -- arch/x86/kernel/devicetree.c | 39 +--- 2 files changed, 56 insertions(+), 20 deletions(-) -- 2.7.4
[PATCH v7 0/2] x86/devicetree: Enable multiprocessing
Current x86 implementation of Device Tree does not support multiprocessing, and the bindings documentation describes the "reg" property as CPU number instead of hardware-assigned local APIC ID. v7: * Change log update v6: * Calling of_property_read_u32() to get Local APIC ID from "reg" * DT documentation changes: corrected CPU node example and changed the "reg" property description v5: * Using the "reg" property to specify Local APIC ID Ivan Gorinov (2): of: Documentation: Specify local APIC ID in "reg" x86/devicetree: Use CPU description from Device Tree Documentation/devicetree/bindings/x86/ce4100.txt | 37 -- arch/x86/kernel/devicetree.c | 39 +--- 2 files changed, 56 insertions(+), 20 deletions(-) -- 2.7.4
Re: [PATCH v6 1/2] of: Documentation: Specify local APIC ID in "reg"
On Mon, Mar 19, 2018 at 07:39:52PM -0500, Rob Herring wrote:
> On Tue, Mar 13, 2018 at 5:05 PM, Ivan Gorinov <ivan.gori...@intel.com> wrote:
> > Use the "reg" property to specify the processor's local APIC ID.
> > Local APIC ID is assigned by hardware and may differ from CPU number.
>
> Is "CPU number" a s/w visible h/w number or has it just been an index
> for DT? In the latter case, I'm okay with this change. In the former
> case, you should stick to the existing numbering. For example on ARM,
> the number here corresponds to a core ID number in a register called
> MPIDR.
The latter case. Apparently, "CPU number" was just an index in the list.
Local APIC ID is the s/w visible h/w assigned number.
Some processor models allow local APIC ID to be changed by software, but
CPUID instruction executed with %eax = 0x0b always returns the initial ID
assigned by hardware in %edx.
APIC ID does not match index in the list in many systems.
> >
> > Signed-off-by: Ivan Gorinov <ivan.gori...@intel.com>
> > ---
> > Documentation/devicetree/bindings/x86/ce4100.txt | 37
> > ++--
> > 1 file changed, 28 insertions(+), 9 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/x86/ce4100.txt
> > b/Documentation/devicetree/bindings/x86/ce4100.txt
> > index b49ae59..1c41cbd 100644
> > --- a/Documentation/devicetree/bindings/x86/ce4100.txt
> > +++ b/Documentation/devicetree/bindings/x86/ce4100.txt
> > @@ -7,17 +7,36 @@ Many of the "generic" devices like HPET or IO APIC have
> > the ce4100
> > name in their compatible property because they first appeared in this
> > SoC.
> >
> > -The CPU node
> > -
> > - cpu@0 {
> > - device_type = "cpu";
> > - compatible = "intel,ce4100";
> > - reg = <0>;
> > - lapic = <>;
> > +The CPU nodes
> > +-
> > +
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + cpu@0x00 {
>
> Drop the '0x' and leading 0s.
>
> > + device_type = "cpu";
> > + compatible = "intel,ce4100";
> > + reg = <0x00>;
> > + };
> > +
> > + cpu@0x02 {
> > + device_type = "cpu";
> > + compatible = "intel,ce4100";
> > + reg = <0x02>;
> > + };
> > };
> >
> > -The reg property describes the CPU number. The lapic property points to
> > -the local APIC timer.
> > +A "cpu" node describes one logical processor (hardware thread).
> > +
> > +Required properties:
> > +
> > +- device_type
> > + Device type, must be "cpu".
> > +
> > +- reg
> > + Local APIC ID, the unique number assigned to each processor by
> > + system hardware.
> >
> > The SoC node
> >
> > --
> > 2.7.4
> >
Re: [PATCH v6 1/2] of: Documentation: Specify local APIC ID in "reg"
On Mon, Mar 19, 2018 at 07:39:52PM -0500, Rob Herring wrote:
> On Tue, Mar 13, 2018 at 5:05 PM, Ivan Gorinov wrote:
> > Use the "reg" property to specify the processor's local APIC ID.
> > Local APIC ID is assigned by hardware and may differ from CPU number.
>
> Is "CPU number" a s/w visible h/w number or has it just been an index
> for DT? In the latter case, I'm okay with this change. In the former
> case, you should stick to the existing numbering. For example on ARM,
> the number here corresponds to a core ID number in a register called
> MPIDR.
The latter case. Apparently, "CPU number" was just an index in the list.
Local APIC ID is the s/w visible h/w assigned number.
Some processor models allow local APIC ID to be changed by software, but
CPUID instruction executed with %eax = 0x0b always returns the initial ID
assigned by hardware in %edx.
APIC ID does not match index in the list in many systems.
> >
> > Signed-off-by: Ivan Gorinov
> > ---
> > Documentation/devicetree/bindings/x86/ce4100.txt | 37
> > ++--
> > 1 file changed, 28 insertions(+), 9 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/x86/ce4100.txt
> > b/Documentation/devicetree/bindings/x86/ce4100.txt
> > index b49ae59..1c41cbd 100644
> > --- a/Documentation/devicetree/bindings/x86/ce4100.txt
> > +++ b/Documentation/devicetree/bindings/x86/ce4100.txt
> > @@ -7,17 +7,36 @@ Many of the "generic" devices like HPET or IO APIC have
> > the ce4100
> > name in their compatible property because they first appeared in this
> > SoC.
> >
> > -The CPU node
> > -
> > - cpu@0 {
> > - device_type = "cpu";
> > - compatible = "intel,ce4100";
> > - reg = <0>;
> > - lapic = <>;
> > +The CPU nodes
> > +-
> > +
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + cpu@0x00 {
>
> Drop the '0x' and leading 0s.
>
> > + device_type = "cpu";
> > + compatible = "intel,ce4100";
> > + reg = <0x00>;
> > + };
> > +
> > + cpu@0x02 {
> > + device_type = "cpu";
> > + compatible = "intel,ce4100";
> > + reg = <0x02>;
> > + };
> > };
> >
> > -The reg property describes the CPU number. The lapic property points to
> > -the local APIC timer.
> > +A "cpu" node describes one logical processor (hardware thread).
> > +
> > +Required properties:
> > +
> > +- device_type
> > + Device type, must be "cpu".
> > +
> > +- reg
> > + Local APIC ID, the unique number assigned to each processor by
> > + system hardware.
> >
> > The SoC node
> >
> > --
> > 2.7.4
> >
[PATCH v6 2/2] x86/devicetree: Use CPU description from Device Tree
Current x86 Device Tree implementation does not support multiprocessing.
Use new DT bindings to describe the processors.
Signed-off-by: Ivan Gorinov <ivan.gori...@intel.com>
---
arch/x86/kernel/devicetree.c | 39 ---
1 file changed, 28 insertions(+), 11 deletions(-)
diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c
index 5cd387f..a601f08 100644
--- a/arch/x86/kernel/devicetree.c
+++ b/arch/x86/kernel/devicetree.c
@@ -131,31 +131,46 @@ static void __init dtb_setup_hpet(void)
#endif
}
+static void __init dtb_cpu_setup(void)
+{
+ struct device_node *dn;
+ u32 apic_id, version;
+ int ret;
+
+ version = GET_APIC_VERSION(apic_read(APIC_LVR));
+ for_each_node_by_type(dn, "cpu") {
+ ret = of_property_read_u32(dn, "reg", _id);
+ if (ret < 0) {
+ pr_warn("%pOF: missing local APIC ID\n", dn);
+ continue;
+ }
+ generic_processor_info(apic_id, version);
+ }
+}
+
static void __init dtb_lapic_setup(void)
{
#ifdef CONFIG_X86_LOCAL_APIC
struct device_node *dn;
struct resource r;
+ unsigned long lapic_addr = APIC_DEFAULT_PHYS_BASE;
int ret;
dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-lapic");
- if (!dn)
- return;
-
- ret = of_address_to_resource(dn, 0, );
- if (WARN_ON(ret))
- return;
+ if (dn) {
+ ret = of_address_to_resource(dn, 0, );
+ if (WARN_ON(ret))
+ return;
+ lapic_addr = r.start;
+ }
/* Did the boot loader setup the local APIC ? */
if (!boot_cpu_has(X86_FEATURE_APIC)) {
- if (apic_force_enable(r.start))
+ if (apic_force_enable(lapic_addr))
return;
}
- smp_found_config = 1;
pic_mode = 1;
- register_lapic_address(r.start);
- generic_processor_info(boot_cpu_physical_apicid,
- GET_APIC_VERSION(apic_read(APIC_LVR)));
+ register_lapic_address(lapic_addr);
#endif
}
@@ -260,6 +275,7 @@ static void __init dtb_ioapic_setup(void) {}
static void __init dtb_apic_setup(void)
{
dtb_lapic_setup();
+ dtb_cpu_setup();
dtb_ioapic_setup();
}
@@ -297,6 +313,7 @@ void __init x86_dtb_init(void)
if (!of_have_populated_dt())
return;
+ smp_found_config = 1;
dtb_setup_hpet();
dtb_apic_setup();
}
--
2.7.4
[PATCH v6 2/2] x86/devicetree: Use CPU description from Device Tree
Current x86 Device Tree implementation does not support multiprocessing.
Use new DT bindings to describe the processors.
Signed-off-by: Ivan Gorinov
---
arch/x86/kernel/devicetree.c | 39 ---
1 file changed, 28 insertions(+), 11 deletions(-)
diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c
index 5cd387f..a601f08 100644
--- a/arch/x86/kernel/devicetree.c
+++ b/arch/x86/kernel/devicetree.c
@@ -131,31 +131,46 @@ static void __init dtb_setup_hpet(void)
#endif
}
+static void __init dtb_cpu_setup(void)
+{
+ struct device_node *dn;
+ u32 apic_id, version;
+ int ret;
+
+ version = GET_APIC_VERSION(apic_read(APIC_LVR));
+ for_each_node_by_type(dn, "cpu") {
+ ret = of_property_read_u32(dn, "reg", _id);
+ if (ret < 0) {
+ pr_warn("%pOF: missing local APIC ID\n", dn);
+ continue;
+ }
+ generic_processor_info(apic_id, version);
+ }
+}
+
static void __init dtb_lapic_setup(void)
{
#ifdef CONFIG_X86_LOCAL_APIC
struct device_node *dn;
struct resource r;
+ unsigned long lapic_addr = APIC_DEFAULT_PHYS_BASE;
int ret;
dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-lapic");
- if (!dn)
- return;
-
- ret = of_address_to_resource(dn, 0, );
- if (WARN_ON(ret))
- return;
+ if (dn) {
+ ret = of_address_to_resource(dn, 0, );
+ if (WARN_ON(ret))
+ return;
+ lapic_addr = r.start;
+ }
/* Did the boot loader setup the local APIC ? */
if (!boot_cpu_has(X86_FEATURE_APIC)) {
- if (apic_force_enable(r.start))
+ if (apic_force_enable(lapic_addr))
return;
}
- smp_found_config = 1;
pic_mode = 1;
- register_lapic_address(r.start);
- generic_processor_info(boot_cpu_physical_apicid,
- GET_APIC_VERSION(apic_read(APIC_LVR)));
+ register_lapic_address(lapic_addr);
#endif
}
@@ -260,6 +275,7 @@ static void __init dtb_ioapic_setup(void) {}
static void __init dtb_apic_setup(void)
{
dtb_lapic_setup();
+ dtb_cpu_setup();
dtb_ioapic_setup();
}
@@ -297,6 +313,7 @@ void __init x86_dtb_init(void)
if (!of_have_populated_dt())
return;
+ smp_found_config = 1;
dtb_setup_hpet();
dtb_apic_setup();
}
--
2.7.4
[PATCH v6 0/2] x86/devicetree: Enable multiprocessing
Current x86 implementation of Device Tree does not support multiprocessing, and the bindings documentation describes the "reg" property as CPU number instead of hardware-assigned local APIC ID. v6: * Calling of_property_read_u32() to get Local APIC ID from "reg" * DT documentation changes: corrected CPU node example and changed the "reg" property description v5: * Using the "reg" property to specify Local APIC ID Ivan Gorinov (2): of: Documentation: Specify local APIC ID in "reg" x86/devicetree: Use CPU description from Device Tree Documentation/devicetree/bindings/x86/ce4100.txt | 37 -- arch/x86/kernel/devicetree.c | 39 +--- 2 files changed, 56 insertions(+), 20 deletions(-) -- 2.7.4
[PATCH v6 0/2] x86/devicetree: Enable multiprocessing
Current x86 implementation of Device Tree does not support multiprocessing, and the bindings documentation describes the "reg" property as CPU number instead of hardware-assigned local APIC ID. v6: * Calling of_property_read_u32() to get Local APIC ID from "reg" * DT documentation changes: corrected CPU node example and changed the "reg" property description v5: * Using the "reg" property to specify Local APIC ID Ivan Gorinov (2): of: Documentation: Specify local APIC ID in "reg" x86/devicetree: Use CPU description from Device Tree Documentation/devicetree/bindings/x86/ce4100.txt | 37 -- arch/x86/kernel/devicetree.c | 39 +--- 2 files changed, 56 insertions(+), 20 deletions(-) -- 2.7.4
[PATCH v6 1/2] of: Documentation: Specify local APIC ID in "reg"
Use the "reg" property to specify the processor's local APIC ID.
Local APIC ID is assigned by hardware and may differ from CPU number.
Signed-off-by: Ivan Gorinov <ivan.gori...@intel.com>
---
Documentation/devicetree/bindings/x86/ce4100.txt | 37 ++--
1 file changed, 28 insertions(+), 9 deletions(-)
diff --git a/Documentation/devicetree/bindings/x86/ce4100.txt
b/Documentation/devicetree/bindings/x86/ce4100.txt
index b49ae59..1c41cbd 100644
--- a/Documentation/devicetree/bindings/x86/ce4100.txt
+++ b/Documentation/devicetree/bindings/x86/ce4100.txt
@@ -7,17 +7,36 @@ Many of the "generic" devices like HPET or IO APIC have the
ce4100
name in their compatible property because they first appeared in this
SoC.
-The CPU node
-
- cpu@0 {
- device_type = "cpu";
- compatible = "intel,ce4100";
- reg = <0>;
- lapic = <>;
+The CPU nodes
+-
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0x00 {
+ device_type = "cpu";
+ compatible = "intel,ce4100";
+ reg = <0x00>;
+ };
+
+ cpu@0x02 {
+ device_type = "cpu";
+ compatible = "intel,ce4100";
+ reg = <0x02>;
+ };
};
-The reg property describes the CPU number. The lapic property points to
-the local APIC timer.
+A "cpu" node describes one logical processor (hardware thread).
+
+Required properties:
+
+- device_type
+ Device type, must be "cpu".
+
+- reg
+ Local APIC ID, the unique number assigned to each processor by
+ system hardware.
The SoC node
--
2.7.4
[PATCH v6 1/2] of: Documentation: Specify local APIC ID in "reg"
Use the "reg" property to specify the processor's local APIC ID.
Local APIC ID is assigned by hardware and may differ from CPU number.
Signed-off-by: Ivan Gorinov
---
Documentation/devicetree/bindings/x86/ce4100.txt | 37 ++--
1 file changed, 28 insertions(+), 9 deletions(-)
diff --git a/Documentation/devicetree/bindings/x86/ce4100.txt
b/Documentation/devicetree/bindings/x86/ce4100.txt
index b49ae59..1c41cbd 100644
--- a/Documentation/devicetree/bindings/x86/ce4100.txt
+++ b/Documentation/devicetree/bindings/x86/ce4100.txt
@@ -7,17 +7,36 @@ Many of the "generic" devices like HPET or IO APIC have the
ce4100
name in their compatible property because they first appeared in this
SoC.
-The CPU node
-
- cpu@0 {
- device_type = "cpu";
- compatible = "intel,ce4100";
- reg = <0>;
- lapic = <>;
+The CPU nodes
+-
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0x00 {
+ device_type = "cpu";
+ compatible = "intel,ce4100";
+ reg = <0x00>;
+ };
+
+ cpu@0x02 {
+ device_type = "cpu";
+ compatible = "intel,ce4100";
+ reg = <0x02>;
+ };
};
-The reg property describes the CPU number. The lapic property points to
-the local APIC timer.
+A "cpu" node describes one logical processor (hardware thread).
+
+Required properties:
+
+- device_type
+ Device type, must be "cpu".
+
+- reg
+ Local APIC ID, the unique number assigned to each processor by
+ system hardware.
The SoC node
--
2.7.4
Re: [PATCH v5 1/2] of: Documentation: Specify local APIC ID in "reg"
On Tue, 2018-03-13 at 11:01 +, Mark Rutland wrote:
> > + cpu@1 {
> > + device_type = "cpu";
> > + compatible = "intel,ce4100";
> > + reg = <0x02>;
> > + };
> The unit-address (the bit after the '@' in the node name) should match
> the reg, so this node should be named cpu@2.
OK
> > -The reg property describes the CPU number. The lapic property points to
> > -the local APIC timer.
> Why was the lapic phandle removed?
The "lapic" node may not be required.
Local APIC is an essential part of every logical CPU described by a "cpu"
node, with registers accessed as memory-mapped I/O (except for x2APIC mode).
Current implementation of local APIC kernel driver requires base address to
be the same on all CPUs, default 0xfee0. If the base address is changed
by firmware, one optional node can describe new address for all CPUs.
Re: [PATCH v5 1/2] of: Documentation: Specify local APIC ID in "reg"
On Tue, 2018-03-13 at 11:01 +, Mark Rutland wrote:
> > + cpu@1 {
> > + device_type = "cpu";
> > + compatible = "intel,ce4100";
> > + reg = <0x02>;
> > + };
> The unit-address (the bit after the '@' in the node name) should match
> the reg, so this node should be named cpu@2.
OK
> > -The reg property describes the CPU number. The lapic property points to
> > -the local APIC timer.
> Why was the lapic phandle removed?
The "lapic" node may not be required.
Local APIC is an essential part of every logical CPU described by a "cpu"
node, with registers accessed as memory-mapped I/O (except for x2APIC mode).
Current implementation of local APIC kernel driver requires base address to
be the same on all CPUs, default 0xfee0. If the base address is changed
by firmware, one optional node can describe new address for all CPUs.
[PATCH v5 2/2] x86/devicetree: Use CPU description from Device Tree
Current x86 Device Tree implementation does not support multiprocessing.
Use new DT bindings to describe the processors.
Signed-off-by: Ivan Gorinov <ivan.gori...@intel.com>
---
arch/x86/kernel/devicetree.c | 42 +++---
1 file changed, 31 insertions(+), 11 deletions(-)
diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c
index 5cd387f..64671db 100644
--- a/arch/x86/kernel/devicetree.c
+++ b/arch/x86/kernel/devicetree.c
@@ -131,31 +131,49 @@ static void __init dtb_setup_hpet(void)
#endif
}
+static void __init dtb_cpu_setup(void)
+{
+ struct device_node *dn;
+ const void *prop;
+ int prop_bytes;
+ int apic_id, version;
+ int ret;
+
+ version = GET_APIC_VERSION(apic_read(APIC_LVR));
+ for_each_node_by_type(dn, "cpu") {
+ prop = of_get_property(dn, "reg", _bytes);
+ if (!prop || prop_bytes < sizeof(u32)) {
+ pr_warn("%pOF: missing local APIC ID\n", dn);
+ continue;
+ }
+ apic_id = be32_to_cpup(prop);
+ generic_processor_info(apic_id, version);
+ }
+}
+
static void __init dtb_lapic_setup(void)
{
#ifdef CONFIG_X86_LOCAL_APIC
struct device_node *dn;
struct resource r;
+ unsigned long lapic_addr = APIC_DEFAULT_PHYS_BASE;
int ret;
dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-lapic");
- if (!dn)
- return;
-
- ret = of_address_to_resource(dn, 0, );
- if (WARN_ON(ret))
- return;
+ if (dn) {
+ ret = of_address_to_resource(dn, 0, );
+ if (WARN_ON(ret))
+ return;
+ lapic_addr = r.start;
+ }
/* Did the boot loader setup the local APIC ? */
if (!boot_cpu_has(X86_FEATURE_APIC)) {
- if (apic_force_enable(r.start))
+ if (apic_force_enable(lapic_addr))
return;
}
- smp_found_config = 1;
pic_mode = 1;
- register_lapic_address(r.start);
- generic_processor_info(boot_cpu_physical_apicid,
- GET_APIC_VERSION(apic_read(APIC_LVR)));
+ register_lapic_address(lapic_addr);
#endif
}
@@ -260,6 +278,7 @@ static void __init dtb_ioapic_setup(void) {}
static void __init dtb_apic_setup(void)
{
dtb_lapic_setup();
+ dtb_cpu_setup();
dtb_ioapic_setup();
}
@@ -297,6 +316,7 @@ void __init x86_dtb_init(void)
if (!of_have_populated_dt())
return;
+ smp_found_config = 1;
dtb_setup_hpet();
dtb_apic_setup();
}
--
2.7.4
[PATCH v5 2/2] x86/devicetree: Use CPU description from Device Tree
Current x86 Device Tree implementation does not support multiprocessing.
Use new DT bindings to describe the processors.
Signed-off-by: Ivan Gorinov
---
arch/x86/kernel/devicetree.c | 42 +++---
1 file changed, 31 insertions(+), 11 deletions(-)
diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c
index 5cd387f..64671db 100644
--- a/arch/x86/kernel/devicetree.c
+++ b/arch/x86/kernel/devicetree.c
@@ -131,31 +131,49 @@ static void __init dtb_setup_hpet(void)
#endif
}
+static void __init dtb_cpu_setup(void)
+{
+ struct device_node *dn;
+ const void *prop;
+ int prop_bytes;
+ int apic_id, version;
+ int ret;
+
+ version = GET_APIC_VERSION(apic_read(APIC_LVR));
+ for_each_node_by_type(dn, "cpu") {
+ prop = of_get_property(dn, "reg", _bytes);
+ if (!prop || prop_bytes < sizeof(u32)) {
+ pr_warn("%pOF: missing local APIC ID\n", dn);
+ continue;
+ }
+ apic_id = be32_to_cpup(prop);
+ generic_processor_info(apic_id, version);
+ }
+}
+
static void __init dtb_lapic_setup(void)
{
#ifdef CONFIG_X86_LOCAL_APIC
struct device_node *dn;
struct resource r;
+ unsigned long lapic_addr = APIC_DEFAULT_PHYS_BASE;
int ret;
dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-lapic");
- if (!dn)
- return;
-
- ret = of_address_to_resource(dn, 0, );
- if (WARN_ON(ret))
- return;
+ if (dn) {
+ ret = of_address_to_resource(dn, 0, );
+ if (WARN_ON(ret))
+ return;
+ lapic_addr = r.start;
+ }
/* Did the boot loader setup the local APIC ? */
if (!boot_cpu_has(X86_FEATURE_APIC)) {
- if (apic_force_enable(r.start))
+ if (apic_force_enable(lapic_addr))
return;
}
- smp_found_config = 1;
pic_mode = 1;
- register_lapic_address(r.start);
- generic_processor_info(boot_cpu_physical_apicid,
- GET_APIC_VERSION(apic_read(APIC_LVR)));
+ register_lapic_address(lapic_addr);
#endif
}
@@ -260,6 +278,7 @@ static void __init dtb_ioapic_setup(void) {}
static void __init dtb_apic_setup(void)
{
dtb_lapic_setup();
+ dtb_cpu_setup();
dtb_ioapic_setup();
}
@@ -297,6 +316,7 @@ void __init x86_dtb_init(void)
if (!of_have_populated_dt())
return;
+ smp_found_config = 1;
dtb_setup_hpet();
dtb_apic_setup();
}
--
2.7.4
[PATCH v5 1/2] of: Documentation: Specify local APIC ID in "reg"
Set the "reg" property to the processor's local APIC ID.
Local APIC ID is assigned by hardware and may differ from CPU number.
Signed-off-by: Ivan Gorinov <ivan.gori...@intel.com>
---
Documentation/devicetree/bindings/x86/ce4100.txt | 38 ++--
1 file changed, 29 insertions(+), 9 deletions(-)
diff --git a/Documentation/devicetree/bindings/x86/ce4100.txt
b/Documentation/devicetree/bindings/x86/ce4100.txt
index b49ae59..5a4bd83 100644
--- a/Documentation/devicetree/bindings/x86/ce4100.txt
+++ b/Documentation/devicetree/bindings/x86/ce4100.txt
@@ -7,17 +7,37 @@ Many of the "generic" devices like HPET or IO APIC have the
ce4100
name in their compatible property because they first appeared in this
SoC.
-The CPU node
-
- cpu@0 {
- device_type = "cpu";
- compatible = "intel,ce4100";
- reg = <0>;
- lapic = <>;
+The CPU nodes
+-
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "intel,ce4100";
+ reg = <0x00>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "intel,ce4100";
+ reg = <0x02>;
+ };
};
-The reg property describes the CPU number. The lapic property points to
-the local APIC timer.
+A "cpu" node describes one logical processor (hardware thread).
+
+Required properties:
+
+- device_type
+ Device type, must be "cpu".
+
+- reg
+ Local APIC ID, a unique number assigned to each processor by
+ hardware. This ID is used to specify the destination of interrupt
+ messages with "physical" destination mode, including startup IPI.
The SoC node
--
2.7.4
[PATCH v5 1/2] of: Documentation: Specify local APIC ID in "reg"
Set the "reg" property to the processor's local APIC ID.
Local APIC ID is assigned by hardware and may differ from CPU number.
Signed-off-by: Ivan Gorinov
---
Documentation/devicetree/bindings/x86/ce4100.txt | 38 ++--
1 file changed, 29 insertions(+), 9 deletions(-)
diff --git a/Documentation/devicetree/bindings/x86/ce4100.txt
b/Documentation/devicetree/bindings/x86/ce4100.txt
index b49ae59..5a4bd83 100644
--- a/Documentation/devicetree/bindings/x86/ce4100.txt
+++ b/Documentation/devicetree/bindings/x86/ce4100.txt
@@ -7,17 +7,37 @@ Many of the "generic" devices like HPET or IO APIC have the
ce4100
name in their compatible property because they first appeared in this
SoC.
-The CPU node
-
- cpu@0 {
- device_type = "cpu";
- compatible = "intel,ce4100";
- reg = <0>;
- lapic = <>;
+The CPU nodes
+-
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "intel,ce4100";
+ reg = <0x00>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "intel,ce4100";
+ reg = <0x02>;
+ };
};
-The reg property describes the CPU number. The lapic property points to
-the local APIC timer.
+A "cpu" node describes one logical processor (hardware thread).
+
+Required properties:
+
+- device_type
+ Device type, must be "cpu".
+
+- reg
+ Local APIC ID, a unique number assigned to each processor by
+ hardware. This ID is used to specify the destination of interrupt
+ messages with "physical" destination mode, including startup IPI.
The SoC node
--
2.7.4
[PATCH v5 0/2] x86/devicetree: Enable multiprocessing
Current x86 implementation of Device Tree does not support multiprocessing, and the bindings documentation describes the "reg" property as CPU number instead of hardware-assigned local APIC ID. Ivan Gorinov (2): of: Documentation: Specify local APIC ID in "reg" x86/devicetree: Use CPU description from Device Tree Documentation/devicetree/bindings/x86/ce4100.txt | 38 - arch/x86/kernel/devicetree.c | 42 +--- 2 files changed, 60 insertions(+), 20 deletions(-) -- 2.7.4
[PATCH v5 0/2] x86/devicetree: Enable multiprocessing
Current x86 implementation of Device Tree does not support multiprocessing, and the bindings documentation describes the "reg" property as CPU number instead of hardware-assigned local APIC ID. Ivan Gorinov (2): of: Documentation: Specify local APIC ID in "reg" x86/devicetree: Use CPU description from Device Tree Documentation/devicetree/bindings/x86/ce4100.txt | 38 - arch/x86/kernel/devicetree.c | 42 +--- 2 files changed, 60 insertions(+), 20 deletions(-) -- 2.7.4
[tip:x86/platform] x86/devicetree: Fix device IRQ settings in DT
Commit-ID: 0a5169add90e43ab45ab1ba34223b8583fcaf675
Gitweb: https://git.kernel.org/tip/0a5169add90e43ab45ab1ba34223b8583fcaf675
Author: Ivan Gorinov <ivan.gori...@intel.com>
AuthorDate: Wed, 7 Mar 2018 11:46:53 -0800
Committer: Thomas Gleixner <t...@linutronix.de>
CommitDate: Thu, 8 Mar 2018 09:59:53 +0100
x86/devicetree: Fix device IRQ settings in DT
IRQ parameters for the SoC devices connected directly to I/O APIC lines
(without PCI IRQ routing) may be specified in the Device Tree.
Called from DT IRQ parser, irq_create_fwspec_mapping() calls
irq_domain_alloc_irqs() with a pointer to irq_fwspec structure as @arg.
But x86-specific DT IRQ allocation code casts @arg to of_phandle_args
structure pointer and crashes trying to read the IRQ parameters. The
function was not converted when the mapping descriptor was changed to
irq_fwspec in the generic irqdomain code.
Fixes: 11e4438ee330 ("irqdomain: Introduce a firmware-specific IRQ specifier
structure")
Signed-off-by: Ivan Gorinov <ivan.gori...@intel.com>
Signed-off-by: Thomas Gleixner <t...@linutronix.de>
Cc: Mark Rutland <mark.rutl...@arm.com>
Cc: Rob Herring <robh...@kernel.org>
Link:
https://lkml.kernel.org/r/a234dee27ea60ce76141872da0d6bdb378b2a9ee.1520450752.git.ivan.gori...@intel.com
---
arch/x86/kernel/devicetree.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c
index 63d2ebc21825..5cd387fcc777 100644
--- a/arch/x86/kernel/devicetree.c
+++ b/arch/x86/kernel/devicetree.c
@@ -195,19 +195,22 @@ static struct of_ioapic_type of_ioapic_type[] =
static int dt_irqdomain_alloc(struct irq_domain *domain, unsigned int virq,
unsigned int nr_irqs, void *arg)
{
- struct of_phandle_args *irq_data = (void *)arg;
+ struct irq_fwspec *fwspec = (struct irq_fwspec *)arg;
struct of_ioapic_type *it;
struct irq_alloc_info tmp;
+ int type_index;
- if (WARN_ON(irq_data->args_count < 2))
+ if (WARN_ON(fwspec->param_count < 2))
return -EINVAL;
- if (irq_data->args[1] >= ARRAY_SIZE(of_ioapic_type))
+
+ type_index = fwspec->param[1];
+ if (type_index >= ARRAY_SIZE(of_ioapic_type))
return -EINVAL;
- it = _ioapic_type[irq_data->args[1]];
+ it = _ioapic_type[type_index];
ioapic_set_alloc_attr(, NUMA_NO_NODE, it->trigger, it->polarity);
tmp.ioapic_id = mpc_ioapic_id(mp_irqdomain_ioapic_idx(domain));
- tmp.ioapic_pin = irq_data->args[0];
+ tmp.ioapic_pin = fwspec->param[0];
return mp_irqdomain_alloc(domain, virq, nr_irqs, );
}
[tip:x86/platform] x86/devicetree: Fix device IRQ settings in DT
Commit-ID: 0a5169add90e43ab45ab1ba34223b8583fcaf675
Gitweb: https://git.kernel.org/tip/0a5169add90e43ab45ab1ba34223b8583fcaf675
Author: Ivan Gorinov
AuthorDate: Wed, 7 Mar 2018 11:46:53 -0800
Committer: Thomas Gleixner
CommitDate: Thu, 8 Mar 2018 09:59:53 +0100
x86/devicetree: Fix device IRQ settings in DT
IRQ parameters for the SoC devices connected directly to I/O APIC lines
(without PCI IRQ routing) may be specified in the Device Tree.
Called from DT IRQ parser, irq_create_fwspec_mapping() calls
irq_domain_alloc_irqs() with a pointer to irq_fwspec structure as @arg.
But x86-specific DT IRQ allocation code casts @arg to of_phandle_args
structure pointer and crashes trying to read the IRQ parameters. The
function was not converted when the mapping descriptor was changed to
irq_fwspec in the generic irqdomain code.
Fixes: 11e4438ee330 ("irqdomain: Introduce a firmware-specific IRQ specifier
structure")
Signed-off-by: Ivan Gorinov
Signed-off-by: Thomas Gleixner
Cc: Mark Rutland
Cc: Rob Herring
Link:
https://lkml.kernel.org/r/a234dee27ea60ce76141872da0d6bdb378b2a9ee.1520450752.git.ivan.gori...@intel.com
---
arch/x86/kernel/devicetree.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c
index 63d2ebc21825..5cd387fcc777 100644
--- a/arch/x86/kernel/devicetree.c
+++ b/arch/x86/kernel/devicetree.c
@@ -195,19 +195,22 @@ static struct of_ioapic_type of_ioapic_type[] =
static int dt_irqdomain_alloc(struct irq_domain *domain, unsigned int virq,
unsigned int nr_irqs, void *arg)
{
- struct of_phandle_args *irq_data = (void *)arg;
+ struct irq_fwspec *fwspec = (struct irq_fwspec *)arg;
struct of_ioapic_type *it;
struct irq_alloc_info tmp;
+ int type_index;
- if (WARN_ON(irq_data->args_count < 2))
+ if (WARN_ON(fwspec->param_count < 2))
return -EINVAL;
- if (irq_data->args[1] >= ARRAY_SIZE(of_ioapic_type))
+
+ type_index = fwspec->param[1];
+ if (type_index >= ARRAY_SIZE(of_ioapic_type))
return -EINVAL;
- it = _ioapic_type[irq_data->args[1]];
+ it = _ioapic_type[type_index];
ioapic_set_alloc_attr(, NUMA_NO_NODE, it->trigger, it->polarity);
tmp.ioapic_id = mpc_ioapic_id(mp_irqdomain_ioapic_idx(domain));
- tmp.ioapic_pin = irq_data->args[0];
+ tmp.ioapic_pin = fwspec->param[0];
return mp_irqdomain_alloc(domain, virq, nr_irqs, );
}
[tip:x86/platform] x86/devicetree: Initialize device tree before using it
Commit-ID: 628df9dc5ad886b0a9b33c75a7b09710eb859ca1
Gitweb: https://git.kernel.org/tip/628df9dc5ad886b0a9b33c75a7b09710eb859ca1
Author: Ivan Gorinov <ivan.gori...@intel.com>
AuthorDate: Wed, 7 Mar 2018 11:46:29 -0800
Committer: Thomas Gleixner <t...@linutronix.de>
CommitDate: Thu, 8 Mar 2018 09:59:53 +0100
x86/devicetree: Initialize device tree before using it
Commit 08d53aa58cb1 added CRC32 calculation in early_init_dt_verify() and
checking in late initcall of_fdt_raw_init(), making early_init_dt_verify()
mandatory.
The required call to early_init_dt_verify() was not added to the
x86-specific implementation, causing failure to create the sysfs entry in
of_fdt_raw_init().
Fixes: 08d53aa58cb1 ("of/fdt: export fdt blob as /sys/firmware/fdt")
Signed-off-by: Ivan Gorinov <ivan.gori...@intel.com>
Signed-off-by: Thomas Gleixner <t...@linutronix.de>
Cc: Mark Rutland <mark.rutl...@arm.com>
Cc: Rob Herring <robh...@kernel.org>
Link:
https://lkml.kernel.org/r/c8c7e941efc63b5d25ebf9b6350b0f3df38f6098.1520450752.git.ivan.gori...@intel.com
---
arch/x86/kernel/devicetree.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c
index 25de5f6ca997..63d2ebc21825 100644
--- a/arch/x86/kernel/devicetree.c
+++ b/arch/x86/kernel/devicetree.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -270,14 +271,15 @@ static void __init x86_flattree_get_config(void)
map_len = max(PAGE_SIZE - (initial_dtb & ~PAGE_MASK), (u64)128);
- initial_boot_params = dt = early_memremap(initial_dtb, map_len);
- size = of_get_flat_dt_size();
+ dt = early_memremap(initial_dtb, map_len);
+ size = fdt_totalsize(dt);
if (map_len < size) {
early_memunmap(dt, map_len);
- initial_boot_params = dt = early_memremap(initial_dtb, size);
+ dt = early_memremap(initial_dtb, size);
map_len = size;
}
+ early_init_dt_verify(dt);
unflatten_and_copy_device_tree();
early_memunmap(dt, map_len);
}
[tip:x86/platform] x86/devicetree: Initialize device tree before using it
Commit-ID: 628df9dc5ad886b0a9b33c75a7b09710eb859ca1
Gitweb: https://git.kernel.org/tip/628df9dc5ad886b0a9b33c75a7b09710eb859ca1
Author: Ivan Gorinov
AuthorDate: Wed, 7 Mar 2018 11:46:29 -0800
Committer: Thomas Gleixner
CommitDate: Thu, 8 Mar 2018 09:59:53 +0100
x86/devicetree: Initialize device tree before using it
Commit 08d53aa58cb1 added CRC32 calculation in early_init_dt_verify() and
checking in late initcall of_fdt_raw_init(), making early_init_dt_verify()
mandatory.
The required call to early_init_dt_verify() was not added to the
x86-specific implementation, causing failure to create the sysfs entry in
of_fdt_raw_init().
Fixes: 08d53aa58cb1 ("of/fdt: export fdt blob as /sys/firmware/fdt")
Signed-off-by: Ivan Gorinov
Signed-off-by: Thomas Gleixner
Cc: Mark Rutland
Cc: Rob Herring
Link:
https://lkml.kernel.org/r/c8c7e941efc63b5d25ebf9b6350b0f3df38f6098.1520450752.git.ivan.gori...@intel.com
---
arch/x86/kernel/devicetree.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c
index 25de5f6ca997..63d2ebc21825 100644
--- a/arch/x86/kernel/devicetree.c
+++ b/arch/x86/kernel/devicetree.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -270,14 +271,15 @@ static void __init x86_flattree_get_config(void)
map_len = max(PAGE_SIZE - (initial_dtb & ~PAGE_MASK), (u64)128);
- initial_boot_params = dt = early_memremap(initial_dtb, map_len);
- size = of_get_flat_dt_size();
+ dt = early_memremap(initial_dtb, map_len);
+ size = fdt_totalsize(dt);
if (map_len < size) {
early_memunmap(dt, map_len);
- initial_boot_params = dt = early_memremap(initial_dtb, size);
+ dt = early_memremap(initial_dtb, size);
map_len = size;
}
+ early_init_dt_verify(dt);
unflatten_and_copy_device_tree();
early_memunmap(dt, map_len);
}
Re: [PATCH v4 3/4] of: Documentation: Add x86 local APIC ID property
On Wed, 2018-03-07 at 14:23 -0600, Rob Herring wrote:
> > Add new "intel,apic-id" property to allow using CPU descriptions
> > in Device Tree data provided by the U-Boot loader.
> > Address specified in 'reg' to be used as default local APIC ID
> > to avoid breaking existing systems with DTB provided by firmware.
> Is there some reason to not always use reg? For when the numbering of
> cpus and timers is different?
Yes, local APIC ID may differ from CPU number.
For example, in Atom E38xx (u-boot/arch/x86/dts/minnowmax.dts):
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "intel,baytrail-cpu";
reg = <0>;
intel,apic-id = <0>;
};
cpu@1 {
device_type = "cpu";
compatible = "intel,baytrail-cpu";
reg = <1>;
intel,apic-id = <4>;
};
};
> Of course, we do have the situation on ARM with the GIC that the GIC
> CPU IDs may be
> >
> >
> > Signed-off-by: Ivan Gorinov <ivan.gori...@intel.com>
> > ---
> > Documentation/devicetree/bindings/x86/ce4100.txt | 6 ++
> > 1 file changed, 6 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/x86/ce4100.txt
> > b/Documentation/devicetree/bindings/x86/ce4100.txt
> > index b49ae59..d15de48 100644
> > --- a/Documentation/devicetree/bindings/x86/ce4100.txt
> > +++ b/Documentation/devicetree/bindings/x86/ce4100.txt
> > @@ -14,11 +14,17 @@ The CPU node
> > compatible = "intel,ce4100";
> > reg = <0>;
> > lapic = <>;
> Isn't this enough? I can't tell because whatever this points to has no
> binding documentation.
Local APIC is a part of CPU, not an external device (except for 486 and early
Pentium).
Every CPU has access to its own local APIC registers at the same base address
(0xfee0).
Therefore, one "lapic" device node can work for all processors in the system.
With more changes in the code, the local APIC description could be made optional
because every processor can always read its local APIC base address from MSR
0x1b.
And when x2APIC mode is enabled, the local APIC registers are accessed as model
specific registers instead of memory-mapped I/O.
> You could perhaps extend it and add a cell with the id value.
This may require different DT data for Linux and U-Boot, or changes in the
latter.
Re: [PATCH v4 3/4] of: Documentation: Add x86 local APIC ID property
On Wed, 2018-03-07 at 14:23 -0600, Rob Herring wrote:
> > Add new "intel,apic-id" property to allow using CPU descriptions
> > in Device Tree data provided by the U-Boot loader.
> > Address specified in 'reg' to be used as default local APIC ID
> > to avoid breaking existing systems with DTB provided by firmware.
> Is there some reason to not always use reg? For when the numbering of
> cpus and timers is different?
Yes, local APIC ID may differ from CPU number.
For example, in Atom E38xx (u-boot/arch/x86/dts/minnowmax.dts):
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "intel,baytrail-cpu";
reg = <0>;
intel,apic-id = <0>;
};
cpu@1 {
device_type = "cpu";
compatible = "intel,baytrail-cpu";
reg = <1>;
intel,apic-id = <4>;
};
};
> Of course, we do have the situation on ARM with the GIC that the GIC
> CPU IDs may be
> >
> >
> > Signed-off-by: Ivan Gorinov
> > ---
> > Documentation/devicetree/bindings/x86/ce4100.txt | 6 ++
> > 1 file changed, 6 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/x86/ce4100.txt
> > b/Documentation/devicetree/bindings/x86/ce4100.txt
> > index b49ae59..d15de48 100644
> > --- a/Documentation/devicetree/bindings/x86/ce4100.txt
> > +++ b/Documentation/devicetree/bindings/x86/ce4100.txt
> > @@ -14,11 +14,17 @@ The CPU node
> > compatible = "intel,ce4100";
> > reg = <0>;
> > lapic = <>;
> Isn't this enough? I can't tell because whatever this points to has no
> binding documentation.
Local APIC is a part of CPU, not an external device (except for 486 and early
Pentium).
Every CPU has access to its own local APIC registers at the same base address
(0xfee0).
Therefore, one "lapic" device node can work for all processors in the system.
With more changes in the code, the local APIC description could be made optional
because every processor can always read its local APIC base address from MSR
0x1b.
And when x2APIC mode is enabled, the local APIC registers are accessed as model
specific registers instead of memory-mapped I/O.
> You could perhaps extend it and add a cell with the id value.
This may require different DT data for Linux and U-Boot, or changes in the
latter.
[PATCH v4 4/4] x86/devicetree: Enable multiprocessing in DT
Current x86 Device Tree implementation does not support multiprocessing.
Use new DT bindings to describe the processors.
Signed-off-by: Ivan Gorinov <ivan.gori...@intel.com>
---
arch/x86/kernel/devicetree.c | 27 +--
1 file changed, 25 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c
index 5cd387f..b28ac84 100644
--- a/arch/x86/kernel/devicetree.c
+++ b/arch/x86/kernel/devicetree.c
@@ -131,6 +131,30 @@ static void __init dtb_setup_hpet(void)
#endif
}
+static void __init dtb_cpu_setup(void)
+{
+ struct device_node *dn;
+ struct resource r;
+ const void *prop;
+ int apic_id, version;
+ int ret;
+
+ version = GET_APIC_VERSION(apic_read(APIC_LVR));
+ for_each_node_by_type(dn, "cpu") {
+ prop = of_get_property(dn, "intel,apic-id", NULL);
+ if (prop) {
+ apic_id = be32_to_cpup(prop);
+ } else {
+ /* use the address field as APIC ID */
+ ret = of_address_to_resource(dn, 0, );
+ if (WARN_ON_ONCE(ret))
+ continue;
+ apic_id = r.start;
+ }
+ generic_processor_info(apic_id, version);
+ }
+}
+
static void __init dtb_lapic_setup(void)
{
#ifdef CONFIG_X86_LOCAL_APIC
@@ -154,8 +178,6 @@ static void __init dtb_lapic_setup(void)
smp_found_config = 1;
pic_mode = 1;
register_lapic_address(r.start);
- generic_processor_info(boot_cpu_physical_apicid,
- GET_APIC_VERSION(apic_read(APIC_LVR)));
#endif
}
@@ -260,6 +282,7 @@ static void __init dtb_ioapic_setup(void) {}
static void __init dtb_apic_setup(void)
{
dtb_lapic_setup();
+ dtb_cpu_setup();
dtb_ioapic_setup();
}
--
2.7.4
[PATCH v4 4/4] x86/devicetree: Enable multiprocessing in DT
Current x86 Device Tree implementation does not support multiprocessing.
Use new DT bindings to describe the processors.
Signed-off-by: Ivan Gorinov
---
arch/x86/kernel/devicetree.c | 27 +--
1 file changed, 25 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c
index 5cd387f..b28ac84 100644
--- a/arch/x86/kernel/devicetree.c
+++ b/arch/x86/kernel/devicetree.c
@@ -131,6 +131,30 @@ static void __init dtb_setup_hpet(void)
#endif
}
+static void __init dtb_cpu_setup(void)
+{
+ struct device_node *dn;
+ struct resource r;
+ const void *prop;
+ int apic_id, version;
+ int ret;
+
+ version = GET_APIC_VERSION(apic_read(APIC_LVR));
+ for_each_node_by_type(dn, "cpu") {
+ prop = of_get_property(dn, "intel,apic-id", NULL);
+ if (prop) {
+ apic_id = be32_to_cpup(prop);
+ } else {
+ /* use the address field as APIC ID */
+ ret = of_address_to_resource(dn, 0, );
+ if (WARN_ON_ONCE(ret))
+ continue;
+ apic_id = r.start;
+ }
+ generic_processor_info(apic_id, version);
+ }
+}
+
static void __init dtb_lapic_setup(void)
{
#ifdef CONFIG_X86_LOCAL_APIC
@@ -154,8 +178,6 @@ static void __init dtb_lapic_setup(void)
smp_found_config = 1;
pic_mode = 1;
register_lapic_address(r.start);
- generic_processor_info(boot_cpu_physical_apicid,
- GET_APIC_VERSION(apic_read(APIC_LVR)));
#endif
}
@@ -260,6 +282,7 @@ static void __init dtb_ioapic_setup(void) {}
static void __init dtb_apic_setup(void)
{
dtb_lapic_setup();
+ dtb_cpu_setup();
dtb_ioapic_setup();
}
--
2.7.4
[PATCH v4 2/4] x86/devicetree: Fix device IRQ settings in DT
IRQ parameters for the SoC devices connected directly to I/O APIC lines
(without PCI IRQ routing) may be specified in the Device Tree.
Called from DT IRQ parser, irq_create_fwspec_mapping() calls
irq_domain_alloc_irqs() with a pointer to irq_fwspec structure as @arg.
But x86-specific DT IRQ allocation code casts @arg to of_phandle_args
structure pointer and crashes trying to read the IRQ parameters.
Signed-off-by: Ivan Gorinov <ivan.gori...@intel.com>
---
arch/x86/kernel/devicetree.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c
index 63d2ebc..5cd387f 100644
--- a/arch/x86/kernel/devicetree.c
+++ b/arch/x86/kernel/devicetree.c
@@ -195,19 +195,22 @@ static struct of_ioapic_type of_ioapic_type[] =
static int dt_irqdomain_alloc(struct irq_domain *domain, unsigned int virq,
unsigned int nr_irqs, void *arg)
{
- struct of_phandle_args *irq_data = (void *)arg;
+ struct irq_fwspec *fwspec = (struct irq_fwspec *)arg;
struct of_ioapic_type *it;
struct irq_alloc_info tmp;
+ int type_index;
- if (WARN_ON(irq_data->args_count < 2))
+ if (WARN_ON(fwspec->param_count < 2))
return -EINVAL;
- if (irq_data->args[1] >= ARRAY_SIZE(of_ioapic_type))
+
+ type_index = fwspec->param[1];
+ if (type_index >= ARRAY_SIZE(of_ioapic_type))
return -EINVAL;
- it = _ioapic_type[irq_data->args[1]];
+ it = _ioapic_type[type_index];
ioapic_set_alloc_attr(, NUMA_NO_NODE, it->trigger, it->polarity);
tmp.ioapic_id = mpc_ioapic_id(mp_irqdomain_ioapic_idx(domain));
- tmp.ioapic_pin = irq_data->args[0];
+ tmp.ioapic_pin = fwspec->param[0];
return mp_irqdomain_alloc(domain, virq, nr_irqs, );
}
--
2.7.4
[PATCH v4 2/4] x86/devicetree: Fix device IRQ settings in DT
IRQ parameters for the SoC devices connected directly to I/O APIC lines
(without PCI IRQ routing) may be specified in the Device Tree.
Called from DT IRQ parser, irq_create_fwspec_mapping() calls
irq_domain_alloc_irqs() with a pointer to irq_fwspec structure as @arg.
But x86-specific DT IRQ allocation code casts @arg to of_phandle_args
structure pointer and crashes trying to read the IRQ parameters.
Signed-off-by: Ivan Gorinov
---
arch/x86/kernel/devicetree.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c
index 63d2ebc..5cd387f 100644
--- a/arch/x86/kernel/devicetree.c
+++ b/arch/x86/kernel/devicetree.c
@@ -195,19 +195,22 @@ static struct of_ioapic_type of_ioapic_type[] =
static int dt_irqdomain_alloc(struct irq_domain *domain, unsigned int virq,
unsigned int nr_irqs, void *arg)
{
- struct of_phandle_args *irq_data = (void *)arg;
+ struct irq_fwspec *fwspec = (struct irq_fwspec *)arg;
struct of_ioapic_type *it;
struct irq_alloc_info tmp;
+ int type_index;
- if (WARN_ON(irq_data->args_count < 2))
+ if (WARN_ON(fwspec->param_count < 2))
return -EINVAL;
- if (irq_data->args[1] >= ARRAY_SIZE(of_ioapic_type))
+
+ type_index = fwspec->param[1];
+ if (type_index >= ARRAY_SIZE(of_ioapic_type))
return -EINVAL;
- it = _ioapic_type[irq_data->args[1]];
+ it = _ioapic_type[type_index];
ioapic_set_alloc_attr(, NUMA_NO_NODE, it->trigger, it->polarity);
tmp.ioapic_id = mpc_ioapic_id(mp_irqdomain_ioapic_idx(domain));
- tmp.ioapic_pin = irq_data->args[0];
+ tmp.ioapic_pin = fwspec->param[0];
return mp_irqdomain_alloc(domain, virq, nr_irqs, );
}
--
2.7.4
[PATCH v4 3/4] of: Documentation: Add x86 local APIC ID property
Current x86 Device Tree implementation does not support multiprocessing. Add new "intel,apic-id" property to allow using CPU descriptions in Device Tree data provided by the U-Boot loader. Address specified in 'reg' to be used as default local APIC ID to avoid breaking existing systems with DTB provided by firmware. Signed-off-by: Ivan Gorinov <ivan.gori...@intel.com> --- Documentation/devicetree/bindings/x86/ce4100.txt | 6 ++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/x86/ce4100.txt b/Documentation/devicetree/bindings/x86/ce4100.txt index b49ae59..d15de48 100644 --- a/Documentation/devicetree/bindings/x86/ce4100.txt +++ b/Documentation/devicetree/bindings/x86/ce4100.txt @@ -14,11 +14,17 @@ The CPU node compatible = "intel,ce4100"; reg = <0>; lapic = <>; + intel,apic-id = <0>; }; The reg property describes the CPU number. The lapic property points to the local APIC timer. +Optional properties: + +- intel,apic-id: local APIC ID. + The address specified in "reg" is used as default local APIC ID. + The SoC node -- 2.7.4
[PATCH v4 3/4] of: Documentation: Add x86 local APIC ID property
Current x86 Device Tree implementation does not support multiprocessing. Add new "intel,apic-id" property to allow using CPU descriptions in Device Tree data provided by the U-Boot loader. Address specified in 'reg' to be used as default local APIC ID to avoid breaking existing systems with DTB provided by firmware. Signed-off-by: Ivan Gorinov --- Documentation/devicetree/bindings/x86/ce4100.txt | 6 ++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/x86/ce4100.txt b/Documentation/devicetree/bindings/x86/ce4100.txt index b49ae59..d15de48 100644 --- a/Documentation/devicetree/bindings/x86/ce4100.txt +++ b/Documentation/devicetree/bindings/x86/ce4100.txt @@ -14,11 +14,17 @@ The CPU node compatible = "intel,ce4100"; reg = <0>; lapic = <>; + intel,apic-id = <0>; }; The reg property describes the CPU number. The lapic property points to the local APIC timer. +Optional properties: + +- intel,apic-id: local APIC ID. + The address specified in "reg" is used as default local APIC ID. + The SoC node -- 2.7.4
[PATCH v4 1/4] x86/devicetree: Initialize device tree before using it
Commit 08d53aa58cb162e6 ("of/fdt: export fdt blob as /sys/firmware/fdt")
adds CRC32 calculation in early_init_dt_verify() and checking in late
initcall of_fdt_raw_init(), making early_init_dt_verify() mandatory.
Required call to early_init_dt_verify() was not added to the x86-specific
implementation, causing failure to create sysfs entry in of_fdt_raw_init().
Signed-off-by: Ivan Gorinov <ivan.gori...@intel.com>
---
arch/x86/kernel/devicetree.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c
index 25de5f6..63d2ebc 100644
--- a/arch/x86/kernel/devicetree.c
+++ b/arch/x86/kernel/devicetree.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -270,14 +271,15 @@ static void __init x86_flattree_get_config(void)
map_len = max(PAGE_SIZE - (initial_dtb & ~PAGE_MASK), (u64)128);
- initial_boot_params = dt = early_memremap(initial_dtb, map_len);
- size = of_get_flat_dt_size();
+ dt = early_memremap(initial_dtb, map_len);
+ size = fdt_totalsize(dt);
if (map_len < size) {
early_memunmap(dt, map_len);
- initial_boot_params = dt = early_memremap(initial_dtb, size);
+ dt = early_memremap(initial_dtb, size);
map_len = size;
}
+ early_init_dt_verify(dt);
unflatten_and_copy_device_tree();
early_memunmap(dt, map_len);
}
--
2.7.4
[PATCH v4 1/4] x86/devicetree: Initialize device tree before using it
Commit 08d53aa58cb162e6 ("of/fdt: export fdt blob as /sys/firmware/fdt")
adds CRC32 calculation in early_init_dt_verify() and checking in late
initcall of_fdt_raw_init(), making early_init_dt_verify() mandatory.
Required call to early_init_dt_verify() was not added to the x86-specific
implementation, causing failure to create sysfs entry in of_fdt_raw_init().
Signed-off-by: Ivan Gorinov
---
arch/x86/kernel/devicetree.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c
index 25de5f6..63d2ebc 100644
--- a/arch/x86/kernel/devicetree.c
+++ b/arch/x86/kernel/devicetree.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -270,14 +271,15 @@ static void __init x86_flattree_get_config(void)
map_len = max(PAGE_SIZE - (initial_dtb & ~PAGE_MASK), (u64)128);
- initial_boot_params = dt = early_memremap(initial_dtb, map_len);
- size = of_get_flat_dt_size();
+ dt = early_memremap(initial_dtb, map_len);
+ size = fdt_totalsize(dt);
if (map_len < size) {
early_memunmap(dt, map_len);
- initial_boot_params = dt = early_memremap(initial_dtb, size);
+ dt = early_memremap(initial_dtb, size);
map_len = size;
}
+ early_init_dt_verify(dt);
unflatten_and_copy_device_tree();
early_memunmap(dt, map_len);
}
--
2.7.4
[PATCH v4 0/4] x86/devicetree: Re-enable x86-specific implementation
Fixing x86-specific DT implementation in the kernel allows reusing most of firmware code for SoC that have ARM core replaced with x86, e.g. SC9853i. Changes since v3: * Using fdt_totalsize() to get DTB size before remapping instead of setting initial_boot_params and calling of_get_flat_dt_size() before early_init_dt_verify(); * Adding new intel,apic-id property to the documentation. Changes since v2: * WARN_ON_ONCE instead of WARN_ON to aviod multiple warnings when APIC ID is missing in CPU device tree nodes * Switched to Mutt because of white space issues: "Preformatted" paragraph style does not work in Evolution 3.18.5.2 Changes since first version: * Splitting a single patch into three parts Ivan Gorinov (4): x86/devicetree: Initialize device tree before using it x86/devicetree: Fix device IRQ settings in DT of: Documentation: Add x86 local APIC ID property x86/devicetree: Enable multiprocessing in DT Documentation/devicetree/bindings/x86/ce4100.txt | 6 +++ arch/x86/kernel/devicetree.c | 48 +++- 2 files changed, 44 insertions(+), 10 deletions(-) -- 2.7.4
[PATCH v4 0/4] x86/devicetree: Re-enable x86-specific implementation
Fixing x86-specific DT implementation in the kernel allows reusing most of firmware code for SoC that have ARM core replaced with x86, e.g. SC9853i. Changes since v3: * Using fdt_totalsize() to get DTB size before remapping instead of setting initial_boot_params and calling of_get_flat_dt_size() before early_init_dt_verify(); * Adding new intel,apic-id property to the documentation. Changes since v2: * WARN_ON_ONCE instead of WARN_ON to aviod multiple warnings when APIC ID is missing in CPU device tree nodes * Switched to Mutt because of white space issues: "Preformatted" paragraph style does not work in Evolution 3.18.5.2 Changes since first version: * Splitting a single patch into three parts Ivan Gorinov (4): x86/devicetree: Initialize device tree before using it x86/devicetree: Fix device IRQ settings in DT of: Documentation: Add x86 local APIC ID property x86/devicetree: Enable multiprocessing in DT Documentation/devicetree/bindings/x86/ce4100.txt | 6 +++ arch/x86/kernel/devicetree.c | 48 +++- 2 files changed, 44 insertions(+), 10 deletions(-) -- 2.7.4
[PATCH v3 2/3] x86: devicetree: enable multiprocessing in DT
Adding code to register the processors described in Device Tree.
APIC ID is specified in 'intel-apic_id' propery as used in U-Boot.
First address specified in 'reg' is used as default APIC ID.
Signed-off-by: Ivan Gorinov <ivan.gori...@intel.com>
---
arch/x86/kernel/devicetree.c | 26 --
1 file changed, 24 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c
index 44189ee..ef1cd85 100644
--- a/arch/x86/kernel/devicetree.c
+++ b/arch/x86/kernel/devicetree.c
@@ -130,6 +130,29 @@ static void __init dtb_setup_hpet(void)
#endif
}
+static void __init dtb_cpu_setup(void)
+{
+ struct device_node *dn;
+ struct resource r;
+ const void *prop;
+ int apic_id, version;
+ int ret;
+
+ version = GET_APIC_VERSION(apic_read(APIC_LVR));
+ for_each_node_by_type(dn, "cpu") {
+ prop = of_get_property(dn, "intel,apic-id", NULL);
+ if (prop) {
+ apic_id = be32_to_cpup(prop);
+ } else {
+ ret = of_address_to_resource(dn, 0, );
+ if (WARN_ON_ONCE(ret))
+ continue;
+ apic_id = r.start;
+ }
+ generic_processor_info(apic_id, version);
+ }
+}
+
static void __init dtb_lapic_setup(void)
{
#ifdef CONFIG_X86_LOCAL_APIC
@@ -153,8 +176,6 @@ static void __init dtb_lapic_setup(void)
smp_found_config = 1;
pic_mode = 1;
register_lapic_address(r.start);
- generic_processor_info(boot_cpu_physical_apicid,
- GET_APIC_VERSION(apic_read(APIC_LVR)));
#endif
}
@@ -256,6 +277,7 @@ static void __init dtb_ioapic_setup(void) {}
static void __init dtb_apic_setup(void)
{
dtb_lapic_setup();
+ dtb_cpu_setup();
dtb_ioapic_setup();
}
--
2.7.4
[PATCH v3 2/3] x86: devicetree: enable multiprocessing in DT
Adding code to register the processors described in Device Tree.
APIC ID is specified in 'intel-apic_id' propery as used in U-Boot.
First address specified in 'reg' is used as default APIC ID.
Signed-off-by: Ivan Gorinov
---
arch/x86/kernel/devicetree.c | 26 --
1 file changed, 24 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c
index 44189ee..ef1cd85 100644
--- a/arch/x86/kernel/devicetree.c
+++ b/arch/x86/kernel/devicetree.c
@@ -130,6 +130,29 @@ static void __init dtb_setup_hpet(void)
#endif
}
+static void __init dtb_cpu_setup(void)
+{
+ struct device_node *dn;
+ struct resource r;
+ const void *prop;
+ int apic_id, version;
+ int ret;
+
+ version = GET_APIC_VERSION(apic_read(APIC_LVR));
+ for_each_node_by_type(dn, "cpu") {
+ prop = of_get_property(dn, "intel,apic-id", NULL);
+ if (prop) {
+ apic_id = be32_to_cpup(prop);
+ } else {
+ ret = of_address_to_resource(dn, 0, );
+ if (WARN_ON_ONCE(ret))
+ continue;
+ apic_id = r.start;
+ }
+ generic_processor_info(apic_id, version);
+ }
+}
+
static void __init dtb_lapic_setup(void)
{
#ifdef CONFIG_X86_LOCAL_APIC
@@ -153,8 +176,6 @@ static void __init dtb_lapic_setup(void)
smp_found_config = 1;
pic_mode = 1;
register_lapic_address(r.start);
- generic_processor_info(boot_cpu_physical_apicid,
- GET_APIC_VERSION(apic_read(APIC_LVR)));
#endif
}
@@ -256,6 +277,7 @@ static void __init dtb_ioapic_setup(void) {}
static void __init dtb_apic_setup(void)
{
dtb_lapic_setup();
+ dtb_cpu_setup();
dtb_ioapic_setup();
}
--
2.7.4
[PATCH v3 3/3] x86: devicetree: fix device IRQ settings in DT
IRQ parameters for SoC devices connected directly to I/O APIC lines
(without PCI IRQ routing) may be specified in the Device Tree.
Called from DT IRQ parser, irq_create_fwspec_mapping() calls
irq_domain_alloc_irqs() with a pointer to irq_fwspec structure as @arg.
But x86-specific DT IRQ allocation code casts @arg to of_phandle_args
structure pointer and crashes trying to read IRQ parameters.
Signed-off-by: Ivan Gorinov <ivan.gori...@intel.com>
---
arch/x86/kernel/devicetree.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c
index ef1cd85..b8b5874 100644
--- a/arch/x86/kernel/devicetree.c
+++ b/arch/x86/kernel/devicetree.c
@@ -215,19 +215,22 @@ static struct of_ioapic_type of_ioapic_type[] =
static int dt_irqdomain_alloc(struct irq_domain *domain, unsigned int virq,
unsigned int nr_irqs, void *arg)
{
- struct of_phandle_args *irq_data = (void *)arg;
+ struct irq_fwspec *fwspec = (struct irq_fwspec *)arg;
struct of_ioapic_type *it;
struct irq_alloc_info tmp;
+ int type_index;
- if (WARN_ON(irq_data->args_count < 2))
+ if (WARN_ON(fwspec->param_count < 2))
return -EINVAL;
- if (irq_data->args[1] >= ARRAY_SIZE(of_ioapic_type))
+
+ type_index = fwspec->param[1];
+ if (type_index >= ARRAY_SIZE(of_ioapic_type))
return -EINVAL;
- it = _ioapic_type[irq_data->args[1]];
+ it = _ioapic_type[type_index];
ioapic_set_alloc_attr(, NUMA_NO_NODE, it->trigger, it->polarity);
tmp.ioapic_id = mpc_ioapic_id(mp_irqdomain_ioapic_idx(domain));
- tmp.ioapic_pin = irq_data->args[0];
+ tmp.ioapic_pin = fwspec->param[0];
return mp_irqdomain_alloc(domain, virq, nr_irqs, );
}
--
2.7.4
[PATCH v3 3/3] x86: devicetree: fix device IRQ settings in DT
IRQ parameters for SoC devices connected directly to I/O APIC lines
(without PCI IRQ routing) may be specified in the Device Tree.
Called from DT IRQ parser, irq_create_fwspec_mapping() calls
irq_domain_alloc_irqs() with a pointer to irq_fwspec structure as @arg.
But x86-specific DT IRQ allocation code casts @arg to of_phandle_args
structure pointer and crashes trying to read IRQ parameters.
Signed-off-by: Ivan Gorinov
---
arch/x86/kernel/devicetree.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c
index ef1cd85..b8b5874 100644
--- a/arch/x86/kernel/devicetree.c
+++ b/arch/x86/kernel/devicetree.c
@@ -215,19 +215,22 @@ static struct of_ioapic_type of_ioapic_type[] =
static int dt_irqdomain_alloc(struct irq_domain *domain, unsigned int virq,
unsigned int nr_irqs, void *arg)
{
- struct of_phandle_args *irq_data = (void *)arg;
+ struct irq_fwspec *fwspec = (struct irq_fwspec *)arg;
struct of_ioapic_type *it;
struct irq_alloc_info tmp;
+ int type_index;
- if (WARN_ON(irq_data->args_count < 2))
+ if (WARN_ON(fwspec->param_count < 2))
return -EINVAL;
- if (irq_data->args[1] >= ARRAY_SIZE(of_ioapic_type))
+
+ type_index = fwspec->param[1];
+ if (type_index >= ARRAY_SIZE(of_ioapic_type))
return -EINVAL;
- it = _ioapic_type[irq_data->args[1]];
+ it = _ioapic_type[type_index];
ioapic_set_alloc_attr(, NUMA_NO_NODE, it->trigger, it->polarity);
tmp.ioapic_id = mpc_ioapic_id(mp_irqdomain_ioapic_idx(domain));
- tmp.ioapic_pin = irq_data->args[0];
+ tmp.ioapic_pin = fwspec->param[0];
return mp_irqdomain_alloc(domain, virq, nr_irqs, );
}
--
2.7.4
[PATCH v3 1/3] x86: devicetree: call early_init_dt_verify()
Call to early_init_dt_verify() is required to prepare DTB data. It was called from arch/arm and arch/powerpc, but not arch/x86. Signed-off-by: Ivan Gorinov <ivan.gori...@intel.com> --- arch/x86/kernel/devicetree.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c index 25de5f6..44189ee 100644 --- a/arch/x86/kernel/devicetree.c +++ b/arch/x86/kernel/devicetree.c @@ -278,6 +278,7 @@ static void __init x86_flattree_get_config(void) map_len = size; } + early_init_dt_verify(dt); unflatten_and_copy_device_tree(); early_memunmap(dt, map_len); } -- 2.7.4
[PATCH v3 1/3] x86: devicetree: call early_init_dt_verify()
Call to early_init_dt_verify() is required to prepare DTB data. It was called from arch/arm and arch/powerpc, but not arch/x86. Signed-off-by: Ivan Gorinov --- arch/x86/kernel/devicetree.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c index 25de5f6..44189ee 100644 --- a/arch/x86/kernel/devicetree.c +++ b/arch/x86/kernel/devicetree.c @@ -278,6 +278,7 @@ static void __init x86_flattree_get_config(void) map_len = size; } + early_init_dt_verify(dt); unflatten_and_copy_device_tree(); early_memunmap(dt, map_len); } -- 2.7.4
[PATCH v3 0/3] x86: devicetree: re-enable x86-specific implementation
Fixing x86-specific DT implementation in the kernel allows reusing most of firmware code for SoC that have ARM core replaced with x86, e.g. SC9853i. Changes since v2: * WARN_ON_ONCE instead of WARN_ON to aviod multiple warnings when APIC ID is missing in CPU device tree nodes * Switched to Mutt because of white space issues: "Preformatted" paragraph style does not work in Evolution 3.18.5.2 Changes since first version: * Splitting a single patch into three parts Ivan Gorinov (3): x86: devicetree: call early_init_dt_verify() x86: devicetree: enable multiprocessing in DT x86: devicetree: fix device IRQ settings in DT arch/x86/kernel/devicetree.c | 40 +--- 1 file changed, 33 insertions(+), 7 deletions(-) -- 2.7.4
[PATCH v3 0/3] x86: devicetree: re-enable x86-specific implementation
Fixing x86-specific DT implementation in the kernel allows reusing most of firmware code for SoC that have ARM core replaced with x86, e.g. SC9853i. Changes since v2: * WARN_ON_ONCE instead of WARN_ON to aviod multiple warnings when APIC ID is missing in CPU device tree nodes * Switched to Mutt because of white space issues: "Preformatted" paragraph style does not work in Evolution 3.18.5.2 Changes since first version: * Splitting a single patch into three parts Ivan Gorinov (3): x86: devicetree: call early_init_dt_verify() x86: devicetree: enable multiprocessing in DT x86: devicetree: fix device IRQ settings in DT arch/x86/kernel/devicetree.c | 40 +--- 1 file changed, 33 insertions(+), 7 deletions(-) -- 2.7.4
[PATCH v2 3/3] x86: devicetree: fix device IRQ settings in DT
IRQ parameters for SoC devices connected directly to I/O APIC lines
(without PCI IRQ routing) may be specified in the Device Tree.
Called from DT IRQ parser, irq_create_fwspec_mapping() calls
irq_domain_alloc_irqs() with a pointer to irq_fwspec structure as @arg.
But x86-specific DT IRQ allocation code casts @arg to of_phandle_args
structure pointer and crashes trying to read IRQ parameters.
Signed-off-by: Ivan Gorinov <ivan.gori...@intel.com>
---
arch/x86/kernel/devicetree.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c
index ef1cd85..b8b5874 100644
--- a/arch/x86/kernel/devicetree.c
+++ b/arch/x86/kernel/devicetree.c
@@ -215,19 +215,22 @@ static struct of_ioapic_type of_ioapic_type[] =
static int dt_irqdomain_alloc(struct irq_domain *domain, unsigned int virq,
unsigned int nr_irqs, void *arg)
{
- struct of_phandle_args *irq_data = (void *)arg;
+ struct irq_fwspec *fwspec = (struct irq_fwspec *)arg;
struct of_ioapic_type *it;
struct irq_alloc_info tmp;
+ int type_index;
- if (WARN_ON(irq_data->args_count < 2))
+ if (WARN_ON(fwspec->param_count < 2))
return -EINVAL;
- if (irq_data->args[1] >= ARRAY_SIZE(of_ioapic_type))
+
+ type_index = fwspec->param[1];
+ if (type_index >= ARRAY_SIZE(of_ioapic_type))
return -EINVAL;
- it = _ioapic_type[irq_data->args[1]];
+ it = _ioapic_type[type_index];
ioapic_set_alloc_attr(, NUMA_NO_NODE, it->trigger, it->polarity);
tmp.ioapic_id = mpc_ioapic_id(mp_irqdomain_ioapic_idx(domain));
- tmp.ioapic_pin = irq_data->args[0];
+ tmp.ioapic_pin = fwspec->param[0];
return mp_irqdomain_alloc(domain, virq, nr_irqs, );
}
--
2.7.4
[PATCH v2 3/3] x86: devicetree: fix device IRQ settings in DT
IRQ parameters for SoC devices connected directly to I/O APIC lines
(without PCI IRQ routing) may be specified in the Device Tree.
Called from DT IRQ parser, irq_create_fwspec_mapping() calls
irq_domain_alloc_irqs() with a pointer to irq_fwspec structure as @arg.
But x86-specific DT IRQ allocation code casts @arg to of_phandle_args
structure pointer and crashes trying to read IRQ parameters.
Signed-off-by: Ivan Gorinov
---
arch/x86/kernel/devicetree.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c
index ef1cd85..b8b5874 100644
--- a/arch/x86/kernel/devicetree.c
+++ b/arch/x86/kernel/devicetree.c
@@ -215,19 +215,22 @@ static struct of_ioapic_type of_ioapic_type[] =
static int dt_irqdomain_alloc(struct irq_domain *domain, unsigned int virq,
unsigned int nr_irqs, void *arg)
{
- struct of_phandle_args *irq_data = (void *)arg;
+ struct irq_fwspec *fwspec = (struct irq_fwspec *)arg;
struct of_ioapic_type *it;
struct irq_alloc_info tmp;
+ int type_index;
- if (WARN_ON(irq_data->args_count < 2))
+ if (WARN_ON(fwspec->param_count < 2))
return -EINVAL;
- if (irq_data->args[1] >= ARRAY_SIZE(of_ioapic_type))
+
+ type_index = fwspec->param[1];
+ if (type_index >= ARRAY_SIZE(of_ioapic_type))
return -EINVAL;
- it = _ioapic_type[irq_data->args[1]];
+ it = _ioapic_type[type_index];
ioapic_set_alloc_attr(, NUMA_NO_NODE, it->trigger, it->polarity);
tmp.ioapic_id = mpc_ioapic_id(mp_irqdomain_ioapic_idx(domain));
- tmp.ioapic_pin = irq_data->args[0];
+ tmp.ioapic_pin = fwspec->param[0];
return mp_irqdomain_alloc(domain, virq, nr_irqs, );
}
--
2.7.4
[PATCH v2 0/3] x86: devicetree: re-enable x86-specific implementation
Fixing x86-specific DT implementation in the kernel allows reusing most of firmware code for SoC that have ARM core replaced with x86, e.g. SC9853i. Changes since first version: * Splitting a single patch into three parts Ivan Gorinov (3): x86: devicetree: call early_init_dt_verify() x86: devicetree: enable multiprocessing in DT x86: devicetree: fix device IRQ settings in DT arch/x86/kernel/devicetree.c | 40 +--- 1 file changed, 33 insertions(+), 7 deletions(-) -- 2.7.4
[PATCH v2 0/3] x86: devicetree: re-enable x86-specific implementation
Fixing x86-specific DT implementation in the kernel allows reusing most of firmware code for SoC that have ARM core replaced with x86, e.g. SC9853i. Changes since first version: * Splitting a single patch into three parts Ivan Gorinov (3): x86: devicetree: call early_init_dt_verify() x86: devicetree: enable multiprocessing in DT x86: devicetree: fix device IRQ settings in DT arch/x86/kernel/devicetree.c | 40 +--- 1 file changed, 33 insertions(+), 7 deletions(-) -- 2.7.4
[PATCH v2 1/3] x86: devicetree: call early_init_dt_verify()
Call to early_init_dt_verify() is required to prepare DTB data. It was called from arch/arm and arch/powerpc, but not arch/x86. Signed-off-by: Ivan Gorinov <ivan.gori...@intel.com> --- arch/x86/kernel/devicetree.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c index 25de5f6..44189ee 100644 --- a/arch/x86/kernel/devicetree.c +++ b/arch/x86/kernel/devicetree.c @@ -278,6 +278,7 @@ static void __init x86_flattree_get_config(void) map_len = size; } + early_init_dt_verify(dt); unflatten_and_copy_device_tree(); early_memunmap(dt, map_len); } -- 2.7.4
[PATCH v2 2/3] x86: devicetree: enable multiprocessing in DT
Adding code to register processors described in Device Tree.
APIC ID is specified in 'intel-apic_id' propery as used in U-Boot.
First address specified in 'reg' is used as default APIC ID.
Signed-off-by: Ivan Gorinov <ivan.gori...@intel.com>
---
arch/x86/kernel/devicetree.c | 26 --
1 file changed, 24 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c
index 44189ee..ef1cd85 100644
--- a/arch/x86/kernel/devicetree.c
+++ b/arch/x86/kernel/devicetree.c
@@ -130,6 +130,29 @@ static void __init dtb_setup_hpet(void)
#endif
}
+static void __init dtb_cpu_setup(void)
+{
+ struct device_node *dn;
+ struct resource r;
+ const void *prop;
+ int apic_id, version;
+ int ret;
+
+ version = GET_APIC_VERSION(apic_read(APIC_LVR));
+ for_each_node_by_type(dn, "cpu") {
+ prop = of_get_property(dn, "intel,apic-id", NULL);
+ if (prop) {
+ apic_id = be32_to_cpup(prop);
+ } else {
+ ret = of_address_to_resource(dn, 0, );
+ if (WARN_ON(ret))
+ continue;
+ apic_id = r.start;
+ }
+ generic_processor_info(apic_id, version);
+ }
+}
+
static void __init dtb_lapic_setup(void)
{
#ifdef CONFIG_X86_LOCAL_APIC
@@ -153,8 +176,6 @@ static void __init dtb_lapic_setup(void)
smp_found_config = 1;
pic_mode = 1;
register_lapic_address(r.start);
- generic_processor_info(boot_cpu_physical_apicid,
- GET_APIC_VERSION(apic_read(APIC_LVR)));
#endif
}
@@ -256,6 +277,7 @@ static void __init dtb_ioapic_setup(void) {}
static void __init dtb_apic_setup(void)
{
dtb_lapic_setup();
+ dtb_cpu_setup();
dtb_ioapic_setup();
}
--
2.7.4
[PATCH v2 1/3] x86: devicetree: call early_init_dt_verify()
Call to early_init_dt_verify() is required to prepare DTB data. It was called from arch/arm and arch/powerpc, but not arch/x86. Signed-off-by: Ivan Gorinov --- arch/x86/kernel/devicetree.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c index 25de5f6..44189ee 100644 --- a/arch/x86/kernel/devicetree.c +++ b/arch/x86/kernel/devicetree.c @@ -278,6 +278,7 @@ static void __init x86_flattree_get_config(void) map_len = size; } + early_init_dt_verify(dt); unflatten_and_copy_device_tree(); early_memunmap(dt, map_len); } -- 2.7.4
[PATCH v2 2/3] x86: devicetree: enable multiprocessing in DT
Adding code to register processors described in Device Tree.
APIC ID is specified in 'intel-apic_id' propery as used in U-Boot.
First address specified in 'reg' is used as default APIC ID.
Signed-off-by: Ivan Gorinov
---
arch/x86/kernel/devicetree.c | 26 --
1 file changed, 24 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c
index 44189ee..ef1cd85 100644
--- a/arch/x86/kernel/devicetree.c
+++ b/arch/x86/kernel/devicetree.c
@@ -130,6 +130,29 @@ static void __init dtb_setup_hpet(void)
#endif
}
+static void __init dtb_cpu_setup(void)
+{
+ struct device_node *dn;
+ struct resource r;
+ const void *prop;
+ int apic_id, version;
+ int ret;
+
+ version = GET_APIC_VERSION(apic_read(APIC_LVR));
+ for_each_node_by_type(dn, "cpu") {
+ prop = of_get_property(dn, "intel,apic-id", NULL);
+ if (prop) {
+ apic_id = be32_to_cpup(prop);
+ } else {
+ ret = of_address_to_resource(dn, 0, );
+ if (WARN_ON(ret))
+ continue;
+ apic_id = r.start;
+ }
+ generic_processor_info(apic_id, version);
+ }
+}
+
static void __init dtb_lapic_setup(void)
{
#ifdef CONFIG_X86_LOCAL_APIC
@@ -153,8 +176,6 @@ static void __init dtb_lapic_setup(void)
smp_found_config = 1;
pic_mode = 1;
register_lapic_address(r.start);
- generic_processor_info(boot_cpu_physical_apicid,
- GET_APIC_VERSION(apic_read(APIC_LVR)));
#endif
}
@@ -256,6 +277,7 @@ static void __init dtb_ioapic_setup(void) {}
static void __init dtb_apic_setup(void)
{
dtb_lapic_setup();
+ dtb_cpu_setup();
dtb_ioapic_setup();
}
--
2.7.4
[PATCH] x86: devicetree: enable multiprocessing and interrupt setting in DT
The x86-specific Device Tree implementation only supported single CPU,
and IRQ allocation from DT parameters was broken in recent versions.
This change enables multiprocessing and fixes broken IRQ allocation.
Signed-off-by: Ivan Gorinov <ivan.gori...@intel.com>
---
arch/x86/kernel/devicetree.c | 41 ++---
1 file changed, 34 insertions(+), 7 deletions(-)
diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c
index 25de5f6..f885eab 100644
--- a/arch/x86/kernel/devicetree.c
+++ b/arch/x86/kernel/devicetree.c
@@ -130,6 +130,29 @@ static void __init dtb_setup_hpet(void)
#endif
}
+static void __init dtb_cpu_setup(void)
+{
+ struct device_node *dn;
+ struct resource r;
+ const void *prop;
+ int apic_id, version;
+ int ret;
+
+ version = GET_APIC_VERSION(apic_read(APIC_LVR));
+ for_each_node_by_type(dn, "cpu") {
+ prop = of_get_property(dn, "intel,apic-id", NULL);
+ if (prop) {
+ apic_id = be32_to_cpup(prop);
+ } else {
+ ret = of_address_to_resource(dn, 0, );
+ if (WARN_ON(ret))
+ continue;
+ apic_id = r.start;
+ }
+ generic_processor_info(apic_id, version);
+ }
+}
+
static void __init dtb_lapic_setup(void)
{
#ifdef CONFIG_X86_LOCAL_APIC
@@ -153,8 +176,6 @@ static void __init dtb_lapic_setup(void)
smp_found_config = 1;
pic_mode = 1;
register_lapic_address(r.start);
- generic_processor_info(boot_cpu_physical_apicid,
- GET_APIC_VERSION(apic_read(APIC_LVR)));
#endif
}
@@ -194,19 +215,22 @@ static struct of_ioapic_type of_ioapic_type[] =
static int dt_irqdomain_alloc(struct irq_domain *domain, unsigned int virq,
unsigned int nr_irqs, void *arg)
{
- struct of_phandle_args *irq_data = (void *)arg;
+ struct irq_fwspec *fwspec = (struct irq_fwspec *)arg;
struct of_ioapic_type *it;
struct irq_alloc_info tmp;
+ int type_index;
- if (WARN_ON(irq_data->args_count < 2))
+ if (WARN_ON(fwspec->param_count < 2))
return -EINVAL;
- if (irq_data->args[1] >= ARRAY_SIZE(of_ioapic_type))
+
+ type_index = fwspec->param[1];
+ if (type_index >= ARRAY_SIZE(of_ioapic_type))
return -EINVAL;
- it = _ioapic_type[irq_data->args[1]];
+ it = _ioapic_type[type_index];
ioapic_set_alloc_attr(, NUMA_NO_NODE, it->trigger, it->polarity);
tmp.ioapic_id = mpc_ioapic_id(mp_irqdomain_ioapic_idx(domain));
- tmp.ioapic_pin = irq_data->args[0];
+ tmp.ioapic_pin = fwspec->param[0];
return mp_irqdomain_alloc(domain, virq, nr_irqs, );
}
@@ -256,6 +280,7 @@ static void __init dtb_ioapic_setup(void) {}
static void __init dtb_apic_setup(void)
{
dtb_lapic_setup();
+ dtb_cpu_setup();
dtb_ioapic_setup();
}
@@ -278,6 +303,8 @@ static void __init x86_flattree_get_config(void)
map_len = size;
}
+ early_init_dt_verify(dt);
+
unflatten_and_copy_device_tree();
early_memunmap(dt, map_len);
}
--
2.7.4
[PATCH] x86: devicetree: enable multiprocessing and interrupt setting in DT
The x86-specific Device Tree implementation only supported single CPU,
and IRQ allocation from DT parameters was broken in recent versions.
This change enables multiprocessing and fixes broken IRQ allocation.
Signed-off-by: Ivan Gorinov
---
arch/x86/kernel/devicetree.c | 41 ++---
1 file changed, 34 insertions(+), 7 deletions(-)
diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c
index 25de5f6..f885eab 100644
--- a/arch/x86/kernel/devicetree.c
+++ b/arch/x86/kernel/devicetree.c
@@ -130,6 +130,29 @@ static void __init dtb_setup_hpet(void)
#endif
}
+static void __init dtb_cpu_setup(void)
+{
+ struct device_node *dn;
+ struct resource r;
+ const void *prop;
+ int apic_id, version;
+ int ret;
+
+ version = GET_APIC_VERSION(apic_read(APIC_LVR));
+ for_each_node_by_type(dn, "cpu") {
+ prop = of_get_property(dn, "intel,apic-id", NULL);
+ if (prop) {
+ apic_id = be32_to_cpup(prop);
+ } else {
+ ret = of_address_to_resource(dn, 0, );
+ if (WARN_ON(ret))
+ continue;
+ apic_id = r.start;
+ }
+ generic_processor_info(apic_id, version);
+ }
+}
+
static void __init dtb_lapic_setup(void)
{
#ifdef CONFIG_X86_LOCAL_APIC
@@ -153,8 +176,6 @@ static void __init dtb_lapic_setup(void)
smp_found_config = 1;
pic_mode = 1;
register_lapic_address(r.start);
- generic_processor_info(boot_cpu_physical_apicid,
- GET_APIC_VERSION(apic_read(APIC_LVR)));
#endif
}
@@ -194,19 +215,22 @@ static struct of_ioapic_type of_ioapic_type[] =
static int dt_irqdomain_alloc(struct irq_domain *domain, unsigned int virq,
unsigned int nr_irqs, void *arg)
{
- struct of_phandle_args *irq_data = (void *)arg;
+ struct irq_fwspec *fwspec = (struct irq_fwspec *)arg;
struct of_ioapic_type *it;
struct irq_alloc_info tmp;
+ int type_index;
- if (WARN_ON(irq_data->args_count < 2))
+ if (WARN_ON(fwspec->param_count < 2))
return -EINVAL;
- if (irq_data->args[1] >= ARRAY_SIZE(of_ioapic_type))
+
+ type_index = fwspec->param[1];
+ if (type_index >= ARRAY_SIZE(of_ioapic_type))
return -EINVAL;
- it = _ioapic_type[irq_data->args[1]];
+ it = _ioapic_type[type_index];
ioapic_set_alloc_attr(, NUMA_NO_NODE, it->trigger, it->polarity);
tmp.ioapic_id = mpc_ioapic_id(mp_irqdomain_ioapic_idx(domain));
- tmp.ioapic_pin = irq_data->args[0];
+ tmp.ioapic_pin = fwspec->param[0];
return mp_irqdomain_alloc(domain, virq, nr_irqs, );
}
@@ -256,6 +280,7 @@ static void __init dtb_ioapic_setup(void) {}
static void __init dtb_apic_setup(void)
{
dtb_lapic_setup();
+ dtb_cpu_setup();
dtb_ioapic_setup();
}
@@ -278,6 +303,8 @@ static void __init x86_flattree_get_config(void)
map_len = size;
}
+ early_init_dt_verify(dt);
+
unflatten_and_copy_device_tree();
early_memunmap(dt, map_len);
}
--
2.7.4
