Re: [PATCH 2/2] mips: generic: allow not building DTB in

2018-06-20 Thread James Hogan
On Wed, Apr 25, 2018 at 11:16:07PM +0200, Alexandre Belloni wrote: > Allow not building any DTB in the generic kernel so it gets smaller. This > is necessary for ocelot because it can be built as a legacy platform that > needs a built-in DTB and it can also handle a separate DTB once it is >

Re: [PATCH 1/2] mips: mscc: build FIT image for Ocelot

2018-06-20 Thread James Hogan
> + from Microsemi in the FIT kernel image. > + This require u-boot on the platform. nit: s/require/requires/ Reviewed-by: James Hogan Cheers James signature.asc Description: PGP signature

Re: [PATCH v2] nds32: Fix build error caused by configuration flag rename

2018-06-15 Thread James Hogan
On Fri, Jun 15, 2018 at 02:12:58PM +0800, Greentime Hu wrote: > Thank you James and Guenter. > Should I pick it in my tree? It will be ok to put in your tree. :) > > Acked-by: Greentime Hu I think your tree makes most sense for this patch, since it only touches nds32 code and it was nds32 that

Re: [PATCH 4/4] rseq/selftests: Implement MIPS support

2018-06-15 Thread James Hogan
\ ARM doesn't do this for DEFINE_ABORT. Is it intentional that we do for MIPS? Otherwise this whole series looks reasonable to me, so feel free to add my rb on the whole series if you do apply youself: Reviewed-by: James Hogan Thanks James signature.asc Description: PGP signature

[PATCH v2] nds32: Fix build error caused by configuration flag rename

2018-06-14 Thread James Hogan
uot;) Signed-off-by: Guenter Roeck [jho...@kernel.org: Rename all 6 symbols, sort, update commit message] Signed-off-by: James Hogan Cc: Greentime Hu Cc: Vincent Chen Cc: Matt Redfearn Cc: Palmer Dabbelt --- Changes in v2: - Rename all 6 symbols, not just the 3 that caused build failures. - Sort sele

Re: [PATCH] nds32: Fix build error caused by incomplete configuration flag rename

2018-06-13 Thread James Hogan
On Wed, Jun 13, 2018 at 02:28:08PM -0700, Guenter Roeck wrote: > On Wed, Jun 13, 2018 at 10:06:13PM +0100, James Hogan wrote: > > Thanks Guenter, > > > > On Wed, Jun 13, 2018 at 12:43:52PM -0700, Guenter Roeck wrote: > > > GENERIC_ASHLDI3, GENERIC_ASHRDI3, an

Re: [PATCH] nds32: Fix build error caused by incomplete configuration flag rename

2018-06-13 Thread James Hogan
Thanks Guenter, On Wed, Jun 13, 2018 at 12:43:52PM -0700, Guenter Roeck wrote: > GENERIC_ASHLDI3, GENERIC_ASHRDI3, and GENERIC_LSHRDI3 were renamed to > GENERIC_LIB_ASHLDI3, GENERIC_LIB_ASHRDI3, and GENERIC_LIB_LSHRDI3 > without making the matching changes in arch/nds32. Well, thats a little

Re: [PATCH 3/7] MIPS: intel: Add initial support for Intel MIPS SoCs

2018-06-12 Thread James Hogan
Hi, Good to see this patch! On Tue, Jun 12, 2018 at 01:40:30PM +0800, Songjun Wu wrote: > diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms > index ac7ad54f984f..bcd647060f3e 100644 > --- a/arch/mips/Kbuild.platforms > +++ b/arch/mips/Kbuild.platforms > @@ -12,6 +12,7 @@

Re: [PATCH] MIPS: ptrace: Make FPU context layout comments match reality

2018-05-31 Thread James Hogan
On Tue, May 15, 2018 at 11:03:09PM +0100, Maciej W. Rozycki wrote: > Correct comments across ptrace(2) handlers about an FPU register context > layout discrepancy between MIPS I and later ISAs, which was fixed with > `linux-mips.org' (LMO) commit 42533948caac ("Major pile of FP emulator >

Re: [PATCH] MIPS: ptrace: Fix PTRACE_PEEKUSR requests for 64-bit FGRs

2018-05-31 Thread James Hogan
On Wed, May 16, 2018 at 04:39:58PM +0100, Maciej W. Rozycki wrote: > Use 64-bit accesses for 64-bit floating-point general registers with > PTRACE_PEEKUSR, removing the truncation of their upper halves in the > FR=1 mode, caused by commit bbd426f542cb ("MIPS: Simplify FP context > access"),

Re: [PATCH] MIPS: prctl: Disallow FRE without FR with PR_SET_FP_MODE requests

2018-05-31 Thread James Hogan
On Tue, May 15, 2018 at 11:04:44PM +0100, Maciej W. Rozycki wrote: > Having PR_FP_MODE_FRE (i.e. Config5.FRE) set without PR_FP_MODE_FR (i.e. > Status.FR) is not supported as the lone purpose of Config5.FRE is to > emulate Status.FR=0 handling on FPU hardware that has Status.FR=1 >

Re: [PATCH] MIPS: ptrace: Fix PTRACE_PEEKUSR requests for 64-bit FGRs

2018-05-24 Thread James Hogan
On Wed, May 16, 2018 at 04:39:58PM +0100, Maciej W. Rozycki wrote: > Use 64-bit accesses for 64-bit floating-point general registers with > PTRACE_PEEKUSR, removing the truncation of their upper halves in the > FR=1 mode, caused by commit bbd426f542cb ("MIPS: Simplify FP context > access"),

Re: [PATCH] MIPS: lantiq: gphy: Drop reboot/remove reset asserts

2018-05-24 Thread James Hogan
On Mon, May 21, 2018 at 05:39:32PM +0100, James Hogan wrote: > On Sun, Apr 08, 2018 at 10:30:03AM +0200, Mathias Kresin wrote: > > While doing a global software reset, these bits are not cleared and let > > some bootloader fail to initialise the GPHYs. The bootloader don't >

Re: [PATCH v1] MIPS: PCI: Use dev_printk() when possible

2018-05-23 Thread James Hogan
RN_ERR "PCI: Device %s not available " > -"because of resource collisions\n", > -pci_name(dev)); > + pci_err(dev, "can't enable device: resource > collisions\n"); The pedantic side of m

Re: [PATCH] MIPS: lantiq: gphy: Drop reboot/remove reset asserts

2018-05-21 Thread James Hogan
On Sun, Apr 08, 2018 at 10:30:03AM +0200, Mathias Kresin wrote: > While doing a global software reset, these bits are not cleared and let > some bootloader fail to initialise the GPHYs. The bootloader don't > expect the GPHYs in reset, as they aren't during power on. > > The asserts were a

Re: [PATCH v2 4/4] MIPS: memset.S: Add comments to fault fixup handlers

2018-05-21 Thread James Hogan
On Tue, Apr 17, 2018 at 04:40:03PM +0100, Matt Redfearn wrote: > diff --git a/arch/mips/lib/memset.S b/arch/mips/lib/memset.S > index 1cc306520a55..a06dabe99d4b 100644 > --- a/arch/mips/lib/memset.S > +++ b/arch/mips/lib/memset.S > @@ -231,16 +231,25 @@ > > #ifdef CONFIG_CPU_MIPSR6 >

Re: [PATCH 7/7] aio: implement io_pgetevents

2018-05-18 Thread James Hogan
Given this: On Wed, May 02, 2018 at 11:14:48PM +0200, Christoph Hellwig wrote: > +struct __aio_sigset { > + sigset_t __user *sigmask; > + size_t sigsetsize; > +}; and: > +asmlinkage long sys_io_pgetevents(aio_context_t ctx_id, > + long min_nr, > +

Re: [PATCH 1/6] MIPS: Move ehb() to barrier.h

2018-05-17 Thread James Hogan
On Fri, Jan 05, 2018 at 10:31:05AM +, Matt Redfearn wrote: > The current location of ehb() in mipsmtregs.h does not make sense, since > it is not strictly related to multi-threading, and may be used in code > which does not include mipsmtregs.h > arch/mips/include/asm/barrier.h| 13

Re: [PATCH v3 5/7] MIPS: perf: Allocate per-core counters on demand

2018-05-16 Thread James Hogan
On Fri, Apr 20, 2018 at 11:23:07AM +0100, Matt Redfearn wrote: > Previously when performance counters are per-core, rather than > per-thread, the number available were divided by 2 on detection, and the > counters used by each thread in a core were "swizzled" to ensure > separation. However, this

Re: [PATCH v3 4/7] MIPS: perf: Fix perf with MT counting other threads

2018-05-16 Thread James Hogan
On Fri, Apr 20, 2018 at 11:23:06AM +0100, Matt Redfearn wrote: > diff --git a/arch/mips/kernel/perf_event_mipsxx.c > b/arch/mips/kernel/perf_event_mipsxx.c > index 7e2b7d38a774..fe50986e83c6 100644 > --- a/arch/mips/kernel/perf_event_mipsxx.c > +++ b/arch/mips/kernel/perf_event_mipsxx.c > @@

Re: [PATCH] MIPS: Fix ptrace(2) PTRACE_PEEKUSR and PTRACE_POKEUSR accesses to o32 FGRs

2018-05-14 Thread James Hogan
On Mon, May 14, 2018 at 04:49:43PM +0100, Maciej W. Rozycki wrote: > Check the TIF_32BIT_FPREGS task setting of the tracee rather than the > tracer in determining the layout of floating-point general registers in > the floating-point context, correcting access to odd-numbered registers > for

Re: [PATCH 1/2] mips: xilfpga: stop generating useless dtb.o

2018-05-14 Thread James Hogan
On Wed, Apr 25, 2018 at 11:10:35PM +0200, Alexandre Belloni wrote: > a dtb.o is generated from nexys4ddr.dts but this is never used since it has > been moved to mips/generic with commit b35565bb16a5 ("MIPS: generic: Add > support > for MIPSfpga") > > Signed-off-by: Alexandre Belloni

Re: [PATCH] KVM: fix spelling mistake: "cop_unsuable" -> "cop_unusable"

2018-05-14 Thread James Hogan
On Mon, May 14, 2018 at 06:23:50PM +0100, Colin King wrote: > From: Colin Ian King > > Trivial fix to spelling mistake in debugfs_entries text > > Signed-off-by: Colin Ian King Adding KVM folk. Its a fairly trivial change so I'll just take

Re: [PATCH net-next v3 0/7] Microsemi Ocelot Ethernet switch support

2018-05-14 Thread James Hogan
On Mon, May 14, 2018 at 10:58:44PM +0200, Andrew Lunn wrote: > Hi Alexandre > > > > The ocelot dts changes are here for reference and should probably go > > through the MIPS tree once the bindings are accepted. > > For your next version, you probably want to drop those patches, so > that David

Re: [PATCH 1/7] i2c: i2c-gpio: move header to platform_data

2018-05-14 Thread James Hogan
gpr.c > > @@ -29,7 +29,7 @@ > > #include > > #include > > #include > > -#include > > +#include > > #include > > #include > > #include Acked-by: James Hogan <jho...@kernel.org> Cheers James signature.asc Description: PGP signature

Re: [PATCH v2] MIPS: c-r4k: fix data corruption related to cache coherence.

2018-05-11 Thread James Hogan
On Tue, May 08, 2018 at 11:22:36AM +1000, NeilBrown wrote: > On Mon, May 07 2018, James Hogan wrote: > > > On Mon, May 07, 2018 at 07:40:49AM +1000, NeilBrown wrote: > >> > >> Hi James, > >> this hasn't appear in linux-next yet, or in any branch > &

Re: [PATCH v2] MIPS: Fix build with DEBUG_ZBOOT and MACH_JZ4770

2018-05-11 Thread James Hogan
On Wed, Mar 28, 2018 at 05:38:12PM +0200, Paul Cercueil wrote: > The debug definitions were missing for MACH_JZ4770, resulting in a build > failure when DEBUG_ZBOOT was set. > > Since the UART addresses are the same across all Ingenic SoCs, we just > use a #ifdef CONFIG_MACH_INGENIC instead of

Re: [PATCH v3 5/8] MIPS: jz4740: dts: Add bindings for the jz4740-wdt driver

2018-05-11 Thread James Hogan
On Fri, May 11, 2018 at 02:14:16PM -0700, Guenter Roeck wrote: > On Fri, May 11, 2018 at 09:54:14PM +0100, James Hogan wrote: > > On Fri, May 11, 2018 at 01:17:04PM -0300, Paul Cercueil wrote: > > > Le 11 mai 2018 11:52, James Hogan <jho...@kernel.org> a écrit : > >

Re: [PATCH v3 5/8] MIPS: jz4740: dts: Add bindings for the jz4740-wdt driver

2018-05-11 Thread James Hogan
On Fri, May 11, 2018 at 01:17:04PM -0300, Paul Cercueil wrote: > Le 11 mai 2018 11:52, James Hogan <jho...@kernel.org> a écrit : > > Otherwise > > Acked-by: James Hogan <jho...@kernel.org> > > > > I'm happy to apply for 4.18 with that change if you w

Re: [PATCH v3 5/8] MIPS: jz4740: dts: Add bindings for the jz4740-wdt driver

2018-05-11 Thread James Hogan
since thats meant to summarise the body. > -struct platform_device jz4740_wdt_device = { There's an extern in arch/mips/include/asm/mach-jz4740/platform.h that should perhaps be removed also? Otherwise Acked-by: James Hogan <jho...@kernel.org> I'm happy to apply for 4.18 with that cha

Re: [PATCH] MIPS: VPE: fix spelling mistake: "uneeded" -> "unneeded"

2018-05-11 Thread James Hogan
On Thu, May 10, 2018 at 05:59:00PM +0100, Colin King wrote: > From: Colin Ian King > > Trivial fix to spelling mistake in pr_warn message text > > Signed-off-by: Colin Ian King > - pr_warn("VPE loader: elf size too big. Perhaps

Re: [PATCH v3 1/2] MIPS: Convert read_persistent_clock() to read_persistent_clock64()

2018-05-08 Thread James Hogan
On Mon, May 07, 2018 at 05:28:27PM +0800, Baolin Wang wrote: > Since struct timespec is not y2038 safe on 32bit machines, this patch > converts read_persistent_clock() to read_persistent_clock64() using > struct timespec64, as well as converting mktime() to mktime64(). > > Signed-off-by: Baolin

Re: [PATCH] MIPS: sni: Remove the read_persistent_clock()

2018-05-08 Thread James Hogan
On Thu, Apr 19, 2018 at 03:21:06PM +0800, Baolin Wang wrote: > The dummy read_persistent_clock() uses a timespec, which is not year 2038 > safe on 32bit systems. Thus remove this obsolete interface. > > Signed-off-by: Baolin Wang Thanks, Applied for 4.18 Cheers James

Re: [PATCH v2] MIPS: c-r4k: fix data corruption related to cache coherence.

2018-05-07 Thread James Hogan
On Mon, May 07, 2018 at 07:40:49AM +1000, NeilBrown wrote: > > Hi James, > this hasn't appear in linux-next yet, or in any branch > of >git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/mips.git > > Should I expect it to? Sorry Neil, I haven't applied it yet. I'm planning to get a few

Re: [PATCH v3 1/3] alpha: Use OPTIMIZE_INLINING instead of asm/compiler.h

2018-05-07 Thread James Hogan
On Sun, May 06, 2018 at 12:33:21PM -0700, Matt Turner wrote: > On Tue, Apr 17, 2018 at 3:11 AM, James Hogan <jho...@kernel.org> wrote: > > Use CONFIG_ARCH_SUPPORTS_OPTIMIZED_INLINING and CONFIG_OPTIMIZE_INLINING > > instead of undefining the inline macros in the alpha specif

Re: Introducing a nanoMIPS port for Linux

2018-05-04 Thread James Hogan
On Thu, May 03, 2018 at 06:40:07PM -0400, Arnd Bergmann wrote: > On Wed, May 2, 2018 at 5:51 PM, James Hogan <jho...@kernel.org> wrote: > > > Due to the binary incompatibility between previous MIPS architecture > > generations and nanoMIPS, and the significantly revamped

Introducing a nanoMIPS port for Linux

2018-05-02 Thread James Hogan
rton, James Hogan, Matt Redfearn, Marcin Nowakowski [1] https://www.mips.com/press/new-mips-i7200-processor-core-delivers-unmatched-performance-and-efficiency-for-advanced-lte5g-communications-and-networking-ic-designs/ signature.asc Description: Digital signature

Re: [PATCH] MIPS: c-r4k: fix data corruption related to cache coherence.

2018-04-25 Thread James Hogan
On Thu, Apr 26, 2018 at 08:00:18AM +1000, NeilBrown wrote: > On Wed, Apr 25 2018, James Hogan wrote: > > So I'm thinking "!mips_cm_present()" should probably be replaced with > > "!r4k_op_needs_ipi(R4K_INDEX)" (and the comment updated to mention that &g

Re: [PATCH] MIPS: c-r4k: fix data corruption related to cache coherence.

2018-04-25 Thread James Hogan
Hi NeilBrown, On Wed, Apr 25, 2018 at 02:08:15PM +1000, NeilBrown wrote: > Cc: sta...@vger.kernel.org (v4.8) FYI my preferred form of this is: Cc: # 4.8+ > /* >* Either no secondary cache or the available caches don't have the >* subset property

Re: [RFC PATCH] MIPS: Oprofile: Drop support

2018-04-24 Thread James Hogan
On Tue, Apr 24, 2018 at 01:55:54PM +0100, Matt Redfearn wrote: > Since it appears that MIPS oprofile support is currently broken, core > oprofile is not getting many updates and not as many architectures > implement support for it compared to perf, remove the MIPS support. That sounds reasonable

Re: [PATCH v2 1/4] MIPS: memset.S: Fix clobber of v1 in last_fixup

2018-04-18 Thread James Hogan
ady contained in > a2, the andi placing a value in v1 is not necessary and actively > harmful in clobbering v1. > > Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") > Cc: sta...@vger.kernel.org > Reported-by: James Hogan <jho...@kernel.org> > Signed-off-by: Matt Redfearn <matt.redfe...@mips.com> Thanks, Patches 1 & 2 applied to my fixes branch. Cheers James signature.asc Description: Digital signature

Re: [PATCH v2 1/6] MIPS: perf: More robustly probe for the presence of per-tc counters

2018-04-18 Thread James Hogan
On Thu, Apr 12, 2018 at 10:36:21AM +0100, Matt Redfearn wrote: > Processors implementing the MIPS MT ASE may have performance counters > implemented per core or per TC. Processors implemented by MIPS > Technologies signify presence per TC through a bit in the implementation > specific Config7

Re: [PATCH 1/2] MIPS: BCM47XX: Add support for Netgear WNR1000 V3

2018-04-18 Thread James Hogan
On Sun, Apr 08, 2018 at 10:57:32PM +0200, Rafał Miłecki wrote: > From: Rafał Miłecki > > This adds support for detecting this model board and registers some LEDs > and buttons. > > There are two uncommon things regarding this device: > 1) It can use two different "board_id" ID

Re: [PATCH v6 3/4] MIPS: vmlinuz: Use generic ashldi3

2018-04-17 Thread James Hogan
On Wed, Apr 11, 2018 at 08:50:18AM +0100, Matt Redfearn wrote: > diff --git a/arch/mips/boot/compressed/Makefile > b/arch/mips/boot/compressed/Makefile > index adce180f3ee4..e03f522c33ac 100644 > --- a/arch/mips/boot/compressed/Makefile > +++ b/arch/mips/boot/compressed/Makefile > @@ -46,9 +46,12

Re: [PATCH] MIPS: dts: avoid unneeded built-in.a creation in vendor DTS directories

2018-04-17 Thread James Hogan
On Tue, Apr 17, 2018 at 12:41:30AM +0900, Masahiro Yamada wrote: > arch/mips/boot/dts/Makefile collects objects from sub-directories > into built-in.a only when CONFIG_BUILTIN_DTB is enabled. Reflect > it also to the sub-directory Makefiles. This suppresses unneeded > built-in.a creation in

Re: [PATCH v3 2/3] compiler.h: Allow arch-specific overrides

2018-04-17 Thread James Hogan
Hi kbuild test robot, On Wed, Apr 18, 2018 at 03:19:47AM +0800, kbuild test robot wrote: >In file included from ./arch/x86/include/generated/asm/compiler.h:1:0, > from include/linux/compiler_types.h:58, > from :0: > >>

Re: [PATCH v3] MIPS: memset.S: Fix return of __clear_user from Lpartial_fixup

2018-04-17 Thread James Hogan
%d) returned %d\n", j, k); > } > } > Which now passes on Creator Ci40 (MIPS32) and Cavium Octeon II (MIPS64). > > Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") > Cc: sta...@vger.kernel.org > Suggested-by: James Hogan <jho...@kernel.org> >

[PATCH v3 0/3] MIPS: Override barrier_before_unreachable() to fix microMIPS

2018-04-17 Thread James Hogan
...@mips.com> Cc: Matthew Fortune <matthew.fort...@mips.com> Cc: Robert Suchanek <robert.sucha...@mips.com> Cc: linux-al...@vger.kernel.org Cc: linux-m...@linux-mips.org Cc: linux-a...@vger.kernel.org James Hogan (1): alpha: Use OPTIMIZE_INLINING instead of asm/compiler.h Pa

[PATCH v3 3/3] MIPS: Workaround GCC __builtin_unreachable reordering bug

2018-04-17 Thread James Hogan
[jho...@kernel.org: Forward port and use asm/compiler.h instead of asm/compiler-gcc.h] Signed-off-by: James Hogan <jho...@kernel.org> Reviewed-by: Paul Burton <paul.bur...@mips.com> Cc: Matthew Fortune <matthew.fort...@mips.com> Cc: Robert Suchanek <robert.sucha...@mips.com>

[PATCH v3 1/3] alpha: Use OPTIMIZE_INLINING instead of asm/compiler.h

2018-04-17 Thread James Hogan
44 +16 cap_capset 488 500 +12 nonroot_raised_pE.constprop 348 --348 Total: Before=5823709, After=5823625, chg -0.00% Suggested-by: Arnd Bergmann <a...@arndb.de> Signed-off-by: James Hogan <jho...@kernel.org> Cc

[PATCH v3 2/3] compiler.h: Allow arch-specific overrides

2018-04-17 Thread James Hogan
tead of asm/compiler-gcc.h] Signed-off-by: James Hogan <jho...@kernel.org> Reviewed-by: Paul Burton <paul.bur...@mips.com> Cc: Arnd Bergmann <a...@arndb.de> Cc: Ralf Baechle <r...@linux-mips.org> Cc: linux-a...@vger.kernel.org Cc: linux-m...@linux-mips.org --- Changes in v3 (Jame

Re: [PATCH 2/2] MIPS: memset.S: Fix return of __clear_user from Lpartial_fixup

2018-04-16 Thread James Hogan
On Thu, Mar 29, 2018 at 10:28:24AM +0100, Matt Redfearn wrote: > The __clear_user function is defined to return the number of bytes that > could not be cleared. From the underlying memset / bzero implementation > this means setting register a2 to that number on return. Currently if a > page fault

Re: [PATCH 1/2] MIPS: memset.S: EVA & fault support for small_memset

2018-04-16 Thread James Hogan
On Thu, Mar 29, 2018 at 10:28:23AM +0100, Matt Redfearn wrote: > @@ -260,6 +260,11 @@ > jr ra > andiv1, a2, STORMASK This patch looks good, well spotted! But whats that v1 write about? Any ideas? Seems to go back to the git epoch, and $3 isn't in the clobber

Re: [PATCH v4 2/2] MIPS: io: add a barrier after register read in readX()

2018-04-13 Thread James Hogan
On Thu, Apr 12, 2018 at 10:33:42PM -0400, Sinan Kaya wrote: > On 4/12/2018 10:30 PM, Sinan Kaya wrote: > > + /* prevent prefetching of coherent DMA dma prematurely */ \ > > I tried to write DMA data but my keyboard is not cooperating. I'll hold onto > posting another version until I hear

Re: [PATCH v3 2/2] MIPS: io: add a barrier after register read in readX()

2018-04-12 Thread James Hogan
On Thu, Apr 12, 2018 at 10:51:49PM +0100, James Hogan wrote: > On Tue, Apr 03, 2018 at 08:55:04AM -0400, Sinan Kaya wrote: > > While a barrier is present in writeX() function before the register write, > > a similar barrier is missing in the readX() function after the register >

Re: [PATCH v3 2/2] MIPS: io: add a barrier after register read in readX()

2018-04-12 Thread James Hogan
On Tue, Apr 03, 2018 at 08:55:04AM -0400, Sinan Kaya wrote: > While a barrier is present in writeX() function before the register write, > a similar barrier is missing in the readX() function after the register > read. This could allow memory accesses following readX() to observe > stale data. >

Re: [PATCH v3 2/2] MIPS: io: add a barrier after register read in readX()

2018-04-11 Thread James Hogan
On Wed, Apr 11, 2018 at 01:10:41PM -0400, Sinan Kaya wrote: > How is the likelihood of getting this fixed on 4.17 kernel? High. Thanks James signature.asc Description: Digital signature

Re: [PATCH] bug.h: Work around GCC PR82365 in BUG()

2018-04-11 Thread James Hogan
On Wed, Apr 11, 2018 at 12:08:51PM +0200, Arnd Bergmann wrote: > On Wed, Apr 11, 2018 at 11:54 AM, James Hogan <jho...@kernel.org> wrote: > > On Wed, Apr 11, 2018 at 09:30:56AM +0200, Arnd Bergmann wrote: > >> On Wed, Apr 11, 2018 at 12:48 AM, James Hogan <jho...@kernel.

Re: [PATCH] bug.h: Work around GCC PR82365 in BUG()

2018-04-11 Thread James Hogan
On Wed, Apr 11, 2018 at 09:30:56AM +0200, Arnd Bergmann wrote: > On Wed, Apr 11, 2018 at 12:48 AM, James Hogan <jho...@kernel.org> wrote: > > Before I forward port those patches to add .insn for MIPS, is that sort > > of approach (an arch specific asm/compiler-gcc.h to allow

Re: [PATCH] bug.h: Work around GCC PR82365 in BUG()

2018-04-10 Thread James Hogan
Hi Arnd, On Tue, Dec 19, 2017 at 12:39:33PM +0100, Arnd Bergmann wrote: > diff --git a/include/linux/compiler-gcc.h b/include/linux/compiler-gcc.h > index 5d595cfdb2c4..66cfdad68f7e 100644 > --- a/include/linux/compiler-gcc.h > +++ b/include/linux/compiler-gcc.h > @@ -205,6 +205,15 @@ > #endif >

Re: [PATCH AUTOSEL for 4.9 173/293] MIPS: Handle tlbex-tlbp race condition

2018-04-09 Thread James Hogan
On Mon, Apr 09, 2018 at 12:25:09AM +, Sasha Levin wrote: > From: Paul Burton > > [ Upstream commit f39878cc5b09c75d35eaf52131e920b872e3feb4 ] > > In systems where there are multiple actors updating the TLB, the > potential exists for a race condition wherein a CPU

Re: [PATCH AUTOSEL for 4.9 160/293] MIPS: Give __secure_computing() access to syscall arguments.

2018-04-09 Thread James Hogan
On Mon, Apr 09, 2018 at 12:24:58AM +, Sasha Levin wrote: > From: David Daney > > [ Upstream commit 669c4092225f0ed5df12ebee654581b558a5e3ed ] > > KProbes of __seccomp_filter() are not very useful without access to > the syscall arguments. > > Do what x86 does, and

Re: [PATCH AUTOSEL for 4.15 048/189] clk: ingenic: Fix recalc_rate for clocks with fixed divider

2018-04-09 Thread James Hogan
On Mon, Apr 09, 2018 at 12:17:24AM +, Sasha Levin wrote: > From: Paul Cercueil > > [ Upstream commit e6cfa64375d34a6c8c1861868a381013b2d3b921 ] > > Previously, the clocks with a fixed divider would report their rate > as being the same as the one of their parent,

Re: [PATCH AUTOSEL for 4.14 043/161] MIPS: JZ4770: Work around config2 misreporting associativity

2018-04-09 Thread James Hogan
On Mon, Apr 09, 2018 at 12:20:20AM +, Sasha Levin wrote: > From: Maarten ter Huurne > > [ Upstream commit 1f7412e0e2f327fe7dc5a0c2fc36d7b319d05d47 ] > > According to config2, the associativity would be 5-ways, but the > documentation states 4-ways, which also matches

Re: [PATCH AUTOSEL for 4.14 041/161] MIPS: Fix clean of vmlinuz.{32,ecoff,bin,srec}

2018-04-09 Thread James Hogan
Hi Sasha, On Mon, Apr 09, 2018 at 12:20:18AM +, Sasha Levin wrote: > From: James Hogan <jho...@kernel.org> > > [ Upstream commit 5f2483eb2423152445b39f2db59d372f523e664e ] > > Make doesn't expand shell style "vmlinuz.{32,ecoff,bin,srec}" to the 4 > separate

Re: [PATCH] MIPS: vmlinuz: Fix compiler intrinsics location and build directly

2018-04-06 Thread James Hogan
On Thu, Apr 05, 2018 at 10:42:19PM +0100, James Hogan wrote: > On Thu, Apr 05, 2018 at 11:13:14AM +0100, Matt Redfearn wrote: > > Actually, this patch would be better inserted as patch 3 in the series > > since it can pull in the generic ashldi3 before the MIPS one is removed &

Re: [PATCH v3 2/2] MIPS: io: add a barrier after register read in readX()

2018-04-06 Thread James Hogan
On Fri, Apr 06, 2018 at 02:15:57PM -0400, Sinan Kaya wrote: > On 4/5/2018 9:34 PM, Sinan Kaya wrote: > > Can we get these merged to 4.17? > > > > There was a consensus to fix the architectures having API violation issues. > > https://www.mail-archive.com/netdev@vger.kernel.org/msg225971.html > >

Re: [PATCH] MIPS: vmlinuz: Fix compiler intrinsics location and build directly

2018-04-05 Thread James Hogan
On Thu, Apr 05, 2018 at 11:13:14AM +0100, Matt Redfearn wrote: > Actually, this patch would be better inserted as patch 3 in the series > since it can pull in the generic ashldi3 before the MIPS one is removed > in the final patch. Here's an updated commit message: Thanks Matt, applied. Cheers

Re: [PATCH v5 2/3] lib: Rename compiler intrinsic selects to GENERIC_LIB_*

2018-04-04 Thread James Hogan
On Tue, Apr 03, 2018 at 03:39:34PM -0700, Palmer Dabbelt wrote: > Sorry, I'm not sure if this is the right patch -- someone suggested acking > this, but it's already Review-By me and if I understand correctly it's going > through your tree. I'm a bit new to this, but if it helps then here's a >

Re: [GIT PULL] arch: remove obsolete architecture ports

2018-04-04 Thread James Hogan
On Wed, Apr 04, 2018 at 10:38:41AM +0200, Arnd Bergmann wrote: > Also, now that the other architectures are gone, a lot of changes can > be done more easily that will be incompatible with a pure revert, so > the more time passes, the harder it will get to do that. Yes, and an out-of-tree arch

Re: [PATCH v5 3/3] MIPS: use generic GCC library routines from lib/

2018-04-03 Thread James Hogan
ff-by: Matt Redfearn <matt.redfe...@mips.com> > Cc: Palmer Dabbelt <pal...@sifive.com> > Cc: Matt Redfearn <matt.redfe...@mips.com> > Cc: James Hogan <jho...@kernel.org> > Cc: Ralf Baechle <r...@linux-mips.org> > Cc: linux-m...@linux-mips.org > Cc:

Re: [PATCH v4 1/3] Add notrace to lib/ucmpdi2.c

2018-04-03 Thread James Hogan
On Tue, Apr 03, 2018 at 02:51:06PM +0100, Matt Redfearn wrote: > On 29/03/18 22:59, Palmer Dabbelt wrote: > > Ah, thanks, I think I must have forgotten about this.  I assume these > > three are going through your tree? > > Yeah I think that's the plan - James will need your ack to patch 2 if >

Re: [PATCH v4 3/3] MIPS: use generic GCC library routines from lib/

2018-04-03 Thread James Hogan
On Thu, Mar 29, 2018 at 11:41:23AM +0100, Matt Redfearn wrote: > This commit removes several generic GCC library routines from > arch/mips/lib/ in favour of similar routines from lib/. > diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile > index e84e12655fa8..6537e022ef62 100644 > ---

Re: [PATCH V4 Resend] ZBOOT: fix stack protector in compressed boot phase

2018-03-28 Thread James Hogan
rt = (unsigned long)(&__image_begin); > zimage_size = (unsigned long)(&__image_end) - > (unsigned long)(&__image_begin); This looks good to me, though I've Cc'd Kees as apparently the original author from commit 8779657d29c0 ("stackprotector: Introduce CONFIG_CC_STAC

Re: [PATCH V3] ZBOOT: fix stack protector in compressed boot phase

2018-03-23 Thread James Hogan
On Fri, Mar 23, 2018 at 11:50:55AM +0800, Jiaxun Yang wrote: > 在 2018-03-22四的 22:21 +0000,James Hogan写道: > > Also I think it worth mentioning in the commit message the MIPS > > configuration you hit this with, presumably a Loongson one? For me > > decompress_kernel

Re: [PATCH V3] ZBOOT: fix stack protector in compressed boot phase

2018-03-22 Thread James Hogan
On Fri, Mar 16, 2018 at 03:55:16PM +0800, Huacai Chen wrote: > diff --git a/arch/mips/boot/compressed/decompress.c > b/arch/mips/boot/compressed/decompress.c > index fdf99e9..5ba431c 100644 > --- a/arch/mips/boot/compressed/decompress.c > +++ b/arch/mips/boot/compressed/decompress.c > @@ -78,11

Re: [PATCH 1/2] MIPS: Introduce has_cpu_mips*_user in cpu-features.h

2018-03-22 Thread James Hogan
On Wed, Mar 21, 2018 at 10:53:03PM +0800, Jiaxun Yang wrote: > Some processors support user mode instructions ISA level witch is nit: s/witch/which/ here, below, and in the comment. Otherwise it doesn't look unreasonable. Cheers James > different with the ISA level it should be treated in

Re: [PATCH 2/2] MIPS: Loongson64: Define has_cpu_mips64r2_user for Loongson-3

2018-03-22 Thread James Hogan
On Wed, Mar 21, 2018 at 10:53:04PM +0800, Jiaxun Yang wrote: > All loongson-3 processors support mips64r2 usermode instructions. > However 3A1000 3B1000 3B1500 should be treated as mips64r1 in kernel. > > Signed-off-by: Jiaxun Yang > --- >

Re: [PATCH] MIPS: Fix build with DEBUG_ZBOOT and MACH_JZ4770

2018-03-22 Thread James Hogan
On Sat, Mar 17, 2018 at 09:11:09PM +0100, Paul Cercueil wrote: > Since the UART addresses are the same across all Ingenic SoCs, we just > use a #ifdef CONFIG_MACH_INGENIC instead of checking for indifidual > Ingenic SoCs. s/indifidual/individual/ > --- a/arch/mips/boot/compressed/uart-16550.c >

Re: [PATCH v3] MIPS: ralink: fix booting on mt7621

2018-03-21 Thread James Hogan
On Wed, Mar 21, 2018 at 02:02:10PM +1100, NeilBrown wrote: > > Since commit 3af5a67c86a3 ("MIPS: Fix early CM probing") the MT7621 > has not been able to boot. > > This patched caused mips_cm_probe() to be called before > mt7621.c::proc_soc_init(). > > prom_soc_init() has a comment explaining

Re: [PATCH] MIPS: ralink: remove ralink_halt()

2018-03-21 Thread James Hogan
On Tue, Mar 20, 2018 at 07:29:51PM +1100, NeilBrown wrote: > > ralink_halt() does nothing that machine_halt() > doesn't already do, so it adds no value. > > It actually causes incorrect behaviour due to the > "unreachable()" at the end. This tell the compiler that the > end of the function will

Re: [PATCH v6 0/6] MIPS: add support for Microsemi MIPS SoCs

2018-03-21 Thread James Hogan
On Tue, Mar 20, 2018 at 02:07:55PM +0100, Alexandre Belloni wrote: > Hi, > > This patch series adds initial support for the Microsemi MIPS SoCs. It > is currently focusing on the Microsemi Ocelot (VSC7513, VSC7514). > > Changes in v6: > - Fixup SPDX identifiers > - remove unit-address for

Re: [PATCH 0/6] irqchip/mips-gic: Enable & use VEIC mode if available

2018-03-14 Thread James Hogan
On Wed, Mar 14, 2018 at 11:15:47AM +, Marc Zyngier wrote: > Hi Matt, > > On 05/01/18 10:31, Matt Redfearn wrote: > > > > This series enables the MIPS GIC driver to make use of the EIC mode > > supported in some MIPS cores. In this mode, the cores 6 interrupt lines > > are switched to

Re: [PATCH 1/2] MIPS: Allow including mach-generic/dma-coherence.h

2018-03-13 Thread James Hogan
On Tue, Jan 23, 2018 at 05:40:09PM -0800, Florian Fainelli wrote: > @@ -71,15 +83,19 @@ static inline void plat_post_dma_flush(struct device *dev) > #endif > > #ifdef CONFIG_SWIOTLB > +#ifndef phys_to_dma > static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr) > { >

Re: [PATCH 2/2] MIPS: Update dma-coherence.h files

2018-03-13 Thread James Hogan
On Tue, Jan 23, 2018 at 05:40:10PM -0800, Florian Fainelli wrote: > diff --git a/arch/mips/include/asm/mach-ath25/dma-coherence.h > b/arch/mips/include/asm/mach-ath25/dma-coherence.h > index d5defdde32db..63bce15fa54d 100644 > --- a/arch/mips/include/asm/mach-ath25/dma-coherence.h > +++

Re: [RFC PATCH] MIPS: Provide cmpxchg64 for 32-bit builds

2018-03-12 Thread James Hogan
On Wed, Feb 14, 2018 at 09:36:33PM +, Keller, Jacob E wrote: > > -Original Message- > > From: Michael, Alice > > Sent: Wednesday, February 14, 2018 1:03 PM > > To: Guenter Roeck <li...@roeck-us.net>; James Hogan <jho...@kernel.org>; > > Keller,

Re: [PATCH v4 1/8] SOC: brcmstb: add memory API

2018-03-09 Thread James Hogan
On Mon, Jan 15, 2018 at 06:28:38PM -0500, Jim Quinlan wrote: > From: Florian Fainelli > > This commit adds a memory API suitable for ascertaining the sizes of > each of the N memory controllers in a Broadcom STB chip. Its first > user will be the Broadcom STB PCIe root

Re: [PATCH v4 7/8] MIPS: BMIPS: Add PCI bindings for 7425, 7435

2018-03-09 Thread James Hogan
On Mon, Jan 15, 2018 at 06:28:44PM -0500, Jim Quinlan wrote: > diff --git a/arch/mips/boot/dts/brcm/bcm7425.dtsi > b/arch/mips/boot/dts/brcm/bcm7425.dtsi > index e4fb9b6..02168d0 100644 > --- a/arch/mips/boot/dts/brcm/bcm7425.dtsi > +++ b/arch/mips/boot/dts/brcm/bcm7425.dtsi > @@ -495,4 +495,30

Re: [PATCH v3] MIPS: pm-cps: Block system suspend when a JTAG probe is present

2018-03-09 Thread James Hogan
On Tue, Feb 20, 2018 at 09:58:16AM +, Matt Redfearn wrote: > If a JTAG probe is connected to a MIPS cluster, then the CPC detects it > and latches the CPC.STAT_CONF.EJTAG_PROBE bit to 1. While set, > attempting to send a power-down command to a core will be blocked, and > the CPC will instead

Re: [PATCH 0/4] MIPS: Introduce isa-rev.h to define MIPS_ISA_REV

2018-03-09 Thread James Hogan
On Mon, Feb 26, 2018 at 05:02:41PM +, Matt Redfearn wrote: > There are multiple instances in the kernel where we need to include or > exclude particular instructions based on the ISA revision of the target > processor. For MIPS32 / MIPS64, the compiler exports a __mips_isa_rev > define.

[PATCH v2] kbuild: Handle builtin dtb file names containing hyphens

2018-03-08 Thread James Hogan
really build all the dtb.o files, but thats a separate issue). Fixes: 695835511f96 ("MIPS: BMIPS: rename bcm96358nb4ser to bcm6358-neufbox4-sercom") Signed-off-by: James Hogan <jho...@kernel.org> Reviewed-by: Frank Rowand <frowand.l...@gmail.com> Cc: Rob Herring <robh...@kernel

Re: [PATCH] kbuild: Handle builtin dtb files containing hyphens

2018-03-07 Thread James Hogan
On Wed, Mar 07, 2018 at 03:19:11PM -0800, Frank Rowand wrote: > On 03/07/18 12:25, James Hogan wrote: > > On Wed, Mar 07, 2018 at 12:11:41PM -0800, Frank Rowand wrote: > >> On 03/07/18 06:06, James Hogan wrote: > >>> Quite a lot of dts files have hyphens, but its only

MIPS DT W=1 warnings (was Re: [PATCH v5 2/5] MIPS: mscc: add ocelot dtsi)

2018-03-07 Thread James Hogan
Hi Rob, On Wed, Mar 07, 2018 at 10:08:28AM -0600, Rob Herring wrote: > Please compile with W=1 and fix any issues like this one which is a > unit-address without a reg property. Drop the unit-address. I was just giving the BMIPS W=1 DT warnings a look, and a few look spurious. I'd value your

Re: [PATCH] kbuild: Handle builtin dtb files containing hyphens

2018-03-07 Thread James Hogan
On Wed, Mar 07, 2018 at 12:11:41PM -0800, Frank Rowand wrote: > I initially misread the patch description (and imagined an entirely > different problem). > > > On 03/07/18 06:06, James Hogan wrote: > > On dtb files which contain hyphens, the dt_S_dtb command to build the>

Re: [PATCH v5 2/5] MIPS: mscc: add ocelot dtsi

2018-03-07 Thread James Hogan
On Wed, Mar 07, 2018 at 04:27:51PM +0100, Alexandre Belloni wrote: > On 07/03/2018 at 15:17:56 +0000, James Hogan wrote: > > On Tue, Mar 06, 2018 at 01:16:04PM +0100, Alexandre Belloni wrote: > > > diff --git a/arch/mips/boot/dts/mscc/ocelot.dtsi > > > b/arch/mip

Re: [PATCH v5 4/5] MIPS: generic: Add support for Microsemi Ocelot

2018-03-07 Thread James Hogan
On Tue, Mar 06, 2018 at 01:16:06PM +0100, Alexandre Belloni wrote: > diff --git a/arch/mips/Makefile b/arch/mips/Makefile > index d1ca839c3981..d2882244cf1f 100644 > --- a/arch/mips/Makefile > +++ b/arch/mips/Makefile > @@ -543,6 +543,10 @@ generic_defconfig: > # now that the boards have been

Re: [PATCH v5 2/5] MIPS: mscc: add ocelot dtsi

2018-03-07 Thread James Hogan
On Tue, Mar 06, 2018 at 01:16:04PM +0100, Alexandre Belloni wrote: > diff --git a/arch/mips/boot/dts/mscc/ocelot.dtsi > b/arch/mips/boot/dts/mscc/ocelot.dtsi > new file mode 100644 > index ..8c3210577410 > --- /dev/null > +++ b/arch/mips/boot/dts/mscc/ocelot.dtsi > @@ -0,0 +1,117 @@ >

Re: [RFC 3/4] MIPS: Ingenic: Initial X1000 SoC support

2018-03-07 Thread James Hogan
On Wed, Mar 07, 2018 at 08:35:00PM +0530, PrasannaKumar Muralidharan wrote: > On 7 March 2018 at 20:05, James Hogan <jho...@kernel.org> wrote: > > On Wed, Mar 07, 2018 at 07:14:49PM +0530, PrasannaKumar Muralidharan wrote: > >> > Does X1000 use a different PRID, or is

Re: [RFC 3/4] MIPS: Ingenic: Initial X1000 SoC support

2018-03-07 Thread James Hogan
On Wed, Mar 07, 2018 at 07:14:49PM +0530, PrasannaKumar Muralidharan wrote: > > Does X1000 use a different PRID, or is it basically just a JZ4780 core > > with different SoC peripherals? > > Yes X1000 does have a different PRID (PRID = 0x2ed1024f). X1000 has Right, so thats 0x2e00 |

[PATCH] kbuild: Handle builtin dtb files containing hyphens

2018-03-07 Thread James Hogan
: 695835511f96 ("MIPS: BMIPS: rename bcm96358nb4ser to bcm6358-neufbox4-sercom") Signed-off-by: James Hogan <jho...@kernel.org> Cc: Rob Herring <robh...@kernel.org> Cc: Frank Rowand <frowand.l...@gmail.com> Cc: Masahiro Yamada <yamada.masah...@socionext.

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