Re: [PATCH v3 3/3] HID: core: fix dmesg flooding if report field larger than 32bit

another stab. ~Joshua On Wed, Sep 18, 2019 at 11:35 AM Benjamin Tissoires wrote: > > On Thu, Aug 29, 2019 at 1:26 AM Joshua Clayton > wrote: > > > > ping? > > I'd love to see this get in. > > with distro kernel I have effectively no dmesg due to this issue > >

Re: [PATCH v3 3/3] HID: core: fix dmesg flooding if report field larger than 32bit

ping? I'd love to see this get in. with distro kernel I have effectively no dmesg due to this issue On Mon, Aug 12, 2019 at 9:20 AM wrote: > > From: Joshua Clayton > > Only warn once of oversize hid report value field > > On HP spectre x360 convertible the message: > hid

Re: [PATCH v2 3/3] HID: core: only warn once of oversize hid report

On Mon, Jul 22, 2019 at 3:30 PM Joe Perches wrote: > > On Mon, 2019-07-22 at 15:26 -0600, stillcompil...@gmail.com wrote: > > From: Joshua Clayton > > Thanks Joshua > > > On HP spectre x360 convertible the message: > > hid-sensor-hub 001F:8087:0AC2.0002: hid_f

Re: [PATCH 2/2] HID: core: only warn once of oversize hid report

On Mon, Jul 22, 2019 at 11:23 AM Joe Perches wrote: > > On Mon, 2019-07-22 at 10:36 -0600, stillcompil...@gmail.com wrote: > > On HP spectre x360 convertible the message: > > hid-sensor-hub 001F:8087:0AC2.0002: hid_field_extract() called with n (192) > > > 32! (kworker/1:2) > > is continually

[PATCH v13 3/6] fpga manager: Add altera-ps-spi driver for Altera FPGAs

altera-ps-spi loads FPGA firmware over SPI, using the "passive serial" interface on Altera Arria 10, Cyclone V or Stratix V FPGAs. This is one of the simpler ways to set up an FPGA at runtime. The signal interface is close to unidirectional SPI with lsb first. Signed-off-by: Josh

[PATCH v13 3/6] fpga manager: Add altera-ps-spi driver for Altera FPGAs

altera-ps-spi loads FPGA firmware over SPI, using the "passive serial" interface on Altera Arria 10, Cyclone V or Stratix V FPGAs. This is one of the simpler ways to set up an FPGA at runtime. The signal interface is close to unidirectional SPI with lsb first. Signed-off-by: Josh

[PATCH v13 4/6] ARM: dts: imx6q-evi: support altera-ps-spi

Add support for Altera FPGA connected to an spi port to the evi devicetree file Signed-off-by: Joshua Clayton <stillcompil...@gmail.com> --- arch/arm/boot/dts/imx6q-evi.dts | 16 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/imx6q-evi.dts b/arch/arm/bo

[PATCH v13 4/6] ARM: dts: imx6q-evi: support altera-ps-spi

Add support for Altera FPGA connected to an spi port to the evi devicetree file Signed-off-by: Joshua Clayton --- arch/arm/boot/dts/imx6q-evi.dts | 16 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/imx6q-evi.dts b/arch/arm/boot/dts/imx6q-evi.dts index

[PATCH v13 1/6] fpga: Add flag to indicate SPI bitstream is bit-reversed

atolij Gustschin <ag...@denx.de> Signed-off-by: Joshua Clayton <stillcompil...@gmail.com> --- Changes since v12: - Change "depends on SPI || COMPILE_TEST" to "depends on SPI" in patch 3 include/linux/fpga/fpga-mgr.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/i

[PATCH v13 1/6] fpga: Add flag to indicate SPI bitstream is bit-reversed

-by: Joshua Clayton --- Changes since v12: - Change "depends on SPI || COMPILE_TEST" to "depends on SPI" in patch 3 include/linux/fpga/fpga-mgr.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/linux/fpga/fpga-mgr.h b/include/linux/fpga/fpga-mgr.h index b4ac24

[PATCH v13 6/6] fpga-manager: altera-ps-spi: use bitrev8x4

Speed up bit reversal by using hardware bit reversal Add extra code to handle less than 4byte remnants, if any Signed-off-by: Joshua Clayton <stillcompil...@gmail.com> --- drivers/fpga/altera-ps-spi.c | 19 +++ 1 file changed, 15 insertions(+), 4 deletions(-) diff

[PATCH v13 6/6] fpga-manager: altera-ps-spi: use bitrev8x4

Speed up bit reversal by using hardware bit reversal Add extra code to handle less than 4byte remnants, if any Signed-off-by: Joshua Clayton --- drivers/fpga/altera-ps-spi.c | 19 +++ 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/drivers/fpga/altera-ps-spi.c b

[PATCH v13 2/6] doc: dt: document altera-passive-serial binding

Describe an altera-passive-serial devicetree entry, required features Signed-off-by: Joshua Clayton <stillcompil...@gmail.com> Acked-by: Rob Herring <r...@kernel.org> --- .../bindings/fpga/altera-passive-serial.txt| 29 ++ 1 file changed, 29 insertions(+)

[PATCH v13 5/6] lib: add bitrev8x4()

Add a function to reverse bytes within a 32 bit word. Operate on a u32 rather than individual bytes. Signed-off-by: Joshua Clayton <stillcompil...@gmail.com> --- include/linux/bitrev.h | 19 +++ 1 file changed, 19 insertions(+) diff --git a/include/linux/bitrev.h b/include

[PATCH v13 2/6] doc: dt: document altera-passive-serial binding

Describe an altera-passive-serial devicetree entry, required features Signed-off-by: Joshua Clayton Acked-by: Rob Herring --- .../bindings/fpga/altera-passive-serial.txt| 29 ++ 1 file changed, 29 insertions(+) create mode 100644 Documentation/devicetree/bindings

[PATCH v13 5/6] lib: add bitrev8x4()

Add a function to reverse bytes within a 32 bit word. Operate on a u32 rather than individual bytes. Signed-off-by: Joshua Clayton --- include/linux/bitrev.h | 19 +++ 1 file changed, 19 insertions(+) diff --git a/include/linux/bitrev.h b/include/linux/bitrev.h index

[PATCH v12 3/6] fpga manager: Add altera-ps-spi driver for Altera FPGAs

altera-ps-spi loads FPGA firmware over SPI, using the "passive serial" interface on Altera Arria 10, Cyclone V or Stratix V FPGAs. This is one of the simpler ways to set up an FPGA at runtime. The signal interface is close to unidirectional SPI with lsb first. Signed-off-by: Josh

[PATCH v12 3/6] fpga manager: Add altera-ps-spi driver for Altera FPGAs

altera-ps-spi loads FPGA firmware over SPI, using the "passive serial" interface on Altera Arria 10, Cyclone V or Stratix V FPGAs. This is one of the simpler ways to set up an FPGA at runtime. The signal interface is close to unidirectional SPI with lsb first. Signed-off-by: Josh

[PATCH v12 6/6] fpga-manager: altera-ps-spi: use bitrev8x4

Speed up bit reversal by using hardware bit reversal Add extra code to handle less than 4byte remnants, if any Signed-off-by: Joshua Clayton <stillcompil...@gmail.com> --- drivers/fpga/altera-ps-spi.c | 19 +++ 1 file changed, 15 insertions(+), 4 deletions(-) diff

[PATCH v12 6/6] fpga-manager: altera-ps-spi: use bitrev8x4

Speed up bit reversal by using hardware bit reversal Add extra code to handle less than 4byte remnants, if any Signed-off-by: Joshua Clayton --- drivers/fpga/altera-ps-spi.c | 19 +++ 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/drivers/fpga/altera-ps-spi.c b

[PATCH v12 5/6] lib: add bitrev8x4()

Add a function to reverse bytes within a 32 bit word. Operate on a u32 rather than individual bytes. Signed-off-by: Joshua Clayton <stillcompil...@gmail.com> --- include/linux/bitrev.h | 19 +++ 1 file changed, 19 insertions(+) diff --git a/include/linux/bitrev.h b/include

[PATCH v12 4/6] ARM: dts: imx6q-evi: support altera-ps-spi

Add support for Altera FPGA connected to an spi port to the evi devicetree file Signed-off-by: Joshua Clayton <stillcompil...@gmail.com> --- arch/arm/boot/dts/imx6q-evi.dts | 16 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/imx6q-evi.dts b/arch/arm/bo

[PATCH v12 5/6] lib: add bitrev8x4()

Add a function to reverse bytes within a 32 bit word. Operate on a u32 rather than individual bytes. Signed-off-by: Joshua Clayton --- include/linux/bitrev.h | 19 +++ 1 file changed, 19 insertions(+) diff --git a/include/linux/bitrev.h b/include/linux/bitrev.h index

[PATCH v12 4/6] ARM: dts: imx6q-evi: support altera-ps-spi

Add support for Altera FPGA connected to an spi port to the evi devicetree file Signed-off-by: Joshua Clayton --- arch/arm/boot/dts/imx6q-evi.dts | 16 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/imx6q-evi.dts b/arch/arm/boot/dts/imx6q-evi.dts index

[PATCH v12 1/6] fpga: Add flag to indicate SPI bitstream is bit-reversed

atolij Gustschin <ag...@denx.de> Signed-off-by: Joshua Clayton <stillcompil...@gmail.com> --- Changes from v11 (all in patch 4/4) - Change "Altera V FPGA" to simply "Altera FPGA" - Change the devicetree name to a generic "fpga: fpga@0" from "fpga_spi: cyclone

[PATCH v12 2/6] doc: dt: document altera-passive-serial binding

Describe an altera-passive-serial devicetree entry, required features Signed-off-by: Joshua Clayton <stillcompil...@gmail.com> Acked-by: Rob Herring <r...@kernel.org> --- .../bindings/fpga/altera-passive-serial.txt| 29 ++ 1 file changed, 29 insertions(+)

[PATCH v12 2/6] doc: dt: document altera-passive-serial binding

Describe an altera-passive-serial devicetree entry, required features Signed-off-by: Joshua Clayton Acked-by: Rob Herring --- .../bindings/fpga/altera-passive-serial.txt| 29 ++ 1 file changed, 29 insertions(+) create mode 100644 Documentation/devicetree/bindings

[PATCH v12 1/6] fpga: Add flag to indicate SPI bitstream is bit-reversed

-by: Joshua Clayton --- Changes from v11 (all in patch 4/4) - Change "Altera V FPGA" to simply "Altera FPGA" - Change the devicetree name to a generic "fpga: fpga@0" from "fpga_spi: cyclonespi@0" include/linux/fpga/fpga-mgr.h | 2 ++ 1 file changed, 2 i

[PATCH v11 1/6] fpga: Add flag to indicate SPI bitstream is bit-reversed

atolij Gustschin <ag...@denx.de> Signed-off-by: Joshua Clayton <stillcompil...@gmail.com> --- include/linux/fpga/fpga-mgr.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/linux/fpga/fpga-mgr.h b/include/linux/fpga/fpga-mgr.h index b4ac24c4411d..01c348ca38b7 100644 --- a/inclu

[PATCH v11 1/6] fpga: Add flag to indicate SPI bitstream is bit-reversed

-by: Joshua Clayton --- include/linux/fpga/fpga-mgr.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/linux/fpga/fpga-mgr.h b/include/linux/fpga/fpga-mgr.h index b4ac24c4411d..01c348ca38b7 100644 --- a/include/linux/fpga/fpga-mgr.h +++ b/include/linux/fpga/fpga-mgr.h @@ -67,10 +67,12

[PATCH v11 6/6] fpga-manager: altera-ps-spi: use bitrev8x4

Speed up bit reversal by using hardware bit reversal Add extra code to handle less than 4byte remnants, if any Signed-off-by: Joshua Clayton <stillcompil...@gmail.com> --- drivers/fpga/altera-ps-spi.c | 19 +++ 1 file changed, 15 insertions(+), 4 deletions(-) diff

[PATCH v11 6/6] fpga-manager: altera-ps-spi: use bitrev8x4

Speed up bit reversal by using hardware bit reversal Add extra code to handle less than 4byte remnants, if any Signed-off-by: Joshua Clayton --- drivers/fpga/altera-ps-spi.c | 19 +++ 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/drivers/fpga/altera-ps-spi.c b

[PATCH v11 3/6] fpga manager: Add altera-ps-spi driver for Altera FPGAs

altera-ps-spi loads FPGA firmware over SPI, using the "passive serial" interface on Altera Arria 10, Cyclone V or Stratix V FPGAs. This is one of the simpler ways to set up an FPGA at runtime. The signal interface is close to unidirectional SPI with lsb first. Signed-off-by: Josh

[PATCH v11 2/6] doc: dt: add altera-ps-spi binding document

Describe an altera-ps-spi devicetree entry, required features Signed-off-by: Joshua Clayton <stillcompil...@gmail.com> Acked-by: Rob Herring <r...@kernel.org> Signed-off-by: Anatolij Gustschin <ag...@denx.de> --- .../bindings/fpga/altera-passive-serial.txt| 29 +++

[PATCH v11 2/6] doc: dt: add altera-ps-spi binding document

Describe an altera-ps-spi devicetree entry, required features Signed-off-by: Joshua Clayton Acked-by: Rob Herring Signed-off-by: Anatolij Gustschin --- .../bindings/fpga/altera-passive-serial.txt| 29 ++ 1 file changed, 29 insertions(+) create mode 100644

[PATCH v11 3/6] fpga manager: Add altera-ps-spi driver for Altera FPGAs

altera-ps-spi loads FPGA firmware over SPI, using the "passive serial" interface on Altera Arria 10, Cyclone V or Stratix V FPGAs. This is one of the simpler ways to set up an FPGA at runtime. The signal interface is close to unidirectional SPI with lsb first. Signed-off-by: Josh

[PATCH v11 5/6] lib: add bitrev8x4()

Add a function to reverse bytes within a 32 bit word. Operate on a u32 rather than individual bytes. Signed-off-by: Joshua Clayton <stillcompil...@gmail.com> --- include/linux/bitrev.h | 19 +++ 1 file changed, 19 insertions(+) diff --git a/include/linux/bitrev.h b/include

[PATCH v11 5/6] lib: add bitrev8x4()

Add a function to reverse bytes within a 32 bit word. Operate on a u32 rather than individual bytes. Signed-off-by: Joshua Clayton --- include/linux/bitrev.h | 19 +++ 1 file changed, 19 insertions(+) diff --git a/include/linux/bitrev.h b/include/linux/bitrev.h index

[PATCH v11 4/6] ARM: dts: imx6q-evi: support altera-ps-spi

Add support for Altera V FPGA connected to an spi port to the evi devicetree file Signed-off-by: Joshua Clayton <stillcompil...@gmail.com> --- arch/arm/boot/dts/imx6q-evi.dts | 16 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/imx6q-evi.dts b/arch/arm/bo

[PATCH v11 4/6] ARM: dts: imx6q-evi: support altera-ps-spi

Add support for Altera V FPGA connected to an spi port to the evi devicetree file Signed-off-by: Joshua Clayton --- arch/arm/boot/dts/imx6q-evi.dts | 16 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/imx6q-evi.dts b/arch/arm/boot/dts/imx6q-evi.dts index

[PATCH v11 0/6] FPGA Manager support for altera passive serial

ze buffer. Anatolij Gustschin (1): fpga: Add flag to indicate SPI bitstream is bit-reversed Joshua Clayton (4): doc: dt: add altera-ps-spi binding document fpga manager: Add altera-ps-spi driver for Altera FPGAs ARM: dts: imx6q-evi: support altera-ps-spi lib: add bitrev8x4() fpga-manager

[PATCH v11 0/6] FPGA Manager support for altera passive serial

ze buffer. Anatolij Gustschin (1): fpga: Add flag to indicate SPI bitstream is bit-reversed Joshua Clayton (4): doc: dt: add altera-ps-spi binding document fpga manager: Add altera-ps-spi driver for Altera FPGAs ARM: dts: imx6q-evi: support altera-ps-spi lib: add bitrev8x4() fpga-manager

Re: [PATCH] fpga: Add flag to indicate SPI bitstream is bit-reversed

Hi Alanatolij, I was just finally able to test this and your other change yesterday On Thursday, April 20, 2017 11:43:01 PM PDT Anatolij Gustschin wrote: > Add a flag that is passed to the write_init() callback, > indicating that the SPI bitstream starts with LSB first. > SPI controllers

Re: [PATCH] fpga: Add flag to indicate SPI bitstream is bit-reversed

Hi Alanatolij, I was just finally able to test this and your other change yesterday On Thursday, April 20, 2017 11:43:01 PM PDT Anatolij Gustschin wrote: > Add a flag that is passed to the write_init() callback, > indicating that the SPI bitstream starts with LSB first. > SPI controllers

[PATCH] ARM: zImage: fix warning in merge_fdt_bootargs()

buffer on the stack, it calls fdt_appendprop_string() Signed-off-by: Joshua Clayton <stillcompil...@gmail.com> --- I tried testing this on my imx6 setup by adding bogus text to the command line, but it appears that with my (recent) uboot the codepath is not executed. So this could be re

[PATCH] ARM: zImage: fix warning in merge_fdt_bootargs()

buffer on the stack, it calls fdt_appendprop_string() Signed-off-by: Joshua Clayton --- I tried testing this on my imx6 setup by adding bogus text to the command line, but it appears that with my (recent) uboot the codepath is not executed. So this could be regarded as little more than compile

Re: [PATCH v9 2/3] fpga manager: Add cyclone-ps-spi driver for Altera FPGAs

On 02/15/2017 09:14 AM, Alan Tull wrote: > On Wed, Feb 15, 2017 at 9:26 AM, Anatolij Gustschin <ag...@denx.de> wrote: >> Hi Joshua, >> >> On Tue, 24 Jan 2017 14:19:33 -0800 >> Joshua Clayton stillcompil...@gmail.com wrote: >> ... >>> +static int

Re: [PATCH v9 2/3] fpga manager: Add cyclone-ps-spi driver for Altera FPGAs

On 02/15/2017 09:14 AM, Alan Tull wrote: > On Wed, Feb 15, 2017 at 9:26 AM, Anatolij Gustschin wrote: >> Hi Joshua, >> >> On Tue, 24 Jan 2017 14:19:33 -0800 >> Joshua Clayton stillcompil...@gmail.com wrote: >> ... >>> +static int cyclonespi_write

Re: [PATCH v9 1/3] doc: dt: add cyclone-ps-spi binding document

Thanks, Rob. On 01/27/2017 02:28 PM, Rob Herring wrote: > On Tue, Jan 24, 2017 at 02:19:32PM -0800, Joshua Clayton wrote: >> Describe a cyclone-ps-spi devicetree entry, required features >> >> Signed-off-by: Joshua Clayton <stillcompil...@gmail.com> >> --- >

Re: [PATCH v9 1/3] doc: dt: add cyclone-ps-spi binding document

Thanks, Rob. On 01/27/2017 02:28 PM, Rob Herring wrote: > On Tue, Jan 24, 2017 at 02:19:32PM -0800, Joshua Clayton wrote: >> Describe a cyclone-ps-spi devicetree entry, required features >> >> Signed-off-by: Joshua Clayton >> --- >> .../bindings/fpga/alte

[PATCH v9 2/3] fpga manager: Add cyclone-ps-spi driver for Altera FPGAs

cyclone-ps-spi loads FPGA firmware over spi, using the "passive serial" interface on Altera Cyclone FPGAS. This is one of the simpler ways to set up an FPGA at runtime. The signal interface is close to unidirectional spi with lsb first. Signed-off-by: Joshua Clayton <stillcompil

[PATCH v9 2/3] fpga manager: Add cyclone-ps-spi driver for Altera FPGAs

cyclone-ps-spi loads FPGA firmware over spi, using the "passive serial" interface on Altera Cyclone FPGAS. This is one of the simpler ways to set up an FPGA at runtime. The signal interface is close to unidirectional spi with lsb first. Signed-off-by: Joshua Clayton --- drivers/fp

[PATCH v9 3/3] ARM: dts: imx6q-evi: support cyclone-ps-spi

Add support for Altera cyclone V FPGA connected to an spi port to the evi devicetree file Signed-off-by: Joshua Clayton <stillcompil...@gmail.com> --- arch/arm/boot/dts/imx6q-evi.dts | 16 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/imx6q-evi.dts b/ar

[PATCH v9 3/3] ARM: dts: imx6q-evi: support cyclone-ps-spi

Add support for Altera cyclone V FPGA connected to an spi port to the evi devicetree file Signed-off-by: Joshua Clayton --- arch/arm/boot/dts/imx6q-evi.dts | 16 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/imx6q-evi.dts b/arch/arm/boot/dts/imx6q-evi.dts

[PATCH v9 0/3] Altera Cyclone Passive Serial SPI FPGA Manager

>From c429cec34a880c0d5438091f436a5946a4db3fc0 Mon Sep 17 00:00:00 2001 Message-Id: <cover.1485211400.git.stillcompil...@gmail.com> From: Joshua Clayton <stillcompil...@gmail.com> Date: Mon, 23 Jan 2017 14:43:20 -0800 Subject: [PATCH v8 0/3] Altera Cyclone Passive Serial S

[PATCH v9 1/3] doc: dt: add cyclone-ps-spi binding document

Describe a cyclone-ps-spi devicetree entry, required features Signed-off-by: Joshua Clayton <stillcompil...@gmail.com> --- .../bindings/fpga/altera-passive-serial.txt| 29 ++ 1 file changed, 29 insertions(+) create mode 100644 Documentation/devicetree/binding

[PATCH v9 1/3] doc: dt: add cyclone-ps-spi binding document

Describe a cyclone-ps-spi devicetree entry, required features Signed-off-by: Joshua Clayton --- .../bindings/fpga/altera-passive-serial.txt| 29 ++ 1 file changed, 29 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/altera-passive-serial.txt

[PATCH v9 0/3] Altera Cyclone Passive Serial SPI FPGA Manager

>From c429cec34a880c0d5438091f436a5946a4db3fc0 Mon Sep 17 00:00:00 2001 Message-Id: From: Joshua Clayton Date: Mon, 23 Jan 2017 14:43:20 -0800 Subject: [PATCH v8 0/3] Altera Cyclone Passive Serial SPI FPGA Manager This series adds an FPGA manager for Altera cyclone FPGAs that can program t

Re: [PATCH v8 3/3] ARM: dts: imx6q-evi: support cyclone-ps-spi

On 01/23/2017 04:00 PM, Fabio Estevam wrote: > On Mon, Jan 23, 2017 at 8:51 PM, Joshua Clayton > <stillcompil...@gmail.com> wrote: >> Add support for Altera cyclone V FPGA connected to an spi port >> to the evi devicetree file >> >> Signed-off-by: Josh

Re: [PATCH v8 3/3] ARM: dts: imx6q-evi: support cyclone-ps-spi

On 01/23/2017 04:00 PM, Fabio Estevam wrote: > On Mon, Jan 23, 2017 at 8:51 PM, Joshua Clayton > wrote: >> Add support for Altera cyclone V FPGA connected to an spi port >> to the evi devicetree file >> >> Signed-off-by: Joshua Clayton >> --- >

[PATCH v8 0/3] Altera Cyclone Passive Serial SPI FPGA Manager

ing refactoring - Replaced magic number for initial delay with a descriptive macro - Poll the fpga to see when it is ready rather than a fixed 1 ms sleep Joshua Clayton (3): doc: dt: add cyclone-ps-spi binding document fpga manager: Add cyclone-ps-spi driver for Altera FPGAs ARM: dts: imx6q-ev

[PATCH v8 0/3] Altera Cyclone Passive Serial SPI FPGA Manager

ing refactoring - Replaced magic number for initial delay with a descriptive macro - Poll the fpga to see when it is ready rather than a fixed 1 ms sleep Joshua Clayton (3): doc: dt: add cyclone-ps-spi binding document fpga manager: Add cyclone-ps-spi driver for Altera FPGAs ARM: dts: imx6q-ev

[PATCH v8 2/3] fpga manager: Add cyclone-ps-spi driver for Altera FPGAs

cyclone-ps-spi loads FPGA firmware over spi, using the "passive serial" interface on Altera Cyclone FPGAS. This is one of the simpler ways to set up an FPGA at runtime. The signal interface is close to unidirectional spi with lsb first. Signed-off-by: Joshua Clayton <stillcompil

[PATCH v8 2/3] fpga manager: Add cyclone-ps-spi driver for Altera FPGAs

cyclone-ps-spi loads FPGA firmware over spi, using the "passive serial" interface on Altera Cyclone FPGAS. This is one of the simpler ways to set up an FPGA at runtime. The signal interface is close to unidirectional spi with lsb first. Signed-off-by: Joshua Clayton --- drivers/fp

[PATCH v8 3/3] ARM: dts: imx6q-evi: support cyclone-ps-spi

Add support for Altera cyclone V FPGA connected to an spi port to the evi devicetree file Signed-off-by: Joshua Clayton <stillcompil...@gmail.com> --- arch/arm/boot/dts/imx6q-evi.dts | 16 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/imx6q-evi.dts b/ar

[PATCH v8 3/3] ARM: dts: imx6q-evi: support cyclone-ps-spi

Add support for Altera cyclone V FPGA connected to an spi port to the evi devicetree file Signed-off-by: Joshua Clayton --- arch/arm/boot/dts/imx6q-evi.dts | 16 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/imx6q-evi.dts b/arch/arm/boot/dts/imx6q-evi.dts

[PATCH v8 1/3] doc: dt: add cyclone-ps-spi binding document

Describe a cyclone-ps-spi devicetree entry, required features Signed-off-by: Joshua Clayton <stillcompil...@gmail.com> Acked-by: Rob Herring <r...@kernel.org> --- .../bindings/fpga/altera-passive-serial.txt| 25 ++ 1 file changed, 25 insertions(+) create

[PATCH v8 1/3] doc: dt: add cyclone-ps-spi binding document

Describe a cyclone-ps-spi devicetree entry, required features Signed-off-by: Joshua Clayton Acked-by: Rob Herring --- .../bindings/fpga/altera-passive-serial.txt| 25 ++ 1 file changed, 25 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga

[PATCH] fpga: fpga-manager: make __fpga_mgr_get() static

Running sparse on this subdirectory suggested __fpga_mgr_get() should be static. __fpga_mgr_get() is internal to the fpga-mgr framework. Define it as static Signed-off-by: Joshua Clayton <stillcompil...@gmail.com> --- drivers/fpga/fpga-mgr.c | 2 +- 1 file changed, 1 insertion(+), 1 de

[PATCH] fpga: fpga-manager: make __fpga_mgr_get() static

Running sparse on this subdirectory suggested __fpga_mgr_get() should be static. __fpga_mgr_get() is internal to the fpga-mgr framework. Define it as static Signed-off-by: Joshua Clayton --- drivers/fpga/fpga-mgr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/fpga

Re: [PATCH v7 2/3] fpga manager: Add cyclone-ps-spi driver for Altera FPGAs

t; > url: > https://github.com/0day-ci/linux/commits/Joshua-Clayton/Altera-Cyclone-Passive-Serial-SPI-FPGA-Manager/20170120-172349 > reproduce: > # apt-get install sparse > make ARCH=x86_64 allmodconfig > make C=1 CF=-D__CHECK_ENDIAN__ &g

Re: [PATCH v7 2/3] fpga manager: Add cyclone-ps-spi driver for Altera FPGAs

t; > url: > https://github.com/0day-ci/linux/commits/Joshua-Clayton/Altera-Cyclone-Passive-Serial-SPI-FPGA-Manager/20170120-172349 > reproduce: > # apt-get install sparse > make ARCH=x86_64 allmodconfig > make C=1 CF=-D__CHECK_ENDIAN__ &g

[PATCH v7 3/3] ARM: dts: imx6q-evi: support cyclone-ps-spi

Add support for Altera cyclone V FPGA connected to an spi port to the evi devicetree file Signed-off-by: Joshua Clayton <stillcompil...@gmail.com> --- arch/arm/boot/dts/imx6q-evi.dts | 16 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/imx6q-evi.dts b/ar

[PATCH v7 3/3] ARM: dts: imx6q-evi: support cyclone-ps-spi

Add support for Altera cyclone V FPGA connected to an spi port to the evi devicetree file Signed-off-by: Joshua Clayton --- arch/arm/boot/dts/imx6q-evi.dts | 16 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/imx6q-evi.dts b/arch/arm/boot/dts/imx6q-evi.dts

[PATCH v7 2/3] fpga manager: Add cyclone-ps-spi driver for Altera FPGAs

cyclone-ps-spi loads FPGA firmware over spi, using the "passive serial" interface on Altera Cyclone FPGAS. This is one of the simpler ways to set up an FPGA at runtime. The signal interface is close to unidirectional spi with lsb first. Signed-off-by: Joshua Clayton <stillcompil

[PATCH v7 2/3] fpga manager: Add cyclone-ps-spi driver for Altera FPGAs

cyclone-ps-spi loads FPGA firmware over spi, using the "passive serial" interface on Altera Cyclone FPGAS. This is one of the simpler ways to set up an FPGA at runtime. The signal interface is close to unidirectional spi with lsb first. Signed-off-by: Joshua Clayton --- drivers/fp

[PATCH v7 0/3] Altera Cyclone Passive Serial SPI FPGA Manager

ng into cyclonespi_write(), as requested. This falls short of my desired generic lsb first spi support, but is a step in that direction. - Fixed whitespace problems introduced during refactoring - Replaced magic number for initial delay with a descriptive macro - Poll the fpga to see when it is read

[PATCH v7 0/3] Altera Cyclone Passive Serial SPI FPGA Manager

ng into cyclonespi_write(), as requested. This falls short of my desired generic lsb first spi support, but is a step in that direction. - Fixed whitespace problems introduced during refactoring - Replaced magic number for initial delay with a descriptive macro - Poll the fpga to see when it is read

[PATCH v7 1/3] doc: dt: add cyclone-ps-spi binding document

Describe a cyclone-ps-spi devicetree entry, required features Signed-off-by: Joshua Clayton <stillcompil...@gmail.com> --- .../bindings/fpga/altera-passive-serial.txt| 25 ++ 1 file changed, 25 insertions(+) create mode 100644 Documentation/devicetree/binding

[PATCH v7 1/3] doc: dt: add cyclone-ps-spi binding document

Describe a cyclone-ps-spi devicetree entry, required features Signed-off-by: Joshua Clayton --- .../bindings/fpga/altera-passive-serial.txt| 25 ++ 1 file changed, 25 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/altera-passive-serial.txt

Re: [PATCH v6 4/5] fpga manager: Add cyclone-ps-spi driver for Altera FPGAs

Uwe, Thanks so much for your review. On 12/18/2016 11:23 PM, Uwe Kleine-König wrote: > On Fri, Dec 16, 2016 at 03:17:53PM -0800, Joshua Clayton wrote: >> cyclone-ps-spi loads FPGA firmware over spi, using the "passive serial" >> interface on Altera Cyclone FPGAS. >>

Re: [PATCH v6 4/5] fpga manager: Add cyclone-ps-spi driver for Altera FPGAs

Uwe, Thanks so much for your review. On 12/18/2016 11:23 PM, Uwe Kleine-König wrote: > On Fri, Dec 16, 2016 at 03:17:53PM -0800, Joshua Clayton wrote: >> cyclone-ps-spi loads FPGA firmware over spi, using the "passive serial" >> interface on Altera Cyclone FPGAS. >>

Re: [PATCH v6 2/5] lib: implement __arch_bitrev8x4()

Will, On 12/19/2016 02:06 AM, Will Deacon wrote: > On Fri, Dec 16, 2016 at 03:17:51PM -0800, Joshua Clayton wrote: >> Implement faster bitrev8x4() for arm, arm64 and mips, all the platforms >> with CONFIG_HAVE_ARCH_BITREVERSE. >> ARM platforms just need a byteswap

Re: [PATCH v6 2/5] lib: implement __arch_bitrev8x4()

Will, On 12/19/2016 02:06 AM, Will Deacon wrote: > On Fri, Dec 16, 2016 at 03:17:51PM -0800, Joshua Clayton wrote: >> Implement faster bitrev8x4() for arm, arm64 and mips, all the platforms >> with CONFIG_HAVE_ARCH_BITREVERSE. >> ARM platforms just need a byteswap

[PATCH v6 2/5] lib: implement __arch_bitrev8x4()

__arch_bitrev32() Signed-off-by: Joshua Clayton <stillcompil...@gmail.com> --- arch/arm/include/asm/bitrev.h | 6 ++ arch/arm64/include/asm/bitrev.h | 6 ++ arch/mips/include/asm/bitrev.h | 6 ++ include/linux/bitrev.h | 1 + 4 files changed, 19 insertions(+) diff --git a/ar

[PATCH v6 2/5] lib: implement __arch_bitrev8x4()

__arch_bitrev32() Signed-off-by: Joshua Clayton --- arch/arm/include/asm/bitrev.h | 6 ++ arch/arm64/include/asm/bitrev.h | 6 ++ arch/mips/include/asm/bitrev.h | 6 ++ include/linux/bitrev.h | 1 + 4 files changed, 19 insertions(+) diff --git a/arch/arm/include/asm/bitrev.h b/arch/arm

[PATCH v6 3/5] doc: dt: add cyclone-ps-spi binding document

Describe a cyclone-ps-spi devicetree entry, required features Signed-off-by: Joshua Clayton <stillcompil...@gmail.com> Acked-by: Rob Herring <r...@kernel.org> --- .../bindings/fpga/cyclone-ps-spi-fpga-mgr.txt | 25 ++ 1 file changed, 25 insertions(+) create

[PATCH v6 5/5] ARM: dts: imx6q-evi: support cyclone-ps-spi

Add support for Altera cyclone V FPGA connected to an spi port to the evi devicetree file Signed-off-by: Joshua Clayton <stillcompil...@gmail.com> --- arch/arm/boot/dts/imx6q-evi.dts | 16 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/imx6q-evi.dts b/ar

[PATCH v6 1/5] lib: add bitrev8x4()

Add a function to reverse bytes within a 32 bit word. Operate on a u32 rather than individual bytes. ARCH specific versions require substantially fewer instructions than working a byte at a time. Signed-off-by: Joshua Clayton <stillcompil...@gmail.com> --- include/linux/bitrev.

[PATCH v6 4/5] fpga manager: Add cyclone-ps-spi driver for Altera FPGAs

cyclone-ps-spi loads FPGA firmware over spi, using the "passive serial" interface on Altera Cyclone FPGAS. This is one of the simpler ways to set up an FPGA at runtime. The signal interface is close to unidirectional spi with lsb first. Signed-off-by: Joshua Clayton <stillcompil

[PATCH v6 3/5] doc: dt: add cyclone-ps-spi binding document

Describe a cyclone-ps-spi devicetree entry, required features Signed-off-by: Joshua Clayton Acked-by: Rob Herring --- .../bindings/fpga/cyclone-ps-spi-fpga-mgr.txt | 25 ++ 1 file changed, 25 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga

[PATCH v6 5/5] ARM: dts: imx6q-evi: support cyclone-ps-spi

Add support for Altera cyclone V FPGA connected to an spi port to the evi devicetree file Signed-off-by: Joshua Clayton --- arch/arm/boot/dts/imx6q-evi.dts | 16 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/imx6q-evi.dts b/arch/arm/boot/dts/imx6q-evi.dts

[PATCH v6 1/5] lib: add bitrev8x4()

Add a function to reverse bytes within a 32 bit word. Operate on a u32 rather than individual bytes. ARCH specific versions require substantially fewer instructions than working a byte at a time. Signed-off-by: Joshua Clayton --- include/linux/bitrev.h | 25 + 1 file

[PATCH v6 4/5] fpga manager: Add cyclone-ps-spi driver for Altera FPGAs

cyclone-ps-spi loads FPGA firmware over spi, using the "passive serial" interface on Altera Cyclone FPGAS. This is one of the simpler ways to set up an FPGA at runtime. The signal interface is close to unidirectional spi with lsb first. Signed-off-by: Joshua Clayton --- drivers/fp

[PATCH v6 0/5] Altera Cyclone Passive Serial SPI FPGA Manager

ng - Replaced magic number for initial delay with a descriptive macro - Poll the fpga to see when it is ready rather than a fixed 1 ms sleep Joshua Clayton (5): lib: add bitrev8x4() lib: implement __arch_bitrev8x4() doc: dt: add cyclone-ps-spi binding document fpga manager: Add cyclone-ps-s

[PATCH v6 0/5] Altera Cyclone Passive Serial SPI FPGA Manager

ng - Replaced magic number for initial delay with a descriptive macro - Poll the fpga to see when it is ready rather than a fixed 1 ms sleep Joshua Clayton (5): lib: add bitrev8x4() lib: implement __arch_bitrev8x4() doc: dt: add cyclone-ps-spi binding document fpga manager: Add cyclone-ps-s

[PATCH v5 0/3] Altera Cyclone Passive Serial SPI FPGA Manager

problems introduced during refactoring - Replaced magic number for initial delay with a descriptive macro - Poll the fpga to see when it is ready rather than a fixed 1 ms sleep Joshua Clayton (3): lib: add bitrev8x4() doc: dt: add cyclone-ps-spi binding document fpga manager: Add cyclone-ps-s

[PATCH v5 0/3] Altera Cyclone Passive Serial SPI FPGA Manager

problems introduced during refactoring - Replaced magic number for initial delay with a descriptive macro - Poll the fpga to see when it is ready rather than a fixed 1 ms sleep Joshua Clayton (3): lib: add bitrev8x4() doc: dt: add cyclone-ps-spi binding document fpga manager: Add cyclone-ps-s

Re: [PATCH v5 3/3] fpga manager: Add cyclone-ps-spi driver for Altera FPGAs

:04:40 -0800 > Joshua Clayton stillcompil...@gmail.com wrote: > ... >> +static int cyclonespi_write_init(struct fpga_manager *mgr, u32 flags, >> + const char *buf, size_t count) > there is a minor API change in linux-next [1]. struct fpga_image_in

Re: [PATCH v5 3/3] fpga manager: Add cyclone-ps-spi driver for Altera FPGAs

:04:40 -0800 > Joshua Clayton stillcompil...@gmail.com wrote: > ... >> +static int cyclonespi_write_init(struct fpga_manager *mgr, u32 flags, >> + const char *buf, size_t count) > there is a minor API change in linux-next [1]. struct fpga_image_in

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