Hi,
On Mon, Mar 29, 2021 at 06:50:46PM +0100, Paul Cercueil wrote:
> Avoid requesting a full modeset if the sharpness property is not
> modified, because then we don't actually need it.
>
> Fixes: fc1acf317b01 ("drm/ingenic: Add support for the IPU")
> Cc: # 5.8+
> Signed-off-by: Paul Cercueil
Hi,
On Fri, Apr 09, 2021 at 09:35:07PM +0800, Kevin Tang wrote:
> > > > > + }
> > > > > +
> > > > > + return MODE_OK;
> > > > > +}
> > > > > +
> > > > > +static void sprd_crtc_atomic_enable(struct drm_crtc *crtc,
> > > > > +struct drm_atomic_state *state)
>
Hi,
On Thu, Apr 15, 2021 at 08:18:52AM +0800, Kevin Tang wrote:
> Maxime Ripard 于2021年3月24日周三 下午7:10写道：
> > > +static struct sprd_dpu *sprd_crtc_init(struct drm_device *drm,
> > > + struct drm_plane *primary)
> > > +{
> > > + struc
On Fri, Apr 09, 2021 at 08:23:19AM +0800, Kevin Tang wrote:
> Maxime Ripard 于2021年4月7日周三 下午6:46写道：
>
> > On Wed, Mar 31, 2021 at 09:49:14AM +0800, Kevin Tang wrote:
> > > Hi Maxime,
> > >
> > > Maxime Ripard 于2021年3月24日周三 下午7:13写道：
> > >
> &g
-by: Jernej Skrabec
Signed-off-by: Maxime Ripard
---
Changes from v1:
- Rebased on latest drm-misc-next tag
- Added the tags
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 3 +--
drivers/gpu/drm/drm_connector.c
drivers.
Reviewed-by: Harry Wentland
Reviewed-by: Jernej Skrabec
Signed-off-by: Maxime Ripard
---
Changes from v1:
- Rebased on latest drm-misc-next tag
- Added the tags
- Fix build breakage on amdgpu
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 23 ++-
drivers/gpu/drm
The intel driver uses the same logic to attach the Colorspace property
in multiple places and we'll need it in vc4 too. Let's move that common
code in a helper.
Signed-off-by: Maxime Ripard
---
Changes from v1:
- New patch
---
drivers/gpu/drm/drm_connector.c | 20
From: Dave Stevenson
Now that we can export deeper colour depths, add in the signalling
for HDR metadata.
Signed-off-by: Dave Stevenson
Signed-off-by: Maxime Ripard
---
Changes from v1:
- Rebased on latest drm-misc-next tag
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 53
Our driver while supporting HDR didn't send the proper colorimetry info
in the AVI infoframe.
Let's add the property needed so that the userspace can let us know what
the colorspace is supposed to be.
Signed-off-by: Maxime Ripard
---
Changes from v1:
- New patch
---
drivers/gpu/drm/vc4
, clk_round_rate has been adjusted to take the requests
into account and return a rate that will be greater or equal to the
requested rates.
Signed-off-by: Maxime Ripard
---
drivers/clk/clk.c | 121
include/linux/clk.h | 4 ++
2 files changed, 125
The new clock request API allows us to increase the rate of the HSM
clock to match our pixel rate requirements while decreasing it when
we're done, resulting in a better power-efficiency.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 19 ---
drivers/gpu/drm
an use-case for something else, this should
maybe be made more flexible?
Let me know what you think
Maxime
Maxime Ripard (2):
clk: Introduce a clock request API
drm/vc4: hdmi: Convert to the new clock request API
drivers/clk/clk.c | 121
On Tue, Apr 06, 2021 at 11:44:27PM +0200, Arnd Bergmann wrote:
> On Tue, Apr 6, 2021 at 12:11 AM Stephen Rothwell
> wrote:
> >
> > Hi all,
> >
> > On Tue, 6 Apr 2021 08:11:00 +1000 Stephen Rothwell
> > wrote:
> > >
> > > Hi all,
> > >
> > > Commit
> > >
> > > 3b493ac0ac04 ("arm64: dts:
On Wed, Mar 31, 2021 at 09:47:12AM +0800, Kevin Tang wrote:
> > > diff --git a/drivers/gpu/drm/sprd/Makefile
> > b/drivers/gpu/drm/sprd/Makefile
> > > index 6c25bfa99..d49f4977b 100644
> > > --- a/drivers/gpu/drm/sprd/Makefile
> > > +++ b/drivers/gpu/drm/sprd/Makefile
> > > @@ -1,5 +1,8 @@
> > >
On Wed, Mar 31, 2021 at 09:49:14AM +0800, Kevin Tang wrote:
> Hi Maxime,
>
> Maxime Ripard 于2021年3月24日周三 下午7:13写道：
>
> > On Mon, Feb 22, 2021 at 09:28:21PM +0800, Kevin Tang wrote:
> > > From: Kevin Tang
> > >
> > > Adds MIPI DSI Controller
Hi,
Adding Jörg, Will and Robin,
On Wed, Mar 31, 2021 at 09:21:19AM +0800, Kevin Tang wrote:
> > > +static u32 check_mmu_isr(struct sprd_dpu *dpu, u32 reg_val)
> > > +{
> > > + struct dpu_context *ctx = >ctx;
> > > + u32 mmu_mask = BIT_DPU_INT_MMU_VAOR_RD |
> > > +
On Wed, Mar 31, 2021 at 03:43:37PM +0200, Clément Péron wrote:
> Hi Jernej,
>
> On Tue, 30 Mar 2021 at 20:42, Jernej Skrabec wrote:
> >
> > Although every Beelink GS1 seems to have external 32768 Hz oscillator,
> > it works only on one from four tested. There are more reports of RTC
> > issues
Hi Samuel,
On Tue, Mar 23, 2021 at 11:44:50PM -0500, Samuel Holland wrote:
> On 3/22/21 8:56 PM, Andre Przywara wrote:
> >> I'm sending this patch as an RFC because it raises questions about how
> >> we handle firmware versioning. How far back does (or should) our support
> >> for old TF-A and
On Mon, Mar 29, 2021 at 04:15:28PM +0100, Paul Cercueil wrote:
> Hi Maxime,
>
> Le lun. 29 mars 2021 à 16:07, Maxime Ripard a écrit :
> > On Sat, Mar 27, 2021 at 11:22:14AM +, Paul Cercueil wrote:
> > > The ingenic-drm driver has two mutually exclusive primary p
On Sat, Mar 27, 2021 at 11:22:14AM +, Paul Cercueil wrote:
> The ingenic-drm driver has two mutually exclusive primary planes
> already; so the fact that a CRTC must have one and only one primary
> plane is an invalid assumption.
I mean, no? It's been documented for a while that a CRTC should
9200 : 24576000;
>^
>
> Signed-off-by: Pierre-Louis Bossart
Acked-by: Maxime Ripard
Thanks!
Maxime
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On Mon, Feb 22, 2021 at 09:28:21PM +0800, Kevin Tang wrote:
> From: Kevin Tang
>
> Adds MIPI DSI Controller
> support for Unisoc's display subsystem.
>
> Cc: Orson Zhai
> Cc: Chunyan Zhang
> Signed-off-by: Kevin Tang
> Reviewed-by: Rob Herring
> ---
>
Hi,
On Mon, Feb 22, 2021 at 09:28:20PM +0800, Kevin Tang wrote:
> Adds DPU(Display Processor Unit) support for the Unisoc's display subsystem.
> It's support multi planes, scaler, rotation, PQ(Picture Quality) and more.
>
> Cc: Orson Zhai
> Cc: Chunyan Zhang
> Signed-off-by: Kevin Tang
>
>
Hi
On Mon, Feb 22, 2021 at 09:28:18PM +0800, Kevin Tang wrote:
> Adds drm support for the Unisoc's display subsystem.
>
> This is drm kms driver, this driver provides support for the
> application framework in Android, Yocto and more.
>
> Application framework can access Unisoc's display
aurent Pinchart
> Cc: Jonas Karlman
> Cc: Andrzej Hajda
> Cc: Jernej Škrabec
> Cc: Daniel Vetter
> Signed-off-by: Robert Foss
Acked-by: Maxime Ripard
Maxime
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On Wed, Mar 24, 2021 at 11:55:35AM +0200, Laurent Pinchart wrote:
> Hi Jagan,
>
> On Wed, Mar 24, 2021 at 03:19:10PM +0530, Jagan Teki wrote:
> > On Wed, Mar 24, 2021 at 3:09 PM Laurent Pinchart wrote:
> > > On Wed, Mar 24, 2021 at 02:44:57PM +0530, Jagan Teki wrote:
> > > > On Wed, Mar 24, 2021
hi,
On Tue, Mar 23, 2021 at 09:43:41PM +0100, Jernej Skrabec wrote:
> Beelink X2 has power button. Add node for it.
>
> Signed-off-by: Jernej Skrabec
Applied, thanks
Maxime
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On Sat, Mar 20, 2021 at 02:20:56AM +0200, Laurent Pinchart wrote:
> Hi Maxime,
>
> Thank you for the patch.
>
> On Fri, Mar 19, 2021 at 04:29:20PM +0100, Maxime Ripard wrote:
> > Commit 977697e20b3d ("drm/atomic: Pass the full state to planes atomic
> > disable
le.
Remove it.
Fixes: 977697e20b3d ("drm/atomic: Pass the full state to planes atomic disable
and update")
Reported-by: Stephen Rothwell
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/r
From: Dave Stevenson
Now that we can export deeper colour depths, add in the signalling
for HDR metadata.
Signed-off-by: Dave Stevenson
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 53 ++
drivers/gpu/drm/vc4/vc4_hdmi.h | 3 ++
2 files
All the drivers that implement HDR output call pretty much the same
function to initialise the hdr_output_metadata property, and while the
creation of that property is in a helper, every driver uses the same
code to attach it.
Provide a helper for it as well
Signed-off-by: Maxime Ripard
drivers.
Signed-off-by: Maxime Ripard
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 21 +-
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 17 +--
drivers/gpu/drm/drm_connector.c | 28 +++
drivers/gpu/drm/i915/display/intel_atomic.c | 13
ed at all.
> In a couple of cases, fixing the compatible revealed some schema errors
> which are fixed.
>
> There's a bunch of others remaining after this which have bindings, but
> those aren't converted to schema yet.
>
> Cc: Stephen Boyd
> Cc: Maxime Ripard
> Cc: Thierry Red
gt; Cc: Nicolas Saenz Julienne
> Cc: Maxime Ripard
> Cc: Linus Walleij
> Cc: Bartosz Golaszewski
> Cc: Bjorn Andersson
> Cc: Krzysztof Kozlowski
> Cc: Marc Kleine-Budde
> Cc: "David S. Miller"
> Cc: Jakub Kicinski
> Cc: Srinivas Kandagatla
> Cc:
r supports only the 32 first locks. This is the reason the
> first way (lock read/write) approach is used to be able to cover all 256
> locks in future devices. The driver also reports the amount of supported
> locks via debugfs.
>
> Signed-off-by: Wilken Gottwalt
Acked-by: Maxime Ripard
Maxime
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On Sun, Mar 14, 2021 at 10:30:49AM +0100, Wilken Gottwalt wrote:
> Adds documentation on how to use the sun6i_hwspinlock driver for sun6i
> compatible series SoCs.
>
> Signed-off-by: Wilken Gottwalt
Acked-by: Maxime Ripard
Maxime
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Hi!
On Mon, Mar 08, 2021 at 10:47:03AM +0800, 班涛 wrote:
> Maxime Ripard 于2021年3月5日周五 上午12:07写道：
>
> > Hi,
> >
> > On Tue, Mar 02, 2021 at 08:37:37PM +0800, Ban Tao wrote:
> > > From: Ban Tao
> > >
> > > The Allwinner R818, A133, R329, V536
Hi,
On Thu, Mar 11, 2021 at 10:59:35PM +0100, Jernej Škrabec wrote:
> Hi!
>
> Dne ponedeljek, 08. marec 2021 ob 14:05:06 CET je Maxime Ripard napisal(a):
> > Hi
> >
> > On Sat, Mar 06, 2021 at 09:36:11PM +0100, Jernej Skrabec wrote:
> > > B
>
> Signed-off-by: Samuel Holland
Acked-by: Maxime Ripard
Thanks!
Maxime
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> Signed-off-by: Samuel Holland
Acked-by: Maxime Ripard
Thanks!
Maxime
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Hi,
On Tue, Mar 09, 2021 at 09:03:14AM +0100, Rasmus Villemoes wrote:
> On 03/09/2020 06.00, Samuel Holland wrote:
> > Stephen, Maxime,
> >
> > You previously asked me to implement the protected-clocks property in a
> > driver-independent way:
> >
> >
Hi,
On Tue, Mar 09, 2021 at 04:21:16AM +0300, Evgeny Boger wrote:
> R40 (aka V40, A40i, T3) has two different Ethernet IP
> called EMAC and GMAC.
> EMAC only support 10/100 Mbit in MII mode,
> while GMAC support both 10/100 (MII) and 10/100/1000 (RGMII).
>
> In contrast to A10/A20 where GMAC and
Hi,
On Tue, Mar 09, 2021 at 04:21:15AM +0300, Evgeny Boger wrote:
> R40 (aka V40/A40i/T3) and A10/A20 share the same EMAC IP.
> However, on R40 the EMAC is gated by default.
>
> Signed-off-by: Evgeny Boger
> ---
> .../net/allwinner,sun4i-a10-emac.yaml | 11 +++-
>
On Sat, Mar 06, 2021 at 12:05:22PM +0100, Wilken Gottwalt wrote:
> On Tue, 2 Mar 2021 18:20:02 +0100
> Maxime Ripard wrote:
>
> > Hi,
> >
> > On Mon, Mar 01, 2021 at 03:06:08PM +0100, Wilken Gottwalt wrote:
> > > On Mon, 1 Mar 2021 14:13
not understand function
> > prototype: 'struct usb_reset_data '
> > drivers/clk/sunxi/clk-sun6i-ar100.c:26: warning: Function parameter or
> > member 'req' not described in 'sun6i_get_ar100_factors'
> >
> > Cc: "Emilio López"
> > Cc: Michael Turque
On Sun, Jan 03, 2021 at 04:00:07AM -0600, Samuel Holland wrote:
> On boards where the only peripheral connected to PL0/PL1 is an X-Powers
> PMIC, configure the connection to use the RSB bus rather than the I2C
> bus. Compared to the I2C controller that shares the pins, the RSB
> controller allows
Hi,
On Sun, Mar 07, 2021 at 06:13:53AM +0300, Evgeny Boger wrote:
> R40 (aka V40, A40i, T3) has two different Ethernet IP
> called EMAC and GMAC.
> EMAC only support 10/100 Mbit in MII mode,
> while GMAC support both 10/100 (MII) and 10/100/1000 (RGMII).
>
> In contrast to A10/A20 where GMAC and
Hi,
On Sun, Mar 07, 2021 at 06:13:51AM +0300, Evgeny Boger wrote:
> R40 (aka V40/A40i/T3) and A10/A20 share the same EMAC IP.
> However, on R40 the EMAC is gated by default.
>
> Signed-off-by: Evgeny Boger
On which device was it tested?
> ---
> drivers/net/ethernet/allwinner/sun4i-emac.c |
Hi
On Sat, Mar 06, 2021 at 09:36:11PM +0100, Jernej Skrabec wrote:
> Beelink X2 has power button. Add node for it.
>
> Signed-off-by: Jernej Skrabec
> ---
> arch/arm/boot/dts/sun8i-h3-beelink-x2.dts | 11 +++
> 1 file changed, 11 insertions(+)
>
> diff --git
Hi,
On Tue, Mar 02, 2021 at 08:40:23PM +0800, Ban Tao wrote:
> From: Ban Tao
>
> This adds binding documentation for sun8i-v536 SoC PWM driver.
>
> Signed-off-by: Ban Tao
> ---
> .../bindings/pwm/pwm-sun8i-v536.txt | 24 +++
Bindings should be done using the YAML
Hi,
On Tue, Mar 02, 2021 at 08:37:37PM +0800, Ban Tao wrote:
> From: Ban Tao
>
> The Allwinner R818, A133, R329, V536 and V833 has a new PWM controller
> IP compared to the older Allwinner SoCs.
>
> Signed-off-by: Ban Tao
Thanks for sending an update.
Like I said in the previous version
On Fri, Feb 26, 2021 at 01:53:00PM +0100, Marjan Pascolo wrote:
> Hi Maxime,
>
> Il 17/02/2021 12:03, Maxime Ripard ha scritto:
> > Hi,
> >
> > On Wed, Feb 10, 2021 at 05:22:37PM +0100, Marjan Pascolo wrote:
> > > On Allwinner SoC interrupt debounce
Hi,
On Mon, Mar 01, 2021 at 03:06:08PM +0100, Wilken Gottwalt wrote:
> On Mon, 1 Mar 2021 14:13:05 +0100
> Maxime Ripard wrote:
>
> > On Sat, Feb 27, 2021 at 02:03:54PM +0100, Wilken Gottwalt wrote:
> > > Adds the sun6i_hwspinlock driver for the hardware spinlock
On Mon, Mar 01, 2021 at 03:06:35PM +0100, Wilken Gottwalt wrote:
> On Mon, 1 Mar 2021 14:12:44 +0100
> Maxime Ripard wrote:
>
> > On Sat, Feb 27, 2021 at 02:03:28PM +0100, Wilken Gottwalt wrote:
> > > Adds documentation on how to use the sun6i_hwspinlock driver for sun6i
On Fri, Feb 26, 2021 at 10:40:24PM +0530, Jagan Teki wrote:
> On Fri, Feb 26, 2021 at 10:27 PM Maxime Ripard wrote:
> >
> > Hi,
> >
> > On Mon, Feb 15, 2021 at 01:11:01AM +0530, Jagan Teki wrote:
> > > Use drm_panel_bridge to replace manual panel handli
Hi,
On Tue, Mar 02, 2021 at 12:23:09AM +0800, Chen-Yu Tsai wrote:
> From: Chen-Yu Tsai
>
> The macros for the clock and reset indices for the RSB hardware block
> were replaced with raw numbers when the RSB controller node was added.
> This was done to avoid cross-tree dependencies.
>
> Now
Hi,
On Fri, Feb 26, 2021 at 11:30:28AM +0100, Tobias Schramm wrote:
> The V3 and S3 SoCs feature an i2s peripheral identical to that of the H3.
> Add it to the dts.
>
> Signed-off-by: Tobias Schramm
Why is it added to the v3 DTSI and not the global one?
> ---
>
On Fri, Feb 26, 2021 at 11:30:26AM +0100, Tobias Schramm wrote:
> The V3s, V3 and S3 SoCs have a dma controller. Add it to the dts.
>
> Signed-off-by: Tobias Schramm
Applied, thanks
Maxime
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On Sat, Feb 27, 2021 at 02:03:54PM +0100, Wilken Gottwalt wrote:
> Adds the sun6i_hwspinlock driver for the hardware spinlock unit found in
> most of the sun6i compatible SoCs.
>
> This unit provides at least 32 spinlocks in hardware. The implementation
> supports 32, 64, 128 or 256 32bit
ion
>
> Changes in v5:
> - changed binding to earliest known supported SoC sun6i-a31
> - dropped unnecessary entries
>
> Changes in v4:
> - changed binding to sun8i-a33-hwpinlock
> - added changes suggested by Maxime Ripard
>
> Changes in v3:
> -
Hi,
On Mon, Feb 15, 2021 at 01:11:01AM +0530, Jagan Teki wrote:
> Use drm_panel_bridge to replace manual panel handling code.
>
> This simplifies the driver to allows all components in the
> display pipeline to be treated as bridges, paving the way
> to generic connector handling.
>
> Use
On Wed, Feb 24, 2021 at 11:52:38AM +0100, Pascal Roeleven wrote:
> On request I'm resending the last two patches from the Topwise A721 tablet
> series from a year ago as they weren't picked up. The other patches are
> already merged, so I didn't resend them.
>
> Changes from v4:
> * Reorder nodes
Hi,
On Wed, Feb 24, 2021 at 12:33:45PM +0100, Thomas Zimmermann wrote:
> Hi Maxime,
>
> for the whole series:
>
> Acked-by: Thomas Zimmermann
Applied the whole series, thanks to everyone involved in the review,
it's been a pretty daunting one :)
Maxime
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Hi,
We're almost there, except for ...
On Mon, Feb 22, 2021 at 11:08:26AM +0100, Pascal Roeleven wrote:
> + {
> + vref-supply = <_ldo2>;
> + status = "okay";
> +
> + button-761 {
> + label = "Volume Down";
> + linux,code = ;
> + channel = <0>;
> +
Hi Thomas,
On Mon, Feb 22, 2021 at 10:12:49AM +0100, Thomas Zimmermann wrote:
> Am 19.02.21 um 13:00 schrieb Maxime Ripard:
> > Many drivers reference the plane->state pointer in order to get the
> > current plane state in their atomic_check hook, which would be the o
Hi Thomas,
Thanks for your review!
On Fri, Feb 19, 2021 at 03:49:22PM +0100, Thomas Zimmermann wrote:
> > diff --git a/drivers/gpu/drm/imx/ipuv3-plane.c
> > b/drivers/gpu/drm/imx/ipuv3-plane.c
> > index 075508051b5f..1873a155bb26 100644
> > --- a/drivers/gpu/drm/imx/ipuv3-plane.c
> > +++
ude
Reviewed-by: Ville Syrjälä
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/arc/arcpgu_crtc.c | 4 +++-
drivers/gpu/drm/arm/hdlcd_crtc.c| 3 ++-
drivers/gpu/drm/arm/malidp_planes.c | 3 ++-
drivers/gpu/drm/armada/armada_overlay.c | 3 ++-
drivers/
state
+ state
...+>
}
Reviewed-by: Laurent Pinchart
Signed-off-by: Maxime Ripard
---
Changes from v1:
- Reintroduce the old_plane_state check in zynqmp_disp_crtc_atomic_disable
---
drivers/gpu/drm/arc/arcpgu_crtc.c | 2 +-
drivers/gpu/drm/arm/display/k
s;
@@
func(struct drm_plane *plane, struct drm_plane_state *old_s)
{
+ struct drm_plane_state *new_s = plane->state;
<+...
- plane->state
+ new_s
...+>
}
Reviewed-by: Laurent Pinchart
Signed-off-by: Maxime Ripard
---
Changes from v1:
- Wrapping cha
On Thu, Feb 18, 2021 at 12:20:01PM +0100, Tobias Schramm wrote:
> Previously it was not possible to achieve clock rates of 24.576MHz and
> 22.5792MHz, which are commonly required core clocks for the i2s
> peripheral of v3s based SoCs.
>
> Add support for those clock rates through the audio pll's
ane_state = drm_atomic_get_new_plane_state(state,
plane);
<...
- plane_state->state
+ state
...>
}
Reviewed-by: Laurent Pinchart
Signed-off-by: Maxime Ripard
---
Changes from v1:
- Fixed the formatting in zynqmp_disp
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
drivers/gpu/drm/
.
Acked-by: Daniel Vetter
Signed-off-by: Maxime Ripard
---
Changes from v1:
- New patch
---
Documentation/gpu/todo.rst | 46 --
1 file changed, 46 deletions(-)
diff --git a/Documentation/gpu/todo.rst b/Documentation/gpu/todo.rst
index f872d3d33218..0631b9b323d5
@ no_include depends on !include && adds_new_state @
@@
+ #include
#include
Reviewed-by: Laurent Pinchart
Signed-off-by: Maxime Ripard
---
Changes from v1:
- Rewording and removal of a coccinelle rule suggested by Laurent
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |
}
Reviewed-by: Laurent Pinchart
Signed-off-by: Maxime Ripard
---
Changes from v1:
- Updated the variable name in the comment in omapdrm
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 13 +++---
.../gpu/drm/arm/display/komeda/komeda_plane.c | 11 ++---
drivers/gpu/drm/arm/hdlcd_crtc.c
c(struct drm_plane *plane, struct drm_plane_state *old_pstate)
{
<...
- state
+ new_pstate
...>
}
Reviewed-by: Ville Syrjälä
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/arm/malidp_planes.c | 34 +++---
drivers/gpu/drm/armada/armada_overlay.c
<+...
- plane_state->state
+ state
...+>
}
Acked-by: Thomas Zimmermann
Signed-off-by: Maxime Ripard
---
Changes from v1:
- Updated the comment according to Thomas suggestions
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 ++-
drivers/gpu/drm/drm_atomic_helper.c
plane->state
+ old_plane_state
...>
}
@ include depends on adds_old_state || replaces_old_state @
@@
#include
@ no_include depends on !include && (adds_old_state || replaces_old_state) @
@@
+ #include
#include
Reviewed-by: Ville Syrjälä
Signed-off-by: Maxime Ripa
Subsequent reworks will pass the global atomic state in the function
prototype, and atomic_check and atomic_update already have such a
variable already. Let's change them to ease the rework.
Acked-by: Sam Ravnborg
Signed-off-by: Maxime Ripard
---
.../gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c
Hi,
On Tue, Feb 16, 2021 at 05:59:54PM +0100, Pascal Roeleven wrote:
> The Topwise A721/LY-F1 tablet is a tablet sold around 2012 under
> different brands. The mainboard mentions A721 clearly, so this tablet
> is best known under this name.
>
> Signed-off-by: Pascal Roeleven
> ---
>
On Thu, Feb 18, 2021 at 05:21:16PM +0800, Icenowy Zheng wrote:
>
>
> 于 2021年2月18日 GMT+08:00 下午5:18:39, Tobias Schramm 写到:
> >Hi Icenowy,
> >
> > > We have introducee SDM-based accurate audio PLL on several
> >> other SoCs. Some people is quite sensitive about audio-related
> >things.
> > >
>
Hi,
On Fri, Feb 12, 2021 at 02:57:25PM +0100, Tobias Schramm wrote:
> Previously the variable rate audio pll output was fixed to a divider of
> four. This is unfortunately incompatible with generating commonly used
> I2S core clock rates like 24.576MHz from the 24MHz parent clock.
> This commit
e" which have 1uS accuracy.
> For acheive nS precision a new device tree poperty is made
> named "input-debounce-ns".
> "input-debounce-ns" is checked only if "input-debounce"
> property is not defined.
>
> Suggested-by: Maxime Ripard
> Sign
or now which will mean that HDMI I2C will be
> polled, like it was before.
>
> Reported-by: Dave Stevenson
> Signed-off-by: Florian Fainelli
Acked-by: Maxime Ripard
Thanks!
Maxime
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r wrote:
> > > >
> > > > Hi Maxime,
> > > >
> > > > On 2021-02-10 14:40, Maxime Ripard wrote:
> > > > > Hi Dave,
> > > > >
> > > > > On Tue, Feb 09, 2021 at 09:49:05AM +, Dave Stevenson wrote:
> > > >
Hi,
On Thu, Feb 11, 2021 at 03:25:23PM +, Yassine Oudjana wrote:
> sun5i has the same Mali 400 GPU as sun4i with the same interrupts, clocks
> and resets. Add node for it in dts.
>
> Signed-off-by: Yassine Oudjana
Unfortunately we already merged a similar patch for 5.12
Maxime
Hi,
On Mon, Feb 08, 2021 at 12:24:57PM +0100, B.R. Oake wrote:
> Since commit bbc4d71d6354 ("net: phy: realtek: fix rtl8211e rx/tx
> delay config"), Ethernet no longer works on the Orange Pi Plus,
> because that commit sets the RX/TX delay according to the phy-mode
> property in the device tree,
Hi Dave,
On Tue, Feb 09, 2021 at 09:49:05AM +, Dave Stevenson wrote:
> On Mon, 11 Jan 2021 at 14:23, Maxime Ripard wrote:
> >
> > The BSC controllers used for the HDMI DDC have an interrupt controller
> > shared between both instances. Let's add it to avoid polling.
&g
On Tue, Feb 09, 2021 at 06:58:55PM +0100, Jernej Skrabec wrote:
> Over the year I got plenty of reports of troubles with H6 HDMI signal.
> Sometimes monitor flickers, sometimes there was no image at all and
> sometimes it didn't play well with AVR.
>
> It turns out there are multiple issues.
d-by: Chen-Yu Tsai
> Tested-by: Andre Heider
> Signed-off-by: Jernej Skrabec
This is a last minute fix for us, can you merge it into clk-fixes directly?
Acked-by: Maxime Ripard
Thanks!
Maxime
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On Thu, Jan 28, 2021 at 01:39:38PM +0200, Roman Stratiienko wrote:
>
> Please review/merge.
>
> v2:
> Initial patch
>
> v3:
> - Skip adding & applying alpha property if VI count > 1 (v3s case)
>
> v4:
> Resend (author's email changed)
>
> v5:
> Resend
Applied, thanks
Maxime
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On Sat, Feb 06, 2021 at 09:27:30PM +0800, 班涛 wrote:
> Maxime Ripard 于2021年2月6日周六 上午12:12写道：
>
> > Hi,
> >
> > On Thu, Feb 04, 2021 at 11:47:34AM +0800, 班涛 wrote:
> > > Maxime Ripard 于2021年2月3日周三 下午11:46写道：
> > >
> > > > Hi,
> > > &g
dt_binding_check] Error 2
>
> > > Signed-off-by: Wilken Gottwalt
> > > ---
> > > Changes in v5:
> > > - changed binding to earliest known supported SoC sun6i-a31
> > > - dropped unnecessary entries
> > >
> > > Changes in v4:
> >
On Fri, Feb 05, 2021 at 07:47:17PM +0100, Jernej Škrabec wrote:
> Dne petek, 05. februar 2021 ob 17:28:23 CET je Chen-Yu Tsai napisal(a):
> > On Sat, Feb 6, 2021 at 12:21 AM Jernej Škrabec
> wrote:
> > >
> > > Dne petek, 05. februar 2021 ob 17:01:3
On Fri, Feb 05, 2021 at 11:21:22AM +0800, Chen-Yu Tsai wrote:
> On Fri, Feb 5, 2021 at 2:48 AM Jernej Skrabec wrote:
> >
> > Channel 1 has polarity bits for vsync and hsync signals but driver never
> > sets them. It turns out that with pre-HDMI2 controllers seemingly there
> > is no issue if
Hi,
On Thu, Feb 04, 2021 at 11:47:34AM +0800, 班涛 wrote:
> Maxime Ripard 于2021年2月3日周三 下午11:46写道：
>
> > Hi,
> >
> > On Wed, Feb 03, 2021 at 08:53:17PM +0800, Ban Tao wrote:
> > > From: Ban Tao
> > >
> > > The Allwinner R818, A133, R329, V536
Hi,
On Wed, Feb 03, 2021 at 08:53:17PM +0800, Ban Tao wrote:
> From: Ban Tao
>
> The Allwinner R818, A133, R329, V536 and V833 has a new PWM controller
> IP compared to the older Allwinner SoCs.
>
> Signed-off-by: Ban Tao
Thanks for your patch. There's a bunch of warnings reported by
On Tue, Jan 26, 2021 at 04:54:59PM +, Lee Jones wrote:
> On Tue, 26 Jan 2021, Maxime Ripard wrote:
>
> > On Tue, Jan 26, 2021 at 12:45:31PM +, Lee Jones wrote:
> > > Fixes the following W=1 kernel build warning(s):
> > >
> > > drivers/clk/sunxi/
On Mon, Feb 01, 2021 at 06:18:18PM +0100, agriveaux wrote:
> On Thu, Jan 28, 2021 at 06:23:29PM +0100, Maxime Ripard wrote:
> > Hi,
> Hi,
> >
> > On Sun, Jan 24, 2021 at 08:39:03PM +0100, Alexandre GRIVEAUX wrote:
> > > Add Inet 86V Rev 2 support, based upon Ine
Cc: Vasily Khoruzhick
> Cc: Yangtao Li
> Cc: Zhang Rui
> Cc: Daniel Lezcano
> Cc: Amit Kucheria
> Cc: Maxime Ripard
> Cc: Chen-Yu Tsai
> Cc: Jernej Skrabec
> Cc: linux...@vger.kernel.org
> Signed-off-by: Rob Herring
Acked-by: Maxime Ripard
Maxime
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-18,7 +18,7 @@ properties:
> > const: 1
> >
> >compatible:
> > -const: allwinner,sun9i-a80-usb-clocks
> > +const: allwinner,sun9i-a80-usb-clks
>
> Should the file name change too?
Ideally yes, and with that change
Acked-by: Maxime Ripard
Maxime
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