[PATCH] mtd: spi-nor: cadence-quadspi: write upto 8-bytes data in STIG mode
cadence-quadspi controller allows upto eight bytes of data to
be written in software Triggered Instruction generator (STIG) mode
of operation. Lower 4 bytes are written through writedatalower and
upper 4 bytes by writedataupper register.
This patch allows all the 8 bytes to be written.
Signed-off-by: Purna Chandra Mandal
---
drivers/mtd/spi-nor/cadence-quadspi.c | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c
b/drivers/mtd/spi-nor/cadence-quadspi.c
index 04cedd3a2bf6..7f78f9409ddd 100644
--- a/drivers/mtd/spi-nor/cadence-quadspi.c
+++ b/drivers/mtd/spi-nor/cadence-quadspi.c
@@ -418,9 +418,10 @@ static int cqspi_command_write(struct spi_nor *nor, const
u8 opcode,
void __iomem *reg_base = cqspi->iobase;
unsigned int reg;
unsigned int data;
+ u32 write_len;
int ret;
- if (n_tx > 4 || (n_tx && !txbuf)) {
+ if (n_tx > CQSPI_STIG_DATA_LEN_MAX || (n_tx && !txbuf)) {
dev_err(nor->dev,
"Invalid input argument, cmdlen %d txbuf 0x%p\n",
n_tx, txbuf);
@@ -433,10 +434,18 @@ static int cqspi_command_write(struct spi_nor *nor, const
u8 opcode,
reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
<< CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
data = 0;
- memcpy(, txbuf, n_tx);
+ write_len = (n_tx > 4) ? 4 : n_tx;
+ memcpy(, txbuf, write_len);
+ txbuf += write_len;
writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER);
- }
+ if (n_tx > 4) {
+ data = 0;
+ write_len = n_tx - 4;
+ memcpy(, txbuf, write_len);
+ writel(data, reg_base + CQSPI_REG_CMDWRITEDATAUPPER);
+ }
+ }
ret = cqspi_exec_flash_cmd(cqspi, reg);
return ret;
}
--
2.13.0
[PATCH] mtd: spi-nor: cadence-quadspi: write upto 8-bytes data in STIG mode
cadence-quadspi controller allows upto eight bytes of data to be transferred
in software Triggered Instruction generator (STIG) mode of operation. Lower
4 bytes are written through writedatalower and upper 4 bytes by
writedataupper register.
This patch allows all the 8 bytes to be written.
Signed-off-by: Purna Chandra Mandal
---
drivers/mtd/spi-nor/cadence-quadspi.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c
b/drivers/mtd/spi-nor/cadence-quadspi.c
index 04cedd3a2bf6..990934387fea 100644
--- a/drivers/mtd/spi-nor/cadence-quadspi.c
+++ b/drivers/mtd/spi-nor/cadence-quadspi.c
@@ -420,7 +420,7 @@ static int cqspi_command_write(struct spi_nor *nor, const
u8 opcode,
unsigned int data;
int ret;
- if (n_tx > 4 || (n_tx && !txbuf)) {
+ if (n_tx > CQSPI_STIG_DATA_LEN_MAX || (n_tx && !txbuf)) {
dev_err(nor->dev,
"Invalid input argument, cmdlen %d txbuf 0x%p\n",
n_tx, txbuf);
@@ -435,8 +435,13 @@ static int cqspi_command_write(struct spi_nor *nor, const
u8 opcode,
data = 0;
memcpy(, txbuf, n_tx);
writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER);
- }
+ if (n_tx > 4) {
+ data = 0;
+ memcpy(, txbuf + 4, n_tx - 4);
+ writel(data, reg_base + CQSPI_REG_CMDWRITEDATAUPPER);
+ }
+ }
ret = cqspi_exec_flash_cmd(cqspi, reg);
return ret;
}
--
2.13.0
[PATCH v2] MIPS: pic32mzda: fix linker error for pic32_get_pbclk().
Early clock API pic32_get_pbclk() is defined in early_clk.c and used by time.c and early_console.c. When CONFIG_EARLY_PRINTK isn't set, early_clk.c isn't compiled and time.c fails to link. Fix it by compiling early_clk.c always. Also sort files in alphabetical order. Cc: Harvey Hunt <harvey.h...@imgtec.com> Cc: Ralf Baechle <r...@linux-mips.org> Cc: linux-m...@linux-mips.org Cc: Joshua Henderson <digitalp...@digitalpeer.com> Reported-by: Harvey Hunt <harvey.h...@imgtec.com> Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com> Reviewed-by: Harvey Hunt <harvey.h...@imgtec.com> --- Changes in v2: - update commit message arch/mips/pic32/pic32mzda/Makefile | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/mips/pic32/pic32mzda/Makefile b/arch/mips/pic32/pic32mzda/Makefile index 4a4c272..c286496 100644 --- a/arch/mips/pic32/pic32mzda/Makefile +++ b/arch/mips/pic32/pic32mzda/Makefile @@ -2,8 +2,7 @@ # Joshua Henderson, <joshua.hender...@microchip.com> # Copyright (C) 2015 Microchip Technology, Inc. All rights reserved. # -obj-y := init.o time.o config.o +obj-y := config.o early_clk.o init.o time.o obj-$(CONFIG_EARLY_PRINTK) += early_console.o \ - early_pin.o \ - early_clk.o + early_pin.o -- 1.8.3.1
[PATCH v2] MIPS: pic32mzda: fix linker error for pic32_get_pbclk().
Early clock API pic32_get_pbclk() is defined in early_clk.c and used by time.c and early_console.c. When CONFIG_EARLY_PRINTK isn't set, early_clk.c isn't compiled and time.c fails to link. Fix it by compiling early_clk.c always. Also sort files in alphabetical order. Cc: Harvey Hunt Cc: Ralf Baechle Cc: linux-m...@linux-mips.org Cc: Joshua Henderson Reported-by: Harvey Hunt Signed-off-by: Purna Chandra Mandal Reviewed-by: Harvey Hunt --- Changes in v2: - update commit message arch/mips/pic32/pic32mzda/Makefile | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/mips/pic32/pic32mzda/Makefile b/arch/mips/pic32/pic32mzda/Makefile index 4a4c272..c286496 100644 --- a/arch/mips/pic32/pic32mzda/Makefile +++ b/arch/mips/pic32/pic32mzda/Makefile @@ -2,8 +2,7 @@ # Joshua Henderson, # Copyright (C) 2015 Microchip Technology, Inc. All rights reserved. # -obj-y := init.o time.o config.o +obj-y := config.o early_clk.o init.o time.o obj-$(CONFIG_EARLY_PRINTK) += early_console.o \ - early_pin.o \ - early_clk.o + early_pin.o -- 1.8.3.1
Re: [PATCH] MIPS: pic32mzda: fix linker error for pic32_get_pbclk().
On 06/02/2016 02:45 PM, Harvey Hunt wrote: > Hi Purna, > > On 02/06/16 06:20, Purna Chandra Mandal wrote: >> Early clock API pic32_get_pbclk() is defined in early_clk.c and >> used by time.c and early_console.c. When CONFIG_EARLY_PRINTK isn't >> set, early_clk.c isn't compiled and so a linker error is reported >> while referring the API from time.c. > > Maybe "early_clk.c isn't compiled and so time.c fails to link"? > ack. >> >> Fix it by compiling early_clk.c always. Also sort files in >> alphabetical order. >> >> Cc: Harvey Hunt <harvey.h...@imgtec.com> >> Cc: Ralf Baechle <r...@linux-mips.org> >> Cc: linux-m...@linux-mips.org >> Cc: Joshua Henderson <digitalp...@digitalpeer.com> >> >> Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com> >> >> --- >> >> arch/mips/pic32/pic32mzda/Makefile | 5 ++--- >> 1 file changed, 2 insertions(+), 3 deletions(-) >> >> diff --git a/arch/mips/pic32/pic32mzda/Makefile >> b/arch/mips/pic32/pic32mzda/Makefile >> index 4a4c272..c286496 100644 >> --- a/arch/mips/pic32/pic32mzda/Makefile >> +++ b/arch/mips/pic32/pic32mzda/Makefile >> @@ -2,8 +2,7 @@ >> # Joshua Henderson, <joshua.hender...@microchip.com> >> # Copyright (C) 2015 Microchip Technology, Inc. All rights reserved. >> # >> -obj-y:= init.o time.o config.o >> +obj-y:= config.o early_clk.o init.o time.o >> >> obj-$(CONFIG_EARLY_PRINTK)+= early_console.o \ >> - early_pin.o\ >> - early_clk.o >> + early_pin.o >> > > Perhaps add: > > Reported-by: Harvey Hunt <harvey.h...@imgtec.com> > > Thanks for fixing this, > > Reviewed-by: Harvey Hunt <harvey.h...@imgtec.com> > Thanks Harvey. > Thanks, > > Harvey
Re: [PATCH] MIPS: pic32mzda: fix linker error for pic32_get_pbclk().
On 06/02/2016 02:45 PM, Harvey Hunt wrote: > Hi Purna, > > On 02/06/16 06:20, Purna Chandra Mandal wrote: >> Early clock API pic32_get_pbclk() is defined in early_clk.c and >> used by time.c and early_console.c. When CONFIG_EARLY_PRINTK isn't >> set, early_clk.c isn't compiled and so a linker error is reported >> while referring the API from time.c. > > Maybe "early_clk.c isn't compiled and so time.c fails to link"? > ack. >> >> Fix it by compiling early_clk.c always. Also sort files in >> alphabetical order. >> >> Cc: Harvey Hunt >> Cc: Ralf Baechle >> Cc: linux-m...@linux-mips.org >> Cc: Joshua Henderson >> >> Signed-off-by: Purna Chandra Mandal >> >> --- >> >> arch/mips/pic32/pic32mzda/Makefile | 5 ++--- >> 1 file changed, 2 insertions(+), 3 deletions(-) >> >> diff --git a/arch/mips/pic32/pic32mzda/Makefile >> b/arch/mips/pic32/pic32mzda/Makefile >> index 4a4c272..c286496 100644 >> --- a/arch/mips/pic32/pic32mzda/Makefile >> +++ b/arch/mips/pic32/pic32mzda/Makefile >> @@ -2,8 +2,7 @@ >> # Joshua Henderson, >> # Copyright (C) 2015 Microchip Technology, Inc. All rights reserved. >> # >> -obj-y:= init.o time.o config.o >> +obj-y:= config.o early_clk.o init.o time.o >> >> obj-$(CONFIG_EARLY_PRINTK)+= early_console.o \ >> - early_pin.o\ >> - early_clk.o >> + early_pin.o >> > > Perhaps add: > > Reported-by: Harvey Hunt > > Thanks for fixing this, > > Reviewed-by: Harvey Hunt > Thanks Harvey. > Thanks, > > Harvey
[PATCH] MIPS: pic32mzda: fix linker error for pic32_get_pbclk().
Early clock API pic32_get_pbclk() is defined in early_clk.c and used by time.c and early_console.c. When CONFIG_EARLY_PRINTK isn't set, early_clk.c isn't compiled and so a linker error is reported while referring the API from time.c. Fix it by compiling early_clk.c always. Also sort files in alphabetical order. Cc: Harvey Hunt <harvey.h...@imgtec.com> Cc: Ralf Baechle <r...@linux-mips.org> Cc: linux-m...@linux-mips.org Cc: Joshua Henderson <digitalp...@digitalpeer.com> Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com> --- arch/mips/pic32/pic32mzda/Makefile | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/mips/pic32/pic32mzda/Makefile b/arch/mips/pic32/pic32mzda/Makefile index 4a4c272..c286496 100644 --- a/arch/mips/pic32/pic32mzda/Makefile +++ b/arch/mips/pic32/pic32mzda/Makefile @@ -2,8 +2,7 @@ # Joshua Henderson, <joshua.hender...@microchip.com> # Copyright (C) 2015 Microchip Technology, Inc. All rights reserved. # -obj-y := init.o time.o config.o +obj-y := config.o early_clk.o init.o time.o obj-$(CONFIG_EARLY_PRINTK) += early_console.o \ - early_pin.o \ - early_clk.o + early_pin.o -- 1.8.3.1
[PATCH] MIPS: pic32mzda: fix linker error for pic32_get_pbclk().
Early clock API pic32_get_pbclk() is defined in early_clk.c and used by time.c and early_console.c. When CONFIG_EARLY_PRINTK isn't set, early_clk.c isn't compiled and so a linker error is reported while referring the API from time.c. Fix it by compiling early_clk.c always. Also sort files in alphabetical order. Cc: Harvey Hunt Cc: Ralf Baechle Cc: linux-m...@linux-mips.org Cc: Joshua Henderson Signed-off-by: Purna Chandra Mandal --- arch/mips/pic32/pic32mzda/Makefile | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/mips/pic32/pic32mzda/Makefile b/arch/mips/pic32/pic32mzda/Makefile index 4a4c272..c286496 100644 --- a/arch/mips/pic32/pic32mzda/Makefile +++ b/arch/mips/pic32/pic32mzda/Makefile @@ -2,8 +2,7 @@ # Joshua Henderson, # Copyright (C) 2015 Microchip Technology, Inc. All rights reserved. # -obj-y := init.o time.o config.o +obj-y := config.o early_clk.o init.o time.o obj-$(CONFIG_EARLY_PRINTK) += early_console.o \ - early_pin.o \ - early_clk.o + early_pin.o -- 1.8.3.1
Re: [PATCH 03/11] MIPS: pic32mzda: fix getting timer clock rate.
On 05/25/2016 09:32 PM, Harvey Hunt wrote:
> Hi Purna,
>
> On 17/05/16 06:05, Purna Chandra Mandal wrote:
>> PIC32 clock driver is now implemented as platform driver instead of
>> as part of of_clk_init(). It meants all the clock modules are available
>> quite late in the boot sequence. So request for CPU clock by clk_get_sys()
>> and clk_get_rate() to find c0_timer rate fails.
>>
>> To fix this use PIC32 specific early clock functions implemented for early
>> console support.
>>
>> Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
>>
>> ---
>> Note: Please pull this complete series through the MIPS tree.
>>
>> ---
>>
>> arch/mips/pic32/pic32mzda/time.c | 13 -
>> 1 file changed, 4 insertions(+), 9 deletions(-)
>>
>> diff --git a/arch/mips/pic32/pic32mzda/time.c
>> b/arch/mips/pic32/pic32mzda/time.c
>> index ca6a62b..62a0a78 100644
>> --- a/arch/mips/pic32/pic32mzda/time.c
>> +++ b/arch/mips/pic32/pic32mzda/time.c
>> @@ -11,13 +11,12 @@
>> * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
>> * for more details.
>> */
>> -#include
>> #include
>> #include
>> #include
>> +#include
>> #include
>> #include
>> -#include
>>
>> #include
>>
>> @@ -58,16 +57,12 @@ unsigned int get_c0_compare_int(void)
>>
>> void __init plat_time_init(void)
>> {
>> -struct clk *clk;
>> +unsigned long rate = pic32_get_pbclk(7);
>
> pic32_get_pbclk() is defined in arch/mips/pic32/pic32mzda/early_clk.c. When
> CONFIG_EARLY_PRINTK isn't set, early_clk.c isn't compiled and so a linker
> error occurs.
>
> Maybe it's best to always build the early_clk.c file, or perhaps there is a
> better place to put pic32_get_pbclk()?
>
Thanks Harvey.
Will fix in separate patch.
> Thanks,
>
> Harvey
>
Re: [PATCH 03/11] MIPS: pic32mzda: fix getting timer clock rate.
On 05/25/2016 09:32 PM, Harvey Hunt wrote:
> Hi Purna,
>
> On 17/05/16 06:05, Purna Chandra Mandal wrote:
>> PIC32 clock driver is now implemented as platform driver instead of
>> as part of of_clk_init(). It meants all the clock modules are available
>> quite late in the boot sequence. So request for CPU clock by clk_get_sys()
>> and clk_get_rate() to find c0_timer rate fails.
>>
>> To fix this use PIC32 specific early clock functions implemented for early
>> console support.
>>
>> Signed-off-by: Purna Chandra Mandal
>>
>> ---
>> Note: Please pull this complete series through the MIPS tree.
>>
>> ---
>>
>> arch/mips/pic32/pic32mzda/time.c | 13 -
>> 1 file changed, 4 insertions(+), 9 deletions(-)
>>
>> diff --git a/arch/mips/pic32/pic32mzda/time.c
>> b/arch/mips/pic32/pic32mzda/time.c
>> index ca6a62b..62a0a78 100644
>> --- a/arch/mips/pic32/pic32mzda/time.c
>> +++ b/arch/mips/pic32/pic32mzda/time.c
>> @@ -11,13 +11,12 @@
>> * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
>> * for more details.
>> */
>> -#include
>> #include
>> #include
>> #include
>> +#include
>> #include
>> #include
>> -#include
>>
>> #include
>>
>> @@ -58,16 +57,12 @@ unsigned int get_c0_compare_int(void)
>>
>> void __init plat_time_init(void)
>> {
>> -struct clk *clk;
>> +unsigned long rate = pic32_get_pbclk(7);
>
> pic32_get_pbclk() is defined in arch/mips/pic32/pic32mzda/early_clk.c. When
> CONFIG_EARLY_PRINTK isn't set, early_clk.c isn't compiled and so a linker
> error occurs.
>
> Maybe it's best to always build the early_clk.c file, or perhaps there is a
> better place to put pic32_get_pbclk()?
>
Thanks Harvey.
Will fix in separate patch.
> Thanks,
>
> Harvey
>
Re: [PATCH] clk: microchip: Remove CLK_IS_ROOT
On 06/02/2016 03:25 AM, Stephen Boyd wrote:
> This flag is a no-op now (see commit 47b0eeb3dc8a "clk: Deprecate
> CLK_IS_ROOT", 2016-02-02) so remove it.
>
> Cc: Purna Chandra Mandal <purna.man...@microchip.com>
> Cc: Ralf Baechle <r...@linux-mips.org>
> Cc: <linux-m...@linux-mips.org>
> Signed-off-by: Stephen Boyd <sb...@codeaurora.org>
> ---
>
> I'm going to send this to Linus tomorrow or Friday so we can finally
> remove this flag entirely.
>
> drivers/clk/microchip/clk-pic32mzda.c | 10 +-
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/clk/microchip/clk-pic32mzda.c
> b/drivers/clk/microchip/clk-pic32mzda.c
> index 020a29acc5b0..51f54380474b 100644
> --- a/drivers/clk/microchip/clk-pic32mzda.c
> +++ b/drivers/clk/microchip/clk-pic32mzda.c
> @@ -180,15 +180,15 @@ static int pic32mzda_clk_probe(struct platform_device
> *pdev)
>
> /* register fixed rate clocks */
> clks[POSCCLK] = clk_register_fixed_rate(>dev, "posc_clk", NULL,
> - CLK_IS_ROOT, 2400);
> + 0, 2400);
> clks[FRCCLK] = clk_register_fixed_rate(>dev, "frc_clk", NULL,
> - CLK_IS_ROOT, 800);
> + 0, 800);
> clks[BFRCCLK] = clk_register_fixed_rate(>dev, "bfrc_clk", NULL,
> - CLK_IS_ROOT, 800);
> + 0, 800);
> clks[LPRCCLK] = clk_register_fixed_rate(>dev, "lprc_clk", NULL,
> - CLK_IS_ROOT, 32000);
> + 0, 32000);
> clks[UPLLCLK] = clk_register_fixed_rate(>dev, "usbphy_clk", NULL,
> - CLK_IS_ROOT, 2400);
> + 0, 2400);
> /* fixed rate (optional) clock */
> if (of_find_property(np, "microchip,pic32mzda-sosc", NULL)) {
> pr_info("pic32-clk: dt requests SOSC.\n");
Tested-by: Purna Chandra Mandal <purna.man...@microchip.com>
Re: [PATCH] clk: microchip: Remove CLK_IS_ROOT
On 06/02/2016 03:25 AM, Stephen Boyd wrote:
> This flag is a no-op now (see commit 47b0eeb3dc8a "clk: Deprecate
> CLK_IS_ROOT", 2016-02-02) so remove it.
>
> Cc: Purna Chandra Mandal
> Cc: Ralf Baechle
> Cc:
> Signed-off-by: Stephen Boyd
> ---
>
> I'm going to send this to Linus tomorrow or Friday so we can finally
> remove this flag entirely.
>
> drivers/clk/microchip/clk-pic32mzda.c | 10 +-
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/clk/microchip/clk-pic32mzda.c
> b/drivers/clk/microchip/clk-pic32mzda.c
> index 020a29acc5b0..51f54380474b 100644
> --- a/drivers/clk/microchip/clk-pic32mzda.c
> +++ b/drivers/clk/microchip/clk-pic32mzda.c
> @@ -180,15 +180,15 @@ static int pic32mzda_clk_probe(struct platform_device
> *pdev)
>
> /* register fixed rate clocks */
> clks[POSCCLK] = clk_register_fixed_rate(>dev, "posc_clk", NULL,
> - CLK_IS_ROOT, 2400);
> + 0, 2400);
> clks[FRCCLK] = clk_register_fixed_rate(>dev, "frc_clk", NULL,
> - CLK_IS_ROOT, 800);
> + 0, 800);
> clks[BFRCCLK] = clk_register_fixed_rate(>dev, "bfrc_clk", NULL,
> - CLK_IS_ROOT, 800);
> + 0, 800);
> clks[LPRCCLK] = clk_register_fixed_rate(>dev, "lprc_clk", NULL,
> - CLK_IS_ROOT, 32000);
> + 0, 32000);
> clks[UPLLCLK] = clk_register_fixed_rate(>dev, "usbphy_clk", NULL,
> - CLK_IS_ROOT, 2400);
> + 0, 2400);
> /* fixed rate (optional) clock */
> if (of_find_property(np, "microchip,pic32mzda-sosc", NULL)) {
> pr_info("pic32-clk: dt requests SOSC.\n");
Tested-by: Purna Chandra Mandal
[PATCH 08/11] dt/bindings: Correct clk binding example for PIC32 serial.
Update binding example based on new clock binding scheme. [1] Documentation/devicetree/bindings/clock/microchip,pic32.txt Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com> --- Documentation/devicetree/bindings/serial/microchip,pic32-uart.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/serial/microchip,pic32-uart.txt b/Documentation/devicetree/bindings/serial/microchip,pic32-uart.txt index 65b38bf..7a34345 100644 --- a/Documentation/devicetree/bindings/serial/microchip,pic32-uart.txt +++ b/Documentation/devicetree/bindings/serial/microchip,pic32-uart.txt @@ -20,7 +20,7 @@ Example: interrupts = <112 IRQ_TYPE_LEVEL_HIGH>, <113 IRQ_TYPE_LEVEL_HIGH>, <114 IRQ_TYPE_LEVEL_HIGH>; - clocks = <>; + clocks = < PB2CLK>; pinctrl-names = "default"; pinctrl-0 = <_uart1 _uart1_cts -- 1.8.3.1
[PATCH 09/11] dt/bindings: Correct clk binding example for PIC32 DMT.
Update binding example based on new clock binding scheme.
[1] Documentation/devicetree/bindings/clock/microchip,pic32.txt
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
---
Documentation/devicetree/bindings/watchdog/microchip,pic32-dmt.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/watchdog/microchip,pic32-dmt.txt
b/Documentation/devicetree/bindings/watchdog/microchip,pic32-dmt.txt
index 852f694..49485f8 100644
--- a/Documentation/devicetree/bindings/watchdog/microchip,pic32-dmt.txt
+++ b/Documentation/devicetree/bindings/watchdog/microchip,pic32-dmt.txt
@@ -8,12 +8,12 @@ Required properties:
- compatible: must be "microchip,pic32mzda-dmt".
- reg: physical base address of the controller and length of memory mapped
region.
-- clocks: phandle of parent clock (should be ).
+- clocks: phandle of source clk. Should be < PB7CLK>.
Example:
watchdog@1f800a00 {
compatible = "microchip,pic32mzda-dmt";
reg = <0x1f800a00 0x80>;
- clocks = <>;
+ clocks = < PB7CLK>;
};
--
1.8.3.1
[PATCH 08/11] dt/bindings: Correct clk binding example for PIC32 serial.
Update binding example based on new clock binding scheme. [1] Documentation/devicetree/bindings/clock/microchip,pic32.txt Signed-off-by: Purna Chandra Mandal --- Documentation/devicetree/bindings/serial/microchip,pic32-uart.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/serial/microchip,pic32-uart.txt b/Documentation/devicetree/bindings/serial/microchip,pic32-uart.txt index 65b38bf..7a34345 100644 --- a/Documentation/devicetree/bindings/serial/microchip,pic32-uart.txt +++ b/Documentation/devicetree/bindings/serial/microchip,pic32-uart.txt @@ -20,7 +20,7 @@ Example: interrupts = <112 IRQ_TYPE_LEVEL_HIGH>, <113 IRQ_TYPE_LEVEL_HIGH>, <114 IRQ_TYPE_LEVEL_HIGH>; - clocks = <>; + clocks = < PB2CLK>; pinctrl-names = "default"; pinctrl-0 = <_uart1 _uart1_cts -- 1.8.3.1
[PATCH 09/11] dt/bindings: Correct clk binding example for PIC32 DMT.
Update binding example based on new clock binding scheme.
[1] Documentation/devicetree/bindings/clock/microchip,pic32.txt
Signed-off-by: Purna Chandra Mandal
---
Documentation/devicetree/bindings/watchdog/microchip,pic32-dmt.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/watchdog/microchip,pic32-dmt.txt
b/Documentation/devicetree/bindings/watchdog/microchip,pic32-dmt.txt
index 852f694..49485f8 100644
--- a/Documentation/devicetree/bindings/watchdog/microchip,pic32-dmt.txt
+++ b/Documentation/devicetree/bindings/watchdog/microchip,pic32-dmt.txt
@@ -8,12 +8,12 @@ Required properties:
- compatible: must be "microchip,pic32mzda-dmt".
- reg: physical base address of the controller and length of memory mapped
region.
-- clocks: phandle of parent clock (should be ).
+- clocks: phandle of source clk. Should be < PB7CLK>.
Example:
watchdog@1f800a00 {
compatible = "microchip,pic32mzda-dmt";
reg = <0x1f800a00 0x80>;
- clocks = <>;
+ clocks = < PB7CLK>;
};
--
1.8.3.1
[PATCH 11/11] dt/bindings: Correct clk binding example for PIC32 gpio.
Update binding example based on new clock binding scheme.
[1] Documentation/devicetree/bindings/clock/microchip,pic32.txt
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
---
Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt
b/Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt
index ef37528..dd031fc 100644
--- a/Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt
+++ b/Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt
@@ -33,7 +33,7 @@ gpio0: gpio0@1f86 {
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <>;
+ clocks = < PB4CLK>;
microchip,gpio-bank = <0>;
gpio-ranges = <_pinctrl 0 0 16>;
};
--
1.8.3.1
[PATCH 10/11] dt/bindings: Correct clk binding example for PIC32 WDT.
Update binding example based on new clock binding scheme.
[1] Documentation/devicetree/bindings/clock/microchip,pic32.txt
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
---
Documentation/devicetree/bindings/watchdog/microchip,pic32-wdt.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/watchdog/microchip,pic32-wdt.txt
b/Documentation/devicetree/bindings/watchdog/microchip,pic32-wdt.txt
index d140103..f03a29a 100644
--- a/Documentation/devicetree/bindings/watchdog/microchip,pic32-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/microchip,pic32-wdt.txt
@@ -7,12 +7,12 @@ Required properties:
- compatible: must be "microchip,pic32mzda-wdt".
- reg: physical base address of the controller and length of memory mapped
region.
-- clocks: phandle of source clk. should be <> clk.
+- clocks: phandle of source clk. Should be < LPRCCLK>.
Example:
watchdog@1f800800 {
compatible = "microchip,pic32mzda-wdt";
reg = <0x1f800800 0x200>;
- clocks = <>;
+ clocks = < LPRCCLK>;
};
--
1.8.3.1
[PATCH 11/11] dt/bindings: Correct clk binding example for PIC32 gpio.
Update binding example based on new clock binding scheme.
[1] Documentation/devicetree/bindings/clock/microchip,pic32.txt
Signed-off-by: Purna Chandra Mandal
---
Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt
b/Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt
index ef37528..dd031fc 100644
--- a/Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt
+++ b/Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt
@@ -33,7 +33,7 @@ gpio0: gpio0@1f86 {
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <>;
+ clocks = < PB4CLK>;
microchip,gpio-bank = <0>;
gpio-ranges = <_pinctrl 0 0 16>;
};
--
1.8.3.1
[PATCH 10/11] dt/bindings: Correct clk binding example for PIC32 WDT.
Update binding example based on new clock binding scheme.
[1] Documentation/devicetree/bindings/clock/microchip,pic32.txt
Signed-off-by: Purna Chandra Mandal
---
Documentation/devicetree/bindings/watchdog/microchip,pic32-wdt.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/watchdog/microchip,pic32-wdt.txt
b/Documentation/devicetree/bindings/watchdog/microchip,pic32-wdt.txt
index d140103..f03a29a 100644
--- a/Documentation/devicetree/bindings/watchdog/microchip,pic32-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/microchip,pic32-wdt.txt
@@ -7,12 +7,12 @@ Required properties:
- compatible: must be "microchip,pic32mzda-wdt".
- reg: physical base address of the controller and length of memory mapped
region.
-- clocks: phandle of source clk. should be <> clk.
+- clocks: phandle of source clk. Should be < LPRCCLK>.
Example:
watchdog@1f800800 {
compatible = "microchip,pic32mzda-wdt";
reg = <0x1f800800 0x200>;
- clocks = <>;
+ clocks = < LPRCCLK>;
};
--
1.8.3.1
[PATCH 06/11] dt/bindings: Correct clk binding example for PIC32 SDHCI
Update binding example based on new clock binding documentation. [1] Documentation/devicetree/bindings/clock/microchip,pic32.txt Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com> --- Documentation/devicetree/bindings/mmc/microchip,sdhci-pic32.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mmc/microchip,sdhci-pic32.txt b/Documentation/devicetree/bindings/mmc/microchip,sdhci-pic32.txt index 71ad57e..3149297 100644 --- a/Documentation/devicetree/bindings/mmc/microchip,sdhci-pic32.txt +++ b/Documentation/devicetree/bindings/mmc/microchip,sdhci-pic32.txt @@ -20,7 +20,7 @@ Example: compatible = "microchip,pic32mzda-sdhci"; reg = <0x1f8ec000 0x100>; interrupts = <191 IRQ_TYPE_LEVEL_HIGH>; - clocks = <>, <>; + clocks = < REF4CLK>, < PB5CLK>; clock-names = "base_clk", "sys_clk"; bus-width = <4>; cap-sd-highspeed; -- 1.8.3.1
[PATCH 07/11] dt/bindings: Correct clk binding example for PIC32 pinctrl
Update binding example based on new clock binding scheme.
[1] Documentation/devicetree/bindings/clock/microchip,pic32.txt
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
---
Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
a/Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt
index 4b5efa5..29b72e3 100644
--- a/Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt
@@ -34,7 +34,7 @@ pic32_pinctrl: pinctrl@1f801400{
#size-cells = <1>;
compatible = "microchip,pic32mzda-pinctrl";
reg = <0x1f801400 0x400>;
- clocks = <>;
+ clocks = < PB1CLK>;
pinctrl_uart2: pinctrl_uart2 {
uart2-tx {
--
1.8.3.1
[PATCH 06/11] dt/bindings: Correct clk binding example for PIC32 SDHCI
Update binding example based on new clock binding documentation. [1] Documentation/devicetree/bindings/clock/microchip,pic32.txt Signed-off-by: Purna Chandra Mandal --- Documentation/devicetree/bindings/mmc/microchip,sdhci-pic32.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mmc/microchip,sdhci-pic32.txt b/Documentation/devicetree/bindings/mmc/microchip,sdhci-pic32.txt index 71ad57e..3149297 100644 --- a/Documentation/devicetree/bindings/mmc/microchip,sdhci-pic32.txt +++ b/Documentation/devicetree/bindings/mmc/microchip,sdhci-pic32.txt @@ -20,7 +20,7 @@ Example: compatible = "microchip,pic32mzda-sdhci"; reg = <0x1f8ec000 0x100>; interrupts = <191 IRQ_TYPE_LEVEL_HIGH>; - clocks = <>, <>; + clocks = < REF4CLK>, < PB5CLK>; clock-names = "base_clk", "sys_clk"; bus-width = <4>; cap-sd-highspeed; -- 1.8.3.1
[PATCH 07/11] dt/bindings: Correct clk binding example for PIC32 pinctrl
Update binding example based on new clock binding scheme.
[1] Documentation/devicetree/bindings/clock/microchip,pic32.txt
Signed-off-by: Purna Chandra Mandal
---
Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
a/Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt
index 4b5efa5..29b72e3 100644
--- a/Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt
@@ -34,7 +34,7 @@ pic32_pinctrl: pinctrl@1f801400{
#size-cells = <1>;
compatible = "microchip,pic32mzda-pinctrl";
reg = <0x1f801400 0x400>;
- clocks = <>;
+ clocks = < PB1CLK>;
pinctrl_uart2: pinctrl_uart2 {
uart2-tx {
--
1.8.3.1
[PATCH 03/11] MIPS: pic32mzda: fix getting timer clock rate.
PIC32 clock driver is now implemented as platform driver instead of
as part of of_clk_init(). It meants all the clock modules are available
quite late in the boot sequence. So request for CPU clock by clk_get_sys()
and clk_get_rate() to find c0_timer rate fails.
To fix this use PIC32 specific early clock functions implemented for early
console support.
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
---
Note: Please pull this complete series through the MIPS tree.
---
arch/mips/pic32/pic32mzda/time.c | 13 -
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/arch/mips/pic32/pic32mzda/time.c b/arch/mips/pic32/pic32mzda/time.c
index ca6a62b..62a0a78 100644
--- a/arch/mips/pic32/pic32mzda/time.c
+++ b/arch/mips/pic32/pic32mzda/time.c
@@ -11,13 +11,12 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*/
-#include
#include
#include
#include
+#include
#include
#include
-#include
#include
@@ -58,16 +57,12 @@ unsigned int get_c0_compare_int(void)
void __init plat_time_init(void)
{
- struct clk *clk;
+ unsigned long rate = pic32_get_pbclk(7);
of_clk_init(NULL);
- clk = clk_get_sys("cpu_clk", NULL);
- if (IS_ERR(clk))
- panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
- clk_prepare_enable(clk);
- pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 100);
- mips_hpt_frequency = clk_get_rate(clk) / 2;
+ pr_info("CPU Clock: %ldMHz\n", rate / 100);
+ mips_hpt_frequency = rate / 2;
clocksource_probe();
}
--
1.8.3.1
[PATCH 04/11] irqchip: irq-pic32-evic: Fix bug with external interrupts.
From: Joshua Henderson <digitalp...@digitalpeer.com>
The wrong external interrupt bits are being set, offset by 1.
Signed-off-by: Joshua Henderson <digitalp...@digitalpeer.com>
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
---
drivers/irqchip/irq-pic32-evic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-pic32-evic.c b/drivers/irqchip/irq-pic32-evic.c
index e7155db..73addb4 100644
--- a/drivers/irqchip/irq-pic32-evic.c
+++ b/drivers/irqchip/irq-pic32-evic.c
@@ -91,7 +91,7 @@ static int pic32_set_type_edge(struct irq_data *data,
/* set polarity for external interrupts only */
for (i = 0; i < ARRAY_SIZE(priv->ext_irqs); i++) {
if (priv->ext_irqs[i] == data->hwirq) {
- ret = pic32_set_ext_polarity(i + 1, flow_type);
+ ret = pic32_set_ext_polarity(i, flow_type);
if (ret)
return ret;
}
--
1.8.3.1
[PATCH 05/11] serial: pic32_uart: Fix double free of 'sport->irq_fault_name'.
Allocated memory for 'sport->irq_fault_name' is freed twice, first
in error check of 'if(!sport->irq_rx_name)' and other in fallback
handler.
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
---
drivers/tty/serial/pic32_uart.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/tty/serial/pic32_uart.c b/drivers/tty/serial/pic32_uart.c
index 62a43bf..7f8e99b 100644
--- a/drivers/tty/serial/pic32_uart.c
+++ b/drivers/tty/serial/pic32_uart.c
@@ -445,7 +445,6 @@ static int pic32_uart_startup(struct uart_port *port)
sport->idx);
if (!sport->irq_rx_name) {
dev_err(port->dev, "%s: kasprintf err!", __func__);
- kfree(sport->irq_fault_name);
ret = -ENOMEM;
goto out_f;
}
--
1.8.3.1
[PATCH 03/11] MIPS: pic32mzda: fix getting timer clock rate.
PIC32 clock driver is now implemented as platform driver instead of
as part of of_clk_init(). It meants all the clock modules are available
quite late in the boot sequence. So request for CPU clock by clk_get_sys()
and clk_get_rate() to find c0_timer rate fails.
To fix this use PIC32 specific early clock functions implemented for early
console support.
Signed-off-by: Purna Chandra Mandal
---
Note: Please pull this complete series through the MIPS tree.
---
arch/mips/pic32/pic32mzda/time.c | 13 -
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/arch/mips/pic32/pic32mzda/time.c b/arch/mips/pic32/pic32mzda/time.c
index ca6a62b..62a0a78 100644
--- a/arch/mips/pic32/pic32mzda/time.c
+++ b/arch/mips/pic32/pic32mzda/time.c
@@ -11,13 +11,12 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*/
-#include
#include
#include
#include
+#include
#include
#include
-#include
#include
@@ -58,16 +57,12 @@ unsigned int get_c0_compare_int(void)
void __init plat_time_init(void)
{
- struct clk *clk;
+ unsigned long rate = pic32_get_pbclk(7);
of_clk_init(NULL);
- clk = clk_get_sys("cpu_clk", NULL);
- if (IS_ERR(clk))
- panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
- clk_prepare_enable(clk);
- pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 100);
- mips_hpt_frequency = clk_get_rate(clk) / 2;
+ pr_info("CPU Clock: %ldMHz\n", rate / 100);
+ mips_hpt_frequency = rate / 2;
clocksource_probe();
}
--
1.8.3.1
[PATCH 04/11] irqchip: irq-pic32-evic: Fix bug with external interrupts.
From: Joshua Henderson
The wrong external interrupt bits are being set, offset by 1.
Signed-off-by: Joshua Henderson
Signed-off-by: Purna Chandra Mandal
---
drivers/irqchip/irq-pic32-evic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-pic32-evic.c b/drivers/irqchip/irq-pic32-evic.c
index e7155db..73addb4 100644
--- a/drivers/irqchip/irq-pic32-evic.c
+++ b/drivers/irqchip/irq-pic32-evic.c
@@ -91,7 +91,7 @@ static int pic32_set_type_edge(struct irq_data *data,
/* set polarity for external interrupts only */
for (i = 0; i < ARRAY_SIZE(priv->ext_irqs); i++) {
if (priv->ext_irqs[i] == data->hwirq) {
- ret = pic32_set_ext_polarity(i + 1, flow_type);
+ ret = pic32_set_ext_polarity(i, flow_type);
if (ret)
return ret;
}
--
1.8.3.1
[PATCH 05/11] serial: pic32_uart: Fix double free of 'sport->irq_fault_name'.
Allocated memory for 'sport->irq_fault_name' is freed twice, first
in error check of 'if(!sport->irq_rx_name)' and other in fallback
handler.
Signed-off-by: Purna Chandra Mandal
---
drivers/tty/serial/pic32_uart.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/tty/serial/pic32_uart.c b/drivers/tty/serial/pic32_uart.c
index 62a43bf..7f8e99b 100644
--- a/drivers/tty/serial/pic32_uart.c
+++ b/drivers/tty/serial/pic32_uart.c
@@ -445,7 +445,6 @@ static int pic32_uart_startup(struct uart_port *port)
sport->idx);
if (!sport->irq_rx_name) {
dev_err(port->dev, "%s: kasprintf err!", __func__);
- kfree(sport->irq_fault_name);
ret = -ENOMEM;
goto out_f;
}
--
1.8.3.1
[PATCH 02/11] clk: microchip: Initialize SOSC clock rate for PIC32MZDA.
Optional SOSC is an external fixed clock running at 32768HZ.
So Initialize SOSC rate as per PIC32MZDA datasheet.
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
---
Note: Please pull this complete series through the MIPS tree.
---
drivers/clk/microchip/clk-pic32mzda.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/microchip/clk-pic32mzda.c
b/drivers/clk/microchip/clk-pic32mzda.c
index 020a29a..210694b 100644
--- a/drivers/clk/microchip/clk-pic32mzda.c
+++ b/drivers/clk/microchip/clk-pic32mzda.c
@@ -118,6 +118,7 @@ static const struct pic32_sec_osc_data sosc_clk = {
.status_reg = 0x1d0,
.enable_mask = BIT(1),
.status_mask = BIT(4),
+ .fixed_rate = 32768,
.init_data = {
.name = "sosc_clk",
.parent_names = NULL,
--
1.8.3.1
[PATCH 01/11] clk: microchip: use readl_poll_timeout() in pbclk_set_rate().
pbclk_set_rate() is using readl_poll_timeout_atomic() even though spinlock is released. Fix it by replacing with readl_poll_timeout(). Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com> --- Note: Please pull this complete series through the MIPS tree. --- drivers/clk/microchip/clk-core.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/microchip/clk-core.c b/drivers/clk/microchip/clk-core.c index ca85cea..c3b3014 100644 --- a/drivers/clk/microchip/clk-core.c +++ b/drivers/clk/microchip/clk-core.c @@ -199,9 +199,9 @@ static int pbclk_set_rate(struct clk_hw *hw, unsigned long rate, spin_unlock_irqrestore(>core->reg_lock, flags); - /* wait again, for pbdivready */ - err = readl_poll_timeout_atomic(pb->ctrl_reg, v, v & PB_DIV_READY, - 1, LOCK_TIMEOUT_US); + /* wait again for DIV_READY */ + err = readl_poll_timeout(pb->ctrl_reg, v, v & PB_DIV_READY, +1, LOCK_TIMEOUT_US); if (err) return err; -- 1.8.3.1
[PATCH 02/11] clk: microchip: Initialize SOSC clock rate for PIC32MZDA.
Optional SOSC is an external fixed clock running at 32768HZ.
So Initialize SOSC rate as per PIC32MZDA datasheet.
Signed-off-by: Purna Chandra Mandal
---
Note: Please pull this complete series through the MIPS tree.
---
drivers/clk/microchip/clk-pic32mzda.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/microchip/clk-pic32mzda.c
b/drivers/clk/microchip/clk-pic32mzda.c
index 020a29a..210694b 100644
--- a/drivers/clk/microchip/clk-pic32mzda.c
+++ b/drivers/clk/microchip/clk-pic32mzda.c
@@ -118,6 +118,7 @@ static const struct pic32_sec_osc_data sosc_clk = {
.status_reg = 0x1d0,
.enable_mask = BIT(1),
.status_mask = BIT(4),
+ .fixed_rate = 32768,
.init_data = {
.name = "sosc_clk",
.parent_names = NULL,
--
1.8.3.1
[PATCH 01/11] clk: microchip: use readl_poll_timeout() in pbclk_set_rate().
pbclk_set_rate() is using readl_poll_timeout_atomic() even though spinlock is released. Fix it by replacing with readl_poll_timeout(). Signed-off-by: Purna Chandra Mandal --- Note: Please pull this complete series through the MIPS tree. --- drivers/clk/microchip/clk-core.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/microchip/clk-core.c b/drivers/clk/microchip/clk-core.c index ca85cea..c3b3014 100644 --- a/drivers/clk/microchip/clk-core.c +++ b/drivers/clk/microchip/clk-core.c @@ -199,9 +199,9 @@ static int pbclk_set_rate(struct clk_hw *hw, unsigned long rate, spin_unlock_irqrestore(>core->reg_lock, flags); - /* wait again, for pbdivready */ - err = readl_poll_timeout_atomic(pb->ctrl_reg, v, v & PB_DIV_READY, - 1, LOCK_TIMEOUT_US); + /* wait again for DIV_READY */ + err = readl_poll_timeout(pb->ctrl_reg, v, v & PB_DIV_READY, +1, LOCK_TIMEOUT_US); if (err) return err; -- 1.8.3.1
[PATCH] spi: pic32-sqi: Fix linker error, undefined reference to `bad_dma_ops'.
Even if DMA support is disabled code using DMA mapping APIs compiles fine, but fails in linking. --- drivers/built-in.o: In function `ring_desc_ring_free': spi-pic32-sqi.c:(.text+0x2cfbe0): undefined reference to `bad_dma_ops' spi-pic32-sqi.c:(.text+0x2cfbe4): undefined reference to `bad_dma_ops' drivers/built-in.o: In function `pic32_sqi_probe': spi-pic32-sqi.c:(.text+0x2cfe48): undefined reference to `bad_dma_ops' spi-pic32-sqi.c:(.text+0x2cfeb0): undefined reference to `bad_dma_ops' spi-pic32-sqi.c:(.text+0x2cff38): undefined reference to `bad_dma_ops' Correct dependency by adding 'depends on HAS_DMA' in Kconfig. Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com> --- drivers/spi/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 281ed5d..0f50755 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -445,6 +445,7 @@ config SPI_PIC32 config SPI_PIC32_SQI tristate "Microchip PIC32 Quad SPI driver" depends on MACH_PIC32 || COMPILE_TEST + depends on HAS_DMA help SPI driver for PIC32 Quad SPI controller. -- 1.8.3.1
[PATCH] spi: pic32-sqi: Fix linker error, undefined reference to `bad_dma_ops'.
Even if DMA support is disabled code using DMA mapping APIs compiles fine, but fails in linking. --- drivers/built-in.o: In function `ring_desc_ring_free': spi-pic32-sqi.c:(.text+0x2cfbe0): undefined reference to `bad_dma_ops' spi-pic32-sqi.c:(.text+0x2cfbe4): undefined reference to `bad_dma_ops' drivers/built-in.o: In function `pic32_sqi_probe': spi-pic32-sqi.c:(.text+0x2cfe48): undefined reference to `bad_dma_ops' spi-pic32-sqi.c:(.text+0x2cfeb0): undefined reference to `bad_dma_ops' spi-pic32-sqi.c:(.text+0x2cff38): undefined reference to `bad_dma_ops' Correct dependency by adding 'depends on HAS_DMA' in Kconfig. Signed-off-by: Purna Chandra Mandal --- drivers/spi/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 281ed5d..0f50755 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -445,6 +445,7 @@ config SPI_PIC32 config SPI_PIC32_SQI tristate "Microchip PIC32 Quad SPI driver" depends on MACH_PIC32 || COMPILE_TEST + depends on HAS_DMA help SPI driver for PIC32 Quad SPI controller. -- 1.8.3.1
[PATCH v11 3/3] MIPS: dts: pic32: Update dts to reflect new PIC32MZDA clk binding
- now clock nodes definition is merged with core .dtsi file
- only one rootclk is now part of DT
- clock clients also updated based on new binding doc
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
Signed-off-by: Joshua Henderson <joshua.hender...@microchip.com>
Cc: Ralf Baechle <r...@linux-mips.org>
Cc: Michael Turquette <mturque...@baylibre.com>
Cc: Stephen Boyd <sb...@codeaurora.org>
---
Note: Please pull this complete series through the MIPS tree.
Changes in v11: None
Changes in v10: None
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v3: None
Changes in v2: None
arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi | 236
arch/mips/boot/dts/pic32/pic32mzda.dtsi | 63 +---
arch/mips/boot/dts/pic32/pic32mzda_sk.dts | 5 +-
3 files changed, 45 insertions(+), 259 deletions(-)
delete mode 100644 arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi
diff --git a/arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi
b/arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi
deleted file mode 100644
index ef13350..000
--- a/arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi
+++ /dev/null
@@ -1,236 +0,0 @@
-/*
- * Device Tree Source for PIC32MZDA clock data
- *
- * Purna Chandra Mandal <purna.man...@microchip.com>
- * Copyright (C) 2015 Microchip Technology Inc. All rights reserved.
- *
- * Licensed under GPLv2 or later.
- */
-
-/* all fixed rate clocks */
-
-/ {
- POSC:posc_clk { /* On-chip primary oscillator */
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <2400>;
- };
-
- FRC:frc_clk { /* internal FRC oscillator */
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <800>;
- };
-
- BFRC:bfrc_clk { /* internal backup FRC oscillator */
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <800>;
- };
-
- LPRC:lprc_clk { /* internal low-power FRC oscillator */
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32000>;
- };
-
- /* UPLL provides clock to USBCORE */
- UPLL:usb_phy_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <2400>;
- clock-output-names = "usbphy_clk";
- };
-
- TxCKI:txcki_clk { /* external clock input on TxCLKI pin */
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <400>;
- status = "disabled";
- };
-
- /* external clock input on REFCLKIx pin */
- REFIx:refix_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <2400>;
- status = "disabled";
- };
-
- /* PIC32 specific clks */
- pic32_clktree {
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x1f801200 0x200>;
- compatible = "microchip,pic32mzda-clk";
- ranges = <0 0x1f801200 0x200>;
-
- /* secondary oscillator; external input on SOSCI pin */
- SOSC:sosc_clk@0 {
- #clock-cells = <0>;
- compatible = "microchip,pic32mzda-sosc";
- clock-frequency = <32768>;
- reg = <0x000 0x10>, /* enable reg */
- <0x1d0 0x10>; /* status reg */
- microchip,bit-mask = <0x02>; /* enable mask */
- microchip,status-bit-mask = <0x10>; /* status-mask*/
- };
-
- FRCDIV:frcdiv_clk {
- #clock-cells = <0>;
- compatible = "microchip,pic32mzda-frcdivclk";
- clocks = <>;
- clock-output-names = "frcdiv_clk";
- };
-
- /* System PLL clock */
- SYSPLL:spll_clk@020 {
- #clock-cells = <0>;
- compatible = "microchip,pic32mzda-syspll";
- reg = <0x020 0x10>, /* SPLL register */
- <0x1d0 0x10>; /* CLKSTAT register */
- clocks = <>, <>;
- clock-output-names = "sys_pll";
- microchip,status-bit-mask = <0x80>; /* SPLLRDY */
- };
-
-
[PATCH v11 3/3] MIPS: dts: pic32: Update dts to reflect new PIC32MZDA clk binding
- now clock nodes definition is merged with core .dtsi file
- only one rootclk is now part of DT
- clock clients also updated based on new binding doc
Signed-off-by: Purna Chandra Mandal
Signed-off-by: Joshua Henderson
Cc: Ralf Baechle
Cc: Michael Turquette
Cc: Stephen Boyd
---
Note: Please pull this complete series through the MIPS tree.
Changes in v11: None
Changes in v10: None
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v3: None
Changes in v2: None
arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi | 236
arch/mips/boot/dts/pic32/pic32mzda.dtsi | 63 +---
arch/mips/boot/dts/pic32/pic32mzda_sk.dts | 5 +-
3 files changed, 45 insertions(+), 259 deletions(-)
delete mode 100644 arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi
diff --git a/arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi
b/arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi
deleted file mode 100644
index ef13350..000
--- a/arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi
+++ /dev/null
@@ -1,236 +0,0 @@
-/*
- * Device Tree Source for PIC32MZDA clock data
- *
- * Purna Chandra Mandal
- * Copyright (C) 2015 Microchip Technology Inc. All rights reserved.
- *
- * Licensed under GPLv2 or later.
- */
-
-/* all fixed rate clocks */
-
-/ {
- POSC:posc_clk { /* On-chip primary oscillator */
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <2400>;
- };
-
- FRC:frc_clk { /* internal FRC oscillator */
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <800>;
- };
-
- BFRC:bfrc_clk { /* internal backup FRC oscillator */
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <800>;
- };
-
- LPRC:lprc_clk { /* internal low-power FRC oscillator */
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32000>;
- };
-
- /* UPLL provides clock to USBCORE */
- UPLL:usb_phy_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <2400>;
- clock-output-names = "usbphy_clk";
- };
-
- TxCKI:txcki_clk { /* external clock input on TxCLKI pin */
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <400>;
- status = "disabled";
- };
-
- /* external clock input on REFCLKIx pin */
- REFIx:refix_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <2400>;
- status = "disabled";
- };
-
- /* PIC32 specific clks */
- pic32_clktree {
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x1f801200 0x200>;
- compatible = "microchip,pic32mzda-clk";
- ranges = <0 0x1f801200 0x200>;
-
- /* secondary oscillator; external input on SOSCI pin */
- SOSC:sosc_clk@0 {
- #clock-cells = <0>;
- compatible = "microchip,pic32mzda-sosc";
- clock-frequency = <32768>;
- reg = <0x000 0x10>, /* enable reg */
- <0x1d0 0x10>; /* status reg */
- microchip,bit-mask = <0x02>; /* enable mask */
- microchip,status-bit-mask = <0x10>; /* status-mask*/
- };
-
- FRCDIV:frcdiv_clk {
- #clock-cells = <0>;
- compatible = "microchip,pic32mzda-frcdivclk";
- clocks = <>;
- clock-output-names = "frcdiv_clk";
- };
-
- /* System PLL clock */
- SYSPLL:spll_clk@020 {
- #clock-cells = <0>;
- compatible = "microchip,pic32mzda-syspll";
- reg = <0x020 0x10>, /* SPLL register */
- <0x1d0 0x10>; /* CLKSTAT register */
- clocks = <>, <>;
- clock-output-names = "sys_pll";
- microchip,status-bit-mask = <0x80>; /* SPLLRDY */
- };
-
- /* system clock; mux with postdiv & slew */
- SYSCLK:sys_clk@1c0 {
- #clock-cells = <0>;
- compatible = &q
[PATCH v11 2/3] clk: microchip: Add Microchip PIC32 clock driver.
This clock driver implements PIC32 specific clock-tree. clock-tree entities can only be configured through device-tree file (OF). Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com> --- Note: Please pull this complete series through the MIPS tree. Changes in v11: - split clock-init-data from clock-driver-data. - calculate iobase from reg offset and regbase. - use readl_poll_timeout() wherever required. - drop explicit typecast where implicit is sufficient. - drop forward declaration of 'clk_hw' in clk-core.h. - force enable critical clocks to avoid gate. Changes in v10: - drop early clock init of CLK_OF_DECLARE way. - complete clock registration as platform_driver. Changes in v9: - split clock registration in two parts, cpu clock (& required parents) as part of CLK_OF_DECLARE and remaining as part of platform_driver. Changes in v8: - Remove .round_rate from clk_ops - Fix rework bug "of_clk_src_onecell_get: invalid clock index 20" Changes in v7: - Reworked PIC32 clock driver based on review. - PIC32 clock driver now separate core functionality from platform specific clock-submodule binding/hierarchy. - moved PIC32 driver under clk/microchip/ - core clk functionality now in clk/microchip/clk-core.c - driver now doesn't use device-tree for clock submodules. - platform now statically defines clock submodule data-structures and bind them accordingly. Changes in v6: - sort linux includes and asm includes. - use BIT() wherever applicable - drop 'microchip,ignore-unused' usage, handling in favor of critical clock - drop 'fixed divider' handling for periph clock - drop use of 'debug_init()' clk operation callback for register dump - drop clk_lock(), clk_unlock() spinlock wrapper - drop unimplemented pic32_devcon_syslock() macro - use readl()/writel() instead of clk_readl()/clk_writel() - drop redundant spinlock, unlock calls in sosc_clk_enable()/disable() - use CLK_SET_RATE_GATE, _SET_PARENT_GATE for refo-clocks - use kcalloc() instead of kmalloc() wherever applicable - use of_io_request_and_map() in soc_clock_init() - drop use of pbclk(/roclk)_endisable() inline function - use readl_poll_timeout_atomic() for wait_for_bit() type loop - drop cpu_relax() after clk gating - promote u8, u16 to u32 wherever applicable - fix sosc clock status polling - drop memory alloc from pic32_of_clk_get_parent_indices() instead callers will supply buffer to hold output parent indices - reword comments about spll_clk_set_rate() pre-conditions - drop use of CLK_BASIC wherever applicable - reword comments in sclk_set_parent() Changes in v3: - Replace __clk_debug with pr_debug - Add of_clk_parent_fill usage in PIC32 clock driver Changes in v2: - Remove unused PIC32 MPLL support. - Remove support for initializing default parent/rate for REFOSC clocks. drivers/clk/Kconfig |3 + drivers/clk/Makefile |1 + drivers/clk/microchip/Makefile|2 + drivers/clk/microchip/clk-core.c | 1031 + drivers/clk/microchip/clk-core.h | 84 +++ drivers/clk/microchip/clk-pic32mzda.c | 275 + 6 files changed, 1396 insertions(+) create mode 100644 drivers/clk/microchip/Makefile create mode 100644 drivers/clk/microchip/clk-core.c create mode 100644 drivers/clk/microchip/clk-core.h create mode 100644 drivers/clk/microchip/clk-pic32mzda.c diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 16f7d33..f189d17 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -197,6 +197,9 @@ config COMMON_CLK_PXA ---help--- Support for the Marvell PXA SoC. +config COMMON_CLK_PIC32 + def_bool COMMON_CLK && MACH_PIC32 + source "drivers/clk/bcm/Kconfig" source "drivers/clk/hisilicon/Kconfig" source "drivers/clk/mvebu/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 46869d6..18e64bb 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -58,6 +58,7 @@ obj-$(CONFIG_ARCH_MXC)+= imx/ obj-$(CONFIG_MACH_INGENIC) += ingenic/ obj-$(CONFIG_COMMON_CLK_KEYSTONE) += keystone/ obj-$(CONFIG_ARCH_MEDIATEK)+= mediatek/ +obj-$(CONFIG_MACH_PIC32) += microchip/ ifeq ($(CONFIG_COMMON_CLK), y) obj-$(CONFIG_ARCH_MMP) += mmp/ endif diff --git a/drivers/clk/microchip/Makefile b/drivers/clk/microchip/Makefile new file mode 100644 index 000..2152f41 --- /dev/null +++ b/drivers/clk/microchip/Makefile @@ -0,0 +1,2 @@ +obj-$(CONFIG_COMMON_CLK_PIC32) += clk-core.o +obj-$(CONFIG_PIC32MZDA) += clk-pic32mzda.o diff --git a/drivers/clk/microchip/clk-core.c b/drivers/clk/microchip/clk-core.c new file mode 100644 index 000..ca85cea --- /dev/null +++ b/drivers/clk/microchip/clk-core.c @@ -0,0 +1,1031 @@ +/* + * Purna Chandra Mandal,<purna.man...@microchip.com> + * Copyright (C) 2015 Microchip Technology Inc. All rights res
[PATCH v11 2/3] clk: microchip: Add Microchip PIC32 clock driver.
This clock driver implements PIC32 specific clock-tree. clock-tree entities can only be configured through device-tree file (OF). Signed-off-by: Purna Chandra Mandal --- Note: Please pull this complete series through the MIPS tree. Changes in v11: - split clock-init-data from clock-driver-data. - calculate iobase from reg offset and regbase. - use readl_poll_timeout() wherever required. - drop explicit typecast where implicit is sufficient. - drop forward declaration of 'clk_hw' in clk-core.h. - force enable critical clocks to avoid gate. Changes in v10: - drop early clock init of CLK_OF_DECLARE way. - complete clock registration as platform_driver. Changes in v9: - split clock registration in two parts, cpu clock (& required parents) as part of CLK_OF_DECLARE and remaining as part of platform_driver. Changes in v8: - Remove .round_rate from clk_ops - Fix rework bug "of_clk_src_onecell_get: invalid clock index 20" Changes in v7: - Reworked PIC32 clock driver based on review. - PIC32 clock driver now separate core functionality from platform specific clock-submodule binding/hierarchy. - moved PIC32 driver under clk/microchip/ - core clk functionality now in clk/microchip/clk-core.c - driver now doesn't use device-tree for clock submodules. - platform now statically defines clock submodule data-structures and bind them accordingly. Changes in v6: - sort linux includes and asm includes. - use BIT() wherever applicable - drop 'microchip,ignore-unused' usage, handling in favor of critical clock - drop 'fixed divider' handling for periph clock - drop use of 'debug_init()' clk operation callback for register dump - drop clk_lock(), clk_unlock() spinlock wrapper - drop unimplemented pic32_devcon_syslock() macro - use readl()/writel() instead of clk_readl()/clk_writel() - drop redundant spinlock, unlock calls in sosc_clk_enable()/disable() - use CLK_SET_RATE_GATE, _SET_PARENT_GATE for refo-clocks - use kcalloc() instead of kmalloc() wherever applicable - use of_io_request_and_map() in soc_clock_init() - drop use of pbclk(/roclk)_endisable() inline function - use readl_poll_timeout_atomic() for wait_for_bit() type loop - drop cpu_relax() after clk gating - promote u8, u16 to u32 wherever applicable - fix sosc clock status polling - drop memory alloc from pic32_of_clk_get_parent_indices() instead callers will supply buffer to hold output parent indices - reword comments about spll_clk_set_rate() pre-conditions - drop use of CLK_BASIC wherever applicable - reword comments in sclk_set_parent() Changes in v3: - Replace __clk_debug with pr_debug - Add of_clk_parent_fill usage in PIC32 clock driver Changes in v2: - Remove unused PIC32 MPLL support. - Remove support for initializing default parent/rate for REFOSC clocks. drivers/clk/Kconfig |3 + drivers/clk/Makefile |1 + drivers/clk/microchip/Makefile|2 + drivers/clk/microchip/clk-core.c | 1031 + drivers/clk/microchip/clk-core.h | 84 +++ drivers/clk/microchip/clk-pic32mzda.c | 275 + 6 files changed, 1396 insertions(+) create mode 100644 drivers/clk/microchip/Makefile create mode 100644 drivers/clk/microchip/clk-core.c create mode 100644 drivers/clk/microchip/clk-core.h create mode 100644 drivers/clk/microchip/clk-pic32mzda.c diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 16f7d33..f189d17 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -197,6 +197,9 @@ config COMMON_CLK_PXA ---help--- Support for the Marvell PXA SoC. +config COMMON_CLK_PIC32 + def_bool COMMON_CLK && MACH_PIC32 + source "drivers/clk/bcm/Kconfig" source "drivers/clk/hisilicon/Kconfig" source "drivers/clk/mvebu/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 46869d6..18e64bb 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -58,6 +58,7 @@ obj-$(CONFIG_ARCH_MXC)+= imx/ obj-$(CONFIG_MACH_INGENIC) += ingenic/ obj-$(CONFIG_COMMON_CLK_KEYSTONE) += keystone/ obj-$(CONFIG_ARCH_MEDIATEK)+= mediatek/ +obj-$(CONFIG_MACH_PIC32) += microchip/ ifeq ($(CONFIG_COMMON_CLK), y) obj-$(CONFIG_ARCH_MMP) += mmp/ endif diff --git a/drivers/clk/microchip/Makefile b/drivers/clk/microchip/Makefile new file mode 100644 index 000..2152f41 --- /dev/null +++ b/drivers/clk/microchip/Makefile @@ -0,0 +1,2 @@ +obj-$(CONFIG_COMMON_CLK_PIC32) += clk-core.o +obj-$(CONFIG_PIC32MZDA) += clk-pic32mzda.o diff --git a/drivers/clk/microchip/clk-core.c b/drivers/clk/microchip/clk-core.c new file mode 100644 index 000..ca85cea --- /dev/null +++ b/drivers/clk/microchip/clk-core.c @@ -0,0 +1,1031 @@ +/* + * Purna Chandra Mandal, + * Copyright (C) 2015 Microchip Technology Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or mod
[PATCH v11 1/3] dt/bindings/clk: Add PIC32 clock binding documentation.
Document the devicetree bindings for the clock driver found on Microchip
PIC32 class devices.
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
Cc: Ralf Baechle <r...@linux-mips.org>
Cc: Michael Turquette <mturque...@baylibre.com>
Cc: Stephen Boyd <sb...@codeaurora.org>
Acked-by: Rob Herring <r...@kernel.org>
Acked-by: Michael Turquette <mturque...@baylibre.com>
---
Note: Please pull this complete series through the MIPS tree.
Changes in v11: None
Changes in v10: None
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6:
- Update Microchip PIC32 clock binding document based on review
- Add header defining clocks
Changes in v3: None
Changes in v2:
- Force lowercase in PIC32 clock binding documentation
.../devicetree/bindings/clock/microchip,pic32.txt | 39
include/dt-bindings/clock/microchip,pic32-clock.h | 42 ++
2 files changed, 81 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/microchip,pic32.txt
create mode 100644 include/dt-bindings/clock/microchip,pic32-clock.h
diff --git a/Documentation/devicetree/bindings/clock/microchip,pic32.txt
b/Documentation/devicetree/bindings/clock/microchip,pic32.txt
new file mode 100644
index 000..c93d88f
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/microchip,pic32.txt
@@ -0,0 +1,39 @@
+Microchip PIC32 Clock Controller Binding
+
+Microchip clock controller is consists of few oscillators, PLL, multiplexer
+and few divider modules.
+
+This binding uses common clock bindings.
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible: shall be "microchip,pic32mzda-clk".
+- reg: shall contain base address and length of clock registers.
+- #clock-cells: shall be 1.
+
+Optional properties:
+- microchip,pic32mzda-sosc: shall be added only if platform has
+ secondary oscillator connected.
+
+Example:
+ rootclk: clock-controller@1f801200 {
+ compatible = "microchip,pic32mzda-clk";
+ reg = <0x1f801200 0x200>;
+ #clock-cells = <1>;
+ /* optional */
+ microchip,pic32mzda-sosc;
+ };
+
+
+The clock consumer shall specify the desired clock-output of the clock
+controller (as defined in [2]) by specifying output-id in its "clock"
+phandle cell.
+[2] include/dt-bindings/clock/microchip,pic32-clock.h
+
+For example for UART2:
+uart2: serial@2 {
+ compatible = "microchip,pic32mzda-uart";
+ reg = <>;
+ interrupts = <>;
+ clocks = < PB2CLK>;
+};
diff --git a/include/dt-bindings/clock/microchip,pic32-clock.h
b/include/dt-bindings/clock/microchip,pic32-clock.h
new file mode 100644
index 000..184647a6
--- /dev/null
+++ b/include/dt-bindings/clock/microchip,pic32-clock.h
@@ -0,0 +1,42 @@
+/*
+ * Purna Chandra Mandal,<purna.man...@microchip.com>
+ * Copyright (C) 2015 Microchip Technology Inc. All rights reserved.
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MICROCHIP_PIC32_H_
+#define _DT_BINDINGS_CLK_MICROCHIP_PIC32_H_
+
+/* clock output indices */
+#define POSCCLK0
+#define FRCCLK 1
+#define BFRCCLK2
+#define LPRCCLK3
+#define SOSCCLK4
+#define FRCDIVCLK 5
+#define PLLCLK 6
+#define SCLK 7
+#define PB1CLK 8
+#define PB2CLK 9
+#define PB3CLK 10
+#define PB4CLK 11
+#define PB5CLK 12
+#define PB6CLK 13
+#define PB7CLK 14
+#define REF1CLK15
+#define REF2CLK16
+#define REF3CLK17
+#define REF4CLK18
+#define REF5CLK19
+#define UPLLCLK20
+#define MAXCLKS21
+
+#endif /* _DT_BINDINGS_CLK_MICROCHIP_PIC32_H_ */
--
1.8.3.1
[PATCH v11 0/3] PIC32MZDA Clock Driver
Clock bindings got acked and then essentially unacked, while the clock driver never made it upstream. In the meantime, the initial DTS file made it upstream. This latest patch series includes a patch to go back and correct the DTS files to reflect the new clock bindings in this patch series. Note: Please pull this complete series through the MIPS tree. Purna Chandra Mandal (3): dt/bindings/clk: Add PIC32 clock binding documentation. clk: microchip: Add Microchip PIC32 clock driver. MIPS: dts: pic32: Update dts to reflect new PIC32MZDA clk binding .../devicetree/bindings/clock/microchip,pic32.txt | 39 + arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi| 236 - arch/mips/boot/dts/pic32/pic32mzda.dtsi| 63 +- arch/mips/boot/dts/pic32/pic32mzda_sk.dts |5 +- drivers/clk/Kconfig|3 + drivers/clk/Makefile |1 + drivers/clk/microchip/Makefile |2 + drivers/clk/microchip/clk-core.c | 1031 drivers/clk/microchip/clk-core.h | 84 ++ drivers/clk/microchip/clk-pic32mzda.c | 275 ++ include/dt-bindings/clock/microchip,pic32-clock.h | 42 + 11 files changed, 1522 insertions(+), 259 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/microchip,pic32.txt delete mode 100644 arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi create mode 100644 drivers/clk/microchip/Makefile create mode 100644 drivers/clk/microchip/clk-core.c create mode 100644 drivers/clk/microchip/clk-core.h create mode 100644 drivers/clk/microchip/clk-pic32mzda.c create mode 100644 include/dt-bindings/clock/microchip,pic32-clock.h -- 1.8.3.1
[PATCH v11 1/3] dt/bindings/clk: Add PIC32 clock binding documentation.
Document the devicetree bindings for the clock driver found on Microchip
PIC32 class devices.
Signed-off-by: Purna Chandra Mandal
Cc: Ralf Baechle
Cc: Michael Turquette
Cc: Stephen Boyd
Acked-by: Rob Herring
Acked-by: Michael Turquette
---
Note: Please pull this complete series through the MIPS tree.
Changes in v11: None
Changes in v10: None
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6:
- Update Microchip PIC32 clock binding document based on review
- Add header defining clocks
Changes in v3: None
Changes in v2:
- Force lowercase in PIC32 clock binding documentation
.../devicetree/bindings/clock/microchip,pic32.txt | 39
include/dt-bindings/clock/microchip,pic32-clock.h | 42 ++
2 files changed, 81 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/microchip,pic32.txt
create mode 100644 include/dt-bindings/clock/microchip,pic32-clock.h
diff --git a/Documentation/devicetree/bindings/clock/microchip,pic32.txt
b/Documentation/devicetree/bindings/clock/microchip,pic32.txt
new file mode 100644
index 000..c93d88f
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/microchip,pic32.txt
@@ -0,0 +1,39 @@
+Microchip PIC32 Clock Controller Binding
+
+Microchip clock controller is consists of few oscillators, PLL, multiplexer
+and few divider modules.
+
+This binding uses common clock bindings.
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible: shall be "microchip,pic32mzda-clk".
+- reg: shall contain base address and length of clock registers.
+- #clock-cells: shall be 1.
+
+Optional properties:
+- microchip,pic32mzda-sosc: shall be added only if platform has
+ secondary oscillator connected.
+
+Example:
+ rootclk: clock-controller@1f801200 {
+ compatible = "microchip,pic32mzda-clk";
+ reg = <0x1f801200 0x200>;
+ #clock-cells = <1>;
+ /* optional */
+ microchip,pic32mzda-sosc;
+ };
+
+
+The clock consumer shall specify the desired clock-output of the clock
+controller (as defined in [2]) by specifying output-id in its "clock"
+phandle cell.
+[2] include/dt-bindings/clock/microchip,pic32-clock.h
+
+For example for UART2:
+uart2: serial@2 {
+ compatible = "microchip,pic32mzda-uart";
+ reg = <>;
+ interrupts = <>;
+ clocks = < PB2CLK>;
+};
diff --git a/include/dt-bindings/clock/microchip,pic32-clock.h
b/include/dt-bindings/clock/microchip,pic32-clock.h
new file mode 100644
index 000..184647a6
--- /dev/null
+++ b/include/dt-bindings/clock/microchip,pic32-clock.h
@@ -0,0 +1,42 @@
+/*
+ * Purna Chandra Mandal,
+ * Copyright (C) 2015 Microchip Technology Inc. All rights reserved.
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MICROCHIP_PIC32_H_
+#define _DT_BINDINGS_CLK_MICROCHIP_PIC32_H_
+
+/* clock output indices */
+#define POSCCLK0
+#define FRCCLK 1
+#define BFRCCLK2
+#define LPRCCLK3
+#define SOSCCLK4
+#define FRCDIVCLK 5
+#define PLLCLK 6
+#define SCLK 7
+#define PB1CLK 8
+#define PB2CLK 9
+#define PB3CLK 10
+#define PB4CLK 11
+#define PB5CLK 12
+#define PB6CLK 13
+#define PB7CLK 14
+#define REF1CLK15
+#define REF2CLK16
+#define REF3CLK17
+#define REF4CLK18
+#define REF5CLK19
+#define UPLLCLK20
+#define MAXCLKS21
+
+#endif /* _DT_BINDINGS_CLK_MICROCHIP_PIC32_H_ */
--
1.8.3.1
[PATCH v11 0/3] PIC32MZDA Clock Driver
Clock bindings got acked and then essentially unacked, while the clock driver never made it upstream. In the meantime, the initial DTS file made it upstream. This latest patch series includes a patch to go back and correct the DTS files to reflect the new clock bindings in this patch series. Note: Please pull this complete series through the MIPS tree. Purna Chandra Mandal (3): dt/bindings/clk: Add PIC32 clock binding documentation. clk: microchip: Add Microchip PIC32 clock driver. MIPS: dts: pic32: Update dts to reflect new PIC32MZDA clk binding .../devicetree/bindings/clock/microchip,pic32.txt | 39 + arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi| 236 - arch/mips/boot/dts/pic32/pic32mzda.dtsi| 63 +- arch/mips/boot/dts/pic32/pic32mzda_sk.dts |5 +- drivers/clk/Kconfig|3 + drivers/clk/Makefile |1 + drivers/clk/microchip/Makefile |2 + drivers/clk/microchip/clk-core.c | 1031 drivers/clk/microchip/clk-core.h | 84 ++ drivers/clk/microchip/clk-pic32mzda.c | 275 ++ include/dt-bindings/clock/microchip,pic32-clock.h | 42 + 11 files changed, 1522 insertions(+), 259 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/microchip,pic32.txt delete mode 100644 arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi create mode 100644 drivers/clk/microchip/Makefile create mode 100644 drivers/clk/microchip/clk-core.c create mode 100644 drivers/clk/microchip/clk-core.h create mode 100644 drivers/clk/microchip/clk-pic32mzda.c create mode 100644 include/dt-bindings/clock/microchip,pic32-clock.h -- 1.8.3.1
Re: [PATCH v10 2/3] clk: microchip: Add PIC32 clock driver
On 05/07/2016 05:40 AM, Stephen Boyd wrote:
> Mostly nitpicks, although I'm worried about the iomem casting and
> addition stuff. I suppose if those are fixed up at some later
> time then I'm fine with this going through MIPS tree.
>
> On 03/23, Purna Chandra Mandal wrote:
>> +static int pbclk_set_rate(struct clk_hw *hw, unsigned long rate,
>> + unsigned long parent_rate)
>> +{
>> +struct pic32_periph_clk *pb = clkhw_to_pbclk(hw);
>> +unsigned long flags;
>> +u32 v, div;
>> +int err;
>> +
>> +/* check & wait for DIV_READY */
>> +err = readl_poll_timeout_atomic(pb->ctrl_reg, v, v & PB_DIV_READY,
>> +1, LOCK_TIMEOUT_US);
>> +if (err)
>> +return err;
>> +
>> +/* calculate clkdiv and best rate */
>> +div = DIV_ROUND_CLOSEST(parent_rate, rate);
>> +
>> +spin_lock_irqsave(, flags);
>> +
>> +/* apply new div */
>> +v = readl(pb->ctrl_reg);
>> +v &= ~PB_DIV_MASK;
>> +v |= (div - 1);
>> +
>> +pic32_syskey_unlock();
>> +
>> +writel(v, pb->ctrl_reg);
>> +
>> +spin_unlock_irqrestore(, flags);
>> +
>> +/* wait again, for pbdivready */
>> +err = readl_poll_timeout_atomic(pb->ctrl_reg, v, v & PB_DIV_READY,
>> +1, LOCK_TIMEOUT_US);
> why atomic? The spinlock was released already.
>
ack. Will fix.
>> +if (err)
>> +return err;
>> +
>> +/* confirm that new div is applied correctly */
>> +return (pbclk_read_pbdiv(pb) == div) ? 0 : -EBUSY;
>> +}
>> +
>> +const struct clk_ops pic32_pbclk_ops = {
>> +.enable = pbclk_enable,
>> +.disable= pbclk_disable,
>> +.is_enabled = pbclk_is_enabled,
>> +.recalc_rate= pbclk_recalc_rate,
>> +.round_rate = pbclk_round_rate,
>> +.set_rate = pbclk_set_rate,
>> +};
>> +
>> +struct clk *pic32_periph_clk_register(struct pic32_periph_clk *pbclk,
>> + void __iomem *clk_iobase)
>> +{
>> +struct clk *clk;
>> +
>> +pbclk->ctrl_reg += (ulong)clk_iobase;
>> +
>> +clk = clk_register(NULL, >hw);
>> +if (IS_ERR(clk)) {
>> +pr_err("%s: clk_register() failed\n", __func__);
>> +return clk;
>> +}
>> +
>> +return clk;
> These two last lines are the same, just print an error and always
> return clk.
ack.
>> +}
>> +
>> +/* Reference Oscillator operations */
>> +#define clkhw_to_refosc(_hw)container_of(_hw, struct pic32_ref_osc,
>> hw)
>> +
>> +static int roclk_is_enabled(struct clk_hw *hw)
>> +{
>> +struct pic32_ref_osc *refo = clkhw_to_refosc(hw);
>> +
>> +return readl(refo->regs) & REFO_ON;
>> +}
>> +
>> +static int roclk_enable(struct clk_hw *hw)
>> +{
>> +struct pic32_ref_osc *refo = clkhw_to_refosc(hw);
>> +
>> +writel(REFO_ON | REFO_OE, PIC32_SET(refo->regs));
>> +return 0;
>> +}
>> +
>> +static void roclk_disable(struct clk_hw *hw)
>> +{
>> +struct pic32_ref_osc *refo = clkhw_to_refosc(hw);
>> +
>> +writel(REFO_ON | REFO_OE, PIC32_CLR(refo->regs));
>> +}
>> +
>> +static void roclk_init(struct clk_hw *hw)
>> +{
>> +/* initialize clock in disabled state */
>> +roclk_disable(hw);
>> +}
>> +
>> +static u8 roclk_get_parent(struct clk_hw *hw)
>> +{
>> +struct pic32_ref_osc *refo = clkhw_to_refosc(hw);
>> +u32 v, i;
>> +
>> +v = (readl(refo->regs) >> REFO_SEL_SHIFT) & REFO_SEL_MASK;
>> +
>> +if (!refo->parent_map)
>> +return (u8)v;
>> +
>> +for (i = 0; i < clk_hw_get_num_parents(hw); i++)
>> +if (refo->parent_map[i] == v)
>> +return (u8)i;
> That cast is implicit already.
>
ack.
>> +
>> +return -EINVAL;
>> +}
>> +
>> +static unsigned long roclk_calc_rate(unsigned long parent_rate,
>> + u32 rodiv, u32 rotrim)
>> +{
>> +u64 rate64;
>> +
>> +/* fout = fin / [2 * {div + (trim / 512)}]
>> + * = fin * 512 / [1024 * div + 2 * trim]
>> + * = fin * 256 / (512 * div + trim)
>> + * = (fin << 8) / ((div << 9) + trim)
>> + */
>> +if (rotrim)
Re: [PATCH v10 2/3] clk: microchip: Add PIC32 clock driver
On 05/07/2016 05:40 AM, Stephen Boyd wrote:
> Mostly nitpicks, although I'm worried about the iomem casting and
> addition stuff. I suppose if those are fixed up at some later
> time then I'm fine with this going through MIPS tree.
>
> On 03/23, Purna Chandra Mandal wrote:
>> +static int pbclk_set_rate(struct clk_hw *hw, unsigned long rate,
>> + unsigned long parent_rate)
>> +{
>> +struct pic32_periph_clk *pb = clkhw_to_pbclk(hw);
>> +unsigned long flags;
>> +u32 v, div;
>> +int err;
>> +
>> +/* check & wait for DIV_READY */
>> +err = readl_poll_timeout_atomic(pb->ctrl_reg, v, v & PB_DIV_READY,
>> +1, LOCK_TIMEOUT_US);
>> +if (err)
>> +return err;
>> +
>> +/* calculate clkdiv and best rate */
>> +div = DIV_ROUND_CLOSEST(parent_rate, rate);
>> +
>> +spin_lock_irqsave(, flags);
>> +
>> +/* apply new div */
>> +v = readl(pb->ctrl_reg);
>> +v &= ~PB_DIV_MASK;
>> +v |= (div - 1);
>> +
>> +pic32_syskey_unlock();
>> +
>> +writel(v, pb->ctrl_reg);
>> +
>> +spin_unlock_irqrestore(, flags);
>> +
>> +/* wait again, for pbdivready */
>> +err = readl_poll_timeout_atomic(pb->ctrl_reg, v, v & PB_DIV_READY,
>> +1, LOCK_TIMEOUT_US);
> why atomic? The spinlock was released already.
>
ack. Will fix.
>> +if (err)
>> +return err;
>> +
>> +/* confirm that new div is applied correctly */
>> +return (pbclk_read_pbdiv(pb) == div) ? 0 : -EBUSY;
>> +}
>> +
>> +const struct clk_ops pic32_pbclk_ops = {
>> +.enable = pbclk_enable,
>> +.disable= pbclk_disable,
>> +.is_enabled = pbclk_is_enabled,
>> +.recalc_rate= pbclk_recalc_rate,
>> +.round_rate = pbclk_round_rate,
>> +.set_rate = pbclk_set_rate,
>> +};
>> +
>> +struct clk *pic32_periph_clk_register(struct pic32_periph_clk *pbclk,
>> + void __iomem *clk_iobase)
>> +{
>> +struct clk *clk;
>> +
>> +pbclk->ctrl_reg += (ulong)clk_iobase;
>> +
>> +clk = clk_register(NULL, >hw);
>> +if (IS_ERR(clk)) {
>> +pr_err("%s: clk_register() failed\n", __func__);
>> +return clk;
>> +}
>> +
>> +return clk;
> These two last lines are the same, just print an error and always
> return clk.
ack.
>> +}
>> +
>> +/* Reference Oscillator operations */
>> +#define clkhw_to_refosc(_hw)container_of(_hw, struct pic32_ref_osc,
>> hw)
>> +
>> +static int roclk_is_enabled(struct clk_hw *hw)
>> +{
>> +struct pic32_ref_osc *refo = clkhw_to_refosc(hw);
>> +
>> +return readl(refo->regs) & REFO_ON;
>> +}
>> +
>> +static int roclk_enable(struct clk_hw *hw)
>> +{
>> +struct pic32_ref_osc *refo = clkhw_to_refosc(hw);
>> +
>> +writel(REFO_ON | REFO_OE, PIC32_SET(refo->regs));
>> +return 0;
>> +}
>> +
>> +static void roclk_disable(struct clk_hw *hw)
>> +{
>> +struct pic32_ref_osc *refo = clkhw_to_refosc(hw);
>> +
>> +writel(REFO_ON | REFO_OE, PIC32_CLR(refo->regs));
>> +}
>> +
>> +static void roclk_init(struct clk_hw *hw)
>> +{
>> +/* initialize clock in disabled state */
>> +roclk_disable(hw);
>> +}
>> +
>> +static u8 roclk_get_parent(struct clk_hw *hw)
>> +{
>> +struct pic32_ref_osc *refo = clkhw_to_refosc(hw);
>> +u32 v, i;
>> +
>> +v = (readl(refo->regs) >> REFO_SEL_SHIFT) & REFO_SEL_MASK;
>> +
>> +if (!refo->parent_map)
>> +return (u8)v;
>> +
>> +for (i = 0; i < clk_hw_get_num_parents(hw); i++)
>> +if (refo->parent_map[i] == v)
>> +return (u8)i;
> That cast is implicit already.
>
ack.
>> +
>> +return -EINVAL;
>> +}
>> +
>> +static unsigned long roclk_calc_rate(unsigned long parent_rate,
>> + u32 rodiv, u32 rotrim)
>> +{
>> +u64 rate64;
>> +
>> +/* fout = fin / [2 * {div + (trim / 512)}]
>> + * = fin * 512 / [1024 * div + 2 * trim]
>> + * = fin * 256 / (512 * div + trim)
>> + * = (fin << 8) / ((div << 9) + trim)
>> + */
>> +if (rotrim)
Re: [patch] spi: pic32-sqi: silence array overflow warning
On 04/22/2016 03:25 PM, Dan Carpenter wrote: > We read one element beyond the end of the array when we access > "rdesc[i + 1]" so it causes a static checker warning. It's harmless > because we write over it again on the next line. But let's just silence > the warning. > > Signed-off-by: Dan Carpenter <dan.carpen...@oracle.com> > > diff --git a/drivers/spi/spi-pic32-sqi.c b/drivers/spi/spi-pic32-sqi.c > index b215347..74b9e68 100644 > --- a/drivers/spi/spi-pic32-sqi.c > +++ b/drivers/spi/spi-pic32-sqi.c > @@ -537,7 +537,7 @@ static int ring_desc_ring_alloc(struct pic32_sqi *sqi) > } > > /* Prepare BD: chain to next BD(s) */ > - for (i = 0, rdesc = sqi->ring; i < PESQI_BD_COUNT; i++) > + for (i = 0, rdesc = sqi->ring; i < PESQI_BD_COUNT - 1; i++) > bd[i].bd_nextp = rdesc[i + 1].bd_dma; > bd[PESQI_BD_COUNT - 1].bd_nextp = 0; > Reviewed-by: Purna Chandra Mandal <purna.man...@microchip.com>
Re: [patch] spi: pic32-sqi: silence array overflow warning
On 04/22/2016 03:25 PM, Dan Carpenter wrote: > We read one element beyond the end of the array when we access > "rdesc[i + 1]" so it causes a static checker warning. It's harmless > because we write over it again on the next line. But let's just silence > the warning. > > Signed-off-by: Dan Carpenter > > diff --git a/drivers/spi/spi-pic32-sqi.c b/drivers/spi/spi-pic32-sqi.c > index b215347..74b9e68 100644 > --- a/drivers/spi/spi-pic32-sqi.c > +++ b/drivers/spi/spi-pic32-sqi.c > @@ -537,7 +537,7 @@ static int ring_desc_ring_alloc(struct pic32_sqi *sqi) > } > > /* Prepare BD: chain to next BD(s) */ > - for (i = 0, rdesc = sqi->ring; i < PESQI_BD_COUNT; i++) > + for (i = 0, rdesc = sqi->ring; i < PESQI_BD_COUNT - 1; i++) > bd[i].bd_nextp = rdesc[i + 1].bd_dma; > bd[PESQI_BD_COUNT - 1].bd_nextp = 0; > Reviewed-by: Purna Chandra Mandal
[PATCH v3 1/2] spi: pic32-sqi: add binding document for PIC32 Quad-SPI driver.
Document Device tree bindings for the quad SPI peripheral
found on Microchip PIC32 class devices.
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
Acked-by: Rob Herring <r...@kernel.org>
Cc: Kumar Gala <ga...@codeaurora.org>
Cc: Ian Campbell <ijc+devicet...@hellion.org.uk>
Cc: Rob Herring <robh...@kernel.org>
Cc: Pawel Moll <pawel.m...@arm.com>
Cc: Mark Rutland <mark.rutl...@arm.com>
Cc: Mark Brown <broo...@kernel.org>
---
Changes in v3:
- update exmaple, replace 'sqi@' with 'spi@'.
Changes in v2: None
Documentation/devicetree/bindings/spi/sqi-pic32.txt | 18 ++
1 file changed, 18 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/sqi-pic32.txt
diff --git a/Documentation/devicetree/bindings/spi/sqi-pic32.txt
b/Documentation/devicetree/bindings/spi/sqi-pic32.txt
new file mode 100644
index 000..c82d021
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/sqi-pic32.txt
@@ -0,0 +1,18 @@
+Microchip PIC32 Quad SPI controller
+---
+Required properties:
+- compatible: Should be "microchip,pic32mzda-sqi".
+- reg: Address and length of SQI controller register space.
+- interrupts: Should contain SQI interrupt.
+- clocks: Should contain phandle of two clocks in sequence, one that drives
+ clock on SPI bus and other that drives SQI controller.
+- clock-names: Should be "spi_ck" and "reg_ck" in order.
+
+Example:
+ sqi1: spi@1f8e2000 {
+ compatible = "microchip,pic32mzda-sqi";
+ reg = <0x1f8e2000 0x200>;
+ clocks = < REF2CLK>, < PB5CLK>;
+ clock-names = "spi_ck", "reg_ck";
+ interrupts = <169 IRQ_TYPE_LEVEL_HIGH>;
+ };
--
1.8.3.1
[PATCH v3 2/2] spi: pic32-sqi: add SPI driver for PIC32 SQI controller.
This driver implements SPI master interface for Quad SPI controller, specifically for accessing quad SPI flash. It uses descriptor-based DMA transfer mode and supports half-duplex communication for single, dual and quad SPI transactions. Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com> Cc: Mark Brown <broo...@kernel.org> --- Changes in v3: - drop sqi_map/unmap_transfer() for core provided one - replace devm_request_irq() with request_irq() for fixing release order - check return value of clk_prepare_enable() - fix checking devm_ioremap_resource() return value Changes in v2: - update subject line of dt/binding patch reflecting style of subsystem. drivers/spi/Kconfig | 6 + drivers/spi/Makefile| 1 + drivers/spi/spi-pic32-sqi.c | 768 3 files changed, 775 insertions(+) create mode 100644 drivers/spi/spi-pic32-sqi.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 8a8ff50..281ed5d 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -442,6 +442,12 @@ config SPI_PIC32 help SPI driver for Microchip PIC32 SPI master controller. +config SPI_PIC32_SQI + tristate "Microchip PIC32 Quad SPI driver" + depends on MACH_PIC32 || COMPILE_TEST + help + SPI driver for PIC32 Quad SPI controller. + config SPI_PL022 tristate "ARM AMBA PL022 SSP controller" depends on ARM_AMBA diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 06019ed..3c74d00 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -63,6 +63,7 @@ obj-$(CONFIG_SPI_OMAP24XX)+= spi-omap2-mcspi.o obj-$(CONFIG_SPI_TI_QSPI) += spi-ti-qspi.o obj-$(CONFIG_SPI_ORION)+= spi-orion.o obj-$(CONFIG_SPI_PIC32)+= spi-pic32.o +obj-$(CONFIG_SPI_PIC32_SQI)+= spi-pic32-sqi.o obj-$(CONFIG_SPI_PL022)+= spi-pl022.o obj-$(CONFIG_SPI_PPC4xx) += spi-ppc4xx.o spi-pxa2xx-platform-objs := spi-pxa2xx.o spi-pxa2xx-dma.o diff --git a/drivers/spi/spi-pic32-sqi.c b/drivers/spi/spi-pic32-sqi.c new file mode 100644 index 000..b215347 --- /dev/null +++ b/drivers/spi/spi-pic32-sqi.c @@ -0,0 +1,768 @@ +/* + * PIC32 Quad SPI controller driver. + * + * Purna Chandra Mandal <purna.man...@microchip.com> + * Copyright (c) 2016, Microchip Technology Inc. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* SQI registers */ +#define PESQI_XIP_CONF1_REG0x00 +#define PESQI_XIP_CONF2_REG0x04 +#define PESQI_CONF_REG 0x08 +#define PESQI_CTRL_REG 0x0C +#define PESQI_CLK_CTRL_REG 0x10 +#define PESQI_CMD_THRES_REG0x14 +#define PESQI_INT_THRES_REG0x18 +#define PESQI_INT_ENABLE_REG 0x1C +#define PESQI_INT_STAT_REG 0x20 +#define PESQI_TX_DATA_REG 0x24 +#define PESQI_RX_DATA_REG 0x28 +#define PESQI_STAT1_REG0x2C +#define PESQI_STAT2_REG0x30 +#define PESQI_BD_CTRL_REG 0x34 +#define PESQI_BD_CUR_ADDR_REG 0x38 +#define PESQI_BD_BASE_ADDR_REG 0x40 +#define PESQI_BD_STAT_REG 0x44 +#define PESQI_BD_POLL_CTRL_REG 0x48 +#define PESQI_BD_TX_DMA_STAT_REG 0x4C +#define PESQI_BD_RX_DMA_STAT_REG 0x50 +#define PESQI_THRES_REG0x54 +#define PESQI_INT_SIGEN_REG0x58 + +/* PESQI_CONF_REG fields */ +#define PESQI_MODE 0x7 +#define PESQI_MODE_BOOT 0 +#define PESQI_MODE_PIO1 +#define PESQI_MODE_DMA2 +#define PESQI_MODE_XIP3 +#define PESQI_MODE_SHIFT 0 +#define PESQI_CPHA BIT(3) +#define PESQI_CPOL BIT(4) +#define PESQI_LSBF BIT(5) +#define PESQI_RXLATCH BIT(7) +#define PESQI_SERMODE BIT(8) +#define PESQI_WP_ENBIT(9) +#define PESQI_HOLD_EN BIT(10) +#define PESQI_BURST_EN BIT(12) +#define PESQI_CS_CTRL_HW BIT(15) +#define PESQI_SOFT_RESET BIT(16) +#define PESQI_LANES_SHIFT 20 +#define PESQI_SINGLE_LANE 0 +#define PESQI_DUAL_LANE 1 +#define PESQI_QUAD_LANE 2 +#define PESQI_CSEN_SHIFT 24 +#define PESQI_EN BIT(23) + +/* PESQI_CLK_CTRL_REG fields */ +#define PESQI_CLK_EN BIT(0) +#define PESQI_CLK_STABLE BIT(1) +#define PESQI_CLKDIV_SHIFT 8 +#define PESQI_CLKDIV 0xff + +/* PESQI_INT_THR/CMD_THR_REG *
[PATCH v3 1/2] spi: pic32-sqi: add binding document for PIC32 Quad-SPI driver.
Document Device tree bindings for the quad SPI peripheral
found on Microchip PIC32 class devices.
Signed-off-by: Purna Chandra Mandal
Acked-by: Rob Herring
Cc: Kumar Gala
Cc: Ian Campbell
Cc: Rob Herring
Cc: Pawel Moll
Cc: Mark Rutland
Cc: Mark Brown
---
Changes in v3:
- update exmaple, replace 'sqi@' with 'spi@'.
Changes in v2: None
Documentation/devicetree/bindings/spi/sqi-pic32.txt | 18 ++
1 file changed, 18 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/sqi-pic32.txt
diff --git a/Documentation/devicetree/bindings/spi/sqi-pic32.txt
b/Documentation/devicetree/bindings/spi/sqi-pic32.txt
new file mode 100644
index 000..c82d021
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/sqi-pic32.txt
@@ -0,0 +1,18 @@
+Microchip PIC32 Quad SPI controller
+---
+Required properties:
+- compatible: Should be "microchip,pic32mzda-sqi".
+- reg: Address and length of SQI controller register space.
+- interrupts: Should contain SQI interrupt.
+- clocks: Should contain phandle of two clocks in sequence, one that drives
+ clock on SPI bus and other that drives SQI controller.
+- clock-names: Should be "spi_ck" and "reg_ck" in order.
+
+Example:
+ sqi1: spi@1f8e2000 {
+ compatible = "microchip,pic32mzda-sqi";
+ reg = <0x1f8e2000 0x200>;
+ clocks = < REF2CLK>, < PB5CLK>;
+ clock-names = "spi_ck", "reg_ck";
+ interrupts = <169 IRQ_TYPE_LEVEL_HIGH>;
+ };
--
1.8.3.1
[PATCH v3 2/2] spi: pic32-sqi: add SPI driver for PIC32 SQI controller.
This driver implements SPI master interface for Quad SPI controller, specifically for accessing quad SPI flash. It uses descriptor-based DMA transfer mode and supports half-duplex communication for single, dual and quad SPI transactions. Signed-off-by: Purna Chandra Mandal Cc: Mark Brown --- Changes in v3: - drop sqi_map/unmap_transfer() for core provided one - replace devm_request_irq() with request_irq() for fixing release order - check return value of clk_prepare_enable() - fix checking devm_ioremap_resource() return value Changes in v2: - update subject line of dt/binding patch reflecting style of subsystem. drivers/spi/Kconfig | 6 + drivers/spi/Makefile| 1 + drivers/spi/spi-pic32-sqi.c | 768 3 files changed, 775 insertions(+) create mode 100644 drivers/spi/spi-pic32-sqi.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 8a8ff50..281ed5d 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -442,6 +442,12 @@ config SPI_PIC32 help SPI driver for Microchip PIC32 SPI master controller. +config SPI_PIC32_SQI + tristate "Microchip PIC32 Quad SPI driver" + depends on MACH_PIC32 || COMPILE_TEST + help + SPI driver for PIC32 Quad SPI controller. + config SPI_PL022 tristate "ARM AMBA PL022 SSP controller" depends on ARM_AMBA diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 06019ed..3c74d00 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -63,6 +63,7 @@ obj-$(CONFIG_SPI_OMAP24XX)+= spi-omap2-mcspi.o obj-$(CONFIG_SPI_TI_QSPI) += spi-ti-qspi.o obj-$(CONFIG_SPI_ORION)+= spi-orion.o obj-$(CONFIG_SPI_PIC32)+= spi-pic32.o +obj-$(CONFIG_SPI_PIC32_SQI)+= spi-pic32-sqi.o obj-$(CONFIG_SPI_PL022)+= spi-pl022.o obj-$(CONFIG_SPI_PPC4xx) += spi-ppc4xx.o spi-pxa2xx-platform-objs := spi-pxa2xx.o spi-pxa2xx-dma.o diff --git a/drivers/spi/spi-pic32-sqi.c b/drivers/spi/spi-pic32-sqi.c new file mode 100644 index 000..b215347 --- /dev/null +++ b/drivers/spi/spi-pic32-sqi.c @@ -0,0 +1,768 @@ +/* + * PIC32 Quad SPI controller driver. + * + * Purna Chandra Mandal + * Copyright (c) 2016, Microchip Technology Inc. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* SQI registers */ +#define PESQI_XIP_CONF1_REG0x00 +#define PESQI_XIP_CONF2_REG0x04 +#define PESQI_CONF_REG 0x08 +#define PESQI_CTRL_REG 0x0C +#define PESQI_CLK_CTRL_REG 0x10 +#define PESQI_CMD_THRES_REG0x14 +#define PESQI_INT_THRES_REG0x18 +#define PESQI_INT_ENABLE_REG 0x1C +#define PESQI_INT_STAT_REG 0x20 +#define PESQI_TX_DATA_REG 0x24 +#define PESQI_RX_DATA_REG 0x28 +#define PESQI_STAT1_REG0x2C +#define PESQI_STAT2_REG0x30 +#define PESQI_BD_CTRL_REG 0x34 +#define PESQI_BD_CUR_ADDR_REG 0x38 +#define PESQI_BD_BASE_ADDR_REG 0x40 +#define PESQI_BD_STAT_REG 0x44 +#define PESQI_BD_POLL_CTRL_REG 0x48 +#define PESQI_BD_TX_DMA_STAT_REG 0x4C +#define PESQI_BD_RX_DMA_STAT_REG 0x50 +#define PESQI_THRES_REG0x54 +#define PESQI_INT_SIGEN_REG0x58 + +/* PESQI_CONF_REG fields */ +#define PESQI_MODE 0x7 +#define PESQI_MODE_BOOT 0 +#define PESQI_MODE_PIO1 +#define PESQI_MODE_DMA2 +#define PESQI_MODE_XIP3 +#define PESQI_MODE_SHIFT 0 +#define PESQI_CPHA BIT(3) +#define PESQI_CPOL BIT(4) +#define PESQI_LSBF BIT(5) +#define PESQI_RXLATCH BIT(7) +#define PESQI_SERMODE BIT(8) +#define PESQI_WP_ENBIT(9) +#define PESQI_HOLD_EN BIT(10) +#define PESQI_BURST_EN BIT(12) +#define PESQI_CS_CTRL_HW BIT(15) +#define PESQI_SOFT_RESET BIT(16) +#define PESQI_LANES_SHIFT 20 +#define PESQI_SINGLE_LANE 0 +#define PESQI_DUAL_LANE 1 +#define PESQI_QUAD_LANE 2 +#define PESQI_CSEN_SHIFT 24 +#define PESQI_EN BIT(23) + +/* PESQI_CLK_CTRL_REG fields */ +#define PESQI_CLK_EN BIT(0) +#define PESQI_CLK_STABLE BIT(1) +#define PESQI_CLKDIV_SHIFT 8 +#define PESQI_CLKDIV 0xff + +/* PESQI_INT_THR/CMD_THR_REG */ +#define PESQI_TXTHR_MASK 0x1f +#define PESQI_TXTHR_SHIFT 8 +#define PESQI_RXTHR_MASK
Re: [PATCH v2 2/2] spi: pic32-sqi: add SPI driver for PIC32 SQI controller.
On 04/14/2016 11:25 AM, Mark Brown wrote:
> On Wed, Apr 13, 2016 at 06:52:58PM +0530, Purna Chandra Mandal wrote:
>
>> +enable = readl(sqi->regs + PESQI_INT_ENABLE_REG);
>> +status = readl(sqi->regs + PESQI_INT_STAT_REG);
>> +if (!status)
>> +return IRQ_NONE;
>> +
> For robustness the check should be if there was anything handled, not if
> there was anything set.
In PESQI controller INT_STAT_REG specifies interrupting reason(s) as usual,
but mostly to confirm completion of on-going DMA operation. It is sticky,
no way to acknowledge the interrupt source except masking the source.
In short, whole interrupt logic is mere extension of status polling logic.
And in driver isr logic is completely depended on the INT_STAT_REG; if status
is zero no handling can be done and is unexpected!
>> +static dma_addr_t pic32_sqi_map_transfer(struct pic32_sqi *sqi,
>> + struct spi_transfer *transfer)
>> +{
>> +struct device *dev = >master->dev;
> Don't open code DMA mapping of the buffers, use the core support.
Make sense. Will use core support.
>> +reg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> +sqi->regs = devm_ioremap_resource(>dev, reg);
>> +if (!sqi->regs) {
>> +dev_err(>dev, "mem map failed\n");
> devm_ioremap_resource() will log for you.
ack.
>> +clk_prepare_enable(sqi->sys_clk);
>> +clk_prepare_enable(sqi->base_clk);
> Check the return value please.
Will add.
>> +/* install irq handlers */
>> +ret = devm_request_irq(>dev, sqi->irq, pic32_sqi_isr,
>> + 0, dev_name(>dev), sqi);
>> +if (ret < 0) {
>> +dev_err(>dev, "request-irq %d, failed ?\n", sqi->irq);
>> +goto err_free_ring;
>> +}
> This will free before the clocks are disabled. Are you sure that's
> safe? It's generally not good to mix devm_ and non-devm operations
> especially things like these that aren't simple frees of data. It is
> safer to use a normal request_irq().
Yes, will use request_irq() instead.
>> +static int pic32_sqi_remove(struct platform_device *pdev)
>> +{
>> +struct pic32_sqi *sqi = platform_get_drvdata(pdev);
>> +
>> +clk_disable_unprepare(sqi->base_clk);
>> +clk_disable_unprepare(sqi->sys_clk);
>> +
>> +/* release memory */
>> +ring_desc_ring_free(sqi);
> This will free the descriptor ring before the interrupt...
ack, Will correct disable/free order.
Re: [PATCH v2 2/2] spi: pic32-sqi: add SPI driver for PIC32 SQI controller.
On 04/14/2016 11:25 AM, Mark Brown wrote:
> On Wed, Apr 13, 2016 at 06:52:58PM +0530, Purna Chandra Mandal wrote:
>
>> +enable = readl(sqi->regs + PESQI_INT_ENABLE_REG);
>> +status = readl(sqi->regs + PESQI_INT_STAT_REG);
>> +if (!status)
>> +return IRQ_NONE;
>> +
> For robustness the check should be if there was anything handled, not if
> there was anything set.
In PESQI controller INT_STAT_REG specifies interrupting reason(s) as usual,
but mostly to confirm completion of on-going DMA operation. It is sticky,
no way to acknowledge the interrupt source except masking the source.
In short, whole interrupt logic is mere extension of status polling logic.
And in driver isr logic is completely depended on the INT_STAT_REG; if status
is zero no handling can be done and is unexpected!
>> +static dma_addr_t pic32_sqi_map_transfer(struct pic32_sqi *sqi,
>> + struct spi_transfer *transfer)
>> +{
>> +struct device *dev = >master->dev;
> Don't open code DMA mapping of the buffers, use the core support.
Make sense. Will use core support.
>> +reg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> +sqi->regs = devm_ioremap_resource(>dev, reg);
>> +if (!sqi->regs) {
>> +dev_err(>dev, "mem map failed\n");
> devm_ioremap_resource() will log for you.
ack.
>> +clk_prepare_enable(sqi->sys_clk);
>> +clk_prepare_enable(sqi->base_clk);
> Check the return value please.
Will add.
>> +/* install irq handlers */
>> +ret = devm_request_irq(>dev, sqi->irq, pic32_sqi_isr,
>> + 0, dev_name(>dev), sqi);
>> +if (ret < 0) {
>> +dev_err(>dev, "request-irq %d, failed ?\n", sqi->irq);
>> +goto err_free_ring;
>> +}
> This will free before the clocks are disabled. Are you sure that's
> safe? It's generally not good to mix devm_ and non-devm operations
> especially things like these that aren't simple frees of data. It is
> safer to use a normal request_irq().
Yes, will use request_irq() instead.
>> +static int pic32_sqi_remove(struct platform_device *pdev)
>> +{
>> +struct pic32_sqi *sqi = platform_get_drvdata(pdev);
>> +
>> +clk_disable_unprepare(sqi->base_clk);
>> +clk_disable_unprepare(sqi->sys_clk);
>> +
>> +/* release memory */
>> +ring_desc_ring_free(sqi);
> This will free the descriptor ring before the interrupt...
ack, Will correct disable/free order.
[PATCH v2 1/2] spi: pic32-sqi: add binding document for PIC32 Quad-SPI driver.
Document Device tree bindings for the quad SPI peripheral
found on Microchip PIC32 class devices.
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
Cc: Kumar Gala <ga...@codeaurora.org>
Cc: Ian Campbell <ijc+devicet...@hellion.org.uk>
Cc: Rob Herring <robh...@kernel.org>
Cc: Pawel Moll <pawel.m...@arm.com>
Cc: Mark Rutland <mark.rutl...@arm.com>
Cc: Mark Brown <broo...@kernel.org>
---
Changes in v2: None
Documentation/devicetree/bindings/spi/sqi-pic32.txt | 18 ++
1 file changed, 18 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/sqi-pic32.txt
diff --git a/Documentation/devicetree/bindings/spi/sqi-pic32.txt
b/Documentation/devicetree/bindings/spi/sqi-pic32.txt
new file mode 100644
index 000..5af9fab
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/sqi-pic32.txt
@@ -0,0 +1,18 @@
+Microchip PIC32 Quad SPI controller
+---
+Required properties:
+- compatible: Should be "microchip,pic32mzda-sqi".
+- reg: Address and length of SQI controller register space.
+- interrupts: Should contain SQI interrupt.
+- clocks: Should contain phandle of two clocks in sequence, clock that drives
+ clock on SPI bus and clock that drives SQI controller.
+- clock-names: Should be "spi_ck" and "reg_ck" in order.
+
+Example:
+ sqi1: sqi@1f8e2000 {
+ compatible = "microchip,pic32mzda-sqi";
+ reg = <0x1f8e2000 0x200>;
+ clocks = < REF2CLK>, < PB5CLK>;
+ clock-names = "spi_ck", "reg_ck";
+ interrupts = <169 IRQ_TYPE_LEVEL_HIGH>;
+ };
--
1.8.3.1
[PATCH v2 2/2] spi: pic32-sqi: add SPI driver for PIC32 SQI controller.
This driver implements SPI master interface for Quad SPI controller, specifically for accessing quad SPI flash. It uses descriptor-based DMA transfer mode and supports half-duplex communication for single, dual and quad SPI transactions. Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com> Cc: Mark Brown <broo...@kernel.org> --- drivers/spi/Kconfig | 6 + drivers/spi/Makefile| 1 + drivers/spi/spi-pic32-sqi.c | 815 3 files changed, 822 insertions(+) create mode 100644 drivers/spi/spi-pic32-sqi.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 8a8ff50..281ed5d 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -442,6 +442,12 @@ config SPI_PIC32 help SPI driver for Microchip PIC32 SPI master controller. +config SPI_PIC32_SQI + tristate "Microchip PIC32 Quad SPI driver" + depends on MACH_PIC32 || COMPILE_TEST + help + SPI driver for PIC32 Quad SPI controller. + config SPI_PL022 tristate "ARM AMBA PL022 SSP controller" depends on ARM_AMBA diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 06019ed..3c74d00 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -63,6 +63,7 @@ obj-$(CONFIG_SPI_OMAP24XX)+= spi-omap2-mcspi.o obj-$(CONFIG_SPI_TI_QSPI) += spi-ti-qspi.o obj-$(CONFIG_SPI_ORION)+= spi-orion.o obj-$(CONFIG_SPI_PIC32)+= spi-pic32.o +obj-$(CONFIG_SPI_PIC32_SQI)+= spi-pic32-sqi.o obj-$(CONFIG_SPI_PL022)+= spi-pl022.o obj-$(CONFIG_SPI_PPC4xx) += spi-ppc4xx.o spi-pxa2xx-platform-objs := spi-pxa2xx.o spi-pxa2xx-dma.o diff --git a/drivers/spi/spi-pic32-sqi.c b/drivers/spi/spi-pic32-sqi.c new file mode 100644 index 000..bb31dc8 --- /dev/null +++ b/drivers/spi/spi-pic32-sqi.c @@ -0,0 +1,815 @@ +/* + * PIC32 Quad SPI controller driver. + * + * Purna Chandra Mandal <purna.man...@microchip.com> + * Copyright (c) 2016, Microchip Technology Inc. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* SQI registers */ +#define PESQI_XIP_CONF1_REG0x00 +#define PESQI_XIP_CONF2_REG0x04 +#define PESQI_CONF_REG 0x08 +#define PESQI_CTRL_REG 0x0C +#define PESQI_CLK_CTRL_REG 0x10 +#define PESQI_CMD_THRES_REG0x14 +#define PESQI_INT_THRES_REG0x18 +#define PESQI_INT_ENABLE_REG 0x1C +#define PESQI_INT_STAT_REG 0x20 +#define PESQI_TX_DATA_REG 0x24 +#define PESQI_RX_DATA_REG 0x28 +#define PESQI_STAT1_REG0x2C +#define PESQI_STAT2_REG0x30 +#define PESQI_BD_CTRL_REG 0x34 +#define PESQI_BD_CUR_ADDR_REG 0x38 +#define PESQI_BD_BASE_ADDR_REG 0x40 +#define PESQI_BD_STAT_REG 0x44 +#define PESQI_BD_POLL_CTRL_REG 0x48 +#define PESQI_BD_TX_DMA_STAT_REG 0x4C +#define PESQI_BD_RX_DMA_STAT_REG 0x50 +#define PESQI_THRES_REG0x54 +#define PESQI_INT_SIGEN_REG0x58 + +/* PESQI_CONF_REG fields */ +#define PESQI_MODE 0x7 +#define PESQI_MODE_BOOT 0 +#define PESQI_MODE_PIO1 +#define PESQI_MODE_DMA2 +#define PESQI_MODE_XIP3 +#define PESQI_MODE_SHIFT 0 +#define PESQI_CPHA BIT(3) +#define PESQI_CPOL BIT(4) +#define PESQI_LSBF BIT(5) +#define PESQI_RXLATCH BIT(7) +#define PESQI_SERMODE BIT(8) +#define PESQI_WP_ENBIT(9) +#define PESQI_HOLD_EN BIT(10) +#define PESQI_BURST_EN BIT(12) +#define PESQI_CS_CTRL_HW BIT(15) +#define PESQI_SOFT_RESET BIT(16) +#define PESQI_LANES_SHIFT 20 +#define PESQI_SINGLE_LANE 0 +#define PESQI_DUAL_LANE 1 +#define PESQI_QUAD_LANE 2 +#define PESQI_CSEN_SHIFT 24 +#define PESQI_EN BIT(23) + +/* PESQI_CLK_CTRL_REG fields */ +#define PESQI_CLK_EN BIT(0) +#define PESQI_CLK_STABLE BIT(1) +#define PESQI_CLKDIV_SHIFT 8 +#define PESQI_CLKDIV 0xff + +/* PESQI_INT_THR/CMD_THR_REG */ +#define PESQI_TXTHR_MASK 0x1f +#define PESQI_TXTHR_SHIFT 8 +#define PESQI_RXTHR_MASK 0x1f +#define PESQI_RXTHR_SHIFT 0 + +/* PESQI_INT_EN/INT_STAT/INT_SIG_EN_REG */ +#define PESQI_TXEMPTY BIT(0) +#define PESQI_TXFULL BIT(1) +#define PESQI_TXTHRBIT(2) +#define
[PATCH v2 1/2] spi: pic32-sqi: add binding document for PIC32 Quad-SPI driver.
Document Device tree bindings for the quad SPI peripheral
found on Microchip PIC32 class devices.
Signed-off-by: Purna Chandra Mandal
Cc: Kumar Gala
Cc: Ian Campbell
Cc: Rob Herring
Cc: Pawel Moll
Cc: Mark Rutland
Cc: Mark Brown
---
Changes in v2: None
Documentation/devicetree/bindings/spi/sqi-pic32.txt | 18 ++
1 file changed, 18 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/sqi-pic32.txt
diff --git a/Documentation/devicetree/bindings/spi/sqi-pic32.txt
b/Documentation/devicetree/bindings/spi/sqi-pic32.txt
new file mode 100644
index 000..5af9fab
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/sqi-pic32.txt
@@ -0,0 +1,18 @@
+Microchip PIC32 Quad SPI controller
+---
+Required properties:
+- compatible: Should be "microchip,pic32mzda-sqi".
+- reg: Address and length of SQI controller register space.
+- interrupts: Should contain SQI interrupt.
+- clocks: Should contain phandle of two clocks in sequence, clock that drives
+ clock on SPI bus and clock that drives SQI controller.
+- clock-names: Should be "spi_ck" and "reg_ck" in order.
+
+Example:
+ sqi1: sqi@1f8e2000 {
+ compatible = "microchip,pic32mzda-sqi";
+ reg = <0x1f8e2000 0x200>;
+ clocks = < REF2CLK>, < PB5CLK>;
+ clock-names = "spi_ck", "reg_ck";
+ interrupts = <169 IRQ_TYPE_LEVEL_HIGH>;
+ };
--
1.8.3.1
[PATCH v2 2/2] spi: pic32-sqi: add SPI driver for PIC32 SQI controller.
This driver implements SPI master interface for Quad SPI controller, specifically for accessing quad SPI flash. It uses descriptor-based DMA transfer mode and supports half-duplex communication for single, dual and quad SPI transactions. Signed-off-by: Purna Chandra Mandal Cc: Mark Brown --- drivers/spi/Kconfig | 6 + drivers/spi/Makefile| 1 + drivers/spi/spi-pic32-sqi.c | 815 3 files changed, 822 insertions(+) create mode 100644 drivers/spi/spi-pic32-sqi.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 8a8ff50..281ed5d 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -442,6 +442,12 @@ config SPI_PIC32 help SPI driver for Microchip PIC32 SPI master controller. +config SPI_PIC32_SQI + tristate "Microchip PIC32 Quad SPI driver" + depends on MACH_PIC32 || COMPILE_TEST + help + SPI driver for PIC32 Quad SPI controller. + config SPI_PL022 tristate "ARM AMBA PL022 SSP controller" depends on ARM_AMBA diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 06019ed..3c74d00 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -63,6 +63,7 @@ obj-$(CONFIG_SPI_OMAP24XX)+= spi-omap2-mcspi.o obj-$(CONFIG_SPI_TI_QSPI) += spi-ti-qspi.o obj-$(CONFIG_SPI_ORION)+= spi-orion.o obj-$(CONFIG_SPI_PIC32)+= spi-pic32.o +obj-$(CONFIG_SPI_PIC32_SQI)+= spi-pic32-sqi.o obj-$(CONFIG_SPI_PL022)+= spi-pl022.o obj-$(CONFIG_SPI_PPC4xx) += spi-ppc4xx.o spi-pxa2xx-platform-objs := spi-pxa2xx.o spi-pxa2xx-dma.o diff --git a/drivers/spi/spi-pic32-sqi.c b/drivers/spi/spi-pic32-sqi.c new file mode 100644 index 000..bb31dc8 --- /dev/null +++ b/drivers/spi/spi-pic32-sqi.c @@ -0,0 +1,815 @@ +/* + * PIC32 Quad SPI controller driver. + * + * Purna Chandra Mandal + * Copyright (c) 2016, Microchip Technology Inc. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* SQI registers */ +#define PESQI_XIP_CONF1_REG0x00 +#define PESQI_XIP_CONF2_REG0x04 +#define PESQI_CONF_REG 0x08 +#define PESQI_CTRL_REG 0x0C +#define PESQI_CLK_CTRL_REG 0x10 +#define PESQI_CMD_THRES_REG0x14 +#define PESQI_INT_THRES_REG0x18 +#define PESQI_INT_ENABLE_REG 0x1C +#define PESQI_INT_STAT_REG 0x20 +#define PESQI_TX_DATA_REG 0x24 +#define PESQI_RX_DATA_REG 0x28 +#define PESQI_STAT1_REG0x2C +#define PESQI_STAT2_REG0x30 +#define PESQI_BD_CTRL_REG 0x34 +#define PESQI_BD_CUR_ADDR_REG 0x38 +#define PESQI_BD_BASE_ADDR_REG 0x40 +#define PESQI_BD_STAT_REG 0x44 +#define PESQI_BD_POLL_CTRL_REG 0x48 +#define PESQI_BD_TX_DMA_STAT_REG 0x4C +#define PESQI_BD_RX_DMA_STAT_REG 0x50 +#define PESQI_THRES_REG0x54 +#define PESQI_INT_SIGEN_REG0x58 + +/* PESQI_CONF_REG fields */ +#define PESQI_MODE 0x7 +#define PESQI_MODE_BOOT 0 +#define PESQI_MODE_PIO1 +#define PESQI_MODE_DMA2 +#define PESQI_MODE_XIP3 +#define PESQI_MODE_SHIFT 0 +#define PESQI_CPHA BIT(3) +#define PESQI_CPOL BIT(4) +#define PESQI_LSBF BIT(5) +#define PESQI_RXLATCH BIT(7) +#define PESQI_SERMODE BIT(8) +#define PESQI_WP_ENBIT(9) +#define PESQI_HOLD_EN BIT(10) +#define PESQI_BURST_EN BIT(12) +#define PESQI_CS_CTRL_HW BIT(15) +#define PESQI_SOFT_RESET BIT(16) +#define PESQI_LANES_SHIFT 20 +#define PESQI_SINGLE_LANE 0 +#define PESQI_DUAL_LANE 1 +#define PESQI_QUAD_LANE 2 +#define PESQI_CSEN_SHIFT 24 +#define PESQI_EN BIT(23) + +/* PESQI_CLK_CTRL_REG fields */ +#define PESQI_CLK_EN BIT(0) +#define PESQI_CLK_STABLE BIT(1) +#define PESQI_CLKDIV_SHIFT 8 +#define PESQI_CLKDIV 0xff + +/* PESQI_INT_THR/CMD_THR_REG */ +#define PESQI_TXTHR_MASK 0x1f +#define PESQI_TXTHR_SHIFT 8 +#define PESQI_RXTHR_MASK 0x1f +#define PESQI_RXTHR_SHIFT 0 + +/* PESQI_INT_EN/INT_STAT/INT_SIG_EN_REG */ +#define PESQI_TXEMPTY BIT(0) +#define PESQI_TXFULL BIT(1) +#define PESQI_TXTHRBIT(2) +#define PESQI_RXEMPTY BIT(3) +#define PESQI_RXFULL BIT(4) +#define PESQI_RXTHR
[PATCH 1/2] dt/bindings/spi: Add bindings for PIC32 Quad-SPI driver.
Document Device tree bindings for quad SPI peripheral
found on Microchip PIC32 class devices.
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
Cc: Rob Herring <robh...@kernel.org>
Cc: Mark Brown <broo...@kernel.org>
---
Documentation/devicetree/bindings/spi/sqi-pic32.txt | 18 ++
1 file changed, 18 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/sqi-pic32.txt
diff --git a/Documentation/devicetree/bindings/spi/sqi-pic32.txt
b/Documentation/devicetree/bindings/spi/sqi-pic32.txt
new file mode 100644
index 000..5af9fab
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/sqi-pic32.txt
@@ -0,0 +1,18 @@
+Microchip PIC32 Quad SPI controller
+---
+Required properties:
+- compatible: Should be "microchip,pic32mzda-sqi".
+- reg: Address and length of SQI controller register space.
+- interrupts: Should contain SQI interrupt.
+- clocks: Should contain phandle of two clocks in sequence, clock that drives
+ clock on SPI bus and clock that drives SQI controller.
+- clock-names: Should be "spi_ck" and "reg_ck" in order.
+
+Example:
+ sqi1: sqi@1f8e2000 {
+ compatible = "microchip,pic32mzda-sqi";
+ reg = <0x1f8e2000 0x200>;
+ clocks = < REF2CLK>, < PB5CLK>;
+ clock-names = "spi_ck", "reg_ck";
+ interrupts = <169 IRQ_TYPE_LEVEL_HIGH>;
+ };
--
1.8.3.1
[PATCH 2/2] spi: pic32-sqi: add SPI driver for PIC32 SQI controller.
This driver implements SPI master interface for Quad SPI controller, specifically for accessing quad SPI flash. It uses descriptor-based DMA to perform half-duplex communication on SPI bus for single, dual and quad-lane SPI transactions. Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com> Cc: Mark Brown <broo...@kernel.org> --- drivers/spi/Kconfig | 6 + drivers/spi/Makefile| 1 + drivers/spi/spi-pic32-sqi.c | 815 3 files changed, 822 insertions(+) create mode 100644 drivers/spi/spi-pic32-sqi.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 8a8ff50..281ed5d 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -442,6 +442,12 @@ config SPI_PIC32 help SPI driver for Microchip PIC32 SPI master controller. +config SPI_PIC32_SQI + tristate "Microchip PIC32 Quad SPI driver" + depends on MACH_PIC32 || COMPILE_TEST + help + SPI driver for PIC32 Quad SPI controller. + config SPI_PL022 tristate "ARM AMBA PL022 SSP controller" depends on ARM_AMBA diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 06019ed..3c74d00 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -63,6 +63,7 @@ obj-$(CONFIG_SPI_OMAP24XX)+= spi-omap2-mcspi.o obj-$(CONFIG_SPI_TI_QSPI) += spi-ti-qspi.o obj-$(CONFIG_SPI_ORION)+= spi-orion.o obj-$(CONFIG_SPI_PIC32)+= spi-pic32.o +obj-$(CONFIG_SPI_PIC32_SQI)+= spi-pic32-sqi.o obj-$(CONFIG_SPI_PL022)+= spi-pl022.o obj-$(CONFIG_SPI_PPC4xx) += spi-ppc4xx.o spi-pxa2xx-platform-objs := spi-pxa2xx.o spi-pxa2xx-dma.o diff --git a/drivers/spi/spi-pic32-sqi.c b/drivers/spi/spi-pic32-sqi.c new file mode 100644 index 000..bb31dc8 --- /dev/null +++ b/drivers/spi/spi-pic32-sqi.c @@ -0,0 +1,815 @@ +/* + * PIC32 Quad SPI controller driver. + * + * Purna Chandra Mandal <purna.man...@microchip.com> + * Copyright (c) 2016, Microchip Technology Inc. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* SQI registers */ +#define PESQI_XIP_CONF1_REG0x00 +#define PESQI_XIP_CONF2_REG0x04 +#define PESQI_CONF_REG 0x08 +#define PESQI_CTRL_REG 0x0C +#define PESQI_CLK_CTRL_REG 0x10 +#define PESQI_CMD_THRES_REG0x14 +#define PESQI_INT_THRES_REG0x18 +#define PESQI_INT_ENABLE_REG 0x1C +#define PESQI_INT_STAT_REG 0x20 +#define PESQI_TX_DATA_REG 0x24 +#define PESQI_RX_DATA_REG 0x28 +#define PESQI_STAT1_REG0x2C +#define PESQI_STAT2_REG0x30 +#define PESQI_BD_CTRL_REG 0x34 +#define PESQI_BD_CUR_ADDR_REG 0x38 +#define PESQI_BD_BASE_ADDR_REG 0x40 +#define PESQI_BD_STAT_REG 0x44 +#define PESQI_BD_POLL_CTRL_REG 0x48 +#define PESQI_BD_TX_DMA_STAT_REG 0x4C +#define PESQI_BD_RX_DMA_STAT_REG 0x50 +#define PESQI_THRES_REG0x54 +#define PESQI_INT_SIGEN_REG0x58 + +/* PESQI_CONF_REG fields */ +#define PESQI_MODE 0x7 +#define PESQI_MODE_BOOT 0 +#define PESQI_MODE_PIO1 +#define PESQI_MODE_DMA2 +#define PESQI_MODE_XIP3 +#define PESQI_MODE_SHIFT 0 +#define PESQI_CPHA BIT(3) +#define PESQI_CPOL BIT(4) +#define PESQI_LSBF BIT(5) +#define PESQI_RXLATCH BIT(7) +#define PESQI_SERMODE BIT(8) +#define PESQI_WP_ENBIT(9) +#define PESQI_HOLD_EN BIT(10) +#define PESQI_BURST_EN BIT(12) +#define PESQI_CS_CTRL_HW BIT(15) +#define PESQI_SOFT_RESET BIT(16) +#define PESQI_LANES_SHIFT 20 +#define PESQI_SINGLE_LANE 0 +#define PESQI_DUAL_LANE 1 +#define PESQI_QUAD_LANE 2 +#define PESQI_CSEN_SHIFT 24 +#define PESQI_EN BIT(23) + +/* PESQI_CLK_CTRL_REG fields */ +#define PESQI_CLK_EN BIT(0) +#define PESQI_CLK_STABLE BIT(1) +#define PESQI_CLKDIV_SHIFT 8 +#define PESQI_CLKDIV 0xff + +/* PESQI_INT_THR/CMD_THR_REG */ +#define PESQI_TXTHR_MASK 0x1f +#define PESQI_TXTHR_SHIFT 8 +#define PESQI_RXTHR_MASK 0x1f +#define PESQI_RXTHR_SHIFT 0 + +/* PESQI_INT_EN/INT_STAT/INT_SIG_EN_REG */ +#define PESQI_TXEMPTY BIT(0) +#define PESQI_TXFULL BIT(1) +#define PESQI_TXTHRBIT(2) +#define
[PATCH 1/2] dt/bindings/spi: Add bindings for PIC32 Quad-SPI driver.
Document Device tree bindings for quad SPI peripheral
found on Microchip PIC32 class devices.
Signed-off-by: Purna Chandra Mandal
Cc: Rob Herring
Cc: Mark Brown
---
Documentation/devicetree/bindings/spi/sqi-pic32.txt | 18 ++
1 file changed, 18 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/sqi-pic32.txt
diff --git a/Documentation/devicetree/bindings/spi/sqi-pic32.txt
b/Documentation/devicetree/bindings/spi/sqi-pic32.txt
new file mode 100644
index 000..5af9fab
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/sqi-pic32.txt
@@ -0,0 +1,18 @@
+Microchip PIC32 Quad SPI controller
+---
+Required properties:
+- compatible: Should be "microchip,pic32mzda-sqi".
+- reg: Address and length of SQI controller register space.
+- interrupts: Should contain SQI interrupt.
+- clocks: Should contain phandle of two clocks in sequence, clock that drives
+ clock on SPI bus and clock that drives SQI controller.
+- clock-names: Should be "spi_ck" and "reg_ck" in order.
+
+Example:
+ sqi1: sqi@1f8e2000 {
+ compatible = "microchip,pic32mzda-sqi";
+ reg = <0x1f8e2000 0x200>;
+ clocks = < REF2CLK>, < PB5CLK>;
+ clock-names = "spi_ck", "reg_ck";
+ interrupts = <169 IRQ_TYPE_LEVEL_HIGH>;
+ };
--
1.8.3.1
[PATCH 2/2] spi: pic32-sqi: add SPI driver for PIC32 SQI controller.
This driver implements SPI master interface for Quad SPI controller, specifically for accessing quad SPI flash. It uses descriptor-based DMA to perform half-duplex communication on SPI bus for single, dual and quad-lane SPI transactions. Signed-off-by: Purna Chandra Mandal Cc: Mark Brown --- drivers/spi/Kconfig | 6 + drivers/spi/Makefile| 1 + drivers/spi/spi-pic32-sqi.c | 815 3 files changed, 822 insertions(+) create mode 100644 drivers/spi/spi-pic32-sqi.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 8a8ff50..281ed5d 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -442,6 +442,12 @@ config SPI_PIC32 help SPI driver for Microchip PIC32 SPI master controller. +config SPI_PIC32_SQI + tristate "Microchip PIC32 Quad SPI driver" + depends on MACH_PIC32 || COMPILE_TEST + help + SPI driver for PIC32 Quad SPI controller. + config SPI_PL022 tristate "ARM AMBA PL022 SSP controller" depends on ARM_AMBA diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 06019ed..3c74d00 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -63,6 +63,7 @@ obj-$(CONFIG_SPI_OMAP24XX)+= spi-omap2-mcspi.o obj-$(CONFIG_SPI_TI_QSPI) += spi-ti-qspi.o obj-$(CONFIG_SPI_ORION)+= spi-orion.o obj-$(CONFIG_SPI_PIC32)+= spi-pic32.o +obj-$(CONFIG_SPI_PIC32_SQI)+= spi-pic32-sqi.o obj-$(CONFIG_SPI_PL022)+= spi-pl022.o obj-$(CONFIG_SPI_PPC4xx) += spi-ppc4xx.o spi-pxa2xx-platform-objs := spi-pxa2xx.o spi-pxa2xx-dma.o diff --git a/drivers/spi/spi-pic32-sqi.c b/drivers/spi/spi-pic32-sqi.c new file mode 100644 index 000..bb31dc8 --- /dev/null +++ b/drivers/spi/spi-pic32-sqi.c @@ -0,0 +1,815 @@ +/* + * PIC32 Quad SPI controller driver. + * + * Purna Chandra Mandal + * Copyright (c) 2016, Microchip Technology Inc. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* SQI registers */ +#define PESQI_XIP_CONF1_REG0x00 +#define PESQI_XIP_CONF2_REG0x04 +#define PESQI_CONF_REG 0x08 +#define PESQI_CTRL_REG 0x0C +#define PESQI_CLK_CTRL_REG 0x10 +#define PESQI_CMD_THRES_REG0x14 +#define PESQI_INT_THRES_REG0x18 +#define PESQI_INT_ENABLE_REG 0x1C +#define PESQI_INT_STAT_REG 0x20 +#define PESQI_TX_DATA_REG 0x24 +#define PESQI_RX_DATA_REG 0x28 +#define PESQI_STAT1_REG0x2C +#define PESQI_STAT2_REG0x30 +#define PESQI_BD_CTRL_REG 0x34 +#define PESQI_BD_CUR_ADDR_REG 0x38 +#define PESQI_BD_BASE_ADDR_REG 0x40 +#define PESQI_BD_STAT_REG 0x44 +#define PESQI_BD_POLL_CTRL_REG 0x48 +#define PESQI_BD_TX_DMA_STAT_REG 0x4C +#define PESQI_BD_RX_DMA_STAT_REG 0x50 +#define PESQI_THRES_REG0x54 +#define PESQI_INT_SIGEN_REG0x58 + +/* PESQI_CONF_REG fields */ +#define PESQI_MODE 0x7 +#define PESQI_MODE_BOOT 0 +#define PESQI_MODE_PIO1 +#define PESQI_MODE_DMA2 +#define PESQI_MODE_XIP3 +#define PESQI_MODE_SHIFT 0 +#define PESQI_CPHA BIT(3) +#define PESQI_CPOL BIT(4) +#define PESQI_LSBF BIT(5) +#define PESQI_RXLATCH BIT(7) +#define PESQI_SERMODE BIT(8) +#define PESQI_WP_ENBIT(9) +#define PESQI_HOLD_EN BIT(10) +#define PESQI_BURST_EN BIT(12) +#define PESQI_CS_CTRL_HW BIT(15) +#define PESQI_SOFT_RESET BIT(16) +#define PESQI_LANES_SHIFT 20 +#define PESQI_SINGLE_LANE 0 +#define PESQI_DUAL_LANE 1 +#define PESQI_QUAD_LANE 2 +#define PESQI_CSEN_SHIFT 24 +#define PESQI_EN BIT(23) + +/* PESQI_CLK_CTRL_REG fields */ +#define PESQI_CLK_EN BIT(0) +#define PESQI_CLK_STABLE BIT(1) +#define PESQI_CLKDIV_SHIFT 8 +#define PESQI_CLKDIV 0xff + +/* PESQI_INT_THR/CMD_THR_REG */ +#define PESQI_TXTHR_MASK 0x1f +#define PESQI_TXTHR_SHIFT 8 +#define PESQI_RXTHR_MASK 0x1f +#define PESQI_RXTHR_SHIFT 0 + +/* PESQI_INT_EN/INT_STAT/INT_SIG_EN_REG */ +#define PESQI_TXEMPTY BIT(0) +#define PESQI_TXFULL BIT(1) +#define PESQI_TXTHRBIT(2) +#define PESQI_RXEMPTY BIT(3) +#define PESQI_RXFULL BIT(4) +#define PESQI_RXTHR
Re: [PATCH v2 1/2] dt/bindings/usb: Add bindings for PIC32 MUSB driver.
On 04/11/2016 08:40 PM, Rob Herring wrote:
> On Thu, Apr 07, 2016 at 06:02:59PM +0530, Purna Chandra Mandal wrote:
>> Document devicetree binding for the USB controller
>> and USB Phy found on Microchip PIC32 class devices.
>>
>> Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
>>
>> ---
>>
>> Changes in v2: None
>>
>> .../bindings/usb/microchip,pic32-musb.txt | 67
>> ++
>> 1 file changed, 67 insertions(+)
>> create mode 100644
>> Documentation/devicetree/bindings/usb/microchip,pic32-musb.txt
>>
>> diff --git a/Documentation/devicetree/bindings/usb/microchip,pic32-musb.txt
>> b/Documentation/devicetree/bindings/usb/microchip,pic32-musb.txt
>> new file mode 100644
>> index 000..e1cec9d
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/usb/microchip,pic32-musb.txt
>> @@ -0,0 +1,67 @@
>> +Microchip PIC32 MUSB DRC/OTG controller
>> +---
>> +
>> +Required properties:
>> + - compatible : should be "microchip,pic32mzda-usb".
>> + - reg : offset and length of "MUSB Core Registers" and
>> + "USB Clock & Reset Registers".
>> + - reg-names: should be "mc", and "usbcr" in order
>> + - clocks : clock specifier for the musb controller clock
>> + - clock-names : should be "usb_clk"
>> + - interrupts : interrupt number for MUSB Core General interrupt
>> + and DMA interrupt
>> + - interrupt-names : must be "mc" and "dma" in order.
>> + - phys : phy specifier for the otg phy.
>> + - dr_mode : should be one of "host", "peripheral" or "otg".
>> + - mentor,multipoint: Should be "1" indicating the musb controller supports
>> + multipoint. This is MUSB configuration-specific
>> setting.
>> + - mentor,num-eps : Specifies the number of endpoints. This is also a
>> + MUSB configuration-specific setting. Should be set to
>> "8".
>> + - mentor,ram-bits : Specifies the ram address size. Should be set to "11".
>> + - mentor,power : Should be "500". This signifies the controller can
>> supply
>> + up to 500mA when operating in host mode.
>> + - phys : phandle of the USB phy.
>> + - usb_overcurrent : phandle to MUSB over-current note. It should have
>> + interrupt number for over-current detection logic.
> This node is only an interrupt? Then you should use interrupts-extended
> and make this interrupt the 3rd one. interrupts-extended will let you
> have different interrupt parents for each irq.
Will use 'interrupts-extended' instead.
>> +
>> +Optional properties:
>> + - microchip,fifo-mode: Specifies layout of internal SRAM for end-point
>> fifos.
>> +Should be 0 (default) or 1.
> Make this a boolean.
ack.
>> +
>> +Example:
>> +aliases {
>> +usb1 =
>> +phy1 = _phy;
>> +};
>> +
>> +usb1: hsusb1_core@1f8e3000 {
>> +compatible = "microchip,pic32mzda-usb";
>> +reg = <0x1f8e3000 0x1000>,
>> + <0x1f884000 0x1000>;
>> +reg-names = "mc", "usbcr";
>> +interrupts = <132 IRQ_TYPE_EDGE_RISING>,
>> + <133 IRQ_TYPE_LEVEL_HIGH>;
>> +interrupt-names = "mc", "dma";
>> +dr_mode = "host";
>> +mentor,multipoint = <1>;
>> +mentor,num-eps = <8>;
>> +mentor,ram-bits = <11>;
>> +mentor,power = <500>;
>> +phys = <_phy>;
>> +clocks = < PB5CLK>;
>> +clock-names = "usb_clk";
>> +usb_overcurrent = <_overcurrent>;
>> +};
>> +
>> +usb1_phy: hsusb1_phy@1f8e4000 {
>> +compatible = "usb-nop-xceiv";
>> +reg = <0x1f8e4000 0x1000>;
>> +clocks = < UPLLCLK>;
>> +clock-names = "main_clk";
>> +clock-frequency = <2400>;
>> +};
>> +
>> +usb1_overcurrent: hsusb1_oc@0 {
>> +interrupt-parent = <>;
>> +interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
>> +};
>> --
>> 1.8.3.1
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe devicetree" in
>> the body of a message to majord...@vger.kernel.org
>> More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 1/2] dt/bindings/usb: Add bindings for PIC32 MUSB driver.
On 04/11/2016 08:40 PM, Rob Herring wrote:
> On Thu, Apr 07, 2016 at 06:02:59PM +0530, Purna Chandra Mandal wrote:
>> Document devicetree binding for the USB controller
>> and USB Phy found on Microchip PIC32 class devices.
>>
>> Signed-off-by: Purna Chandra Mandal
>>
>> ---
>>
>> Changes in v2: None
>>
>> .../bindings/usb/microchip,pic32-musb.txt | 67
>> ++
>> 1 file changed, 67 insertions(+)
>> create mode 100644
>> Documentation/devicetree/bindings/usb/microchip,pic32-musb.txt
>>
>> diff --git a/Documentation/devicetree/bindings/usb/microchip,pic32-musb.txt
>> b/Documentation/devicetree/bindings/usb/microchip,pic32-musb.txt
>> new file mode 100644
>> index 000..e1cec9d
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/usb/microchip,pic32-musb.txt
>> @@ -0,0 +1,67 @@
>> +Microchip PIC32 MUSB DRC/OTG controller
>> +---
>> +
>> +Required properties:
>> + - compatible : should be "microchip,pic32mzda-usb".
>> + - reg : offset and length of "MUSB Core Registers" and
>> + "USB Clock & Reset Registers".
>> + - reg-names: should be "mc", and "usbcr" in order
>> + - clocks : clock specifier for the musb controller clock
>> + - clock-names : should be "usb_clk"
>> + - interrupts : interrupt number for MUSB Core General interrupt
>> + and DMA interrupt
>> + - interrupt-names : must be "mc" and "dma" in order.
>> + - phys : phy specifier for the otg phy.
>> + - dr_mode : should be one of "host", "peripheral" or "otg".
>> + - mentor,multipoint: Should be "1" indicating the musb controller supports
>> + multipoint. This is MUSB configuration-specific
>> setting.
>> + - mentor,num-eps : Specifies the number of endpoints. This is also a
>> + MUSB configuration-specific setting. Should be set to
>> "8".
>> + - mentor,ram-bits : Specifies the ram address size. Should be set to "11".
>> + - mentor,power : Should be "500". This signifies the controller can
>> supply
>> + up to 500mA when operating in host mode.
>> + - phys : phandle of the USB phy.
>> + - usb_overcurrent : phandle to MUSB over-current note. It should have
>> + interrupt number for over-current detection logic.
> This node is only an interrupt? Then you should use interrupts-extended
> and make this interrupt the 3rd one. interrupts-extended will let you
> have different interrupt parents for each irq.
Will use 'interrupts-extended' instead.
>> +
>> +Optional properties:
>> + - microchip,fifo-mode: Specifies layout of internal SRAM for end-point
>> fifos.
>> +Should be 0 (default) or 1.
> Make this a boolean.
ack.
>> +
>> +Example:
>> +aliases {
>> +usb1 =
>> +phy1 = _phy;
>> +};
>> +
>> +usb1: hsusb1_core@1f8e3000 {
>> +compatible = "microchip,pic32mzda-usb";
>> +reg = <0x1f8e3000 0x1000>,
>> + <0x1f884000 0x1000>;
>> +reg-names = "mc", "usbcr";
>> +interrupts = <132 IRQ_TYPE_EDGE_RISING>,
>> + <133 IRQ_TYPE_LEVEL_HIGH>;
>> +interrupt-names = "mc", "dma";
>> +dr_mode = "host";
>> +mentor,multipoint = <1>;
>> +mentor,num-eps = <8>;
>> +mentor,ram-bits = <11>;
>> +mentor,power = <500>;
>> +phys = <_phy>;
>> +clocks = < PB5CLK>;
>> +clock-names = "usb_clk";
>> +usb_overcurrent = <_overcurrent>;
>> +};
>> +
>> +usb1_phy: hsusb1_phy@1f8e4000 {
>> +compatible = "usb-nop-xceiv";
>> +reg = <0x1f8e4000 0x1000>;
>> +clocks = < UPLLCLK>;
>> +clock-names = "main_clk";
>> +clock-frequency = <2400>;
>> +};
>> +
>> +usb1_overcurrent: hsusb1_oc@0 {
>> +interrupt-parent = <>;
>> +interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
>> +};
>> --
>> 1.8.3.1
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe devicetree" in
>> the body of a message to majord...@vger.kernel.org
>> More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 1/2] dt/bindings/usb: Add bindings for PIC32 MUSB driver.
On 04/07/2016 07:04 PM, Sergei Shtylyov wrote: > On 4/7/2016 3:32 PM, Purna Chandra Mandal wrote: > >> Document devicetree binding for the USB controller >> and USB Phy found on Microchip PIC32 class devices. >> >> Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com> >> >> --- >> >> Changes in v2: None >> >> .../bindings/usb/microchip,pic32-musb.txt | 67 >> ++ >> 1 file changed, 67 insertions(+) >> create mode 100644 >> Documentation/devicetree/bindings/usb/microchip,pic32-musb.txt >> >> diff --git a/Documentation/devicetree/bindings/usb/microchip,pic32-musb.txt >> b/Documentation/devicetree/bindings/usb/microchip,pic32-musb.txt >> new file mode 100644 >> index 000..e1cec9d >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/usb/microchip,pic32-musb.txt >> @@ -0,0 +1,67 @@ >> +Microchip PIC32 MUSB DRC/OTG controller >> +--- >> + >> +Required properties: >> + - compatible : should be "microchip,pic32mzda-usb". >> + - reg : offset and length of "MUSB Core Registers" and >> + "USB Clock & Reset Registers". >> + - reg-names: should be "mc", and "usbcr" in order >> + - clocks : clock specifier for the musb controller clock >> + - clock-names : should be "usb_clk" >> + - interrupts : interrupt number for MUSB Core General interrupt >> + and DMA interrupt >> + - interrupt-names : must be "mc" and "dma" in order. >> + - phys : phy specifier for the otg phy. >> + - dr_mode : should be one of "host", "peripheral" or "otg". >> + - mentor,multipoint: Should be "1" indicating the musb controller supports >> + multipoint. This is MUSB configuration-specific >> setting. >> + - mentor,num-eps : Specifies the number of endpoints. This is also a >> + MUSB configuration-specific setting. Should be set to >> "8". >> + - mentor,ram-bits : Specifies the ram address size. Should be set to "11". >> + - mentor,power : Should be "500". This signifies the controller can >> supply >> + up to 500mA when operating in host mode. >> + - phys : phandle of the USB phy. > >Just noticed that "phys" is described twice. :-/ > Noted. Thanks. :) > MBR, Sergei >
Re: [PATCH v2 1/2] dt/bindings/usb: Add bindings for PIC32 MUSB driver.
On 04/07/2016 07:04 PM, Sergei Shtylyov wrote: > On 4/7/2016 3:32 PM, Purna Chandra Mandal wrote: > >> Document devicetree binding for the USB controller >> and USB Phy found on Microchip PIC32 class devices. >> >> Signed-off-by: Purna Chandra Mandal >> >> --- >> >> Changes in v2: None >> >> .../bindings/usb/microchip,pic32-musb.txt | 67 >> ++ >> 1 file changed, 67 insertions(+) >> create mode 100644 >> Documentation/devicetree/bindings/usb/microchip,pic32-musb.txt >> >> diff --git a/Documentation/devicetree/bindings/usb/microchip,pic32-musb.txt >> b/Documentation/devicetree/bindings/usb/microchip,pic32-musb.txt >> new file mode 100644 >> index 000..e1cec9d >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/usb/microchip,pic32-musb.txt >> @@ -0,0 +1,67 @@ >> +Microchip PIC32 MUSB DRC/OTG controller >> +--- >> + >> +Required properties: >> + - compatible : should be "microchip,pic32mzda-usb". >> + - reg : offset and length of "MUSB Core Registers" and >> + "USB Clock & Reset Registers". >> + - reg-names: should be "mc", and "usbcr" in order >> + - clocks : clock specifier for the musb controller clock >> + - clock-names : should be "usb_clk" >> + - interrupts : interrupt number for MUSB Core General interrupt >> + and DMA interrupt >> + - interrupt-names : must be "mc" and "dma" in order. >> + - phys : phy specifier for the otg phy. >> + - dr_mode : should be one of "host", "peripheral" or "otg". >> + - mentor,multipoint: Should be "1" indicating the musb controller supports >> + multipoint. This is MUSB configuration-specific >> setting. >> + - mentor,num-eps : Specifies the number of endpoints. This is also a >> + MUSB configuration-specific setting. Should be set to >> "8". >> + - mentor,ram-bits : Specifies the ram address size. Should be set to "11". >> + - mentor,power : Should be "500". This signifies the controller can >> supply >> + up to 500mA when operating in host mode. >> + - phys : phandle of the USB phy. > >Just noticed that "phys" is described twice. :-/ > Noted. Thanks. :) > MBR, Sergei >
Re: [PATCH v1 1/2] dt/bindings/usb: Add bindings for PIC32 MUSB driver.
On 04/07/2016 06:42 PM, Sergei Shtylyov wrote: > On 4/7/2016 4:02 PM, Purna Chandra Mandal wrote: > >>>> Document devicetree binding for the USB controller >>> >>> Device tree. >>> >> ack. >> >>>> and USB Phy found on Microchip PIC32 class devices. >>> >>> PHY. >>> >> ack. >> >>>> Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com> >>>> >>>> --- >>>> >>>>.../bindings/usb/microchip,pic32-musb.txt | 67 >>>> ++ >>>>1 file changed, 67 insertions(+) >>>>create mode 100644 >>>> Documentation/devicetree/bindings/usb/microchip,pic32-musb.txt >>>> >>>> diff --git >>>> a/Documentation/devicetree/bindings/usb/microchip,pic32-musb.txt >>>> b/Documentation/devicetree/bindings/usb/microchip,pic32-musb.txt >>>> new file mode 100644 >>>> index 000..e1cec9d >>>> --- /dev/null >>>> +++ b/Documentation/devicetree/bindings/usb/microchip,pic32-musb.txt >>>> @@ -0,0 +1,67 @@ >>>> +Microchip PIC32 MUSB DRC/OTG controller >>>> +--- >>>> + >>>> +Required properties: >>>> + - compatible : should be "microchip,pic32mzda-usb". >>>> + - reg : offset and length of "MUSB Core Registers" and >>>> + "USB Clock & Reset Registers". >>>> + - reg-names: should be "mc", and "usbcr" in order >>>> + - clocks : clock specifier for the musb controller clock >>>> + - clock-names : should be "usb_clk" >>>> + - interrupts : interrupt number for MUSB Core General interrupt >>>> + and DMA interrupt >>>> + - interrupt-names : must be "mc" and "dma" in order. >>>> + - phys : phy specifier for the otg phy. >>>> + - dr_mode : should be one of "host", "peripheral" or "otg". >>>> + - mentor,multipoint: Should be "1" indicating the musb controller >>>> supports >>>> + multipoint. This is MUSB configuration-specific >>>> setting. >>>> + - mentor,num-eps : Specifies the number of endpoints. This is also a >>>> + MUSB configuration-specific setting. Should be set >>>> to "8". >>>> + - mentor,ram-bits : Specifies the ram address size. Should be set to >>>> "11". >>>> + - mentor,power : Should be "500". This signifies the controller can >>>> supply >>>> + up to 500mA when operating in host mode. >>> >>> No, these "nentor" prefixed parameters must be determined from the >>> "compatible" prop. >>> >> Prefix "mentor" here is used to signify configuration of the MUSB controller >> IP, not >> specifics of the chip or glue logic. > >I know. > >> Please suggest if replacing with "microchip" makes it better. > >No, nothing of that sort. These parameters are probably fixed for the said > PIC32 implementation? If so, they shouldn't appear as the node props but > should instead be hard-coded in the glue layer. Don't look at the OMAP glues, > they are a bad example. ack. Will hard code. > >>>> + - phys : phandle of the USB phy. > >"phys" are reserved for use by the drivers/phy/, while your PHY seems to > be controlled by drivers/usb/phy/. Please rename this property to "usb-phy". > Will rename. >>>> + interrupt number for over-current detection logic. >>>> + >>>> +Optional properties: >>>> + - microchip,fifo-mode: Specifies layout of internal SRAM for end-point >>>> fifos. >>>> +Should be 0 (default) or 1. > >Probably would be better as a boolean prop... This is software defined configuration of SRAM layout. In future, we might add more variants depending on use-cases to extract better performance. Will prefer to keep it as integer property. And update description accordingly; like "Specifies layout of internal SRAM for end-point fifos. Defaults 0." > > [...] > > MBR, Sergei > Thanks, Purna
Re: [PATCH v1 1/2] dt/bindings/usb: Add bindings for PIC32 MUSB driver.
On 04/07/2016 06:42 PM, Sergei Shtylyov wrote: > On 4/7/2016 4:02 PM, Purna Chandra Mandal wrote: > >>>> Document devicetree binding for the USB controller >>> >>> Device tree. >>> >> ack. >> >>>> and USB Phy found on Microchip PIC32 class devices. >>> >>> PHY. >>> >> ack. >> >>>> Signed-off-by: Purna Chandra Mandal >>>> >>>> --- >>>> >>>>.../bindings/usb/microchip,pic32-musb.txt | 67 >>>> ++ >>>>1 file changed, 67 insertions(+) >>>>create mode 100644 >>>> Documentation/devicetree/bindings/usb/microchip,pic32-musb.txt >>>> >>>> diff --git >>>> a/Documentation/devicetree/bindings/usb/microchip,pic32-musb.txt >>>> b/Documentation/devicetree/bindings/usb/microchip,pic32-musb.txt >>>> new file mode 100644 >>>> index 000..e1cec9d >>>> --- /dev/null >>>> +++ b/Documentation/devicetree/bindings/usb/microchip,pic32-musb.txt >>>> @@ -0,0 +1,67 @@ >>>> +Microchip PIC32 MUSB DRC/OTG controller >>>> +--- >>>> + >>>> +Required properties: >>>> + - compatible : should be "microchip,pic32mzda-usb". >>>> + - reg : offset and length of "MUSB Core Registers" and >>>> + "USB Clock & Reset Registers". >>>> + - reg-names: should be "mc", and "usbcr" in order >>>> + - clocks : clock specifier for the musb controller clock >>>> + - clock-names : should be "usb_clk" >>>> + - interrupts : interrupt number for MUSB Core General interrupt >>>> + and DMA interrupt >>>> + - interrupt-names : must be "mc" and "dma" in order. >>>> + - phys : phy specifier for the otg phy. >>>> + - dr_mode : should be one of "host", "peripheral" or "otg". >>>> + - mentor,multipoint: Should be "1" indicating the musb controller >>>> supports >>>> + multipoint. This is MUSB configuration-specific >>>> setting. >>>> + - mentor,num-eps : Specifies the number of endpoints. This is also a >>>> + MUSB configuration-specific setting. Should be set >>>> to "8". >>>> + - mentor,ram-bits : Specifies the ram address size. Should be set to >>>> "11". >>>> + - mentor,power : Should be "500". This signifies the controller can >>>> supply >>>> + up to 500mA when operating in host mode. >>> >>> No, these "nentor" prefixed parameters must be determined from the >>> "compatible" prop. >>> >> Prefix "mentor" here is used to signify configuration of the MUSB controller >> IP, not >> specifics of the chip or glue logic. > >I know. > >> Please suggest if replacing with "microchip" makes it better. > >No, nothing of that sort. These parameters are probably fixed for the said > PIC32 implementation? If so, they shouldn't appear as the node props but > should instead be hard-coded in the glue layer. Don't look at the OMAP glues, > they are a bad example. ack. Will hard code. > >>>> + - phys : phandle of the USB phy. > >"phys" are reserved for use by the drivers/phy/, while your PHY seems to > be controlled by drivers/usb/phy/. Please rename this property to "usb-phy". > Will rename. >>>> + interrupt number for over-current detection logic. >>>> + >>>> +Optional properties: >>>> + - microchip,fifo-mode: Specifies layout of internal SRAM for end-point >>>> fifos. >>>> +Should be 0 (default) or 1. > >Probably would be better as a boolean prop... This is software defined configuration of SRAM layout. In future, we might add more variants depending on use-cases to extract better performance. Will prefer to keep it as integer property. And update description accordingly; like "Specifies layout of internal SRAM for end-point fifos. Defaults 0." > > [...] > > MBR, Sergei > Thanks, Purna
Re: [PATCH v1 1/2] dt/bindings/usb: Add bindings for PIC32 MUSB driver.
On 04/07/2016 06:23 PM, Sergei Shtylyov wrote:
> Hello.
>
> On 4/7/2016 2:16 PM, Purna Chandra Mandal wrote:
>
>> Document devicetree binding for the USB controller
>
>Device tree.
>
ack.
>> and USB Phy found on Microchip PIC32 class devices.
>
> PHY.
>
ack.
>> Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
>>
>> ---
>>
>> .../bindings/usb/microchip,pic32-musb.txt | 67
>> ++
>> 1 file changed, 67 insertions(+)
>> create mode 100644
>> Documentation/devicetree/bindings/usb/microchip,pic32-musb.txt
>>
>> diff --git a/Documentation/devicetree/bindings/usb/microchip,pic32-musb.txt
>> b/Documentation/devicetree/bindings/usb/microchip,pic32-musb.txt
>> new file mode 100644
>> index 000..e1cec9d
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/usb/microchip,pic32-musb.txt
>> @@ -0,0 +1,67 @@
>> +Microchip PIC32 MUSB DRC/OTG controller
>> +---
>> +
>> +Required properties:
>> + - compatible : should be "microchip,pic32mzda-usb".
>> + - reg : offset and length of "MUSB Core Registers" and
>> + "USB Clock & Reset Registers".
>> + - reg-names: should be "mc", and "usbcr" in order
>> + - clocks : clock specifier for the musb controller clock
>> + - clock-names : should be "usb_clk"
>> + - interrupts : interrupt number for MUSB Core General interrupt
>> + and DMA interrupt
>> + - interrupt-names : must be "mc" and "dma" in order.
>> + - phys : phy specifier for the otg phy.
>> + - dr_mode : should be one of "host", "peripheral" or "otg".
>> + - mentor,multipoint: Should be "1" indicating the musb controller supports
>> + multipoint. This is MUSB configuration-specific
>> setting.
>> + - mentor,num-eps : Specifies the number of endpoints. This is also a
>> + MUSB configuration-specific setting. Should be set to
>> "8".
>> + - mentor,ram-bits : Specifies the ram address size. Should be set to "11".
>> + - mentor,power : Should be "500". This signifies the controller can
>> supply
>> + up to 500mA when operating in host mode.
>
>No, these "nentor" prefixed parameters must be determined from the
> "compatible" prop.
>
Prefix "mentor" here is used to signify configuration of the MUSB controller
IP, not
specifics of the chip or glue logic.
Please suggest if replacing with "microchip" makes it better.
>> + - phys : phandle of the USB phy.
>> + - usb_overcurrent : phandle to MUSB over-current note. It should have
>
>s/note/node/? Also,
>Also, hyphens are preferred to underscores in the device trees.
>
ack. Will use hyphen.
>> + interrupt number for over-current detection logic.
>> +
>> +Optional properties:
>> + - microchip,fifo-mode: Specifies layout of internal SRAM for end-point
>> fifos.
>> +Should be 0 (default) or 1.
>> +
>> +Example:
>> +aliases {
>> +usb1 =
>> +phy1 = _phy;
>> +};
>> +
>> +usb1: hsusb1_core@1f8e3000 {
>
>The ePAPR standard tells us to use the generic names, not chip specific,
> the name standardized in this case is "usb@...".
>
ack.
>> +compatible = "microchip,pic32mzda-usb";
>> +reg = <0x1f8e3000 0x1000>,
>> + <0x1f884000 0x1000>;
>> +reg-names = "mc", "usbcr";
>> +interrupts = <132 IRQ_TYPE_EDGE_RISING>,
>> + <133 IRQ_TYPE_LEVEL_HIGH>;
>> +interrupt-names = "mc", "dma";
>> +dr_mode = "host";
>> +mentor,multipoint = <1>;
>> +mentor,num-eps = <8>;
>> +mentor,ram-bits = <11>;
>> +mentor,power = <500>;
>> +phys = <_phy>;
>> +clocks = < PB5CLK>;
>> +clock-names = "usb_clk";
>> +usb_overcurrent = <_overcurrent>;
>> +};
>> +
>> +usb1_phy: hsusb1_phy@1f8e4000 {
>
>"usb-phy@..."
>
ack.
>> +compatible = "usb-nop-xceiv";
>> +reg = <0x1f8e4000 0x1000>;
>> +clocks = < UPLLCLK>;
>> +clock-names = "main_clk";
>> +clock-frequency = <2400>;
>> +};
>> +
>> +usb1_overcurrent: hsusb1_oc@0 {
>
>"usb-overcurrent@...", perhaps?
>
ack.
>> +interrupt-parent = <>;
>> +interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
>> +};
>
> MBR, Sergei
>
Re: [PATCH v1 1/2] dt/bindings/usb: Add bindings for PIC32 MUSB driver.
On 04/07/2016 06:23 PM, Sergei Shtylyov wrote:
> Hello.
>
> On 4/7/2016 2:16 PM, Purna Chandra Mandal wrote:
>
>> Document devicetree binding for the USB controller
>
>Device tree.
>
ack.
>> and USB Phy found on Microchip PIC32 class devices.
>
> PHY.
>
ack.
>> Signed-off-by: Purna Chandra Mandal
>>
>> ---
>>
>> .../bindings/usb/microchip,pic32-musb.txt | 67
>> ++
>> 1 file changed, 67 insertions(+)
>> create mode 100644
>> Documentation/devicetree/bindings/usb/microchip,pic32-musb.txt
>>
>> diff --git a/Documentation/devicetree/bindings/usb/microchip,pic32-musb.txt
>> b/Documentation/devicetree/bindings/usb/microchip,pic32-musb.txt
>> new file mode 100644
>> index 000..e1cec9d
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/usb/microchip,pic32-musb.txt
>> @@ -0,0 +1,67 @@
>> +Microchip PIC32 MUSB DRC/OTG controller
>> +---
>> +
>> +Required properties:
>> + - compatible : should be "microchip,pic32mzda-usb".
>> + - reg : offset and length of "MUSB Core Registers" and
>> + "USB Clock & Reset Registers".
>> + - reg-names: should be "mc", and "usbcr" in order
>> + - clocks : clock specifier for the musb controller clock
>> + - clock-names : should be "usb_clk"
>> + - interrupts : interrupt number for MUSB Core General interrupt
>> + and DMA interrupt
>> + - interrupt-names : must be "mc" and "dma" in order.
>> + - phys : phy specifier for the otg phy.
>> + - dr_mode : should be one of "host", "peripheral" or "otg".
>> + - mentor,multipoint: Should be "1" indicating the musb controller supports
>> + multipoint. This is MUSB configuration-specific
>> setting.
>> + - mentor,num-eps : Specifies the number of endpoints. This is also a
>> + MUSB configuration-specific setting. Should be set to
>> "8".
>> + - mentor,ram-bits : Specifies the ram address size. Should be set to "11".
>> + - mentor,power : Should be "500". This signifies the controller can
>> supply
>> + up to 500mA when operating in host mode.
>
>No, these "nentor" prefixed parameters must be determined from the
> "compatible" prop.
>
Prefix "mentor" here is used to signify configuration of the MUSB controller
IP, not
specifics of the chip or glue logic.
Please suggest if replacing with "microchip" makes it better.
>> + - phys : phandle of the USB phy.
>> + - usb_overcurrent : phandle to MUSB over-current note. It should have
>
>s/note/node/? Also,
>Also, hyphens are preferred to underscores in the device trees.
>
ack. Will use hyphen.
>> + interrupt number for over-current detection logic.
>> +
>> +Optional properties:
>> + - microchip,fifo-mode: Specifies layout of internal SRAM for end-point
>> fifos.
>> +Should be 0 (default) or 1.
>> +
>> +Example:
>> +aliases {
>> +usb1 =
>> +phy1 = _phy;
>> +};
>> +
>> +usb1: hsusb1_core@1f8e3000 {
>
>The ePAPR standard tells us to use the generic names, not chip specific,
> the name standardized in this case is "usb@...".
>
ack.
>> +compatible = "microchip,pic32mzda-usb";
>> +reg = <0x1f8e3000 0x1000>,
>> + <0x1f884000 0x1000>;
>> +reg-names = "mc", "usbcr";
>> +interrupts = <132 IRQ_TYPE_EDGE_RISING>,
>> + <133 IRQ_TYPE_LEVEL_HIGH>;
>> +interrupt-names = "mc", "dma";
>> +dr_mode = "host";
>> +mentor,multipoint = <1>;
>> +mentor,num-eps = <8>;
>> +mentor,ram-bits = <11>;
>> +mentor,power = <500>;
>> +phys = <_phy>;
>> +clocks = < PB5CLK>;
>> +clock-names = "usb_clk";
>> +usb_overcurrent = <_overcurrent>;
>> +};
>> +
>> +usb1_phy: hsusb1_phy@1f8e4000 {
>
>"usb-phy@..."
>
ack.
>> +compatible = "usb-nop-xceiv";
>> +reg = <0x1f8e4000 0x1000>;
>> +clocks = < UPLLCLK>;
>> +clock-names = "main_clk";
>> +clock-frequency = <2400>;
>> +};
>> +
>> +usb1_overcurrent: hsusb1_oc@0 {
>
>"usb-overcurrent@...", perhaps?
>
ack.
>> +interrupt-parent = <>;
>> +interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
>> +};
>
> MBR, Sergei
>
Re: [PATCH v2 2/2] usb: musb: pic32: Add USB DRC driver for PIC32 OTG controller.
On 04/07/2016 06:09 PM, Felipe Balbi wrote: > Purna Chandra Mandal <purna.man...@microchip.com> writes: >> From: Cristian Birsan <cristian.bir...@microchip.com> >> >> This driver adds support of PIC32 MUSB OTG controller as >> dual role device. It implements platform specific glue to >> reuse musb core. >> >> Signed-off-by: Cristian Birsan <cristian.bir...@microchip.com> >> Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com> >> >> In-reply-to: 460027775-20729-2-git-send-email-purna.man...@microchip.com >> >> --- >> >> Changes in v2: >> - fix i386 build >> - fix indentation >> >> drivers/usb/musb/Kconfig | 9 +- >> drivers/usb/musb/Makefile | 1 + >> drivers/usb/musb/pic32.c | 608 >> ++ >> 3 files changed, 617 insertions(+), 1 deletion(-) >> create mode 100644 drivers/usb/musb/pic32.c >> >> diff --git a/drivers/usb/musb/Kconfig b/drivers/usb/musb/Kconfig >> index 886526b..1970c1e 100644 >> --- a/drivers/usb/musb/Kconfig >> +++ b/drivers/usb/musb/Kconfig >> @@ -112,6 +112,13 @@ config USB_MUSB_BLACKFIN >> depends on (BF54x && !BF544) || (BF52x && ! BF522 && !BF523) >> depends on NOP_USB_XCEIV >> >> +config USB_MUSB_PIC32 >> +tristate "Microchip PIC32 USB platforms" >> +depends on MACH_PIC32 > no, we like to build stuff on other arches, this should be: > > depends on MACH_PIC32 || COMPILE_TEST > > and you should *really* fix the build error, not work around it. This driver is for PIC32MZDA platforms which are powered by MIPS 14Kec CPU. The offending API 'readsl()' is implemented by MIPS arch (in arch/mips/include/asm/io.h), but not by i386 arch. IMO compiling for i386 is not required.
Re: [PATCH v2 2/2] usb: musb: pic32: Add USB DRC driver for PIC32 OTG controller.
On 04/07/2016 06:09 PM, Felipe Balbi wrote: > Purna Chandra Mandal writes: >> From: Cristian Birsan >> >> This driver adds support of PIC32 MUSB OTG controller as >> dual role device. It implements platform specific glue to >> reuse musb core. >> >> Signed-off-by: Cristian Birsan >> Signed-off-by: Purna Chandra Mandal >> >> In-reply-to: 460027775-20729-2-git-send-email-purna.man...@microchip.com >> >> --- >> >> Changes in v2: >> - fix i386 build >> - fix indentation >> >> drivers/usb/musb/Kconfig | 9 +- >> drivers/usb/musb/Makefile | 1 + >> drivers/usb/musb/pic32.c | 608 >> ++ >> 3 files changed, 617 insertions(+), 1 deletion(-) >> create mode 100644 drivers/usb/musb/pic32.c >> >> diff --git a/drivers/usb/musb/Kconfig b/drivers/usb/musb/Kconfig >> index 886526b..1970c1e 100644 >> --- a/drivers/usb/musb/Kconfig >> +++ b/drivers/usb/musb/Kconfig >> @@ -112,6 +112,13 @@ config USB_MUSB_BLACKFIN >> depends on (BF54x && !BF544) || (BF52x && ! BF522 && !BF523) >> depends on NOP_USB_XCEIV >> >> +config USB_MUSB_PIC32 >> +tristate "Microchip PIC32 USB platforms" >> +depends on MACH_PIC32 > no, we like to build stuff on other arches, this should be: > > depends on MACH_PIC32 || COMPILE_TEST > > and you should *really* fix the build error, not work around it. This driver is for PIC32MZDA platforms which are powered by MIPS 14Kec CPU. The offending API 'readsl()' is implemented by MIPS arch (in arch/mips/include/asm/io.h), but not by i386 arch. IMO compiling for i386 is not required.
[PATCH v2 2/2] usb: musb: pic32: Add USB DRC driver for PIC32 OTG controller.
From: Cristian Birsan <cristian.bir...@microchip.com>
This driver adds support of PIC32 MUSB OTG controller as
dual role device. It implements platform specific glue to
reuse musb core.
Signed-off-by: Cristian Birsan <cristian.bir...@microchip.com>
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
In-reply-to: 460027775-20729-2-git-send-email-purna.man...@microchip.com
---
Changes in v2:
- fix i386 build
- fix indentation
drivers/usb/musb/Kconfig | 9 +-
drivers/usb/musb/Makefile | 1 +
drivers/usb/musb/pic32.c | 608 ++
3 files changed, 617 insertions(+), 1 deletion(-)
create mode 100644 drivers/usb/musb/pic32.c
diff --git a/drivers/usb/musb/Kconfig b/drivers/usb/musb/Kconfig
index 886526b..1970c1e 100644
--- a/drivers/usb/musb/Kconfig
+++ b/drivers/usb/musb/Kconfig
@@ -112,6 +112,13 @@ config USB_MUSB_BLACKFIN
depends on (BF54x && !BF544) || (BF52x && ! BF522 && !BF523)
depends on NOP_USB_XCEIV
+config USB_MUSB_PIC32
+ tristate "Microchip PIC32 USB platforms"
+ depends on MACH_PIC32
+ depends on NOP_USB_XCEIV
+ help
+ Say y to enable PIC32 USB DRC controller support
+
config USB_MUSB_UX500
tristate "Ux500 platforms"
depends on ARCH_U8500 || COMPILE_TEST
@@ -149,7 +156,7 @@ config USB_UX500_DMA
config USB_INVENTRA_DMA
bool 'Inventra'
- depends on USB_MUSB_OMAP2PLUS || USB_MUSB_BLACKFIN
+ depends on USB_MUSB_OMAP2PLUS || USB_MUSB_BLACKFIN || USB_MUSB_PIC32
help
Enable DMA transfers using Mentor's engine.
diff --git a/drivers/usb/musb/Makefile b/drivers/usb/musb/Makefile
index f95befe..a38ebb7 100644
--- a/drivers/usb/musb/Makefile
+++ b/drivers/usb/musb/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_USB_MUSB_DA8XX) += da8xx.o
obj-$(CONFIG_USB_MUSB_BLACKFIN)+= blackfin.o
obj-$(CONFIG_USB_MUSB_UX500) += ux500.o
obj-$(CONFIG_USB_MUSB_JZ4740) += jz4740.o
+obj-$(CONFIG_USB_MUSB_PIC32) += pic32.o
obj-$(CONFIG_USB_MUSB_SUNXI) += sunxi.o
diff --git a/drivers/usb/musb/pic32.c b/drivers/usb/musb/pic32.c
new file mode 100644
index 000..be36236
--- /dev/null
+++ b/drivers/usb/musb/pic32.c
@@ -0,0 +1,608 @@
+/*
+ * Microchip PIC32 MUSB Dual-Role Controller "glue layer".
+ *
+ * Cristian Birsan <cristian.bir...@microchip.com>
+ * Purna Chandra Mandal <purna.man...@microchip.com>
+ * Copyright (C) 2015 Microchip Technology Inc. All rights reserved.
+ *
+ * Based on the am35x and dsps "glue layer" code.
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "musb_core.h"
+
+#define MUSB_SOFTRST 0x7f
+#define MUSB_SOFTRST_NRST BIT(0)
+#define MUSB_SOFTRST_NRSTX BIT(1)
+
+/* USB Clock & Reset Control */
+#define USBCRCON 0x0
+#define USBCRCON_USBWKUPENBIT(0) /* Enable remote wakeup interrupt */
+#define USBCRCON_USBRIE BIT(1) /* Enable Remote resume interrupt */
+#define USBCRCON_USBIEBIT(2) /* Enable USB General interrupt
*/
+#define USBCRCON_SENDMONEN BIT(3) /* Enable Session End VBUS monitoring
*/
+#define USBCRCON_BSVALMONENBIT(4) /* Enable B-Device VBUS monitoring */
+#define USBCRCON_ASVALMONENBIT(5) /* Enable A-Device VBUS monitoring */
+#define USBCRCON_VBUSMONEN BIT(6) /* Enable VBUS monitoring */
+#define USBCRCON_PHYIDEN BIT(7) /* Enabale USBPhy USBID monitoring */
+#define USBCRCON_USBIDVAL BIT(8) /* USBID override value */
+#define USBCRCON_USBIDOVENBIT(9) /* Enable USBID override */
+#define USBCRCON_USBWKUP BIT(24) /* Remote wakeup status */
+#define USBCRCON_USBRFBIT(25) /* USB Remote resume status */
+#define USBCRCON_USBIFBIT(26) /* USB General interrupt status
*/
+
+#define PIC32_TX_EP_MASK 0x /* EP0 + 15 Tx EPs */
+#define PIC32_RX_EP_MASK 0xfffe /* 15 Rx EPs */
+
+#define POLL_SECONDS 2
+
+struct pic32_musb {
+ void __iomem*cru;
+ struct clk *clk;
+ int oc_irq;
+ struct platform_device *platdev;
+ struct timer_list timer; /* otg_workaround timer */
+ unsigned long last_timer; /* last timer data for */
+};
+
+static irqretur
[PATCH v2 2/2] usb: musb: pic32: Add USB DRC driver for PIC32 OTG controller.
From: Cristian Birsan
This driver adds support of PIC32 MUSB OTG controller as
dual role device. It implements platform specific glue to
reuse musb core.
Signed-off-by: Cristian Birsan
Signed-off-by: Purna Chandra Mandal
In-reply-to: 460027775-20729-2-git-send-email-purna.man...@microchip.com
---
Changes in v2:
- fix i386 build
- fix indentation
drivers/usb/musb/Kconfig | 9 +-
drivers/usb/musb/Makefile | 1 +
drivers/usb/musb/pic32.c | 608 ++
3 files changed, 617 insertions(+), 1 deletion(-)
create mode 100644 drivers/usb/musb/pic32.c
diff --git a/drivers/usb/musb/Kconfig b/drivers/usb/musb/Kconfig
index 886526b..1970c1e 100644
--- a/drivers/usb/musb/Kconfig
+++ b/drivers/usb/musb/Kconfig
@@ -112,6 +112,13 @@ config USB_MUSB_BLACKFIN
depends on (BF54x && !BF544) || (BF52x && ! BF522 && !BF523)
depends on NOP_USB_XCEIV
+config USB_MUSB_PIC32
+ tristate "Microchip PIC32 USB platforms"
+ depends on MACH_PIC32
+ depends on NOP_USB_XCEIV
+ help
+ Say y to enable PIC32 USB DRC controller support
+
config USB_MUSB_UX500
tristate "Ux500 platforms"
depends on ARCH_U8500 || COMPILE_TEST
@@ -149,7 +156,7 @@ config USB_UX500_DMA
config USB_INVENTRA_DMA
bool 'Inventra'
- depends on USB_MUSB_OMAP2PLUS || USB_MUSB_BLACKFIN
+ depends on USB_MUSB_OMAP2PLUS || USB_MUSB_BLACKFIN || USB_MUSB_PIC32
help
Enable DMA transfers using Mentor's engine.
diff --git a/drivers/usb/musb/Makefile b/drivers/usb/musb/Makefile
index f95befe..a38ebb7 100644
--- a/drivers/usb/musb/Makefile
+++ b/drivers/usb/musb/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_USB_MUSB_DA8XX) += da8xx.o
obj-$(CONFIG_USB_MUSB_BLACKFIN)+= blackfin.o
obj-$(CONFIG_USB_MUSB_UX500) += ux500.o
obj-$(CONFIG_USB_MUSB_JZ4740) += jz4740.o
+obj-$(CONFIG_USB_MUSB_PIC32) += pic32.o
obj-$(CONFIG_USB_MUSB_SUNXI) += sunxi.o
diff --git a/drivers/usb/musb/pic32.c b/drivers/usb/musb/pic32.c
new file mode 100644
index 000..be36236
--- /dev/null
+++ b/drivers/usb/musb/pic32.c
@@ -0,0 +1,608 @@
+/*
+ * Microchip PIC32 MUSB Dual-Role Controller "glue layer".
+ *
+ * Cristian Birsan
+ * Purna Chandra Mandal
+ * Copyright (C) 2015 Microchip Technology Inc. All rights reserved.
+ *
+ * Based on the am35x and dsps "glue layer" code.
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "musb_core.h"
+
+#define MUSB_SOFTRST 0x7f
+#define MUSB_SOFTRST_NRST BIT(0)
+#define MUSB_SOFTRST_NRSTX BIT(1)
+
+/* USB Clock & Reset Control */
+#define USBCRCON 0x0
+#define USBCRCON_USBWKUPENBIT(0) /* Enable remote wakeup interrupt */
+#define USBCRCON_USBRIE BIT(1) /* Enable Remote resume interrupt */
+#define USBCRCON_USBIEBIT(2) /* Enable USB General interrupt
*/
+#define USBCRCON_SENDMONEN BIT(3) /* Enable Session End VBUS monitoring
*/
+#define USBCRCON_BSVALMONENBIT(4) /* Enable B-Device VBUS monitoring */
+#define USBCRCON_ASVALMONENBIT(5) /* Enable A-Device VBUS monitoring */
+#define USBCRCON_VBUSMONEN BIT(6) /* Enable VBUS monitoring */
+#define USBCRCON_PHYIDEN BIT(7) /* Enabale USBPhy USBID monitoring */
+#define USBCRCON_USBIDVAL BIT(8) /* USBID override value */
+#define USBCRCON_USBIDOVENBIT(9) /* Enable USBID override */
+#define USBCRCON_USBWKUP BIT(24) /* Remote wakeup status */
+#define USBCRCON_USBRFBIT(25) /* USB Remote resume status */
+#define USBCRCON_USBIFBIT(26) /* USB General interrupt status
*/
+
+#define PIC32_TX_EP_MASK 0x /* EP0 + 15 Tx EPs */
+#define PIC32_RX_EP_MASK 0xfffe /* 15 Rx EPs */
+
+#define POLL_SECONDS 2
+
+struct pic32_musb {
+ void __iomem*cru;
+ struct clk *clk;
+ int oc_irq;
+ struct platform_device *platdev;
+ struct timer_list timer; /* otg_workaround timer */
+ unsigned long last_timer; /* last timer data for */
+};
+
+static irqreturn_t pic32_over_current(int irq, void *d)
+{
+ struct device *dev = d;
+
+ dev_err(dev, "USB Host over-current detected !\n");
+
+ return IRQ_HANDLED;
+}
[PATCH v2 1/2] dt/bindings/usb: Add bindings for PIC32 MUSB driver.
Document devicetree binding for the USB controller
and USB Phy found on Microchip PIC32 class devices.
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
---
Changes in v2: None
.../bindings/usb/microchip,pic32-musb.txt | 67 ++
1 file changed, 67 insertions(+)
create mode 100644
Documentation/devicetree/bindings/usb/microchip,pic32-musb.txt
diff --git a/Documentation/devicetree/bindings/usb/microchip,pic32-musb.txt
b/Documentation/devicetree/bindings/usb/microchip,pic32-musb.txt
new file mode 100644
index 000..e1cec9d
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/microchip,pic32-musb.txt
@@ -0,0 +1,67 @@
+Microchip PIC32 MUSB DRC/OTG controller
+---
+
+Required properties:
+ - compatible : should be "microchip,pic32mzda-usb".
+ - reg : offset and length of "MUSB Core Registers" and
+ "USB Clock & Reset Registers".
+ - reg-names: should be "mc", and "usbcr" in order
+ - clocks : clock specifier for the musb controller clock
+ - clock-names : should be "usb_clk"
+ - interrupts : interrupt number for MUSB Core General interrupt
+ and DMA interrupt
+ - interrupt-names : must be "mc" and "dma" in order.
+ - phys : phy specifier for the otg phy.
+ - dr_mode : should be one of "host", "peripheral" or "otg".
+ - mentor,multipoint: Should be "1" indicating the musb controller supports
+ multipoint. This is MUSB configuration-specific setting.
+ - mentor,num-eps : Specifies the number of endpoints. This is also a
+ MUSB configuration-specific setting. Should be set to
"8".
+ - mentor,ram-bits : Specifies the ram address size. Should be set to "11".
+ - mentor,power : Should be "500". This signifies the controller can supply
+ up to 500mA when operating in host mode.
+ - phys : phandle of the USB phy.
+ - usb_overcurrent : phandle to MUSB over-current note. It should have
+ interrupt number for over-current detection logic.
+
+Optional properties:
+ - microchip,fifo-mode: Specifies layout of internal SRAM for end-point fifos.
+Should be 0 (default) or 1.
+
+Example:
+ aliases {
+ usb1 =
+ phy1 = _phy;
+ };
+
+ usb1: hsusb1_core@1f8e3000 {
+ compatible = "microchip,pic32mzda-usb";
+ reg = <0x1f8e3000 0x1000>,
+ <0x1f884000 0x1000>;
+ reg-names = "mc", "usbcr";
+ interrupts = <132 IRQ_TYPE_EDGE_RISING>,
+<133 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "mc", "dma";
+ dr_mode = "host";
+ mentor,multipoint = <1>;
+ mentor,num-eps = <8>;
+ mentor,ram-bits = <11>;
+ mentor,power = <500>;
+ phys = <_phy>;
+ clocks = < PB5CLK>;
+ clock-names = "usb_clk";
+ usb_overcurrent = <_overcurrent>;
+ };
+
+ usb1_phy: hsusb1_phy@1f8e4000 {
+ compatible = "usb-nop-xceiv";
+ reg = <0x1f8e4000 0x1000>;
+ clocks = < UPLLCLK>;
+ clock-names = "main_clk";
+ clock-frequency = <2400>;
+ };
+
+ usb1_overcurrent: hsusb1_oc@0 {
+ interrupt-parent = <>;
+ interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+ };
--
1.8.3.1
[PATCH v2 1/2] dt/bindings/usb: Add bindings for PIC32 MUSB driver.
Document devicetree binding for the USB controller
and USB Phy found on Microchip PIC32 class devices.
Signed-off-by: Purna Chandra Mandal
---
Changes in v2: None
.../bindings/usb/microchip,pic32-musb.txt | 67 ++
1 file changed, 67 insertions(+)
create mode 100644
Documentation/devicetree/bindings/usb/microchip,pic32-musb.txt
diff --git a/Documentation/devicetree/bindings/usb/microchip,pic32-musb.txt
b/Documentation/devicetree/bindings/usb/microchip,pic32-musb.txt
new file mode 100644
index 000..e1cec9d
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/microchip,pic32-musb.txt
@@ -0,0 +1,67 @@
+Microchip PIC32 MUSB DRC/OTG controller
+---
+
+Required properties:
+ - compatible : should be "microchip,pic32mzda-usb".
+ - reg : offset and length of "MUSB Core Registers" and
+ "USB Clock & Reset Registers".
+ - reg-names: should be "mc", and "usbcr" in order
+ - clocks : clock specifier for the musb controller clock
+ - clock-names : should be "usb_clk"
+ - interrupts : interrupt number for MUSB Core General interrupt
+ and DMA interrupt
+ - interrupt-names : must be "mc" and "dma" in order.
+ - phys : phy specifier for the otg phy.
+ - dr_mode : should be one of "host", "peripheral" or "otg".
+ - mentor,multipoint: Should be "1" indicating the musb controller supports
+ multipoint. This is MUSB configuration-specific setting.
+ - mentor,num-eps : Specifies the number of endpoints. This is also a
+ MUSB configuration-specific setting. Should be set to
"8".
+ - mentor,ram-bits : Specifies the ram address size. Should be set to "11".
+ - mentor,power : Should be "500". This signifies the controller can supply
+ up to 500mA when operating in host mode.
+ - phys : phandle of the USB phy.
+ - usb_overcurrent : phandle to MUSB over-current note. It should have
+ interrupt number for over-current detection logic.
+
+Optional properties:
+ - microchip,fifo-mode: Specifies layout of internal SRAM for end-point fifos.
+Should be 0 (default) or 1.
+
+Example:
+ aliases {
+ usb1 =
+ phy1 = _phy;
+ };
+
+ usb1: hsusb1_core@1f8e3000 {
+ compatible = "microchip,pic32mzda-usb";
+ reg = <0x1f8e3000 0x1000>,
+ <0x1f884000 0x1000>;
+ reg-names = "mc", "usbcr";
+ interrupts = <132 IRQ_TYPE_EDGE_RISING>,
+<133 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "mc", "dma";
+ dr_mode = "host";
+ mentor,multipoint = <1>;
+ mentor,num-eps = <8>;
+ mentor,ram-bits = <11>;
+ mentor,power = <500>;
+ phys = <_phy>;
+ clocks = < PB5CLK>;
+ clock-names = "usb_clk";
+ usb_overcurrent = <_overcurrent>;
+ };
+
+ usb1_phy: hsusb1_phy@1f8e4000 {
+ compatible = "usb-nop-xceiv";
+ reg = <0x1f8e4000 0x1000>;
+ clocks = < UPLLCLK>;
+ clock-names = "main_clk";
+ clock-frequency = <2400>;
+ };
+
+ usb1_overcurrent: hsusb1_oc@0 {
+ interrupt-parent = <>;
+ interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+ };
--
1.8.3.1
[PATCH v1 1/2] dt/bindings/usb: Add bindings for PIC32 MUSB driver.
Document devicetree binding for the USB controller
and USB Phy found on Microchip PIC32 class devices.
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
---
.../bindings/usb/microchip,pic32-musb.txt | 67 ++
1 file changed, 67 insertions(+)
create mode 100644
Documentation/devicetree/bindings/usb/microchip,pic32-musb.txt
diff --git a/Documentation/devicetree/bindings/usb/microchip,pic32-musb.txt
b/Documentation/devicetree/bindings/usb/microchip,pic32-musb.txt
new file mode 100644
index 000..e1cec9d
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/microchip,pic32-musb.txt
@@ -0,0 +1,67 @@
+Microchip PIC32 MUSB DRC/OTG controller
+---
+
+Required properties:
+ - compatible : should be "microchip,pic32mzda-usb".
+ - reg : offset and length of "MUSB Core Registers" and
+ "USB Clock & Reset Registers".
+ - reg-names: should be "mc", and "usbcr" in order
+ - clocks : clock specifier for the musb controller clock
+ - clock-names : should be "usb_clk"
+ - interrupts : interrupt number for MUSB Core General interrupt
+ and DMA interrupt
+ - interrupt-names : must be "mc" and "dma" in order.
+ - phys : phy specifier for the otg phy.
+ - dr_mode : should be one of "host", "peripheral" or "otg".
+ - mentor,multipoint: Should be "1" indicating the musb controller supports
+ multipoint. This is MUSB configuration-specific setting.
+ - mentor,num-eps : Specifies the number of endpoints. This is also a
+ MUSB configuration-specific setting. Should be set to
"8".
+ - mentor,ram-bits : Specifies the ram address size. Should be set to "11".
+ - mentor,power : Should be "500". This signifies the controller can supply
+ up to 500mA when operating in host mode.
+ - phys : phandle of the USB phy.
+ - usb_overcurrent : phandle to MUSB over-current note. It should have
+ interrupt number for over-current detection logic.
+
+Optional properties:
+ - microchip,fifo-mode: Specifies layout of internal SRAM for end-point fifos.
+Should be 0 (default) or 1.
+
+Example:
+ aliases {
+ usb1 =
+ phy1 = _phy;
+ };
+
+ usb1: hsusb1_core@1f8e3000 {
+ compatible = "microchip,pic32mzda-usb";
+ reg = <0x1f8e3000 0x1000>,
+ <0x1f884000 0x1000>;
+ reg-names = "mc", "usbcr";
+ interrupts = <132 IRQ_TYPE_EDGE_RISING>,
+<133 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "mc", "dma";
+ dr_mode = "host";
+ mentor,multipoint = <1>;
+ mentor,num-eps = <8>;
+ mentor,ram-bits = <11>;
+ mentor,power = <500>;
+ phys = <_phy>;
+ clocks = < PB5CLK>;
+ clock-names = "usb_clk";
+ usb_overcurrent = <_overcurrent>;
+ };
+
+ usb1_phy: hsusb1_phy@1f8e4000 {
+ compatible = "usb-nop-xceiv";
+ reg = <0x1f8e4000 0x1000>;
+ clocks = < UPLLCLK>;
+ clock-names = "main_clk";
+ clock-frequency = <2400>;
+ };
+
+ usb1_overcurrent: hsusb1_oc@0 {
+ interrupt-parent = <>;
+ interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+ };
--
1.8.3.1
[PATCH v1 1/2] dt/bindings/usb: Add bindings for PIC32 MUSB driver.
Document devicetree binding for the USB controller
and USB Phy found on Microchip PIC32 class devices.
Signed-off-by: Purna Chandra Mandal
---
.../bindings/usb/microchip,pic32-musb.txt | 67 ++
1 file changed, 67 insertions(+)
create mode 100644
Documentation/devicetree/bindings/usb/microchip,pic32-musb.txt
diff --git a/Documentation/devicetree/bindings/usb/microchip,pic32-musb.txt
b/Documentation/devicetree/bindings/usb/microchip,pic32-musb.txt
new file mode 100644
index 000..e1cec9d
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/microchip,pic32-musb.txt
@@ -0,0 +1,67 @@
+Microchip PIC32 MUSB DRC/OTG controller
+---
+
+Required properties:
+ - compatible : should be "microchip,pic32mzda-usb".
+ - reg : offset and length of "MUSB Core Registers" and
+ "USB Clock & Reset Registers".
+ - reg-names: should be "mc", and "usbcr" in order
+ - clocks : clock specifier for the musb controller clock
+ - clock-names : should be "usb_clk"
+ - interrupts : interrupt number for MUSB Core General interrupt
+ and DMA interrupt
+ - interrupt-names : must be "mc" and "dma" in order.
+ - phys : phy specifier for the otg phy.
+ - dr_mode : should be one of "host", "peripheral" or "otg".
+ - mentor,multipoint: Should be "1" indicating the musb controller supports
+ multipoint. This is MUSB configuration-specific setting.
+ - mentor,num-eps : Specifies the number of endpoints. This is also a
+ MUSB configuration-specific setting. Should be set to
"8".
+ - mentor,ram-bits : Specifies the ram address size. Should be set to "11".
+ - mentor,power : Should be "500". This signifies the controller can supply
+ up to 500mA when operating in host mode.
+ - phys : phandle of the USB phy.
+ - usb_overcurrent : phandle to MUSB over-current note. It should have
+ interrupt number for over-current detection logic.
+
+Optional properties:
+ - microchip,fifo-mode: Specifies layout of internal SRAM for end-point fifos.
+Should be 0 (default) or 1.
+
+Example:
+ aliases {
+ usb1 =
+ phy1 = _phy;
+ };
+
+ usb1: hsusb1_core@1f8e3000 {
+ compatible = "microchip,pic32mzda-usb";
+ reg = <0x1f8e3000 0x1000>,
+ <0x1f884000 0x1000>;
+ reg-names = "mc", "usbcr";
+ interrupts = <132 IRQ_TYPE_EDGE_RISING>,
+<133 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "mc", "dma";
+ dr_mode = "host";
+ mentor,multipoint = <1>;
+ mentor,num-eps = <8>;
+ mentor,ram-bits = <11>;
+ mentor,power = <500>;
+ phys = <_phy>;
+ clocks = < PB5CLK>;
+ clock-names = "usb_clk";
+ usb_overcurrent = <_overcurrent>;
+ };
+
+ usb1_phy: hsusb1_phy@1f8e4000 {
+ compatible = "usb-nop-xceiv";
+ reg = <0x1f8e4000 0x1000>;
+ clocks = < UPLLCLK>;
+ clock-names = "main_clk";
+ clock-frequency = <2400>;
+ };
+
+ usb1_overcurrent: hsusb1_oc@0 {
+ interrupt-parent = <>;
+ interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+ };
--
1.8.3.1
[PATCH v1 2/2] usb: musb: pic32: Add USB DRC driver for PIC32 OTG controller.
From: Cristian Birsan <cristian.bir...@microchip.com>
This driver adds support of PIC32 MUSB OTG controller as
dual role device. It implements platform specific glue to
reuse musb core.
Signed-off-by: Cristian Birsan <cristian.bir...@microchip.com>
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
---
drivers/usb/musb/Kconfig | 9 +-
drivers/usb/musb/Makefile | 3 +-
drivers/usb/musb/pic32.c | 608 ++
3 files changed, 617 insertions(+), 3 deletions(-)
create mode 100644 drivers/usb/musb/pic32.c
diff --git a/drivers/usb/musb/Kconfig b/drivers/usb/musb/Kconfig
index 886526b..705f8b8 100644
--- a/drivers/usb/musb/Kconfig
+++ b/drivers/usb/musb/Kconfig
@@ -112,6 +112,13 @@ config USB_MUSB_BLACKFIN
depends on (BF54x && !BF544) || (BF52x && ! BF522 && !BF523)
depends on NOP_USB_XCEIV
+config USB_MUSB_PIC32
+ tristate "Microchip PIC32 USB platforms"
+ depends on MACH_PIC32 || COMPILE_TEST
+ depends on NOP_USB_XCEIV
+ help
+ Say y to enable PIC32 USB DRC controller support
+
config USB_MUSB_UX500
tristate "Ux500 platforms"
depends on ARCH_U8500 || COMPILE_TEST
@@ -149,7 +156,7 @@ config USB_UX500_DMA
config USB_INVENTRA_DMA
bool 'Inventra'
- depends on USB_MUSB_OMAP2PLUS || USB_MUSB_BLACKFIN
+ depends on USB_MUSB_OMAP2PLUS || USB_MUSB_BLACKFIN || USB_MUSB_PIC32
help
Enable DMA transfers using Mentor's engine.
diff --git a/drivers/usb/musb/Makefile b/drivers/usb/musb/Makefile
index f95befe..b9275cd 100644
--- a/drivers/usb/musb/Makefile
+++ b/drivers/usb/musb/Makefile
@@ -1,7 +1,6 @@
#
# for USB OTG silicon based on Mentor Graphics INVENTRA designs
#
-
obj-$(CONFIG_USB_MUSB_HDRC) += musb_hdrc.o
musb_hdrc-y := musb_core.o
@@ -20,9 +19,9 @@ obj-$(CONFIG_USB_MUSB_DA8XX) += da8xx.o
obj-$(CONFIG_USB_MUSB_BLACKFIN)+= blackfin.o
obj-$(CONFIG_USB_MUSB_UX500) += ux500.o
obj-$(CONFIG_USB_MUSB_JZ4740) += jz4740.o
+obj-$(CONFIG_USB_MUSB_PIC32) += pic32.o
obj-$(CONFIG_USB_MUSB_SUNXI) += sunxi.o
-
obj-$(CONFIG_USB_MUSB_AM335X_CHILD)+= musb_am335x.o
# the kconfig must guarantee that only one of the
diff --git a/drivers/usb/musb/pic32.c b/drivers/usb/musb/pic32.c
new file mode 100644
index 000..3921088
--- /dev/null
+++ b/drivers/usb/musb/pic32.c
@@ -0,0 +1,608 @@
+/*
+ * Microchip PIC32 MUSB Dual-Role Controller "glue layer".
+ *
+ * Cristian Birsan <cristian.bir...@microchip.com>
+ * Purna Chandra Mandal <purna.man...@microchip.com>
+ * Copyright (C) 2015 Microchip Technology Inc. All rights reserved.
+ *
+ * Based on the am35x and dsps "glue layer" code.
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "musb_core.h"
+
+#define MUSB_SOFTRST 0x7f
+#define MUSB_SOFTRST_NRST BIT(0)
+#define MUSB_SOFTRST_NRSTX BIT(1)
+
+/* USB Clock & Reset Control */
+#define USBCRCON 0x0
+#define USBCRCON_USBWKUPENBIT(0) /* Enable remote wakeup interrupt */
+#define USBCRCON_USBRIE BIT(1) /* Enable Remote resume interrupt */
+#define USBCRCON_USBIEBIT(2) /* Enable USB General interrupt
*/
+#define USBCRCON_SENDMONEN BIT(3) /* Enable Session End VBUS monitoring
*/
+#define USBCRCON_BSVALMONENBIT(4) /* Enable B-Device VBUS monitoring */
+#define USBCRCON_ASVALMONENBIT(5) /* Enable A-Device VBUS monitoring */
+#define USBCRCON_VBUSMONEN BIT(6) /* Enable VBUS monitoring */
+#define USBCRCON_PHYIDEN BIT(7) /* Enabale USBPhy USBID monitoring */
+#define USBCRCON_USBIDVAL BIT(8) /* USBID override value */
+#define USBCRCON_USBIDOVENBIT(9) /* Enable USBID override */
+#define USBCRCON_USBWKUP BIT(24) /* Remote wakeup status */
+#define USBCRCON_USBRFBIT(25) /* USB Remote resume status */
+#define USBCRCON_USBIFBIT(26) /* USB General interrupt status
*/
+
+#define PIC32_TX_EP_MASK 0x /* EP0 + 15 Tx EPs */
+#define PIC32_RX_EP_MASK 0xfffe /* 15 Rx EPs */
+
+#definePOLL_SECONDS2
+
+struct pic32_musb {
+ void __iomem*cru;
+ struct clk *clk;
+ int oc_irq;
+ struct platform_device
[PATCH v1 2/2] usb: musb: pic32: Add USB DRC driver for PIC32 OTG controller.
From: Cristian Birsan
This driver adds support of PIC32 MUSB OTG controller as
dual role device. It implements platform specific glue to
reuse musb core.
Signed-off-by: Cristian Birsan
Signed-off-by: Purna Chandra Mandal
---
drivers/usb/musb/Kconfig | 9 +-
drivers/usb/musb/Makefile | 3 +-
drivers/usb/musb/pic32.c | 608 ++
3 files changed, 617 insertions(+), 3 deletions(-)
create mode 100644 drivers/usb/musb/pic32.c
diff --git a/drivers/usb/musb/Kconfig b/drivers/usb/musb/Kconfig
index 886526b..705f8b8 100644
--- a/drivers/usb/musb/Kconfig
+++ b/drivers/usb/musb/Kconfig
@@ -112,6 +112,13 @@ config USB_MUSB_BLACKFIN
depends on (BF54x && !BF544) || (BF52x && ! BF522 && !BF523)
depends on NOP_USB_XCEIV
+config USB_MUSB_PIC32
+ tristate "Microchip PIC32 USB platforms"
+ depends on MACH_PIC32 || COMPILE_TEST
+ depends on NOP_USB_XCEIV
+ help
+ Say y to enable PIC32 USB DRC controller support
+
config USB_MUSB_UX500
tristate "Ux500 platforms"
depends on ARCH_U8500 || COMPILE_TEST
@@ -149,7 +156,7 @@ config USB_UX500_DMA
config USB_INVENTRA_DMA
bool 'Inventra'
- depends on USB_MUSB_OMAP2PLUS || USB_MUSB_BLACKFIN
+ depends on USB_MUSB_OMAP2PLUS || USB_MUSB_BLACKFIN || USB_MUSB_PIC32
help
Enable DMA transfers using Mentor's engine.
diff --git a/drivers/usb/musb/Makefile b/drivers/usb/musb/Makefile
index f95befe..b9275cd 100644
--- a/drivers/usb/musb/Makefile
+++ b/drivers/usb/musb/Makefile
@@ -1,7 +1,6 @@
#
# for USB OTG silicon based on Mentor Graphics INVENTRA designs
#
-
obj-$(CONFIG_USB_MUSB_HDRC) += musb_hdrc.o
musb_hdrc-y := musb_core.o
@@ -20,9 +19,9 @@ obj-$(CONFIG_USB_MUSB_DA8XX) += da8xx.o
obj-$(CONFIG_USB_MUSB_BLACKFIN)+= blackfin.o
obj-$(CONFIG_USB_MUSB_UX500) += ux500.o
obj-$(CONFIG_USB_MUSB_JZ4740) += jz4740.o
+obj-$(CONFIG_USB_MUSB_PIC32) += pic32.o
obj-$(CONFIG_USB_MUSB_SUNXI) += sunxi.o
-
obj-$(CONFIG_USB_MUSB_AM335X_CHILD)+= musb_am335x.o
# the kconfig must guarantee that only one of the
diff --git a/drivers/usb/musb/pic32.c b/drivers/usb/musb/pic32.c
new file mode 100644
index 000..3921088
--- /dev/null
+++ b/drivers/usb/musb/pic32.c
@@ -0,0 +1,608 @@
+/*
+ * Microchip PIC32 MUSB Dual-Role Controller "glue layer".
+ *
+ * Cristian Birsan
+ * Purna Chandra Mandal
+ * Copyright (C) 2015 Microchip Technology Inc. All rights reserved.
+ *
+ * Based on the am35x and dsps "glue layer" code.
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "musb_core.h"
+
+#define MUSB_SOFTRST 0x7f
+#define MUSB_SOFTRST_NRST BIT(0)
+#define MUSB_SOFTRST_NRSTX BIT(1)
+
+/* USB Clock & Reset Control */
+#define USBCRCON 0x0
+#define USBCRCON_USBWKUPENBIT(0) /* Enable remote wakeup interrupt */
+#define USBCRCON_USBRIE BIT(1) /* Enable Remote resume interrupt */
+#define USBCRCON_USBIEBIT(2) /* Enable USB General interrupt
*/
+#define USBCRCON_SENDMONEN BIT(3) /* Enable Session End VBUS monitoring
*/
+#define USBCRCON_BSVALMONENBIT(4) /* Enable B-Device VBUS monitoring */
+#define USBCRCON_ASVALMONENBIT(5) /* Enable A-Device VBUS monitoring */
+#define USBCRCON_VBUSMONEN BIT(6) /* Enable VBUS monitoring */
+#define USBCRCON_PHYIDEN BIT(7) /* Enabale USBPhy USBID monitoring */
+#define USBCRCON_USBIDVAL BIT(8) /* USBID override value */
+#define USBCRCON_USBIDOVENBIT(9) /* Enable USBID override */
+#define USBCRCON_USBWKUP BIT(24) /* Remote wakeup status */
+#define USBCRCON_USBRFBIT(25) /* USB Remote resume status */
+#define USBCRCON_USBIFBIT(26) /* USB General interrupt status
*/
+
+#define PIC32_TX_EP_MASK 0x /* EP0 + 15 Tx EPs */
+#define PIC32_RX_EP_MASK 0xfffe /* 15 Rx EPs */
+
+#definePOLL_SECONDS2
+
+struct pic32_musb {
+ void __iomem*cru;
+ struct clk *clk;
+ int oc_irq;
+ struct platform_device *platdev;
+ struct timer_list timer; /* otg_workaround timer */
+ unsigned long last_timer; /* last timer data for */
+};
+
+static irqr
Re: [PATCH v5 1/2] dt/bindings: Add bindings for PIC32 SPI peripheral
On 04/02/2016 10:05 PM, Mark Brown wrote: > On Fri, Apr 01, 2016 at 04:48:49PM +0530, Purna Chandra Mandal wrote: >> Document the devicetree bindings for the SPI peripheral found >> on Microchip PIC32 class devices. > Please use subject lines reflecting the style for the subsystem. ack. Will do.
Re: [PATCH v5 1/2] dt/bindings: Add bindings for PIC32 SPI peripheral
On 04/02/2016 10:05 PM, Mark Brown wrote: > On Fri, Apr 01, 2016 at 04:48:49PM +0530, Purna Chandra Mandal wrote: >> Document the devicetree bindings for the SPI peripheral found >> on Microchip PIC32 class devices. > Please use subject lines reflecting the style for the subsystem. ack. Will do.
[PATCH v5 1/2] dt/bindings: Add bindings for PIC32 SPI peripheral
Document the devicetree bindings for the SPI peripheral found
on Microchip PIC32 class devices.
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
Acked-by: Rob Herring <r...@kernel.org>
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- fix indentation
- add space after comma
- moved 'cs-gpios' section under 'required' properties.
.../bindings/spi/microchip,spi-pic32.txt | 34 ++
1 file changed, 34 insertions(+)
create mode 100644
Documentation/devicetree/bindings/spi/microchip,spi-pic32.txt
diff --git a/Documentation/devicetree/bindings/spi/microchip,spi-pic32.txt
b/Documentation/devicetree/bindings/spi/microchip,spi-pic32.txt
new file mode 100644
index 000..79de379f
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/microchip,spi-pic32.txt
@@ -0,0 +1,34 @@
+Microchip PIC32 SPI Master controller
+
+Required properties:
+- compatible: Should be "microchip,pic32mzda-spi".
+- reg: Address and length of register space for the device.
+- interrupts: Should contain all three spi interrupts in sequence
+ of , , .
+- interrupt-names: Should be "fault", "rx", "tx" in order.
+- clocks: Phandle of the clock generating SPI clock on the bus.
+- clock-names: Should be "mck0".
+- cs-gpios: Specifies the gpio pins to be used for chipselects.
+See: Documentation/devicetree/bindings/spi/spi-bus.txt
+
+Optional properties:
+- dmas: Two or more DMA channel specifiers following the convention outlined
+in Documentation/devicetree/bindings/dma/dma.txt
+- dma-names: Names for the dma channels. There must be at least one channel
+ named "spi-tx" for transmit and named "spi-rx" for receive.
+
+Example:
+
+spi1: spi@1f821000 {
+compatible = "microchip,pic32mzda-spi";
+reg = <0x1f821000 0x200>;
+interrupts = <109 IRQ_TYPE_LEVEL_HIGH>,
+ <110 IRQ_TYPE_LEVEL_HIGH>,
+ <111 IRQ_TYPE_LEVEL_HIGH>;
+interrupt-names = "fault", "rx", "tx";
+clocks = <>;
+clock-names = "mck0";
+cs-gpios = < 4 GPIO_ACTIVE_LOW>;
+dmas = < 134>, < 135>;
+dma-names = "spi-rx", "spi-tx";
+};
--
1.8.3.1
[PATCH v5 2/2] spi: spi-pic32: Add PIC32 SPI master driver
The PIC32 SPI driver is capable of performing SPI transfers
using PIO or external DMA engine. GPIO controlled /CS support
is made default in the driver for correct operation of the
controller. This can be enabled by adding "cs-gpios" property
of the SPI node in board dts file.
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
---
Changes in v5:
- report error for unsupported bits_per_word.
- drop custom debugging messages in favor of core provided one.
- use if-else instead of 'goto'
- moved enable/disable of controller to prepare/unprepare_hardware()
- refactor setup(), just retain cs-deselect logic in setup()
and apply the other setting in prepare_message().
Changes in v4:
- report error and bailout in case of missing irq(s).
- remove fallback to PIO mode in case of failure in DMA transfer.
- remove polling based PIO completely.
- drop spinlock
- update error message and comments.
Changes in v3:
- drop 'owner' field in driver struct.
- fix compilation warning in dma_addr_t print.
Changes in v2:
- drop internal function drain_rx_fifo()
- merge wrapper functions with callers wherever applicable
- sort includes alphabetically
- Kconfig: sort SPI_PIC32 alphabetically and add || COMPILE_TEST
- Makefile: sort SPI_PIC32 alphabetically
- replace cpu_relax() with ndelay() in disable_chip()
- drop spi controller driven /CS management completely, use only
GPIO controller /CS.
- rename function names starting with 'spi' to avoid namespace conflict
- use .one_transfer() callback instead of .one_message().
- drop /CS assert-deassert functions as core provides those.
- fix race while completing transfer before disabling interrupt.
drivers/spi/Kconfig | 6 +
drivers/spi/Makefile| 1 +
drivers/spi/spi-pic32.c | 888
3 files changed, 895 insertions(+)
create mode 100644 drivers/spi/spi-pic32.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 7706416..22f973f 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -396,6 +396,12 @@ config SPI_ORION
help
This enables using the SPI master controller on the Orion chips.
+config SPI_PIC32
+ tristate "Microchip PIC32 series SPI"
+ depends on MACH_PIC32 || COMPILE_TEST
+ help
+ SPI driver for Microchip PIC32 SPI master controller.
+
config SPI_PL022
tristate "ARM AMBA PL022 SSP controller"
depends on ARM_AMBA
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 8991ffc..1bcb417 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -60,6 +60,7 @@ obj-$(CONFIG_SPI_OMAP_100K) += spi-omap-100k.o
obj-$(CONFIG_SPI_OMAP24XX) += spi-omap2-mcspi.o
obj-$(CONFIG_SPI_TI_QSPI) += spi-ti-qspi.o
obj-$(CONFIG_SPI_ORION)+= spi-orion.o
+obj-$(CONFIG_SPI_PIC32)+= spi-pic32.o
obj-$(CONFIG_SPI_PL022)+= spi-pl022.o
obj-$(CONFIG_SPI_PPC4xx) += spi-ppc4xx.o
spi-pxa2xx-platform-objs := spi-pxa2xx.o
diff --git a/drivers/spi/spi-pic32.c b/drivers/spi/spi-pic32.c
new file mode 100644
index 000..f8313ea
--- /dev/null
+++ b/drivers/spi/spi-pic32.c
@@ -0,0 +1,888 @@
+/*
+ * Microchip PIC32 SPI controller driver.
+ *
+ * Purna Chandra Mandal <purna.man...@microchip.com>
+ * Copyright (c) 2016, Microchip Technology Inc.
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* SPI controller registers */
+struct pic32_spi_regs {
+ u32 ctrl;
+ u32 ctrl_clr;
+ u32 ctrl_set;
+ u32 ctrl_inv;
+ u32 status;
+ u32 status_clr;
+ u32 status_set;
+ u32 status_inv;
+ u32 buf;
+ u32 dontuse[3];
+ u32 baud;
+ u32 dontuse2[3];
+ u32 ctrl2;
+ u32 ctrl2_clr;
+ u32 ctrl2_set;
+ u32 ctrl2_inv;
+};
+
+/* Bit fields of SPI Control Register */
+#define CTRL_RX_INT_SHIFT 0 /* Rx interrupt generation */
+#define RX_FIFO_EMTPY 0
+#define RX_FIFO_NOT_EMPTY 1 /* not empty */
+#define RX_FIFO_HALF_FULL 2 /* full by half or more */
+#define RX_FIFO_FULL 3 /* completely full */
+
+#define CTRL_TX_INT_SHIFT 2 /* TX interrupt generation */
+#define TX_FIFO_ALL_EMPTY 0 /* completely empty */
+#define TX_FIFO_EMTPY 1 /* empty */
+#define TX_FIFO_HALF_EMPTY
[PATCH v5 1/2] dt/bindings: Add bindings for PIC32 SPI peripheral
Document the devicetree bindings for the SPI peripheral found
on Microchip PIC32 class devices.
Signed-off-by: Purna Chandra Mandal
Acked-by: Rob Herring
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- fix indentation
- add space after comma
- moved 'cs-gpios' section under 'required' properties.
.../bindings/spi/microchip,spi-pic32.txt | 34 ++
1 file changed, 34 insertions(+)
create mode 100644
Documentation/devicetree/bindings/spi/microchip,spi-pic32.txt
diff --git a/Documentation/devicetree/bindings/spi/microchip,spi-pic32.txt
b/Documentation/devicetree/bindings/spi/microchip,spi-pic32.txt
new file mode 100644
index 000..79de379f
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/microchip,spi-pic32.txt
@@ -0,0 +1,34 @@
+Microchip PIC32 SPI Master controller
+
+Required properties:
+- compatible: Should be "microchip,pic32mzda-spi".
+- reg: Address and length of register space for the device.
+- interrupts: Should contain all three spi interrupts in sequence
+ of , , .
+- interrupt-names: Should be "fault", "rx", "tx" in order.
+- clocks: Phandle of the clock generating SPI clock on the bus.
+- clock-names: Should be "mck0".
+- cs-gpios: Specifies the gpio pins to be used for chipselects.
+See: Documentation/devicetree/bindings/spi/spi-bus.txt
+
+Optional properties:
+- dmas: Two or more DMA channel specifiers following the convention outlined
+in Documentation/devicetree/bindings/dma/dma.txt
+- dma-names: Names for the dma channels. There must be at least one channel
+ named "spi-tx" for transmit and named "spi-rx" for receive.
+
+Example:
+
+spi1: spi@1f821000 {
+compatible = "microchip,pic32mzda-spi";
+reg = <0x1f821000 0x200>;
+interrupts = <109 IRQ_TYPE_LEVEL_HIGH>,
+ <110 IRQ_TYPE_LEVEL_HIGH>,
+ <111 IRQ_TYPE_LEVEL_HIGH>;
+interrupt-names = "fault", "rx", "tx";
+clocks = <>;
+clock-names = "mck0";
+cs-gpios = < 4 GPIO_ACTIVE_LOW>;
+dmas = < 134>, < 135>;
+dma-names = "spi-rx", "spi-tx";
+};
--
1.8.3.1
[PATCH v5 2/2] spi: spi-pic32: Add PIC32 SPI master driver
The PIC32 SPI driver is capable of performing SPI transfers
using PIO or external DMA engine. GPIO controlled /CS support
is made default in the driver for correct operation of the
controller. This can be enabled by adding "cs-gpios" property
of the SPI node in board dts file.
Signed-off-by: Purna Chandra Mandal
---
Changes in v5:
- report error for unsupported bits_per_word.
- drop custom debugging messages in favor of core provided one.
- use if-else instead of 'goto'
- moved enable/disable of controller to prepare/unprepare_hardware()
- refactor setup(), just retain cs-deselect logic in setup()
and apply the other setting in prepare_message().
Changes in v4:
- report error and bailout in case of missing irq(s).
- remove fallback to PIO mode in case of failure in DMA transfer.
- remove polling based PIO completely.
- drop spinlock
- update error message and comments.
Changes in v3:
- drop 'owner' field in driver struct.
- fix compilation warning in dma_addr_t print.
Changes in v2:
- drop internal function drain_rx_fifo()
- merge wrapper functions with callers wherever applicable
- sort includes alphabetically
- Kconfig: sort SPI_PIC32 alphabetically and add || COMPILE_TEST
- Makefile: sort SPI_PIC32 alphabetically
- replace cpu_relax() with ndelay() in disable_chip()
- drop spi controller driven /CS management completely, use only
GPIO controller /CS.
- rename function names starting with 'spi' to avoid namespace conflict
- use .one_transfer() callback instead of .one_message().
- drop /CS assert-deassert functions as core provides those.
- fix race while completing transfer before disabling interrupt.
drivers/spi/Kconfig | 6 +
drivers/spi/Makefile| 1 +
drivers/spi/spi-pic32.c | 888
3 files changed, 895 insertions(+)
create mode 100644 drivers/spi/spi-pic32.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 7706416..22f973f 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -396,6 +396,12 @@ config SPI_ORION
help
This enables using the SPI master controller on the Orion chips.
+config SPI_PIC32
+ tristate "Microchip PIC32 series SPI"
+ depends on MACH_PIC32 || COMPILE_TEST
+ help
+ SPI driver for Microchip PIC32 SPI master controller.
+
config SPI_PL022
tristate "ARM AMBA PL022 SSP controller"
depends on ARM_AMBA
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 8991ffc..1bcb417 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -60,6 +60,7 @@ obj-$(CONFIG_SPI_OMAP_100K) += spi-omap-100k.o
obj-$(CONFIG_SPI_OMAP24XX) += spi-omap2-mcspi.o
obj-$(CONFIG_SPI_TI_QSPI) += spi-ti-qspi.o
obj-$(CONFIG_SPI_ORION)+= spi-orion.o
+obj-$(CONFIG_SPI_PIC32)+= spi-pic32.o
obj-$(CONFIG_SPI_PL022)+= spi-pl022.o
obj-$(CONFIG_SPI_PPC4xx) += spi-ppc4xx.o
spi-pxa2xx-platform-objs := spi-pxa2xx.o
diff --git a/drivers/spi/spi-pic32.c b/drivers/spi/spi-pic32.c
new file mode 100644
index 000..f8313ea
--- /dev/null
+++ b/drivers/spi/spi-pic32.c
@@ -0,0 +1,888 @@
+/*
+ * Microchip PIC32 SPI controller driver.
+ *
+ * Purna Chandra Mandal
+ * Copyright (c) 2016, Microchip Technology Inc.
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* SPI controller registers */
+struct pic32_spi_regs {
+ u32 ctrl;
+ u32 ctrl_clr;
+ u32 ctrl_set;
+ u32 ctrl_inv;
+ u32 status;
+ u32 status_clr;
+ u32 status_set;
+ u32 status_inv;
+ u32 buf;
+ u32 dontuse[3];
+ u32 baud;
+ u32 dontuse2[3];
+ u32 ctrl2;
+ u32 ctrl2_clr;
+ u32 ctrl2_set;
+ u32 ctrl2_inv;
+};
+
+/* Bit fields of SPI Control Register */
+#define CTRL_RX_INT_SHIFT 0 /* Rx interrupt generation */
+#define RX_FIFO_EMTPY 0
+#define RX_FIFO_NOT_EMPTY 1 /* not empty */
+#define RX_FIFO_HALF_FULL 2 /* full by half or more */
+#define RX_FIFO_FULL 3 /* completely full */
+
+#define CTRL_TX_INT_SHIFT 2 /* TX interrupt generation */
+#define TX_FIFO_ALL_EMPTY 0 /* completely empty */
+#define TX_FIFO_EMTPY 1 /* empty */
+#define TX_FIFO_HALF_EMPTY2 /* empty by half or more */
+#define TX_FIFO_NOT_FULL 3 /* a
Re: [PATCH v4 2/2] spi: spi-pic32: Add PIC32 SPI master driver
On 03/30/2016 09:18 PM, Mark Brown wrote: > On Wed, Mar 30, 2016 at 04:19:16PM +0530, Purna Chandra Mandal wrote: >> On 03/29/2016 09:55 PM, Mark Brown wrote: >>> On Tue, Mar 29, 2016 at 05:32:41PM +0530, Purna Chandra Mandal wrote: >>>> MMC_SPI will have to terminate on-going MMC transactions and it is >>>> done by calling setup(). It is assumed that setup() will always leave >>>> the chip-select deactivated. >>> No, this is just completely broken - that's quite simply not what >>> setup() does. See spi-summary. There is *no* code in the core that >>> terminates ongoing transfers as a result of calling setup(), if that's >>> happening it's a result of triggering error handling. >> Description of spi_setup() in spi.c clearly mentions that "When this >> function returns, the spi device is deselected" and this is only >> possible if (at least) chip-select is deactivated. > This doesn't say anything about any ongoing operations! Trying to do a > setup() with active transfers on the device is just not sensible, it is > intended to be used on an idle device. I would not expect it to work > reliably on an active device. agreed.
Re: [PATCH v4 2/2] spi: spi-pic32: Add PIC32 SPI master driver
On 03/30/2016 09:18 PM, Mark Brown wrote: > On Wed, Mar 30, 2016 at 04:19:16PM +0530, Purna Chandra Mandal wrote: >> On 03/29/2016 09:55 PM, Mark Brown wrote: >>> On Tue, Mar 29, 2016 at 05:32:41PM +0530, Purna Chandra Mandal wrote: >>>> MMC_SPI will have to terminate on-going MMC transactions and it is >>>> done by calling setup(). It is assumed that setup() will always leave >>>> the chip-select deactivated. >>> No, this is just completely broken - that's quite simply not what >>> setup() does. See spi-summary. There is *no* code in the core that >>> terminates ongoing transfers as a result of calling setup(), if that's >>> happening it's a result of triggering error handling. >> Description of spi_setup() in spi.c clearly mentions that "When this >> function returns, the spi device is deselected" and this is only >> possible if (at least) chip-select is deactivated. > This doesn't say anything about any ongoing operations! Trying to do a > setup() with active transfers on the device is just not sensible, it is > intended to be used on an idle device. I would not expect it to work > reliably on an active device. agreed.
Re: [PATCH v4 2/2] spi: spi-pic32: Add PIC32 SPI master driver
On 03/29/2016 09:55 PM, Mark Brown wrote: > On Tue, Mar 29, 2016 at 05:32:41PM +0530, Purna Chandra Mandal wrote: > >> It is required for MMC-over-SPI support. Linux MMC_SPI driver sometimes >> (depending on some logic) want chip-select to be kept enabled (using >> transfer.cs_change) even at the end of SPI message so that following >> message(s) can also be made part of the running MMC transaction. >> In this case if there is any error (and in some other cases as well) > If your hardware doesn't support per-/CS setup then your driver needs to > record whatever is configured via setup() and apply it later. PIC32 SPI controller supports one /CS per instance. So per-/CS specific logic might not be required. >> MMC_SPI will have to terminate on-going MMC transactions and it is >> done by calling setup(). It is assumed that setup() will always leave >> the chip-select deactivated. > No, this is just completely broken - that's quite simply not what > setup() does. See spi-summary. There is *no* code in the core that > terminates ongoing transfers as a result of calling setup(), if that's > happening it's a result of triggering error handling. Description of spi_setup() in spi.c clearly mentions that "When this function returns, the spi device is deselected" and this is only possible if (at least) chip-select is deactivated. So based on spi-summary and spi_setup() description, except chip-select, all other settings has to be recorded and applied later when device is selected and data is transferred to or from the device. Keeping this in mind I'll just retain cs-deselect logic in setup() and apply the recorded setting in prepare_message() callback, if and when required. >> Best thing I can add is wait for unprepare_message() before calling >> cleanup(). > The cleanup() function is for deallocating dynamically allocated data, > it will be called by the core. ack. >> If you could suggest better alternative that will be great. > If you want to change the chip select you need to use the normal > interfaces for changing the chip select via message processing. ack.
Re: [PATCH v4 2/2] spi: spi-pic32: Add PIC32 SPI master driver
On 03/29/2016 09:55 PM, Mark Brown wrote: > On Tue, Mar 29, 2016 at 05:32:41PM +0530, Purna Chandra Mandal wrote: > >> It is required for MMC-over-SPI support. Linux MMC_SPI driver sometimes >> (depending on some logic) want chip-select to be kept enabled (using >> transfer.cs_change) even at the end of SPI message so that following >> message(s) can also be made part of the running MMC transaction. >> In this case if there is any error (and in some other cases as well) > If your hardware doesn't support per-/CS setup then your driver needs to > record whatever is configured via setup() and apply it later. PIC32 SPI controller supports one /CS per instance. So per-/CS specific logic might not be required. >> MMC_SPI will have to terminate on-going MMC transactions and it is >> done by calling setup(). It is assumed that setup() will always leave >> the chip-select deactivated. > No, this is just completely broken - that's quite simply not what > setup() does. See spi-summary. There is *no* code in the core that > terminates ongoing transfers as a result of calling setup(), if that's > happening it's a result of triggering error handling. Description of spi_setup() in spi.c clearly mentions that "When this function returns, the spi device is deselected" and this is only possible if (at least) chip-select is deactivated. So based on spi-summary and spi_setup() description, except chip-select, all other settings has to be recorded and applied later when device is selected and data is transferred to or from the device. Keeping this in mind I'll just retain cs-deselect logic in setup() and apply the recorded setting in prepare_message() callback, if and when required. >> Best thing I can add is wait for unprepare_message() before calling >> cleanup(). > The cleanup() function is for deallocating dynamically allocated data, > it will be called by the core. ack. >> If you could suggest better alternative that will be great. > If you want to change the chip select you need to use the normal > interfaces for changing the chip select via message processing. ack.
Re: [PATCH v4 2/2] spi: spi-pic32: Add PIC32 SPI master driver
On 03/29/2016 12:56 AM, Mark Brown wrote:
> On Wed, Mar 23, 2016 at 07:12:56PM +0530, Purna Chandra Mandal wrote:
>
>> +switch (bits_per_word) {
>> +default:
>> +case 8:
> Are you sure that all bits per word settings other than those explicitly
> supported should be handled in exactly the same fashion as 8 bits per
> word? That doesn't seem entirely expected. I'd expect the default to
> be to return an error.
ack. Will treat default case as error.
>> +static int pic32_spi_prepare_message(struct spi_master *master,
>> + struct spi_message *msg)
>> +{
>> +struct spi_device *spi = msg->spi;
>> +struct spi_transfer *xfer;
>> +struct pic32_spi *pic32s;
>> +
>> +pic32s = spi_master_get_devdata(master);
>> +
>> +pic32s->mesg = msg;
>> +pic32_spi_disable_chip(pic32s);
>> +
>> +if (!pic32_spi_debug)
>> +return 0;
> This appears to be some half implemented debugging code which is never
> enabled, please remove it.
ack. Will remove the debug logic.
>> +list_for_each_entry(xfer, >transfers, transfer_list) {
>> +dev_dbg(>dev, " xfer %p: len %u tx %p rx %p\n",
>> +xfer, xfer->len, xfer->tx_buf, xfer->rx_buf);
>> +print_hex_dump(KERN_DEBUG, "tx_buf ",
>> + DUMP_PREFIX_ADDRESS,
>> + 16, 1, xfer->tx_buf,
>> + min_t(u32, xfer->len, 16), 1);
>> +}
> Similarly here, the core already has extensive trace stuff in it which
> you can use.
Will remove.
>> +/* transact by DMA mode */
>> +if (transfer->rx_sg.nents && transfer->tx_sg.nents) {
>> +ret = pic32_spi_dma_transfer(pic32s, transfer);
>> +if (ret) {
>> +dev_err(>dev, "dma submit error\n");
>> +return ret;
>> +}
>> +
>> +/* DMA issued, wait for completion */
>> +set_bit(PIC32F_DMA_ISSUED, >flags);
>> +goto out_wait_for_xfer;
>> +}
> ...
>
>> +
>> +out_wait_for_xfer:
> Please write normal code with an if/else rather than using gotos, it's a
> lot easier to follow.
Make sense. Will use if-else.
>> +pic32s = spi_master_get_devdata(master);
>> +
>> +pic32_spi_disable_chip(pic32s);
> Do we really need tod isable the hardware after every single message?
> It's normally more efficient to just leave the hardware powered until it
> goes idle and unprepare_transfer_hardware() is called.
>
Ack. There is no particular need to disable h/w per message.
Will instead implement prepare/unprepare_transfer_hardware() and add there.
>> +/* SPI master supports only one spi-device at a time.
>> + * So multiple spi_setup() to different devices is not allowed.
>> + */
>> +if (unlikely(pic32s->spi_dev && (pic32s->spi_dev != spi))) {
> unlikely() is for fast paths, outside of them it's just noise.
ack.
>> +/* But spi_setup() can be called multiple times by same device.
>> + * In that case stop current on-going transaction and release
>> + * resource(s).
>> + */
>> +if (pic32s->spi_dev == spi)
>> +pic32_spi_cleanup(spi);
> This is broken, it will break in progress transfers. setup() shouldn't
> be doing anything that disrupts them, anything that can't be run when
> other transfers are in progress needs to be deferred till we actually do
> the transfers (or done earlier in probe).
Normally setup() and cleanup() are called in-pair by spi-client driver.
In these cases the above condition won't met and will not be a problem.
It is required for MMC-over-SPI support. Linux MMC_SPI driver sometimes
(depending on some logic) want chip-select to be kept enabled (using
transfer.cs_change) even at the end of SPI message so that following
message(s) can also be made part of the running MMC transaction.
In this case if there is any error (and in some other cases as well)
MMC_SPI will have to terminate on-going MMC transactions and it is
done by calling setup(). It is assumed that setup() will always leave
the chip-select deactivated.
Reference from drivers/mmc/host/mmc_spi.c:
---
/*
* MMC-over-SPI protocol glue, used by the MMC stack interface
*/
static inline int mmc_cs_off(struct mmc_spi_host *host)
{
/* chipselect will always be inactive after setup() */
return spi_setup(host->spi);
}
Best thing I can add is wait for unprepare_message() before calling
cleanup().
If you could suggest better alternative that will be great.
Re: [PATCH v4 2/2] spi: spi-pic32: Add PIC32 SPI master driver
On 03/29/2016 12:56 AM, Mark Brown wrote:
> On Wed, Mar 23, 2016 at 07:12:56PM +0530, Purna Chandra Mandal wrote:
>
>> +switch (bits_per_word) {
>> +default:
>> +case 8:
> Are you sure that all bits per word settings other than those explicitly
> supported should be handled in exactly the same fashion as 8 bits per
> word? That doesn't seem entirely expected. I'd expect the default to
> be to return an error.
ack. Will treat default case as error.
>> +static int pic32_spi_prepare_message(struct spi_master *master,
>> + struct spi_message *msg)
>> +{
>> +struct spi_device *spi = msg->spi;
>> +struct spi_transfer *xfer;
>> +struct pic32_spi *pic32s;
>> +
>> +pic32s = spi_master_get_devdata(master);
>> +
>> +pic32s->mesg = msg;
>> +pic32_spi_disable_chip(pic32s);
>> +
>> +if (!pic32_spi_debug)
>> +return 0;
> This appears to be some half implemented debugging code which is never
> enabled, please remove it.
ack. Will remove the debug logic.
>> +list_for_each_entry(xfer, >transfers, transfer_list) {
>> +dev_dbg(>dev, " xfer %p: len %u tx %p rx %p\n",
>> +xfer, xfer->len, xfer->tx_buf, xfer->rx_buf);
>> +print_hex_dump(KERN_DEBUG, "tx_buf ",
>> + DUMP_PREFIX_ADDRESS,
>> + 16, 1, xfer->tx_buf,
>> + min_t(u32, xfer->len, 16), 1);
>> +}
> Similarly here, the core already has extensive trace stuff in it which
> you can use.
Will remove.
>> +/* transact by DMA mode */
>> +if (transfer->rx_sg.nents && transfer->tx_sg.nents) {
>> +ret = pic32_spi_dma_transfer(pic32s, transfer);
>> +if (ret) {
>> +dev_err(>dev, "dma submit error\n");
>> +return ret;
>> +}
>> +
>> +/* DMA issued, wait for completion */
>> +set_bit(PIC32F_DMA_ISSUED, >flags);
>> +goto out_wait_for_xfer;
>> +}
> ...
>
>> +
>> +out_wait_for_xfer:
> Please write normal code with an if/else rather than using gotos, it's a
> lot easier to follow.
Make sense. Will use if-else.
>> +pic32s = spi_master_get_devdata(master);
>> +
>> +pic32_spi_disable_chip(pic32s);
> Do we really need tod isable the hardware after every single message?
> It's normally more efficient to just leave the hardware powered until it
> goes idle and unprepare_transfer_hardware() is called.
>
Ack. There is no particular need to disable h/w per message.
Will instead implement prepare/unprepare_transfer_hardware() and add there.
>> +/* SPI master supports only one spi-device at a time.
>> + * So multiple spi_setup() to different devices is not allowed.
>> + */
>> +if (unlikely(pic32s->spi_dev && (pic32s->spi_dev != spi))) {
> unlikely() is for fast paths, outside of them it's just noise.
ack.
>> +/* But spi_setup() can be called multiple times by same device.
>> + * In that case stop current on-going transaction and release
>> + * resource(s).
>> + */
>> +if (pic32s->spi_dev == spi)
>> +pic32_spi_cleanup(spi);
> This is broken, it will break in progress transfers. setup() shouldn't
> be doing anything that disrupts them, anything that can't be run when
> other transfers are in progress needs to be deferred till we actually do
> the transfers (or done earlier in probe).
Normally setup() and cleanup() are called in-pair by spi-client driver.
In these cases the above condition won't met and will not be a problem.
It is required for MMC-over-SPI support. Linux MMC_SPI driver sometimes
(depending on some logic) want chip-select to be kept enabled (using
transfer.cs_change) even at the end of SPI message so that following
message(s) can also be made part of the running MMC transaction.
In this case if there is any error (and in some other cases as well)
MMC_SPI will have to terminate on-going MMC transactions and it is
done by calling setup(). It is assumed that setup() will always leave
the chip-select deactivated.
Reference from drivers/mmc/host/mmc_spi.c:
---
/*
* MMC-over-SPI protocol glue, used by the MMC stack interface
*/
static inline int mmc_cs_off(struct mmc_spi_host *host)
{
/* chipselect will always be inactive after setup() */
return spi_setup(host->spi);
}
Best thing I can add is wait for unprepare_message() before calling
cleanup().
If you could suggest better alternative that will be great.
[PATCH v4 1/2] dt/bindings: Add bindings for PIC32 SPI peripheral
Document the devicetree bindings for the SPI peripheral found
on Microchip PIC32 class devices.
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
Acked-by: Rob Herring <r...@kernel.org>
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- fix indentation
- add space after comma
- moved 'cs-gpios' section under 'required' properties.
.../bindings/spi/microchip,spi-pic32.txt | 34 ++
1 file changed, 34 insertions(+)
create mode 100644
Documentation/devicetree/bindings/spi/microchip,spi-pic32.txt
diff --git a/Documentation/devicetree/bindings/spi/microchip,spi-pic32.txt
b/Documentation/devicetree/bindings/spi/microchip,spi-pic32.txt
new file mode 100644
index 000..79de379f
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/microchip,spi-pic32.txt
@@ -0,0 +1,34 @@
+Microchip PIC32 SPI Master controller
+
+Required properties:
+- compatible: Should be "microchip,pic32mzda-spi".
+- reg: Address and length of register space for the device.
+- interrupts: Should contain all three spi interrupts in sequence
+ of , , .
+- interrupt-names: Should be "fault", "rx", "tx" in order.
+- clocks: Phandle of the clock generating SPI clock on the bus.
+- clock-names: Should be "mck0".
+- cs-gpios: Specifies the gpio pins to be used for chipselects.
+See: Documentation/devicetree/bindings/spi/spi-bus.txt
+
+Optional properties:
+- dmas: Two or more DMA channel specifiers following the convention outlined
+in Documentation/devicetree/bindings/dma/dma.txt
+- dma-names: Names for the dma channels. There must be at least one channel
+ named "spi-tx" for transmit and named "spi-rx" for receive.
+
+Example:
+
+spi1: spi@1f821000 {
+compatible = "microchip,pic32mzda-spi";
+reg = <0x1f821000 0x200>;
+interrupts = <109 IRQ_TYPE_LEVEL_HIGH>,
+ <110 IRQ_TYPE_LEVEL_HIGH>,
+ <111 IRQ_TYPE_LEVEL_HIGH>;
+interrupt-names = "fault", "rx", "tx";
+clocks = <>;
+clock-names = "mck0";
+cs-gpios = < 4 GPIO_ACTIVE_LOW>;
+dmas = < 134>, < 135>;
+dma-names = "spi-rx", "spi-tx";
+};
--
1.8.3.1
[PATCH v4 1/2] dt/bindings: Add bindings for PIC32 SPI peripheral
Document the devicetree bindings for the SPI peripheral found
on Microchip PIC32 class devices.
Signed-off-by: Purna Chandra Mandal
Acked-by: Rob Herring
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- fix indentation
- add space after comma
- moved 'cs-gpios' section under 'required' properties.
.../bindings/spi/microchip,spi-pic32.txt | 34 ++
1 file changed, 34 insertions(+)
create mode 100644
Documentation/devicetree/bindings/spi/microchip,spi-pic32.txt
diff --git a/Documentation/devicetree/bindings/spi/microchip,spi-pic32.txt
b/Documentation/devicetree/bindings/spi/microchip,spi-pic32.txt
new file mode 100644
index 000..79de379f
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/microchip,spi-pic32.txt
@@ -0,0 +1,34 @@
+Microchip PIC32 SPI Master controller
+
+Required properties:
+- compatible: Should be "microchip,pic32mzda-spi".
+- reg: Address and length of register space for the device.
+- interrupts: Should contain all three spi interrupts in sequence
+ of , , .
+- interrupt-names: Should be "fault", "rx", "tx" in order.
+- clocks: Phandle of the clock generating SPI clock on the bus.
+- clock-names: Should be "mck0".
+- cs-gpios: Specifies the gpio pins to be used for chipselects.
+See: Documentation/devicetree/bindings/spi/spi-bus.txt
+
+Optional properties:
+- dmas: Two or more DMA channel specifiers following the convention outlined
+in Documentation/devicetree/bindings/dma/dma.txt
+- dma-names: Names for the dma channels. There must be at least one channel
+ named "spi-tx" for transmit and named "spi-rx" for receive.
+
+Example:
+
+spi1: spi@1f821000 {
+compatible = "microchip,pic32mzda-spi";
+reg = <0x1f821000 0x200>;
+interrupts = <109 IRQ_TYPE_LEVEL_HIGH>,
+ <110 IRQ_TYPE_LEVEL_HIGH>,
+ <111 IRQ_TYPE_LEVEL_HIGH>;
+interrupt-names = "fault", "rx", "tx";
+clocks = <>;
+clock-names = "mck0";
+cs-gpios = < 4 GPIO_ACTIVE_LOW>;
+dmas = < 134>, < 135>;
+dma-names = "spi-rx", "spi-tx";
+};
--
1.8.3.1
[PATCH v4 2/2] spi: spi-pic32: Add PIC32 SPI master driver
The PIC32 SPI driver is capable of performing SPI transfers
using PIO or external DMA engine. GPIO controlled /CS support
is made default in the driver for correct operation of the
controller. This can be enabled by adding "cs-gpios" property
of the SPI node in board dts file.
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
---
Changes in v4:
- report error and bailout in case of missing irq(s).
- remove fallback to PIO mode in case of failure in DMA transfer.
- remove polling based PIO completely.
- drop spinlock
- update error message and comments.
Changes in v3:
- drop 'owner' field in driver struct.
- fix compilation warning in dma_addr_t print.
Changes in v2:
- drop internal function drain_rx_fifo()
- merge wrapper functions with callers wherever applicable
- sort includes alphabetically
- Kconfig: sort SPI_PIC32 alphabetically and add || COMPILE_TEST
- Makefile: sort SPI_PIC32 alphabetically
- replace cpu_relax() with ndelay() in disable_chip()
- drop spi controller driven /CS management completely, use only
GPIO controller /CS.
- rename function names starting with 'spi' to avoid namespace conflict
- use .one_transfer() callback instead of .one_message().
- drop /CS assert-deassert functions as core provides those.
- fix race while completing transfer before disabling interrupt.
drivers/spi/Kconfig | 6 +
drivers/spi/Makefile| 1 +
drivers/spi/spi-pic32.c | 958
3 files changed, 965 insertions(+)
create mode 100644 drivers/spi/spi-pic32.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 7706416..22f973f 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -396,6 +396,12 @@ config SPI_ORION
help
This enables using the SPI master controller on the Orion chips.
+config SPI_PIC32
+ tristate "Microchip PIC32 series SPI"
+ depends on MACH_PIC32 || COMPILE_TEST
+ help
+ SPI driver for Microchip PIC32 SPI master controller.
+
config SPI_PL022
tristate "ARM AMBA PL022 SSP controller"
depends on ARM_AMBA
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 8991ffc..1bcb417 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -60,6 +60,7 @@ obj-$(CONFIG_SPI_OMAP_100K) += spi-omap-100k.o
obj-$(CONFIG_SPI_OMAP24XX) += spi-omap2-mcspi.o
obj-$(CONFIG_SPI_TI_QSPI) += spi-ti-qspi.o
obj-$(CONFIG_SPI_ORION)+= spi-orion.o
+obj-$(CONFIG_SPI_PIC32)+= spi-pic32.o
obj-$(CONFIG_SPI_PL022)+= spi-pl022.o
obj-$(CONFIG_SPI_PPC4xx) += spi-ppc4xx.o
spi-pxa2xx-platform-objs := spi-pxa2xx.o
diff --git a/drivers/spi/spi-pic32.c b/drivers/spi/spi-pic32.c
new file mode 100644
index 000..78776f1
--- /dev/null
+++ b/drivers/spi/spi-pic32.c
@@ -0,0 +1,958 @@
+/*
+ * Microchip PIC32 SPI controller driver.
+ *
+ * Purna Chandra Mandal <purna.man...@microchip.com>
+ * Copyright (c) 2016, Microchip Technology Inc.
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* SPI controller registers */
+struct pic32_spi_regs {
+ u32 ctrl;
+ u32 ctrl_clr;
+ u32 ctrl_set;
+ u32 ctrl_inv;
+ u32 status;
+ u32 status_clr;
+ u32 status_set;
+ u32 status_inv;
+ u32 buf;
+ u32 dontuse[3];
+ u32 baud;
+ u32 dontuse2[3];
+ u32 ctrl2;
+ u32 ctrl2_clr;
+ u32 ctrl2_set;
+ u32 ctrl2_inv;
+};
+
+/* Bit fields in SPI Control Register */
+#define CTRL_RX_INT_SHIFT 0 /* Rx interrupt generation */
+#define RX_FIFO_EMTPY 0
+#define RX_FIFO_NOT_EMPTY 1 /* not empty */
+#define RX_FIFO_HALF_FULL 2 /* full by half or more */
+#define RX_FIFO_FULL 3 /* completely full */
+
+#define CTRL_TX_INT_SHIFT 2 /* TX interrupt generation */
+#define TX_FIFO_ALL_EMPTY 0 /* completely empty */
+#define TX_FIFO_EMTPY 1 /* empty */
+#define TX_FIFO_HALF_EMPTY2 /* empty by half or more */
+#define TX_FIFO_NOT_FULL 3 /* atleast one empty */
+
+#define CTRL_MSTEN BIT(5) /* enable master mode */
+#define CTRL_CKP BIT(6) /* active low */
+#define CTRL_CKE BIT(8) /* Tx on falling edge */
+#define CTRL_SMP BIT(9) /* Rx at middle or end of tx */
+#define CTRL_BPW_MASK
[PATCH v4 2/2] spi: spi-pic32: Add PIC32 SPI master driver
The PIC32 SPI driver is capable of performing SPI transfers
using PIO or external DMA engine. GPIO controlled /CS support
is made default in the driver for correct operation of the
controller. This can be enabled by adding "cs-gpios" property
of the SPI node in board dts file.
Signed-off-by: Purna Chandra Mandal
---
Changes in v4:
- report error and bailout in case of missing irq(s).
- remove fallback to PIO mode in case of failure in DMA transfer.
- remove polling based PIO completely.
- drop spinlock
- update error message and comments.
Changes in v3:
- drop 'owner' field in driver struct.
- fix compilation warning in dma_addr_t print.
Changes in v2:
- drop internal function drain_rx_fifo()
- merge wrapper functions with callers wherever applicable
- sort includes alphabetically
- Kconfig: sort SPI_PIC32 alphabetically and add || COMPILE_TEST
- Makefile: sort SPI_PIC32 alphabetically
- replace cpu_relax() with ndelay() in disable_chip()
- drop spi controller driven /CS management completely, use only
GPIO controller /CS.
- rename function names starting with 'spi' to avoid namespace conflict
- use .one_transfer() callback instead of .one_message().
- drop /CS assert-deassert functions as core provides those.
- fix race while completing transfer before disabling interrupt.
drivers/spi/Kconfig | 6 +
drivers/spi/Makefile| 1 +
drivers/spi/spi-pic32.c | 958
3 files changed, 965 insertions(+)
create mode 100644 drivers/spi/spi-pic32.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 7706416..22f973f 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -396,6 +396,12 @@ config SPI_ORION
help
This enables using the SPI master controller on the Orion chips.
+config SPI_PIC32
+ tristate "Microchip PIC32 series SPI"
+ depends on MACH_PIC32 || COMPILE_TEST
+ help
+ SPI driver for Microchip PIC32 SPI master controller.
+
config SPI_PL022
tristate "ARM AMBA PL022 SSP controller"
depends on ARM_AMBA
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 8991ffc..1bcb417 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -60,6 +60,7 @@ obj-$(CONFIG_SPI_OMAP_100K) += spi-omap-100k.o
obj-$(CONFIG_SPI_OMAP24XX) += spi-omap2-mcspi.o
obj-$(CONFIG_SPI_TI_QSPI) += spi-ti-qspi.o
obj-$(CONFIG_SPI_ORION)+= spi-orion.o
+obj-$(CONFIG_SPI_PIC32)+= spi-pic32.o
obj-$(CONFIG_SPI_PL022)+= spi-pl022.o
obj-$(CONFIG_SPI_PPC4xx) += spi-ppc4xx.o
spi-pxa2xx-platform-objs := spi-pxa2xx.o
diff --git a/drivers/spi/spi-pic32.c b/drivers/spi/spi-pic32.c
new file mode 100644
index 000..78776f1
--- /dev/null
+++ b/drivers/spi/spi-pic32.c
@@ -0,0 +1,958 @@
+/*
+ * Microchip PIC32 SPI controller driver.
+ *
+ * Purna Chandra Mandal
+ * Copyright (c) 2016, Microchip Technology Inc.
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* SPI controller registers */
+struct pic32_spi_regs {
+ u32 ctrl;
+ u32 ctrl_clr;
+ u32 ctrl_set;
+ u32 ctrl_inv;
+ u32 status;
+ u32 status_clr;
+ u32 status_set;
+ u32 status_inv;
+ u32 buf;
+ u32 dontuse[3];
+ u32 baud;
+ u32 dontuse2[3];
+ u32 ctrl2;
+ u32 ctrl2_clr;
+ u32 ctrl2_set;
+ u32 ctrl2_inv;
+};
+
+/* Bit fields in SPI Control Register */
+#define CTRL_RX_INT_SHIFT 0 /* Rx interrupt generation */
+#define RX_FIFO_EMTPY 0
+#define RX_FIFO_NOT_EMPTY 1 /* not empty */
+#define RX_FIFO_HALF_FULL 2 /* full by half or more */
+#define RX_FIFO_FULL 3 /* completely full */
+
+#define CTRL_TX_INT_SHIFT 2 /* TX interrupt generation */
+#define TX_FIFO_ALL_EMPTY 0 /* completely empty */
+#define TX_FIFO_EMTPY 1 /* empty */
+#define TX_FIFO_HALF_EMPTY2 /* empty by half or more */
+#define TX_FIFO_NOT_FULL 3 /* atleast one empty */
+
+#define CTRL_MSTEN BIT(5) /* enable master mode */
+#define CTRL_CKP BIT(6) /* active low */
+#define CTRL_CKE BIT(8) /* Tx on falling edge */
+#define CTRL_SMP BIT(9) /* Rx at middle or end of tx */
+#define CTRL_BPW_MASK 0x03 /* bits per word/sample */
+#define CTRL_BPW_SHIFT 10
+#define PIC32_BP
[PATCH v10 3/3] MIPS: dts: pic32: Update dts to reflect new PIC32MZDA clk binding
- now clock nodes definition is merged with core .dtsi file
- only one rootclk is now part of DT
- clock clients also updated based on new binding doc
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
Note: Please pull this complete series through the MIPS tree.
---
Changes in v10: None
Changes in v9: None
Changes in v8: None
Changes in v7:
- now clock nodes definition is merged with core .dtsi file
- only one rootclk is now part of DT
- clock clients also updated based on new binding doc
Changes in v6: None
Changes in v3: None
Changes in v2: None
---
arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi | 236
arch/mips/boot/dts/pic32/pic32mzda.dtsi | 63 +---
arch/mips/boot/dts/pic32/pic32mzda_sk.dts | 5 +-
3 files changed, 45 insertions(+), 259 deletions(-)
delete mode 100644 arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi
diff --git a/arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi
b/arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi
deleted file mode 100644
index ef13350..000
--- a/arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi
+++ /dev/null
@@ -1,236 +0,0 @@
-/*
- * Device Tree Source for PIC32MZDA clock data
- *
- * Purna Chandra Mandal <purna.man...@microchip.com>
- * Copyright (C) 2015 Microchip Technology Inc. All rights reserved.
- *
- * Licensed under GPLv2 or later.
- */
-
-/* all fixed rate clocks */
-
-/ {
- POSC:posc_clk { /* On-chip primary oscillator */
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <2400>;
- };
-
- FRC:frc_clk { /* internal FRC oscillator */
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <800>;
- };
-
- BFRC:bfrc_clk { /* internal backup FRC oscillator */
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <800>;
- };
-
- LPRC:lprc_clk { /* internal low-power FRC oscillator */
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32000>;
- };
-
- /* UPLL provides clock to USBCORE */
- UPLL:usb_phy_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <2400>;
- clock-output-names = "usbphy_clk";
- };
-
- TxCKI:txcki_clk { /* external clock input on TxCLKI pin */
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <400>;
- status = "disabled";
- };
-
- /* external clock input on REFCLKIx pin */
- REFIx:refix_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <2400>;
- status = "disabled";
- };
-
- /* PIC32 specific clks */
- pic32_clktree {
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x1f801200 0x200>;
- compatible = "microchip,pic32mzda-clk";
- ranges = <0 0x1f801200 0x200>;
-
- /* secondary oscillator; external input on SOSCI pin */
- SOSC:sosc_clk@0 {
- #clock-cells = <0>;
- compatible = "microchip,pic32mzda-sosc";
- clock-frequency = <32768>;
- reg = <0x000 0x10>, /* enable reg */
- <0x1d0 0x10>; /* status reg */
- microchip,bit-mask = <0x02>; /* enable mask */
- microchip,status-bit-mask = <0x10>; /* status-mask*/
- };
-
- FRCDIV:frcdiv_clk {
- #clock-cells = <0>;
- compatible = "microchip,pic32mzda-frcdivclk";
- clocks = <>;
- clock-output-names = "frcdiv_clk";
- };
-
- /* System PLL clock */
- SYSPLL:spll_clk@020 {
- #clock-cells = <0>;
- compatible = "microchip,pic32mzda-syspll";
- reg = <0x020 0x10>, /* SPLL register */
- <0x1d0 0x10>; /* CLKSTAT register */
- clocks = <>, <>;
- clock-output-names = "sys_pll";
- microchip,status-bit-mask = <0x80>; /* SPLLRDY */
- };
-
- /* system clock; mux with postdiv & slew *
[PATCH v10 3/3] MIPS: dts: pic32: Update dts to reflect new PIC32MZDA clk binding
- now clock nodes definition is merged with core .dtsi file
- only one rootclk is now part of DT
- clock clients also updated based on new binding doc
Signed-off-by: Purna Chandra Mandal
Note: Please pull this complete series through the MIPS tree.
---
Changes in v10: None
Changes in v9: None
Changes in v8: None
Changes in v7:
- now clock nodes definition is merged with core .dtsi file
- only one rootclk is now part of DT
- clock clients also updated based on new binding doc
Changes in v6: None
Changes in v3: None
Changes in v2: None
---
arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi | 236
arch/mips/boot/dts/pic32/pic32mzda.dtsi | 63 +---
arch/mips/boot/dts/pic32/pic32mzda_sk.dts | 5 +-
3 files changed, 45 insertions(+), 259 deletions(-)
delete mode 100644 arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi
diff --git a/arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi
b/arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi
deleted file mode 100644
index ef13350..000
--- a/arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi
+++ /dev/null
@@ -1,236 +0,0 @@
-/*
- * Device Tree Source for PIC32MZDA clock data
- *
- * Purna Chandra Mandal
- * Copyright (C) 2015 Microchip Technology Inc. All rights reserved.
- *
- * Licensed under GPLv2 or later.
- */
-
-/* all fixed rate clocks */
-
-/ {
- POSC:posc_clk { /* On-chip primary oscillator */
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <2400>;
- };
-
- FRC:frc_clk { /* internal FRC oscillator */
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <800>;
- };
-
- BFRC:bfrc_clk { /* internal backup FRC oscillator */
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <800>;
- };
-
- LPRC:lprc_clk { /* internal low-power FRC oscillator */
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32000>;
- };
-
- /* UPLL provides clock to USBCORE */
- UPLL:usb_phy_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <2400>;
- clock-output-names = "usbphy_clk";
- };
-
- TxCKI:txcki_clk { /* external clock input on TxCLKI pin */
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <400>;
- status = "disabled";
- };
-
- /* external clock input on REFCLKIx pin */
- REFIx:refix_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <2400>;
- status = "disabled";
- };
-
- /* PIC32 specific clks */
- pic32_clktree {
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x1f801200 0x200>;
- compatible = "microchip,pic32mzda-clk";
- ranges = <0 0x1f801200 0x200>;
-
- /* secondary oscillator; external input on SOSCI pin */
- SOSC:sosc_clk@0 {
- #clock-cells = <0>;
- compatible = "microchip,pic32mzda-sosc";
- clock-frequency = <32768>;
- reg = <0x000 0x10>, /* enable reg */
- <0x1d0 0x10>; /* status reg */
- microchip,bit-mask = <0x02>; /* enable mask */
- microchip,status-bit-mask = <0x10>; /* status-mask*/
- };
-
- FRCDIV:frcdiv_clk {
- #clock-cells = <0>;
- compatible = "microchip,pic32mzda-frcdivclk";
- clocks = <>;
- clock-output-names = "frcdiv_clk";
- };
-
- /* System PLL clock */
- SYSPLL:spll_clk@020 {
- #clock-cells = <0>;
- compatible = "microchip,pic32mzda-syspll";
- reg = <0x020 0x10>, /* SPLL register */
- <0x1d0 0x10>; /* CLKSTAT register */
- clocks = <>, <>;
- clock-output-names = "sys_pll";
- microchip,status-bit-mask = <0x80>; /* SPLLRDY */
- };
-
- /* system clock; mux with postdiv & slew */
- SYSCLK:sys_clk@1c0 {
- #clock-ce
[PATCH v10 2/3] clk: microchip: Add PIC32 clock driver
This clock driver implements PIC32 specific clock-tree. clock-tree entities can only be configured through device-tree file (OF). Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com> Note: Please pull this complete series through the MIPS tree. --- Changes in v10: - drop early clock init of CLK_OF_DECLARE way. - complete clock registration as platform_driver. Changes in v9: - split clock registration in two parts, cpu clock (& required parents) as part of CLK_OF_DECLARE and remaining as part of platform_driver. Changes in v8: - Remove .round_rate from clk_ops - Fix rework bug "of_clk_src_onecell_get: invalid clock index 20" Changes in v7: - Reworked PIC32 clock driver based on review. - PIC32 clock driver now separate core functionality from platform specific clock-submodule binding/hierarchy. - moved PIC32 driver under clk/microchip/ - core clk functionality now in clk/microchip/clk-core.c - driver now doesn't use device-tree for clock submodules. - platform now statically defines clock submodule data-structures and bind them accordingly. Changes in v6: - sort linux includes and asm includes. - use BIT() wherever applicable - drop 'microchip,ignore-unused' usage, handling in favor of critical clock - drop 'fixed divider' handling for periph clock - drop use of 'debug_init()' clk operation callback for register dump - drop clk_lock(), clk_unlock() spinlock wrapper - drop unimplemented pic32_devcon_syslock() macro - use readl()/writel() instead of clk_readl()/clk_writel() - drop redundant spinlock, unlock calls in sosc_clk_enable()/disable() - use CLK_SET_RATE_GATE, _SET_PARENT_GATE for refo-clocks - use kcalloc() instead of kmalloc() wherever applicable - use of_io_request_and_map() in soc_clock_init() - drop use of pbclk(/roclk)_endisable() inline function - use readl_poll_timeout_atomic() for wait_for_bit() type loop - drop cpu_relax() after clk gating - promote u8, u16 to u32 wherever applicable - fix sosc clock status polling - drop memory alloc from pic32_of_clk_get_parent_indices() instead callers will supply buffer to hold output parent indices - reword comments about spll_clk_set_rate() pre-conditions - drop use of CLK_BASIC wherever applicable - reword comments in sclk_set_parent() Changes in v3: - Replace __clk_debug with pr_debug - Add of_clk_parent_fill usage in PIC32 clock driver Changes in v2: - Remove unused PIC32 MPLL support. - Remove support for initializing default parent/rate for REFOSC clocks. --- drivers/clk/Kconfig | 3 + drivers/clk/Makefile | 1 + drivers/clk/microchip/Makefile| 2 + drivers/clk/microchip/clk-core.c | 954 ++ drivers/clk/microchip/clk-core.h | 78 +++ drivers/clk/microchip/clk-pic32mzda.c | 240 + 6 files changed, 1278 insertions(+) create mode 100644 drivers/clk/microchip/Makefile create mode 100644 drivers/clk/microchip/clk-core.c create mode 100644 drivers/clk/microchip/clk-core.h create mode 100644 drivers/clk/microchip/clk-pic32mzda.c diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index eca8e01..41e9c14 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -200,6 +200,9 @@ config COMMON_CLK_CDCE706 ---help--- This driver supports TI CDCE706 programmable 3-PLL clock synthesizer. +config COMMON_CLK_PIC32 + def_bool COMMON_CLK && MACH_PIC32 + source "drivers/clk/bcm/Kconfig" source "drivers/clk/hisilicon/Kconfig" source "drivers/clk/qcom/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index bae4be6..976188e 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -58,6 +58,7 @@ obj-$(CONFIG_ARCH_MXC)+= imx/ obj-$(CONFIG_MACH_INGENIC) += ingenic/ obj-$(CONFIG_COMMON_CLK_KEYSTONE) += keystone/ obj-$(CONFIG_ARCH_MEDIATEK)+= mediatek/ +obj-$(CONFIG_MACH_PIC32) += microchip/ ifeq ($(CONFIG_COMMON_CLK), y) obj-$(CONFIG_ARCH_MMP) += mmp/ endif diff --git a/drivers/clk/microchip/Makefile b/drivers/clk/microchip/Makefile new file mode 100644 index 000..2152f41 --- /dev/null +++ b/drivers/clk/microchip/Makefile @@ -0,0 +1,2 @@ +obj-$(CONFIG_COMMON_CLK_PIC32) += clk-core.o +obj-$(CONFIG_PIC32MZDA) += clk-pic32mzda.o diff --git a/drivers/clk/microchip/clk-core.c b/drivers/clk/microchip/clk-core.c new file mode 100644 index 000..62cda93 --- /dev/null +++ b/drivers/clk/microchip/clk-core.c @@ -0,0 +1,954 @@ +/* + * Purna Chandra Mandal,<purna.man...@microchip.com> + * C
[PATCH v10 0/3] PIC32MZDA Clock Driver
Clock bindings got acked and then essentially unacked, while the clock driver never made it upstream. In the meantime, the initial DTS file made it upstream. This latest patch series includes a patch to go back and correct the DTS files to reflect the new clock bindings in this patch series. Purna Chandra Mandal (3): dt/bindings: Add PIC32 clock binding documentation clk: microchip: Add PIC32 clock driver MIPS: dts: pic32: Update dts to reflect new PIC32MZDA clk binding .../devicetree/bindings/clock/microchip,pic32.txt | 39 + arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi| 236 - arch/mips/boot/dts/pic32/pic32mzda.dtsi| 63 +- arch/mips/boot/dts/pic32/pic32mzda_sk.dts | 5 +- drivers/clk/Kconfig| 3 + drivers/clk/Makefile | 1 + drivers/clk/microchip/Makefile | 2 + drivers/clk/microchip/clk-core.c | 954 + drivers/clk/microchip/clk-core.h | 78 ++ drivers/clk/microchip/clk-pic32mzda.c | 240 ++ include/dt-bindings/clock/microchip,pic32-clock.h | 42 + 11 files changed, 1404 insertions(+), 259 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/microchip,pic32.txt delete mode 100644 arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi create mode 100644 drivers/clk/microchip/Makefile create mode 100644 drivers/clk/microchip/clk-core.c create mode 100644 drivers/clk/microchip/clk-core.h create mode 100644 drivers/clk/microchip/clk-pic32mzda.c create mode 100644 include/dt-bindings/clock/microchip,pic32-clock.h -- 1.8.3.1
