RE: [PATCH v10 1/6] drivers/platform/x86/p2sb: New Primary to Sideband bridge support driver for Intel SOC's

2016-12-08 Thread Tan, Jui Nee 


> -Original Message-
> From: linux-gpio-ow...@vger.kernel.org [mailto:linux-gpio-
> ow...@vger.kernel.org] On Behalf Of Andy Shevchenko
> Sent: Friday, November 11, 2016 12:07 AM
> To: Tan, Jui Nee <jui.nee@intel.com>; mika.westerb...@linux.intel.com;
> heikki.kroge...@linux.intel.com; t...@linutronix.de; dvh...@infradead.org;
> mi...@redhat.com; h...@zytor.com; x...@kernel.org; pty...@xes-inc.com;
> lee.jo...@linaro.org; linus.wall...@linaro.org
> Cc: linux-g...@vger.kernel.org; platform-driver-...@vger.kernel.org;
> linux-kernel@vger.kernel.org; Yong, Jonathan <jonathan.y...@intel.com>;
> Yu, Ong Hock <ong.hock...@intel.com>; Luck, Tony <tony.l...@intel.com>;
> Wan Mohamad, Wan Ahmad Zainie <wan.ahmad.zainie.wan.moha...@intel.com>;
> Sun, Yunying <yunying@intel.com>
> Subject: Re: [PATCH v10 1/6] drivers/platform/x86/p2sb: New Primary to
> Sideband bridge support driver for Intel SOC's
> 
> On Thu, 2016-11-10 at 17:00 +0800, Tan Jui Nee wrote:
> > From: Andy Shevchenko <andriy.shevche...@linux.intel.com>
> >
> > There is already one and at least one more user coming which require
> > an access to Primary to Sideband bridge (P2SB) in order to get IO or
> > MMIO bar hidden by BIOS.
> > Create a driver to access P2SB for x86 devices.
> >
> > Signed-off-by: Yong, Jonathan <jonathan.y...@intel.com>
> > Signed-off-by: Andy Shevchenko <andriy.shevche...@linux.intel.com>
> 
> 
> > +int p2sb_bar(struct pci_dev *pdev, unsigned int devfn,
> > +   struct resource *res)
> > +{
> > +   u32 base_addr;
> > +   u64 base64_addr;
> > +   unsigned long flags;
> > +
> >
> 
> > +   if (!res)
> > +   return -EINVAL;
> 
> I don't remember the details, one version was quite changed, so, I think
> these lines are not needed anymore.
> 
Noted, these lines will be removed in next patch version (v12).
> > +   /* Get IO or MMIO BAR */
> > +   pci_bus_read_config_dword(pdev->bus, devfn, SBREG_BAR,
> > _addr);
> > +   if ((base_addr & PCI_BASE_ADDRESS_SPACE) ==
> > PCI_BASE_ADDRESS_SPACE_IO) {
> > +   flags = IORESOURCE_IO;
> > +   base64_addr = base_addr & PCI_BASE_ADDRESS_IO_MASK;
> > +   } else {
> > +   flags = IORESOURCE_MEM;
> > +   base64_addr = base_addr & PCI_BASE_ADDRESS_MEM_MASK;
> > +   if (base_addr & PCI_BASE_ADDRESS_MEM_TYPE_64) {
> > +   flags |= IORESOURCE_MEM_64;
> >
> 
> > +   pci_bus_read_config_dword(pdev->bus, devfn,
> > +   SBREG_BAR + 4, _addr);
> 
> Fix indentation.
> 
Thanks for pointing that out. I will fix that in next patch version (v12). 
> > +   base64_addr |= (u64)base_addr << 32;
> > +   }
> > +   }
> > +
> > +   /* Hide the P2SB device */
> > +   pci_bus_write_config_byte(pdev->bus, devfn, SBREG_HIDE,
> > 0x01);
> > +
> > +   spin_unlock(_spinlock);
> > +
> 
> > +   /* User provides prefilled resources */
> 
> Not anymore as far I as I can see. You just return here the result.
> 
Current version is returning status of p2sb_bar function, i.e., 0 on success or 
appropriate errno value on error. Perhaps you could share the reason of return 
the result instead of status. 
> > +   res->start = (resource_size_t)base64_addr;
> > +   res->flags = flags;
> 
> --
> Andy Shevchenko <andriy.shevche...@linux.intel.com>
> Intel Finland Oy
> --
> To unsubscribe from this list: send the line "unsubscribe linux-gpio" in
> the body of a message to majord...@vger.kernel.org More majordomo info at
> http://vger.kernel.org/majordomo-info.html

RE: [PATCH v10 1/6] drivers/platform/x86/p2sb: New Primary to Sideband bridge support driver for Intel SOC's

2016-12-08 Thread Tan, Jui Nee 


> -Original Message-
> From: linux-gpio-ow...@vger.kernel.org [mailto:linux-gpio-
> ow...@vger.kernel.org] On Behalf Of Andy Shevchenko
> Sent: Friday, November 11, 2016 12:07 AM
> To: Tan, Jui Nee ; mika.westerb...@linux.intel.com;
> heikki.kroge...@linux.intel.com; t...@linutronix.de; dvh...@infradead.org;
> mi...@redhat.com; h...@zytor.com; x...@kernel.org; pty...@xes-inc.com;
> lee.jo...@linaro.org; linus.wall...@linaro.org
> Cc: linux-g...@vger.kernel.org; platform-driver-...@vger.kernel.org;
> linux-kernel@vger.kernel.org; Yong, Jonathan ;
> Yu, Ong Hock ; Luck, Tony ;
> Wan Mohamad, Wan Ahmad Zainie ;
> Sun, Yunying 
> Subject: Re: [PATCH v10 1/6] drivers/platform/x86/p2sb: New Primary to
> Sideband bridge support driver for Intel SOC's
> 
> On Thu, 2016-11-10 at 17:00 +0800, Tan Jui Nee wrote:
> > From: Andy Shevchenko 
> >
> > There is already one and at least one more user coming which require
> > an access to Primary to Sideband bridge (P2SB) in order to get IO or
> > MMIO bar hidden by BIOS.
> > Create a driver to access P2SB for x86 devices.
> >
> > Signed-off-by: Yong, Jonathan 
> > Signed-off-by: Andy Shevchenko 
> 
> 
> > +int p2sb_bar(struct pci_dev *pdev, unsigned int devfn,
> > +   struct resource *res)
> > +{
> > +   u32 base_addr;
> > +   u64 base64_addr;
> > +   unsigned long flags;
> > +
> >
> 
> > +   if (!res)
> > +   return -EINVAL;
> 
> I don't remember the details, one version was quite changed, so, I think
> these lines are not needed anymore.
> 
Noted, these lines will be removed in next patch version (v12).
> > +   /* Get IO or MMIO BAR */
> > +   pci_bus_read_config_dword(pdev->bus, devfn, SBREG_BAR,
> > _addr);
> > +   if ((base_addr & PCI_BASE_ADDRESS_SPACE) ==
> > PCI_BASE_ADDRESS_SPACE_IO) {
> > +   flags = IORESOURCE_IO;
> > +   base64_addr = base_addr & PCI_BASE_ADDRESS_IO_MASK;
> > +   } else {
> > +   flags = IORESOURCE_MEM;
> > +   base64_addr = base_addr & PCI_BASE_ADDRESS_MEM_MASK;
> > +   if (base_addr & PCI_BASE_ADDRESS_MEM_TYPE_64) {
> > +   flags |= IORESOURCE_MEM_64;
> >
> 
> > +   pci_bus_read_config_dword(pdev->bus, devfn,
> > +   SBREG_BAR + 4, _addr);
> 
> Fix indentation.
> 
Thanks for pointing that out. I will fix that in next patch version (v12). 
> > +   base64_addr |= (u64)base_addr << 32;
> > +   }
> > +   }
> > +
> > +   /* Hide the P2SB device */
> > +   pci_bus_write_config_byte(pdev->bus, devfn, SBREG_HIDE,
> > 0x01);
> > +
> > +   spin_unlock(_spinlock);
> > +
> 
> > +   /* User provides prefilled resources */
> 
> Not anymore as far I as I can see. You just return here the result.
> 
Current version is returning status of p2sb_bar function, i.e., 0 on success or 
appropriate errno value on error. Perhaps you could share the reason of return 
the result instead of status. 
> > +   res->start = (resource_size_t)base64_addr;
> > +   res->flags = flags;
> 
> --
> Andy Shevchenko 
> Intel Finland Oy
> --
> To unsubscribe from this list: send the line "unsubscribe linux-gpio" in
> the body of a message to majord...@vger.kernel.org More majordomo info at
> http://vger.kernel.org/majordomo-info.html

RE: [PATCH v11 1/6] drivers/platform/x86/p2sb: New Primary to Sideband bridge support driver for Intel SOC's

2016-11-20 Thread Tan, Jui Nee 


> -Original Message-
> From: Andy Shevchenko [mailto:andriy.shevche...@linux.intel.com]
> Sent: Friday, November 18, 2016 7:22 PM
> To: Tan, Jui Nee <jui.nee@intel.com>; mika.westerb...@linux.intel.com;
> heikki.kroge...@linux.intel.com; t...@linutronix.de; dvh...@infradead.org;
> mi...@redhat.com; h...@zytor.com; x...@kernel.org; pty...@xes-inc.com;
> lee.jo...@linaro.org; linus.wall...@linaro.org
> Cc: linux-g...@vger.kernel.org; platform-driver-...@vger.kernel.org;
> linux-kernel@vger.kernel.org; Yong, Jonathan <jonathan.y...@intel.com>;
> Yu, Ong Hock <ong.hock...@intel.com>; Luck, Tony <tony.l...@intel.com>;
> Wan Mohamad, Wan Ahmad Zainie <wan.ahmad.zainie.wan.moha...@intel.com>;
> Sun, Yunying <yunying@intel.com>
> Subject: Re: [PATCH v11 1/6] drivers/platform/x86/p2sb: New Primary to
> Sideband bridge support driver for Intel SOC's
> 
> On Fri, 2016-11-18 at 13:22 +0800, Tan Jui Nee wrote:
> > From: Andy Shevchenko <andriy.shevche...@linux.intel.com>
> >
> > There is already one and at least one more user coming which require
> > an access to Primary to Sideband bridge (P2SB) in order to get IO or
> > MMIO bar hidden by BIOS.
> > Create a driver to access P2SB for x86 devices.
> >
> > Signed-off-by: Yong, Jonathan <jonathan.y...@intel.com>
> > Signed-off-by: Andy Shevchenko <andriy.shevche...@linux.intel.com>
> > ---
> > Changes in V11:
> > - No change
> 
> Any particular reason you ignored my comments to v10 of this patch?
>
Hi Andy,
I am sorry for missing your comments as the email filtered into other folder 
and I was not aware of that. I will applied your comments into next patch 
version.
 
> --
> Andy Shevchenko <andriy.shevche...@linux.intel.com>
> Intel Finland Oy

RE: [PATCH v11 1/6] drivers/platform/x86/p2sb: New Primary to Sideband bridge support driver for Intel SOC's

2016-11-20 Thread Tan, Jui Nee 


> -Original Message-
> From: Andy Shevchenko [mailto:andriy.shevche...@linux.intel.com]
> Sent: Friday, November 18, 2016 7:22 PM
> To: Tan, Jui Nee ; mika.westerb...@linux.intel.com;
> heikki.kroge...@linux.intel.com; t...@linutronix.de; dvh...@infradead.org;
> mi...@redhat.com; h...@zytor.com; x...@kernel.org; pty...@xes-inc.com;
> lee.jo...@linaro.org; linus.wall...@linaro.org
> Cc: linux-g...@vger.kernel.org; platform-driver-...@vger.kernel.org;
> linux-kernel@vger.kernel.org; Yong, Jonathan ;
> Yu, Ong Hock ; Luck, Tony ;
> Wan Mohamad, Wan Ahmad Zainie ;
> Sun, Yunying 
> Subject: Re: [PATCH v11 1/6] drivers/platform/x86/p2sb: New Primary to
> Sideband bridge support driver for Intel SOC's
> 
> On Fri, 2016-11-18 at 13:22 +0800, Tan Jui Nee wrote:
> > From: Andy Shevchenko 
> >
> > There is already one and at least one more user coming which require
> > an access to Primary to Sideband bridge (P2SB) in order to get IO or
> > MMIO bar hidden by BIOS.
> > Create a driver to access P2SB for x86 devices.
> >
> > Signed-off-by: Yong, Jonathan 
> > Signed-off-by: Andy Shevchenko 
> > ---
> > Changes in V11:
> > - No change
> 
> Any particular reason you ignored my comments to v10 of this patch?
>
Hi Andy,
I am sorry for missing your comments as the email filtered into other folder 
and I was not aware of that. I will applied your comments into next patch 
version.
 
> --
> Andy Shevchenko 
> Intel Finland Oy

[PATCH v11 1/6] drivers/platform/x86/p2sb: New Primary to Sideband bridge support driver for Intel SOC's

2016-11-17 Thread Tan Jui Nee 
From: Andy Shevchenko 

There is already one and at least one more user coming which
require an access to Primary to Sideband bridge (P2SB) in order
to get IO or MMIO bar hidden by BIOS.
Create a driver to access P2SB for x86 devices.

Signed-off-by: Yong, Jonathan 
Signed-off-by: Andy Shevchenko 
---
Changes in V11:
- No change

Changes in V10:
- Since P2SB is platform enablement driver and therefore should go into
  drivers/platform/x86 (suggested by tglx).

Changes in V9:
- No change

Changes in V8:
- No change

Changes in V7:
- EXPORT_SYMBOL_GPL() and MODULE_LICENSE("GPL v2") are used for new file
  p2sb.c.

Changes in V6:
- No change

Changes in V5:
- No change

Changes in V4:
- Move Kconfig option CONFIG_X86_INTEL_NON_ACPI from
  [PATCH 2/3] x86/platform/p2sb: New Primary to Sideband bridge support 
driver for Intel SOC's
  to
  [PATCH 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO 
pinctrl in non-ACPI system
  since the config is used in latter patch.

Changes in V3:
- No change

Changes in V2:
- Add new config option CONFIG_X86_INTEL_NON_ACPI and "select PINCTRL"
  to fix kbuildbot error

 arch/x86/include/asm/p2sb.h   | 27 
 drivers/platform/x86/Kconfig  |  4 ++
 drivers/platform/x86/Makefile |  1 +
 drivers/platform/x86/p2sb.c   | 98 +++
 4 files changed, 130 insertions(+)
 create mode 100644 arch/x86/include/asm/p2sb.h
 create mode 100644 drivers/platform/x86/p2sb.c

diff --git a/arch/x86/include/asm/p2sb.h b/arch/x86/include/asm/p2sb.h
new file mode 100644
index 000..686e07b
--- /dev/null
+++ b/arch/x86/include/asm/p2sb.h
@@ -0,0 +1,27 @@
+/*
+ * Primary to Sideband bridge (P2SB) access support
+ */
+
+#ifndef P2SB_SYMS_H
+#define P2SB_SYMS_H
+
+#include 
+#include 
+
+#if IS_ENABLED(CONFIG_P2SB)
+
+int p2sb_bar(struct pci_dev *pdev, unsigned int devfn,
+   struct resource *res);
+
+#else /* CONFIG_P2SB is not set */
+
+static inline
+int p2sb_bar(struct pci_dev *pdev, unsigned int devfn,
+   struct resource *res)
+{
+   return -ENODEV;
+}
+
+#endif /* CONFIG_P2SB */
+
+#endif /* P2SB_SYMS_H */
diff --git a/drivers/platform/x86/Kconfig b/drivers/platform/x86/Kconfig
index b8a21d7..65ef6a0 100644
--- a/drivers/platform/x86/Kconfig
+++ b/drivers/platform/x86/Kconfig
@@ -1027,4 +1027,8 @@ config INTEL_TELEMETRY
  used to get various SoC events and parameters
  directly via debugfs files. Various tools may use
  this interface for SoC state monitoring.
+
+config P2SB
+   tristate
+   depends on PCI
 endif # X86_PLATFORM_DEVICES
diff --git a/drivers/platform/x86/Makefile b/drivers/platform/x86/Makefile
index 2efa86d..c39a13d 100644
--- a/drivers/platform/x86/Makefile
+++ b/drivers/platform/x86/Makefile
@@ -71,3 +71,4 @@ obj-$(CONFIG_INTEL_TELEMETRY) += intel_telemetry_core.o \
   intel_telemetry_pltdrv.o \
   intel_telemetry_debugfs.o
 obj-$(CONFIG_INTEL_PMC_CORE)+= intel_pmc_core.o
+obj-$(CONFIG_P2SB) += p2sb.o
diff --git a/drivers/platform/x86/p2sb.c b/drivers/platform/x86/p2sb.c
new file mode 100644
index 000..b1d784c
--- /dev/null
+++ b/drivers/platform/x86/p2sb.c
@@ -0,0 +1,98 @@
+/*
+ * Primary to Sideband bridge (P2SB) driver
+ *
+ * Copyright (c) 2016, Intel Corporation.
+ *
+ * Authors: Andy Shevchenko 
+ * Jonathan Yong 
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#define SBREG_BAR  0x10
+#define SBREG_HIDE 0xe1
+
+static DEFINE_SPINLOCK(p2sb_spinlock);
+
+/*
+ * p2sb_bar - Get Primary to Sideband bridge (P2SB) BAR
+ * @pdev:  PCI device to get PCI bus to communicate with
+ * @devfn: PCI device and function to communicate with
+ * @res:   resources to be filled in
+ *
+ * The BIOS prevents the P2SB device from being enumerated by the PCI
+ * subsystem, so we need to unhide and hide it back to lookup the P2SB BAR.
+ *
+ * Locking is handled by spinlock - cannot sleep.
+ *
+ * Return:
+ * 0 on success or appropriate errno value on error.
+ */
+int p2sb_bar(struct pci_dev *pdev, unsigned int devfn,
+   struct resource *res)
+{
+   u32 base_addr;
+   u64 base64_addr;
+

[PATCH v11 1/6] drivers/platform/x86/p2sb: New Primary to Sideband bridge support driver for Intel SOC's

2016-11-17 Thread Tan Jui Nee 
From: Andy Shevchenko 

There is already one and at least one more user coming which
require an access to Primary to Sideband bridge (P2SB) in order
to get IO or MMIO bar hidden by BIOS.
Create a driver to access P2SB for x86 devices.

Signed-off-by: Yong, Jonathan 
Signed-off-by: Andy Shevchenko 
---
Changes in V11:
- No change

Changes in V10:
- Since P2SB is platform enablement driver and therefore should go into
  drivers/platform/x86 (suggested by tglx).

Changes in V9:
- No change

Changes in V8:
- No change

Changes in V7:
- EXPORT_SYMBOL_GPL() and MODULE_LICENSE("GPL v2") are used for new file
  p2sb.c.

Changes in V6:
- No change

Changes in V5:
- No change

Changes in V4:
- Move Kconfig option CONFIG_X86_INTEL_NON_ACPI from
  [PATCH 2/3] x86/platform/p2sb: New Primary to Sideband bridge support 
driver for Intel SOC's
  to
  [PATCH 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO 
pinctrl in non-ACPI system
  since the config is used in latter patch.

Changes in V3:
- No change

Changes in V2:
- Add new config option CONFIG_X86_INTEL_NON_ACPI and "select PINCTRL"
  to fix kbuildbot error

 arch/x86/include/asm/p2sb.h   | 27 
 drivers/platform/x86/Kconfig  |  4 ++
 drivers/platform/x86/Makefile |  1 +
 drivers/platform/x86/p2sb.c   | 98 +++
 4 files changed, 130 insertions(+)
 create mode 100644 arch/x86/include/asm/p2sb.h
 create mode 100644 drivers/platform/x86/p2sb.c

diff --git a/arch/x86/include/asm/p2sb.h b/arch/x86/include/asm/p2sb.h
new file mode 100644
index 000..686e07b
--- /dev/null
+++ b/arch/x86/include/asm/p2sb.h
@@ -0,0 +1,27 @@
+/*
+ * Primary to Sideband bridge (P2SB) access support
+ */
+
+#ifndef P2SB_SYMS_H
+#define P2SB_SYMS_H
+
+#include 
+#include 
+
+#if IS_ENABLED(CONFIG_P2SB)
+
+int p2sb_bar(struct pci_dev *pdev, unsigned int devfn,
+   struct resource *res);
+
+#else /* CONFIG_P2SB is not set */
+
+static inline
+int p2sb_bar(struct pci_dev *pdev, unsigned int devfn,
+   struct resource *res)
+{
+   return -ENODEV;
+}
+
+#endif /* CONFIG_P2SB */
+
+#endif /* P2SB_SYMS_H */
diff --git a/drivers/platform/x86/Kconfig b/drivers/platform/x86/Kconfig
index b8a21d7..65ef6a0 100644
--- a/drivers/platform/x86/Kconfig
+++ b/drivers/platform/x86/Kconfig
@@ -1027,4 +1027,8 @@ config INTEL_TELEMETRY
  used to get various SoC events and parameters
  directly via debugfs files. Various tools may use
  this interface for SoC state monitoring.
+
+config P2SB
+   tristate
+   depends on PCI
 endif # X86_PLATFORM_DEVICES
diff --git a/drivers/platform/x86/Makefile b/drivers/platform/x86/Makefile
index 2efa86d..c39a13d 100644
--- a/drivers/platform/x86/Makefile
+++ b/drivers/platform/x86/Makefile
@@ -71,3 +71,4 @@ obj-$(CONFIG_INTEL_TELEMETRY) += intel_telemetry_core.o \
   intel_telemetry_pltdrv.o \
   intel_telemetry_debugfs.o
 obj-$(CONFIG_INTEL_PMC_CORE)+= intel_pmc_core.o
+obj-$(CONFIG_P2SB) += p2sb.o
diff --git a/drivers/platform/x86/p2sb.c b/drivers/platform/x86/p2sb.c
new file mode 100644
index 000..b1d784c
--- /dev/null
+++ b/drivers/platform/x86/p2sb.c
@@ -0,0 +1,98 @@
+/*
+ * Primary to Sideband bridge (P2SB) driver
+ *
+ * Copyright (c) 2016, Intel Corporation.
+ *
+ * Authors: Andy Shevchenko 
+ * Jonathan Yong 
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#define SBREG_BAR  0x10
+#define SBREG_HIDE 0xe1
+
+static DEFINE_SPINLOCK(p2sb_spinlock);
+
+/*
+ * p2sb_bar - Get Primary to Sideband bridge (P2SB) BAR
+ * @pdev:  PCI device to get PCI bus to communicate with
+ * @devfn: PCI device and function to communicate with
+ * @res:   resources to be filled in
+ *
+ * The BIOS prevents the P2SB device from being enumerated by the PCI
+ * subsystem, so we need to unhide and hide it back to lookup the P2SB BAR.
+ *
+ * Locking is handled by spinlock - cannot sleep.
+ *
+ * Return:
+ * 0 on success or appropriate errno value on error.
+ */
+int p2sb_bar(struct pci_dev *pdev, unsigned int devfn,
+   struct resource *res)
+{
+   u32 base_addr;
+   u64 base64_addr;
+   unsigned long flags;
+
+   if (!res)
+   return -EINVAL;
+
+   spin_lock(_spinlock);
+
+   /* Unhide the P2SB device */
+

[PATCH v11 4/6] mfd: move enum lpc_chipsets into lpc_ich.h

2016-11-17 Thread Tan Jui Nee 
Move the enum's definition into a standalone header file which can be used
wherever its definition is needed.

Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
Reviewed-by: Mika Westerberg <mika.westerb...@linux.intel.com>
---
Changes in V11:
- No change

Changes in V10:
- No change

Changes in V9:
- No change

Changes in V8:
- No change

 drivers/mfd/lpc_ich_core.c  | 71 -
 include/linux/mfd/lpc_ich.h | 71 +
 2 files changed, 71 insertions(+), 71 deletions(-)

diff --git a/drivers/mfd/lpc_ich_core.c b/drivers/mfd/lpc_ich_core.c
index 7cbe037..920198a 100644
--- a/drivers/mfd/lpc_ich_core.c
+++ b/drivers/mfd/lpc_ich_core.c
@@ -145,77 +145,6 @@ struct lpc_ich_priv {
.ignore_resource_conflicts = true,
 };
 
-/* chipset related info */
-enum lpc_chipsets {
-   LPC_ICH = 0,/* ICH */
-   LPC_ICH0,   /* ICH0 */
-   LPC_ICH2,   /* ICH2 */
-   LPC_ICH2M,  /* ICH2-M */
-   LPC_ICH3,   /* ICH3-S */
-   LPC_ICH3M,  /* ICH3-M */
-   LPC_ICH4,   /* ICH4 */
-   LPC_ICH4M,  /* ICH4-M */
-   LPC_CICH,   /* C-ICH */
-   LPC_ICH5,   /* ICH5 & ICH5R */
-   LPC_6300ESB,/* 6300ESB */
-   LPC_ICH6,   /* ICH6 & ICH6R */
-   LPC_ICH6M,  /* ICH6-M */
-   LPC_ICH6W,  /* ICH6W & ICH6RW */
-   LPC_631XESB,/* 631xESB/632xESB */
-   LPC_ICH7,   /* ICH7 & ICH7R */
-   LPC_ICH7DH, /* ICH7DH */
-   LPC_ICH7M,  /* ICH7-M & ICH7-U */
-   LPC_ICH7MDH,/* ICH7-M DH */
-   LPC_NM10,   /* NM10 */
-   LPC_ICH8,   /* ICH8 & ICH8R */
-   LPC_ICH8DH, /* ICH8DH */
-   LPC_ICH8DO, /* ICH8DO */
-   LPC_ICH8M,  /* ICH8M */
-   LPC_ICH8ME, /* ICH8M-E */
-   LPC_ICH9,   /* ICH9 */
-   LPC_ICH9R,  /* ICH9R */
-   LPC_ICH9DH, /* ICH9DH */
-   LPC_ICH9DO, /* ICH9DO */
-   LPC_ICH9M,  /* ICH9M */
-   LPC_ICH9ME, /* ICH9M-E */
-   LPC_ICH10,  /* ICH10 */
-   LPC_ICH10R, /* ICH10R */
-   LPC_ICH10D, /* ICH10D */
-   LPC_ICH10DO,/* ICH10DO */
-   LPC_PCH,/* PCH Desktop Full Featured */
-   LPC_PCHM,   /* PCH Mobile Full Featured */
-   LPC_P55,/* P55 */
-   LPC_PM55,   /* PM55 */
-   LPC_H55,/* H55 */
-   LPC_QM57,   /* QM57 */
-   LPC_H57,/* H57 */
-   LPC_HM55,   /* HM55 */
-   LPC_Q57,/* Q57 */
-   LPC_HM57,   /* HM57 */
-   LPC_PCHMSFF,/* PCH Mobile SFF Full Featured */
-   LPC_QS57,   /* QS57 */
-   LPC_3400,   /* 3400 */
-   LPC_3420,   /* 3420 */
-   LPC_3450,   /* 3450 */
-   LPC_EP80579,/* EP80579 */
-   LPC_CPT,/* Cougar Point */
-   LPC_CPTD,   /* Cougar Point Desktop */
-   LPC_CPTM,   /* Cougar Point Mobile */
-   LPC_PBG,/* Patsburg */
-   LPC_DH89XXCC,   /* DH89xxCC */
-   LPC_PPT,/* Panther Point */
-   LPC_LPT,/* Lynx Point */
-   LPC_LPT_LP, /* Lynx Point-LP */
-   LPC_WBG,/* Wellsburg */
-   LPC_AVN,/* Avoton SoC */
-   LPC_BAYTRAIL,   /* Bay Trail SoC */
-   LPC_COLETO, /* Coleto Creek */
-   LPC_WPT_LP, /* Wildcat Point-LP */
-   LPC_BRASWELL,   /* Braswell SoC */
-   LPC_LEWISBURG,  /* Lewisburg */
-   LPC_9S, /* 9 Series */
-};
-
 static struct lpc_ich_info lpc_chipset_info[] = {
[LPC_ICH] = {
.name = "ICH",
diff --git a/include/linux/mfd/lpc_ich.h b/include/linux/mfd/lpc_ich.h
index 2b300b4..42307ee 100644
--- a/include/linux/mfd/lpc_ich.h
+++ b/include/linux/mfd/lpc_ich.h
@@ -43,4 +43,75 @@ struct lpc_ich_info {
u8 use_gpio;
 };
 
+/* chipset related info */
+enum lpc_chipsets {
+   LPC_ICH = 0,/* ICH */
+   LPC_ICH0,   /* ICH0 */
+   LPC_ICH2,   /* ICH2 */
+   LPC_ICH2M,  /* ICH2-M */
+   LPC_ICH3,   /* ICH3-S */
+   LPC_ICH3M,  /* ICH3-M */
+   LPC_ICH4,   /* ICH4 */
+   LPC_ICH4M,  /* ICH4-M */
+   LPC_CICH,   /* C-ICH */
+   LPC_ICH5,   /* ICH5 & ICH5R */
+   LPC_6300ESB,/* 6300ESB */
+   LPC_ICH6,   /* ICH6 & ICH6R */
+   LPC_ICH6M,  /* ICH6-M */
+   LPC_ICH6W,  /* ICH6W & ICH6RW */
+   LPC_631XESB,/* 631xESB/632xESB */
+   LPC_ICH7,   /* ICH7 & ICH7R */
+   LPC_ICH7DH, /* ICH7DH */
+   LPC_ICH7M,  /* ICH7-M & ICH7-U */
+   LPC_ICH7MDH,/* ICH7-M DH */
+   LPC_NM10,   /* NM10 */
+   LPC_ICH8,   /* ICH8 & ICH8R */
+   LPC_ICH8DH, /* ICH8DH */
+   LPC_ICH8DO, /* ICH8DO */
+   LPC_ICH8M,  /* ICH8M */
+   LPC_ICH8ME, /* ICH8M-E */
+   LPC_ICH9,

[PATCH v11 5/6] mfd: lpc_ich: Add Device IDs for Intel Apollo Lake PCH

2016-11-17 Thread Tan Jui Nee 
Adding Intel codename Apollo Lake platform device IDs for PCH.

Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
Acked-for-MFD-by: Lee Jones <lee.jo...@linaro.org>
---
Changes in V11:
- No change

Changes in V10:
- No change

Changes in V9:
- No change

Changes in V8:
- No change

 drivers/mfd/lpc_ich_core.c  | 6 ++
 include/linux/mfd/lpc_ich.h | 1 +
 2 files changed, 7 insertions(+)

diff --git a/drivers/mfd/lpc_ich_core.c b/drivers/mfd/lpc_ich_core.c
index 920198a..3bb6334 100644
--- a/drivers/mfd/lpc_ich_core.c
+++ b/drivers/mfd/lpc_ich_core.c
@@ -54,6 +54,7 @@
  * document number TBD : Wildcat Point-LP
  * document number TBD : 9 Series
  * document number TBD : Lewisburg
+ * document number TBD : Apollo Lake
  */
 
 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
@@ -458,6 +459,10 @@ struct lpc_ich_priv {
.name = "9 Series",
.iTCO_version = 2,
},
+   [LPC_APL]  = {
+   .name = "Apollo Lake SoC",
+   .iTCO_version = 5,
+   },
 };
 
 /*
@@ -606,6 +611,7 @@ struct lpc_ich_priv {
{ PCI_VDEVICE(INTEL, 0x3b14), LPC_3420},
{ PCI_VDEVICE(INTEL, 0x3b16), LPC_3450},
{ PCI_VDEVICE(INTEL, 0x5031), LPC_EP80579},
+   { PCI_VDEVICE(INTEL, 0x5ae8), LPC_APL},
{ PCI_VDEVICE(INTEL, 0x8c40), LPC_LPT},
{ PCI_VDEVICE(INTEL, 0x8c41), LPC_LPT},
{ PCI_VDEVICE(INTEL, 0x8c42), LPC_LPT},
diff --git a/include/linux/mfd/lpc_ich.h b/include/linux/mfd/lpc_ich.h
index 42307ee..397008c 100644
--- a/include/linux/mfd/lpc_ich.h
+++ b/include/linux/mfd/lpc_ich.h
@@ -112,6 +112,7 @@ enum lpc_chipsets {
LPC_BRASWELL,   /* Braswell SoC */
LPC_LEWISBURG,  /* Lewisburg */
LPC_9S, /* 9 Series */
+   LPC_APL,/* Apollo Lake SoC */
 };
 
 #endif
-- 
1.9.1

[PATCH v11 6/6] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO pinctrl in non-ACPI system

2016-11-17 Thread Tan Jui Nee 
This driver uses the P2SB hide/unhide mechanism cooperatively
to pass the PCI BAR address to the gpio platform driver.

Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
Reviewed-by: Mika Westerberg <mika.westerb...@linux.intel.com>
---
Changes in V11:
- Remove duplicated object file lpc_ich-objs in Makefile.
- Put p2sb.h header file in separate section in lpc_ich-apl.c, as asm 
stuff
  is platform specific (suggested by Andy).
- Rearrange variable declarations in lpc_ich_add_gpio() function
  (suggested by Andy).
- Move warn_continue label before if/else statement for the sake of
  readability (suggested by Andy).
- Add comment to #endif in lpc_ich_apl.h file.

Changes in V10:
- No change

Changes in V9:
- No change

Changes in V8:
- Rename source file lpc_ich-apl.c to lpc_ich_apl.c (suggested by Mika).

Changes in V7:
- Add author information and rewrite description of source file 
  lpc_ich-apl.c and lpc_ich_apl.h.
- Sort the header files by alphabetical order in lpc_ich-apl.c.
- Rename header file lpc_ich-apl.h to lpc_ich_apl.h (suggested by Lee).
- Remove unneeded pdata_size and platform_data from mfd_cell.
  Also, remove unneeded apl_pinctrl_pdata.
- Since variable apl_p2sb is only used once, hence switch it out for the
  PCI_DEVFN macro (suggested by Lee).
- Define APL_GPIO_COMMUNITY_MAX as total Apollo Lake GPIO communities
  supported.
- Set resources in mfd_cell for each GPIO community.
- Call p2sb_bar() function once instead of four times inside the for 
loop.
  And make p2sb_bar() function just to fill in the base address into a
  scratch "struct resource" and have the loop do the additions to 
base/end.
- Remove entire apl_pinctrl_pdata.name memory allocation since it is no
  longer needed.
- Return ret at the end of lpc_ich_add_gpio() function.

Changes in V6:
- Rename CONFIG_X86_INTEL_APL to CONFIG_X86_INTEL_IVI so that it
  relates to the actual product, as suggested by Mika.
- Rework Makefile according Andy's comments.
- Rename lpc_ich_misc() to lpc_ich_add_gpio() so that the name should 
not
  be so generic, as suggested by Andy.
- Call lpc_ich_add_gpio() via priv->chipset.
- lpc_ich_add_gpio() function will be moved from 
  .../include/linux/mfd/lpc_ich.h to
  .../drivers/mfd/lpc_ich-apl.h
  as this is a part of internal driver interface as suggested by Andy.
- Move enum lpc_chipsets from 
  .../drivers/mfd/lpc_ich-core.c to
  .../include/linux/mfd/lpc_ich.h
  as lpc_chipsets is also accessed by lpc_ich_add_gpio().
- Check if kasprintf return value for all 4 gpio controllers before
  proceed to add platform device by using mfd_add_devices().

Changes in V5:
- Split lpc-ich driver into two parts (lpc_ich-core and lpc_ich-apl).
  The file lpc_ich-apl.c introduces gpio platform driver in MFD.
- Rename Kconfig option CONFIG_X86_INTEL_NON_ACPI to 
CONFIG_X86_INTEL_APL
  so that it reflects actual product as suggested by Mika.

Changes in V4:
- Move Kconfig option CONFIG_X86_INTEL_NON_ACPI from
  [PATCH 2/3] x86/platform/p2sb: New Primary to Sideband bridge support 
driver for Intel SOC's
  to
  [PATCH 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO 
pinctrl in non-ACPI system
  since the config is used in latter patch.
- Select CONFIG_P2SB when CONFIG_LPC_ICH is enabled.
- Remove #ifdef CONFIG_X86_INTEL_NON_ACPI and use
  #if defined(CONFIG_X86_INTEL_NON_ACPI) when lpc_ich_misc is called
  as suggested by Lee Jones.
- Use single dimensional array instead of 2D array for apl_gpio_io_res
  structure and use DEFINE_RES_IRQ for its IRQ resource.

Changes in V3:
- Simplify register addresses calculation and use DEFINE_RES_MEM_NAMED
  defines for apl_gpio_io_res structure
- Define magic number for P2SB PCI ID
- Replace switch-case with if-else since currently we have only one
  use case
- Only call mfd_add_devices() once for all gpio communities

Changes in V2:
- Add new config option CONFIG_X86_INTEL_NON_ACPI and "select PINCTRL"
  to fix kbuildbot error

 drivers/mfd/Makefile   |   3 ++
 drivers/mfd/lpc_ich_apl.c  | 121 +
 drivers/mfd/lpc_ich_apl.h  |  28 +++
 drivers/mfd/lpc_ich_core.c |   5 ++
 4 files changed, 157 insertions(+)
 create mode 100644 drivers/mfd/lpc_ich_apl.c
 create mode 100644 drivers/mfd/lpc_ich_apl.h

diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 06a91ea..b7fb703 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/m

[PATCH v11 3/6] x86/intel-ivi: Add Intel In-Vehicle Infotainment (IVI) systems used in cars support

2016-11-17 Thread Tan Jui Nee 
Add support for non ACPI system, such as system that uses Advanced Boot
Loader (ABL) whereby a platform device has to be created in order to bind
with PINCTRL/GPIO.

At the moment, Intel Apollo Lake SoC requires P2SB driver to hide and
unhide P2SB to lookup P2SB BAR and pass the PCI BAR address to GPIO.

Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
Reviewed-by: Mika Westerberg <mika.westerb...@linux.intel.com>
---
Changes in V11:
- Select CONFIG_P2SB when CONFIG_X86_INTEL_IVI is enabled instead of
  CONFIG_LPC_ICH is enabled. This is to fix kbuildbot error.

Changes in V10:
- No change

Changes in V9:
- No change

Changes in V8:
- No change

 arch/x86/Kconfig | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index bada636..6019755 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -512,6 +512,16 @@ config X86_INTEL_CE
  This option compiles in support for the CE4100 SOC for settop
  boxes and media devices.
 
+config X86_INTEL_IVI
+   bool "Intel In-Vehicle Infotainment (IVI) systems used in cars"
+   depends on X86 && PCI
+   select P2SB
+   ---help---
+ Select this option to enable MMIO BAR access over the P2SB for
+ non-ACPI Intel Apollo Lake SoC platforms. This driver uses the P2SB
+ hide/unhide mechanism cooperatively to pass the PCI BAR address to
+ the platform driver, currently GPIO.
+
 config X86_INTEL_MID
bool "Intel MID platform support"
depends on X86_EXTENDED_PLATFORM
-- 
1.9.1

[PATCH v11 4/6] mfd: move enum lpc_chipsets into lpc_ich.h

2016-11-17 Thread Tan Jui Nee 
Move the enum's definition into a standalone header file which can be used
wherever its definition is needed.

Signed-off-by: Tan Jui Nee 
Reviewed-by: Mika Westerberg 
---
Changes in V11:
- No change

Changes in V10:
- No change

Changes in V9:
- No change

Changes in V8:
- No change

 drivers/mfd/lpc_ich_core.c  | 71 -
 include/linux/mfd/lpc_ich.h | 71 +
 2 files changed, 71 insertions(+), 71 deletions(-)

diff --git a/drivers/mfd/lpc_ich_core.c b/drivers/mfd/lpc_ich_core.c
index 7cbe037..920198a 100644
--- a/drivers/mfd/lpc_ich_core.c
+++ b/drivers/mfd/lpc_ich_core.c
@@ -145,77 +145,6 @@ struct lpc_ich_priv {
.ignore_resource_conflicts = true,
 };
 
-/* chipset related info */
-enum lpc_chipsets {
-   LPC_ICH = 0,/* ICH */
-   LPC_ICH0,   /* ICH0 */
-   LPC_ICH2,   /* ICH2 */
-   LPC_ICH2M,  /* ICH2-M */
-   LPC_ICH3,   /* ICH3-S */
-   LPC_ICH3M,  /* ICH3-M */
-   LPC_ICH4,   /* ICH4 */
-   LPC_ICH4M,  /* ICH4-M */
-   LPC_CICH,   /* C-ICH */
-   LPC_ICH5,   /* ICH5 & ICH5R */
-   LPC_6300ESB,/* 6300ESB */
-   LPC_ICH6,   /* ICH6 & ICH6R */
-   LPC_ICH6M,  /* ICH6-M */
-   LPC_ICH6W,  /* ICH6W & ICH6RW */
-   LPC_631XESB,/* 631xESB/632xESB */
-   LPC_ICH7,   /* ICH7 & ICH7R */
-   LPC_ICH7DH, /* ICH7DH */
-   LPC_ICH7M,  /* ICH7-M & ICH7-U */
-   LPC_ICH7MDH,/* ICH7-M DH */
-   LPC_NM10,   /* NM10 */
-   LPC_ICH8,   /* ICH8 & ICH8R */
-   LPC_ICH8DH, /* ICH8DH */
-   LPC_ICH8DO, /* ICH8DO */
-   LPC_ICH8M,  /* ICH8M */
-   LPC_ICH8ME, /* ICH8M-E */
-   LPC_ICH9,   /* ICH9 */
-   LPC_ICH9R,  /* ICH9R */
-   LPC_ICH9DH, /* ICH9DH */
-   LPC_ICH9DO, /* ICH9DO */
-   LPC_ICH9M,  /* ICH9M */
-   LPC_ICH9ME, /* ICH9M-E */
-   LPC_ICH10,  /* ICH10 */
-   LPC_ICH10R, /* ICH10R */
-   LPC_ICH10D, /* ICH10D */
-   LPC_ICH10DO,/* ICH10DO */
-   LPC_PCH,/* PCH Desktop Full Featured */
-   LPC_PCHM,   /* PCH Mobile Full Featured */
-   LPC_P55,/* P55 */
-   LPC_PM55,   /* PM55 */
-   LPC_H55,/* H55 */
-   LPC_QM57,   /* QM57 */
-   LPC_H57,/* H57 */
-   LPC_HM55,   /* HM55 */
-   LPC_Q57,/* Q57 */
-   LPC_HM57,   /* HM57 */
-   LPC_PCHMSFF,/* PCH Mobile SFF Full Featured */
-   LPC_QS57,   /* QS57 */
-   LPC_3400,   /* 3400 */
-   LPC_3420,   /* 3420 */
-   LPC_3450,   /* 3450 */
-   LPC_EP80579,/* EP80579 */
-   LPC_CPT,/* Cougar Point */
-   LPC_CPTD,   /* Cougar Point Desktop */
-   LPC_CPTM,   /* Cougar Point Mobile */
-   LPC_PBG,/* Patsburg */
-   LPC_DH89XXCC,   /* DH89xxCC */
-   LPC_PPT,/* Panther Point */
-   LPC_LPT,/* Lynx Point */
-   LPC_LPT_LP, /* Lynx Point-LP */
-   LPC_WBG,/* Wellsburg */
-   LPC_AVN,/* Avoton SoC */
-   LPC_BAYTRAIL,   /* Bay Trail SoC */
-   LPC_COLETO, /* Coleto Creek */
-   LPC_WPT_LP, /* Wildcat Point-LP */
-   LPC_BRASWELL,   /* Braswell SoC */
-   LPC_LEWISBURG,  /* Lewisburg */
-   LPC_9S, /* 9 Series */
-};
-
 static struct lpc_ich_info lpc_chipset_info[] = {
[LPC_ICH] = {
.name = "ICH",
diff --git a/include/linux/mfd/lpc_ich.h b/include/linux/mfd/lpc_ich.h
index 2b300b4..42307ee 100644
--- a/include/linux/mfd/lpc_ich.h
+++ b/include/linux/mfd/lpc_ich.h
@@ -43,4 +43,75 @@ struct lpc_ich_info {
u8 use_gpio;
 };
 
+/* chipset related info */
+enum lpc_chipsets {
+   LPC_ICH = 0,/* ICH */
+   LPC_ICH0,   /* ICH0 */
+   LPC_ICH2,   /* ICH2 */
+   LPC_ICH2M,  /* ICH2-M */
+   LPC_ICH3,   /* ICH3-S */
+   LPC_ICH3M,  /* ICH3-M */
+   LPC_ICH4,   /* ICH4 */
+   LPC_ICH4M,  /* ICH4-M */
+   LPC_CICH,   /* C-ICH */
+   LPC_ICH5,   /* ICH5 & ICH5R */
+   LPC_6300ESB,/* 6300ESB */
+   LPC_ICH6,   /* ICH6 & ICH6R */
+   LPC_ICH6M,  /* ICH6-M */
+   LPC_ICH6W,  /* ICH6W & ICH6RW */
+   LPC_631XESB,/* 631xESB/632xESB */
+   LPC_ICH7,   /* ICH7 & ICH7R */
+   LPC_ICH7DH, /* ICH7DH */
+   LPC_ICH7M,  /* ICH7-M & ICH7-U */
+   LPC_ICH7MDH,/* ICH7-M DH */
+   LPC_NM10,   /* NM10 */
+   LPC_ICH8,   /* ICH8 & ICH8R */
+   LPC_ICH8DH, /* ICH8DH */
+   LPC_ICH8DO, /* ICH8DO */
+   LPC_ICH8M,  /* ICH8M */
+   LPC_ICH8ME, /* ICH8M-E */
+   LPC_ICH9,   /* ICH9 */
+   LPC_ICH9R,  /* ICH9R */
+   LPC_

[PATCH v11 5/6] mfd: lpc_ich: Add Device IDs for Intel Apollo Lake PCH

2016-11-17 Thread Tan Jui Nee 
Adding Intel codename Apollo Lake platform device IDs for PCH.

Signed-off-by: Tan Jui Nee 
Acked-for-MFD-by: Lee Jones 
---
Changes in V11:
- No change

Changes in V10:
- No change

Changes in V9:
- No change

Changes in V8:
- No change

 drivers/mfd/lpc_ich_core.c  | 6 ++
 include/linux/mfd/lpc_ich.h | 1 +
 2 files changed, 7 insertions(+)

diff --git a/drivers/mfd/lpc_ich_core.c b/drivers/mfd/lpc_ich_core.c
index 920198a..3bb6334 100644
--- a/drivers/mfd/lpc_ich_core.c
+++ b/drivers/mfd/lpc_ich_core.c
@@ -54,6 +54,7 @@
  * document number TBD : Wildcat Point-LP
  * document number TBD : 9 Series
  * document number TBD : Lewisburg
+ * document number TBD : Apollo Lake
  */
 
 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
@@ -458,6 +459,10 @@ struct lpc_ich_priv {
.name = "9 Series",
.iTCO_version = 2,
},
+   [LPC_APL]  = {
+   .name = "Apollo Lake SoC",
+   .iTCO_version = 5,
+   },
 };
 
 /*
@@ -606,6 +611,7 @@ struct lpc_ich_priv {
{ PCI_VDEVICE(INTEL, 0x3b14), LPC_3420},
{ PCI_VDEVICE(INTEL, 0x3b16), LPC_3450},
{ PCI_VDEVICE(INTEL, 0x5031), LPC_EP80579},
+   { PCI_VDEVICE(INTEL, 0x5ae8), LPC_APL},
{ PCI_VDEVICE(INTEL, 0x8c40), LPC_LPT},
{ PCI_VDEVICE(INTEL, 0x8c41), LPC_LPT},
{ PCI_VDEVICE(INTEL, 0x8c42), LPC_LPT},
diff --git a/include/linux/mfd/lpc_ich.h b/include/linux/mfd/lpc_ich.h
index 42307ee..397008c 100644
--- a/include/linux/mfd/lpc_ich.h
+++ b/include/linux/mfd/lpc_ich.h
@@ -112,6 +112,7 @@ enum lpc_chipsets {
LPC_BRASWELL,   /* Braswell SoC */
LPC_LEWISBURG,  /* Lewisburg */
LPC_9S, /* 9 Series */
+   LPC_APL,/* Apollo Lake SoC */
 };
 
 #endif
-- 
1.9.1

[PATCH v11 6/6] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO pinctrl in non-ACPI system

2016-11-17 Thread Tan Jui Nee 
This driver uses the P2SB hide/unhide mechanism cooperatively
to pass the PCI BAR address to the gpio platform driver.

Signed-off-by: Tan Jui Nee 
Reviewed-by: Mika Westerberg 
---
Changes in V11:
- Remove duplicated object file lpc_ich-objs in Makefile.
- Put p2sb.h header file in separate section in lpc_ich-apl.c, as asm 
stuff
  is platform specific (suggested by Andy).
- Rearrange variable declarations in lpc_ich_add_gpio() function
  (suggested by Andy).
- Move warn_continue label before if/else statement for the sake of
  readability (suggested by Andy).
- Add comment to #endif in lpc_ich_apl.h file.

Changes in V10:
- No change

Changes in V9:
- No change

Changes in V8:
- Rename source file lpc_ich-apl.c to lpc_ich_apl.c (suggested by Mika).

Changes in V7:
- Add author information and rewrite description of source file 
  lpc_ich-apl.c and lpc_ich_apl.h.
- Sort the header files by alphabetical order in lpc_ich-apl.c.
- Rename header file lpc_ich-apl.h to lpc_ich_apl.h (suggested by Lee).
- Remove unneeded pdata_size and platform_data from mfd_cell.
  Also, remove unneeded apl_pinctrl_pdata.
- Since variable apl_p2sb is only used once, hence switch it out for the
  PCI_DEVFN macro (suggested by Lee).
- Define APL_GPIO_COMMUNITY_MAX as total Apollo Lake GPIO communities
  supported.
- Set resources in mfd_cell for each GPIO community.
- Call p2sb_bar() function once instead of four times inside the for 
loop.
  And make p2sb_bar() function just to fill in the base address into a
  scratch "struct resource" and have the loop do the additions to 
base/end.
- Remove entire apl_pinctrl_pdata.name memory allocation since it is no
  longer needed.
- Return ret at the end of lpc_ich_add_gpio() function.

Changes in V6:
- Rename CONFIG_X86_INTEL_APL to CONFIG_X86_INTEL_IVI so that it
  relates to the actual product, as suggested by Mika.
- Rework Makefile according Andy's comments.
- Rename lpc_ich_misc() to lpc_ich_add_gpio() so that the name should 
not
  be so generic, as suggested by Andy.
- Call lpc_ich_add_gpio() via priv->chipset.
- lpc_ich_add_gpio() function will be moved from 
  .../include/linux/mfd/lpc_ich.h to
  .../drivers/mfd/lpc_ich-apl.h
  as this is a part of internal driver interface as suggested by Andy.
- Move enum lpc_chipsets from 
  .../drivers/mfd/lpc_ich-core.c to
  .../include/linux/mfd/lpc_ich.h
  as lpc_chipsets is also accessed by lpc_ich_add_gpio().
- Check if kasprintf return value for all 4 gpio controllers before
  proceed to add platform device by using mfd_add_devices().

Changes in V5:
- Split lpc-ich driver into two parts (lpc_ich-core and lpc_ich-apl).
  The file lpc_ich-apl.c introduces gpio platform driver in MFD.
- Rename Kconfig option CONFIG_X86_INTEL_NON_ACPI to 
CONFIG_X86_INTEL_APL
  so that it reflects actual product as suggested by Mika.

Changes in V4:
- Move Kconfig option CONFIG_X86_INTEL_NON_ACPI from
  [PATCH 2/3] x86/platform/p2sb: New Primary to Sideband bridge support 
driver for Intel SOC's
  to
  [PATCH 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO 
pinctrl in non-ACPI system
  since the config is used in latter patch.
- Select CONFIG_P2SB when CONFIG_LPC_ICH is enabled.
- Remove #ifdef CONFIG_X86_INTEL_NON_ACPI and use
  #if defined(CONFIG_X86_INTEL_NON_ACPI) when lpc_ich_misc is called
  as suggested by Lee Jones.
- Use single dimensional array instead of 2D array for apl_gpio_io_res
  structure and use DEFINE_RES_IRQ for its IRQ resource.

Changes in V3:
- Simplify register addresses calculation and use DEFINE_RES_MEM_NAMED
  defines for apl_gpio_io_res structure
- Define magic number for P2SB PCI ID
- Replace switch-case with if-else since currently we have only one
  use case
- Only call mfd_add_devices() once for all gpio communities

Changes in V2:
- Add new config option CONFIG_X86_INTEL_NON_ACPI and "select PINCTRL"
  to fix kbuildbot error

 drivers/mfd/Makefile   |   3 ++
 drivers/mfd/lpc_ich_apl.c  | 121 +
 drivers/mfd/lpc_ich_apl.h  |  28 +++
 drivers/mfd/lpc_ich_core.c |   5 ++
 4 files changed, 157 insertions(+)
 create mode 100644 drivers/mfd/lpc_ich_apl.c
 create mode 100644 drivers/mfd/lpc_ich_apl.h

diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 06a91ea..b7fb703 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -161,6 +161,9 @@ obj-$(CONFIG_MFD_INTEL_QUARK_I2C_GPIO)  += 
inte

[PATCH v11 3/6] x86/intel-ivi: Add Intel In-Vehicle Infotainment (IVI) systems used in cars support

2016-11-17 Thread Tan Jui Nee 
Add support for non ACPI system, such as system that uses Advanced Boot
Loader (ABL) whereby a platform device has to be created in order to bind
with PINCTRL/GPIO.

At the moment, Intel Apollo Lake SoC requires P2SB driver to hide and
unhide P2SB to lookup P2SB BAR and pass the PCI BAR address to GPIO.

Signed-off-by: Tan Jui Nee 
Reviewed-by: Mika Westerberg 
---
Changes in V11:
- Select CONFIG_P2SB when CONFIG_X86_INTEL_IVI is enabled instead of
  CONFIG_LPC_ICH is enabled. This is to fix kbuildbot error.

Changes in V10:
- No change

Changes in V9:
- No change

Changes in V8:
- No change

 arch/x86/Kconfig | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index bada636..6019755 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -512,6 +512,16 @@ config X86_INTEL_CE
  This option compiles in support for the CE4100 SOC for settop
  boxes and media devices.
 
+config X86_INTEL_IVI
+   bool "Intel In-Vehicle Infotainment (IVI) systems used in cars"
+   depends on X86 && PCI
+   select P2SB
+   ---help---
+ Select this option to enable MMIO BAR access over the P2SB for
+ non-ACPI Intel Apollo Lake SoC platforms. This driver uses the P2SB
+ hide/unhide mechanism cooperatively to pass the PCI BAR address to
+ the platform driver, currently GPIO.
+
 config X86_INTEL_MID
bool "Intel MID platform support"
depends on X86_EXTENDED_PLATFORM
-- 
1.9.1

[PATCH v11 2/6] mfd: lpc_ich: Rename lpc-ich driver

2016-11-17 Thread Tan Jui Nee 
This patch follows the example of mfd/wm831x to rename the driver
from "lpc_ich" to "lpc_ich_core".

Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
Reviewed-by: Mika Westerberg <mika.westerb...@linux.intel.com>
---
Changes in V11:
- No change

Changes in V10:
- No change

Changes in V9:
- Remove the filename from the header of lpc_ich_core.c (suggested by 
Lee).

Changes in V8:
- Update new file name with lpc_ich_core.c at description of source 
file.
- Rework Makefile with new source file name lpc_ich_apl.c.

Changes in V7:
- No change

Changes in V6:
- none, just a subject line and commit message change.

 drivers/mfd/Makefile  | 1 +
 drivers/mfd/{lpc_ich.c => lpc_ich_core.c} | 2 --
 2 files changed, 1 insertion(+), 2 deletions(-)
 rename drivers/mfd/{lpc_ich.c => lpc_ich_core.c} (99%)

diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 9834e66..06a91ea 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -159,6 +159,7 @@ obj-$(CONFIG_PMIC_ADP5520)  += adp5520.o
 obj-$(CONFIG_MFD_KEMPLD)   += kempld-core.o
 obj-$(CONFIG_MFD_INTEL_QUARK_I2C_GPIO) += intel_quark_i2c_gpio.o
 obj-$(CONFIG_LPC_SCH)  += lpc_sch.o
+lpc_ich-objs   := lpc_ich_core.o
 obj-$(CONFIG_LPC_ICH)  += lpc_ich.o
 obj-$(CONFIG_MFD_RDC321X)  += rdc321x-southbridge.o
 obj-$(CONFIG_MFD_JANZ_CMODIO)  += janz-cmodio.o
diff --git a/drivers/mfd/lpc_ich.c b/drivers/mfd/lpc_ich_core.c
similarity index 99%
rename from drivers/mfd/lpc_ich.c
rename to drivers/mfd/lpc_ich_core.c
index c8dee47..7cbe037 100644
--- a/drivers/mfd/lpc_ich.c
+++ b/drivers/mfd/lpc_ich_core.c
@@ -1,6 +1,4 @@
 /*
- *  lpc_ich.c - LPC interface for Intel ICH
- *
  *  LPC bridge function of the Intel ICH contains many other
  *  functional units, such as Interrupt controllers, Timers,
  *  Power Management, System Management, GPIO, RTC, and LPC
-- 
1.9.1

[PATCH v11 0/6] pinctrl/broxton: enable platform device in the absent of ACPI enumeration

2016-11-17 Thread Tan Jui Nee 
Select CONFIG_P2SB when CONFIG_LPC_ICH is enabled.
- Remove #ifdef CONFIG_X86_INTEL_NON_ACPI and use
  #if defined(CONFIG_X86_INTEL_NON_ACPI) when lpc_ich_misc is called
  as suggested by Lee Jones.
- Use single dimensional array instead of 2D array for apl_gpio_io_res
  structure and use DEFINE_RES_IRQ for its IRQ resource.

Changes in V3:
- Simplify register addresses calculation and use DEFINE_RES_MEM_NAMED
  defines for apl_gpio_io_res structure
- Define magic number for P2SB PCI ID
- Replace switch-case with if-else since currently we have only one
  use case
- Only call mfd_add_devices() once for all gpio communities

Changes in V2:
- Add new config option CONFIG_X86_INTEL_NON_ACPI and "select PINCTRL"
  to fix kbuildbot error

Andy Shevchenko (1):
  drivers/platform/x86/p2sb: New Primary to Sideband bridge support
    driver for Intel SOC's

Tan Jui Nee (5):
  mfd: lpc_ich: Rename lpc-ich driver
  x86/intel-ivi: Add Intel In-Vehicle Infotainment (IVI) systems used in
cars support
  mfd: move enum lpc_chipsets into lpc_ich.h
  mfd: lpc_ich: Add Device IDs for Intel Apollo Lake PCH
  mfd: lpc_ich: Add support for Intel Apollo Lake GPIO pinctrl in
non-ACPI system

 arch/x86/Kconfig  |  10 +++
 arch/x86/include/asm/p2sb.h   |  27 +++
 drivers/mfd/Makefile  |   4 +
 drivers/mfd/lpc_ich_apl.c | 121 ++
 drivers/mfd/lpc_ich_apl.h |  28 +++
 drivers/mfd/{lpc_ich.c => lpc_ich_core.c} |  84 +++--
 drivers/platform/x86/Kconfig  |   4 +
 drivers/platform/x86/Makefile |   1 +
 drivers/platform/x86/p2sb.c   |  98 
 include/linux/mfd/lpc_ich.h   |  72 ++
 10 files changed, 376 insertions(+), 73 deletions(-)
 create mode 100644 arch/x86/include/asm/p2sb.h
 create mode 100644 drivers/mfd/lpc_ich_apl.c
 create mode 100644 drivers/mfd/lpc_ich_apl.h
 rename drivers/mfd/{lpc_ich.c => lpc_ich_core.c} (93%)
 create mode 100644 drivers/platform/x86/p2sb.c

-- 
1.9.1

[PATCH v11 2/6] mfd: lpc_ich: Rename lpc-ich driver

2016-11-17 Thread Tan Jui Nee 
This patch follows the example of mfd/wm831x to rename the driver
from "lpc_ich" to "lpc_ich_core".

Signed-off-by: Tan Jui Nee 
Reviewed-by: Mika Westerberg 
---
Changes in V11:
- No change

Changes in V10:
- No change

Changes in V9:
- Remove the filename from the header of lpc_ich_core.c (suggested by 
Lee).

Changes in V8:
- Update new file name with lpc_ich_core.c at description of source 
file.
- Rework Makefile with new source file name lpc_ich_apl.c.

Changes in V7:
- No change

Changes in V6:
- none, just a subject line and commit message change.

 drivers/mfd/Makefile  | 1 +
 drivers/mfd/{lpc_ich.c => lpc_ich_core.c} | 2 --
 2 files changed, 1 insertion(+), 2 deletions(-)
 rename drivers/mfd/{lpc_ich.c => lpc_ich_core.c} (99%)

diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 9834e66..06a91ea 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -159,6 +159,7 @@ obj-$(CONFIG_PMIC_ADP5520)  += adp5520.o
 obj-$(CONFIG_MFD_KEMPLD)   += kempld-core.o
 obj-$(CONFIG_MFD_INTEL_QUARK_I2C_GPIO) += intel_quark_i2c_gpio.o
 obj-$(CONFIG_LPC_SCH)  += lpc_sch.o
+lpc_ich-objs   := lpc_ich_core.o
 obj-$(CONFIG_LPC_ICH)  += lpc_ich.o
 obj-$(CONFIG_MFD_RDC321X)  += rdc321x-southbridge.o
 obj-$(CONFIG_MFD_JANZ_CMODIO)  += janz-cmodio.o
diff --git a/drivers/mfd/lpc_ich.c b/drivers/mfd/lpc_ich_core.c
similarity index 99%
rename from drivers/mfd/lpc_ich.c
rename to drivers/mfd/lpc_ich_core.c
index c8dee47..7cbe037 100644
--- a/drivers/mfd/lpc_ich.c
+++ b/drivers/mfd/lpc_ich_core.c
@@ -1,6 +1,4 @@
 /*
- *  lpc_ich.c - LPC interface for Intel ICH
- *
  *  LPC bridge function of the Intel ICH contains many other
  *  functional units, such as Interrupt controllers, Timers,
  *  Power Management, System Management, GPIO, RTC, and LPC
-- 
1.9.1

[PATCH v11 0/6] pinctrl/broxton: enable platform device in the absent of ACPI enumeration

2016-11-17 Thread Tan Jui Nee 
Select CONFIG_P2SB when CONFIG_LPC_ICH is enabled.
- Remove #ifdef CONFIG_X86_INTEL_NON_ACPI and use
  #if defined(CONFIG_X86_INTEL_NON_ACPI) when lpc_ich_misc is called
  as suggested by Lee Jones.
- Use single dimensional array instead of 2D array for apl_gpio_io_res
  structure and use DEFINE_RES_IRQ for its IRQ resource.

Changes in V3:
- Simplify register addresses calculation and use DEFINE_RES_MEM_NAMED
  defines for apl_gpio_io_res structure
- Define magic number for P2SB PCI ID
- Replace switch-case with if-else since currently we have only one
  use case
- Only call mfd_add_devices() once for all gpio communities

Changes in V2:
- Add new config option CONFIG_X86_INTEL_NON_ACPI and "select PINCTRL"
  to fix kbuildbot error

Andy Shevchenko (1):
  drivers/platform/x86/p2sb: New Primary to Sideband bridge support
    driver for Intel SOC's

Tan Jui Nee (5):
  mfd: lpc_ich: Rename lpc-ich driver
  x86/intel-ivi: Add Intel In-Vehicle Infotainment (IVI) systems used in
cars support
  mfd: move enum lpc_chipsets into lpc_ich.h
  mfd: lpc_ich: Add Device IDs for Intel Apollo Lake PCH
  mfd: lpc_ich: Add support for Intel Apollo Lake GPIO pinctrl in
non-ACPI system

 arch/x86/Kconfig  |  10 +++
 arch/x86/include/asm/p2sb.h   |  27 +++
 drivers/mfd/Makefile  |   4 +
 drivers/mfd/lpc_ich_apl.c | 121 ++
 drivers/mfd/lpc_ich_apl.h |  28 +++
 drivers/mfd/{lpc_ich.c => lpc_ich_core.c} |  84 +++--
 drivers/platform/x86/Kconfig  |   4 +
 drivers/platform/x86/Makefile |   1 +
 drivers/platform/x86/p2sb.c   |  98 
 include/linux/mfd/lpc_ich.h   |  72 ++
 10 files changed, 376 insertions(+), 73 deletions(-)
 create mode 100644 arch/x86/include/asm/p2sb.h
 create mode 100644 drivers/mfd/lpc_ich_apl.c
 create mode 100644 drivers/mfd/lpc_ich_apl.h
 rename drivers/mfd/{lpc_ich.c => lpc_ich_core.c} (93%)
 create mode 100644 drivers/platform/x86/p2sb.c

-- 
1.9.1

[PATCH v10 3/6] x86/intel-ivi: Add Intel In-Vehicle Infotainment (IVI) systems used in cars support

2016-11-10 Thread Tan Jui Nee 
Add support for non ACPI system, such as system that uses Advanced Boot
Loader (ABL) whereby a platform device has to be created in order to bind
with PINCTRL/GPIO.

At the moment, Intel Apollo Lake SoC requires P2SB driver to hide and
unhide P2SB to lookup P2SB BAR and pass the PCI BAR address to GPIO.

Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
Reviewed-by: Mika Westerberg <mika.westerb...@linux.intel.com>
---
Changes in V10:
- No change

Changes in V9:
- No change

Changes in V8:
- No change

 arch/x86/Kconfig | 8 
 1 file changed, 8 insertions(+)

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index bada636..9c98002 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -512,6 +512,14 @@ config X86_INTEL_CE
  This option compiles in support for the CE4100 SOC for settop
  boxes and media devices.
 
+config X86_INTEL_IVI
+   bool "Intel In-Vehicle Infotainment (IVI) systems used in cars"
+   ---help---
+ Select this option to enable MMIO BAR access over the P2SB for
+ non-ACPI Intel Apollo Lake SoC platforms. This driver uses the P2SB
+ hide/unhide mechanism cooperatively to pass the PCI BAR address to
+ the platform driver, currently GPIO.
+
 config X86_INTEL_MID
bool "Intel MID platform support"
depends on X86_EXTENDED_PLATFORM
-- 
1.9.1

[PATCH v10 3/6] x86/intel-ivi: Add Intel In-Vehicle Infotainment (IVI) systems used in cars support

2016-11-10 Thread Tan Jui Nee 
Add support for non ACPI system, such as system that uses Advanced Boot
Loader (ABL) whereby a platform device has to be created in order to bind
with PINCTRL/GPIO.

At the moment, Intel Apollo Lake SoC requires P2SB driver to hide and
unhide P2SB to lookup P2SB BAR and pass the PCI BAR address to GPIO.

Signed-off-by: Tan Jui Nee 
Reviewed-by: Mika Westerberg 
---
Changes in V10:
- No change

Changes in V9:
- No change

Changes in V8:
- No change

 arch/x86/Kconfig | 8 
 1 file changed, 8 insertions(+)

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index bada636..9c98002 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -512,6 +512,14 @@ config X86_INTEL_CE
  This option compiles in support for the CE4100 SOC for settop
  boxes and media devices.
 
+config X86_INTEL_IVI
+   bool "Intel In-Vehicle Infotainment (IVI) systems used in cars"
+   ---help---
+ Select this option to enable MMIO BAR access over the P2SB for
+ non-ACPI Intel Apollo Lake SoC platforms. This driver uses the P2SB
+ hide/unhide mechanism cooperatively to pass the PCI BAR address to
+ the platform driver, currently GPIO.
+
 config X86_INTEL_MID
bool "Intel MID platform support"
depends on X86_EXTENDED_PLATFORM
-- 
1.9.1

[PATCH v10 1/6] drivers/platform/x86/p2sb: New Primary to Sideband bridge support driver for Intel SOC's

2016-11-10 Thread Tan Jui Nee 
From: Andy Shevchenko 

There is already one and at least one more user coming which
require an access to Primary to Sideband bridge (P2SB) in order
to get IO or MMIO bar hidden by BIOS.
Create a driver to access P2SB for x86 devices.

Signed-off-by: Yong, Jonathan 
Signed-off-by: Andy Shevchenko 
---
Changes in V10:
- Since P2SB is platform enablement driver and therefore should go into
  drivers/platform/x86 (suggested by tglx).

Changes in V9:
- No change

Changes in V8:
- No change

Changes in V7:
- EXPORT_SYMBOL_GPL() and MODULE_LICENSE("GPL v2") are used for new file
  p2sb.c.

Changes in V6:
- No change

Changes in V5:
- No change

Changes in V4:
- Move Kconfig option CONFIG_X86_INTEL_NON_ACPI from
  [PATCH 2/3] x86/platform/p2sb: New Primary to Sideband bridge support 
driver for Intel SOC's
  to
  [PATCH 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO 
pinctrl in non-ACPI system
  since the config is used in latter patch.

Changes in V3:
- No change

Changes in V2:
- Add new config option CONFIG_X86_INTEL_NON_ACPI and "select PINCTRL"
  to fix kbuildbot error

 arch/x86/include/asm/p2sb.h   | 27 
 drivers/platform/x86/Kconfig  |  4 ++
 drivers/platform/x86/Makefile |  1 +
 drivers/platform/x86/p2sb.c   | 98 +++
 4 files changed, 130 insertions(+)
 create mode 100644 arch/x86/include/asm/p2sb.h
 create mode 100644 drivers/platform/x86/p2sb.c

diff --git a/arch/x86/include/asm/p2sb.h b/arch/x86/include/asm/p2sb.h
new file mode 100644
index 000..686e07b
--- /dev/null
+++ b/arch/x86/include/asm/p2sb.h
@@ -0,0 +1,27 @@
+/*
+ * Primary to Sideband bridge (P2SB) access support
+ */
+
+#ifndef P2SB_SYMS_H
+#define P2SB_SYMS_H
+
+#include 
+#include 
+
+#if IS_ENABLED(CONFIG_P2SB)
+
+int p2sb_bar(struct pci_dev *pdev, unsigned int devfn,
+   struct resource *res);
+
+#else /* CONFIG_P2SB is not set */
+
+static inline
+int p2sb_bar(struct pci_dev *pdev, unsigned int devfn,
+   struct resource *res)
+{
+   return -ENODEV;
+}
+
+#endif /* CONFIG_P2SB */
+
+#endif /* P2SB_SYMS_H */
diff --git a/drivers/platform/x86/Kconfig b/drivers/platform/x86/Kconfig
index b8a21d7..65ef6a0 100644
--- a/drivers/platform/x86/Kconfig
+++ b/drivers/platform/x86/Kconfig
@@ -1027,4 +1027,8 @@ config INTEL_TELEMETRY
  used to get various SoC events and parameters
  directly via debugfs files. Various tools may use
  this interface for SoC state monitoring.
+
+config P2SB
+   tristate
+   depends on PCI
 endif # X86_PLATFORM_DEVICES
diff --git a/drivers/platform/x86/Makefile b/drivers/platform/x86/Makefile
index 2efa86d..c39a13d 100644
--- a/drivers/platform/x86/Makefile
+++ b/drivers/platform/x86/Makefile
@@ -71,3 +71,4 @@ obj-$(CONFIG_INTEL_TELEMETRY) += intel_telemetry_core.o \
   intel_telemetry_pltdrv.o \
   intel_telemetry_debugfs.o
 obj-$(CONFIG_INTEL_PMC_CORE)+= intel_pmc_core.o
+obj-$(CONFIG_P2SB) += p2sb.o
diff --git a/drivers/platform/x86/p2sb.c b/drivers/platform/x86/p2sb.c
new file mode 100644
index 000..b1d784c
--- /dev/null
+++ b/drivers/platform/x86/p2sb.c
@@ -0,0 +1,98 @@
+/*
+ * Primary to Sideband bridge (P2SB) driver
+ *
+ * Copyright (c) 2016, Intel Corporation.
+ *
+ * Authors: Andy Shevchenko 
+ * Jonathan Yong 
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#define SBREG_BAR  0x10
+#define SBREG_HIDE 0xe1
+
+static DEFINE_SPINLOCK(p2sb_spinlock);
+
+/*
+ * p2sb_bar - Get Primary to Sideband bridge (P2SB) BAR
+ * @pdev:  PCI device to get PCI bus to communicate with
+ * @devfn: PCI device and function to communicate with
+ * @res:   resources to be filled in
+ *
+ * The BIOS prevents the P2SB device from being enumerated by the PCI
+ * subsystem, so we need to unhide and hide it back to lookup the P2SB BAR.
+ *
+ * Locking is handled by spinlock - cannot sleep.
+ *
+ * Return:
+ * 0 on success or appropriate errno value on error.
+ */
+int p2sb_bar(struct pci_dev *pdev, unsigned int devfn,
+   struct resource *res)
+{
+   u32 base_addr;
+   u64 base64_addr;
+   unsigned long flags;
+
+   if (!res)

[PATCH v10 1/6] drivers/platform/x86/p2sb: New Primary to Sideband bridge support driver for Intel SOC's

2016-11-10 Thread Tan Jui Nee 
From: Andy Shevchenko 

There is already one and at least one more user coming which
require an access to Primary to Sideband bridge (P2SB) in order
to get IO or MMIO bar hidden by BIOS.
Create a driver to access P2SB for x86 devices.

Signed-off-by: Yong, Jonathan 
Signed-off-by: Andy Shevchenko 
---
Changes in V10:
- Since P2SB is platform enablement driver and therefore should go into
  drivers/platform/x86 (suggested by tglx).

Changes in V9:
- No change

Changes in V8:
- No change

Changes in V7:
- EXPORT_SYMBOL_GPL() and MODULE_LICENSE("GPL v2") are used for new file
  p2sb.c.

Changes in V6:
- No change

Changes in V5:
- No change

Changes in V4:
- Move Kconfig option CONFIG_X86_INTEL_NON_ACPI from
  [PATCH 2/3] x86/platform/p2sb: New Primary to Sideband bridge support 
driver for Intel SOC's
  to
  [PATCH 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO 
pinctrl in non-ACPI system
  since the config is used in latter patch.

Changes in V3:
- No change

Changes in V2:
- Add new config option CONFIG_X86_INTEL_NON_ACPI and "select PINCTRL"
  to fix kbuildbot error

 arch/x86/include/asm/p2sb.h   | 27 
 drivers/platform/x86/Kconfig  |  4 ++
 drivers/platform/x86/Makefile |  1 +
 drivers/platform/x86/p2sb.c   | 98 +++
 4 files changed, 130 insertions(+)
 create mode 100644 arch/x86/include/asm/p2sb.h
 create mode 100644 drivers/platform/x86/p2sb.c

diff --git a/arch/x86/include/asm/p2sb.h b/arch/x86/include/asm/p2sb.h
new file mode 100644
index 000..686e07b
--- /dev/null
+++ b/arch/x86/include/asm/p2sb.h
@@ -0,0 +1,27 @@
+/*
+ * Primary to Sideband bridge (P2SB) access support
+ */
+
+#ifndef P2SB_SYMS_H
+#define P2SB_SYMS_H
+
+#include 
+#include 
+
+#if IS_ENABLED(CONFIG_P2SB)
+
+int p2sb_bar(struct pci_dev *pdev, unsigned int devfn,
+   struct resource *res);
+
+#else /* CONFIG_P2SB is not set */
+
+static inline
+int p2sb_bar(struct pci_dev *pdev, unsigned int devfn,
+   struct resource *res)
+{
+   return -ENODEV;
+}
+
+#endif /* CONFIG_P2SB */
+
+#endif /* P2SB_SYMS_H */
diff --git a/drivers/platform/x86/Kconfig b/drivers/platform/x86/Kconfig
index b8a21d7..65ef6a0 100644
--- a/drivers/platform/x86/Kconfig
+++ b/drivers/platform/x86/Kconfig
@@ -1027,4 +1027,8 @@ config INTEL_TELEMETRY
  used to get various SoC events and parameters
  directly via debugfs files. Various tools may use
  this interface for SoC state monitoring.
+
+config P2SB
+   tristate
+   depends on PCI
 endif # X86_PLATFORM_DEVICES
diff --git a/drivers/platform/x86/Makefile b/drivers/platform/x86/Makefile
index 2efa86d..c39a13d 100644
--- a/drivers/platform/x86/Makefile
+++ b/drivers/platform/x86/Makefile
@@ -71,3 +71,4 @@ obj-$(CONFIG_INTEL_TELEMETRY) += intel_telemetry_core.o \
   intel_telemetry_pltdrv.o \
   intel_telemetry_debugfs.o
 obj-$(CONFIG_INTEL_PMC_CORE)+= intel_pmc_core.o
+obj-$(CONFIG_P2SB) += p2sb.o
diff --git a/drivers/platform/x86/p2sb.c b/drivers/platform/x86/p2sb.c
new file mode 100644
index 000..b1d784c
--- /dev/null
+++ b/drivers/platform/x86/p2sb.c
@@ -0,0 +1,98 @@
+/*
+ * Primary to Sideband bridge (P2SB) driver
+ *
+ * Copyright (c) 2016, Intel Corporation.
+ *
+ * Authors: Andy Shevchenko 
+ * Jonathan Yong 
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#define SBREG_BAR  0x10
+#define SBREG_HIDE 0xe1
+
+static DEFINE_SPINLOCK(p2sb_spinlock);
+
+/*
+ * p2sb_bar - Get Primary to Sideband bridge (P2SB) BAR
+ * @pdev:  PCI device to get PCI bus to communicate with
+ * @devfn: PCI device and function to communicate with
+ * @res:   resources to be filled in
+ *
+ * The BIOS prevents the P2SB device from being enumerated by the PCI
+ * subsystem, so we need to unhide and hide it back to lookup the P2SB BAR.
+ *
+ * Locking is handled by spinlock - cannot sleep.
+ *
+ * Return:
+ * 0 on success or appropriate errno value on error.
+ */
+int p2sb_bar(struct pci_dev *pdev, unsigned int devfn,
+   struct resource *res)
+{
+   u32 base_addr;
+   u64 base64_addr;
+   unsigned long flags;
+
+   if (!res)
+   return -EINVAL;
+
+   spin_lock(_spinlock);
+
+   /* Unhide the P2SB device */
+   pci_bus_write_config_byte(pdev->bus, devfn,

[PATCH v10 0/6] pinctrl/broxton: enable platform device in the absent of ACPI enumeration

2016-11-10 Thread Tan Jui Nee 
ase
- Only call mfd_add_devices() once for all gpio communities

Changes in V2:
- Add new config option CONFIG_X86_INTEL_NON_ACPI and "select PINCTRL"
  to fix kbuildbot error

Andy Shevchenko (1):
  drivers/platform/x86/p2sb: New Primary to Sideband bridge support
    driver for Intel SOC's

Tan Jui Nee (5):
  mfd: lpc_ich: Rename lpc-ich driver
  x86/intel-ivi: Add Intel In-Vehicle Infotainment (IVI) systems used in
cars support
  mfd: move enum lpc_chipsets into lpc_ich.h
  mfd: lpc_ich: Add Device IDs for Intel Apollo Lake PCH
  mfd: lpc_ich: Add support for Intel Apollo Lake GPIO pinctrl in
non-ACPI system

 arch/x86/Kconfig  |   8 ++
 arch/x86/include/asm/p2sb.h   |  27 +++
 drivers/mfd/Kconfig   |   2 +
 drivers/mfd/Makefile  |   5 ++
 drivers/mfd/lpc_ich_apl.c | 120 ++
 drivers/mfd/lpc_ich_apl.h |  29 
 drivers/mfd/{lpc_ich.c => lpc_ich_core.c} |  84 +++--
 drivers/platform/x86/Kconfig  |   4 +
 drivers/platform/x86/Makefile |   1 +
 drivers/platform/x86/p2sb.c   |  98 
 include/linux/mfd/lpc_ich.h   |  72 ++
 11 files changed, 377 insertions(+), 73 deletions(-)
 create mode 100644 arch/x86/include/asm/p2sb.h
 create mode 100644 drivers/mfd/lpc_ich_apl.c
 create mode 100644 drivers/mfd/lpc_ich_apl.h
 rename drivers/mfd/{lpc_ich.c => lpc_ich_core.c} (93%)
 create mode 100644 drivers/platform/x86/p2sb.c

-- 
1.9.1

[PATCH v10 4/6] mfd: move enum lpc_chipsets into lpc_ich.h

2016-11-10 Thread Tan Jui Nee 
Move the enum's definition into a standalone header file which can be used
wherever its definition is needed.

Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
Reviewed-by: Mika Westerberg <mika.westerb...@linux.intel.com>
---
Changes in V10:
- No change

Changes in V9:
- No change

Changes in V8:
- No change

 drivers/mfd/lpc_ich_core.c  | 71 -
 include/linux/mfd/lpc_ich.h | 71 +
 2 files changed, 71 insertions(+), 71 deletions(-)

diff --git a/drivers/mfd/lpc_ich_core.c b/drivers/mfd/lpc_ich_core.c
index 7cbe037..920198a 100644
--- a/drivers/mfd/lpc_ich_core.c
+++ b/drivers/mfd/lpc_ich_core.c
@@ -145,77 +145,6 @@ struct lpc_ich_priv {
.ignore_resource_conflicts = true,
 };
 
-/* chipset related info */
-enum lpc_chipsets {
-   LPC_ICH = 0,/* ICH */
-   LPC_ICH0,   /* ICH0 */
-   LPC_ICH2,   /* ICH2 */
-   LPC_ICH2M,  /* ICH2-M */
-   LPC_ICH3,   /* ICH3-S */
-   LPC_ICH3M,  /* ICH3-M */
-   LPC_ICH4,   /* ICH4 */
-   LPC_ICH4M,  /* ICH4-M */
-   LPC_CICH,   /* C-ICH */
-   LPC_ICH5,   /* ICH5 & ICH5R */
-   LPC_6300ESB,/* 6300ESB */
-   LPC_ICH6,   /* ICH6 & ICH6R */
-   LPC_ICH6M,  /* ICH6-M */
-   LPC_ICH6W,  /* ICH6W & ICH6RW */
-   LPC_631XESB,/* 631xESB/632xESB */
-   LPC_ICH7,   /* ICH7 & ICH7R */
-   LPC_ICH7DH, /* ICH7DH */
-   LPC_ICH7M,  /* ICH7-M & ICH7-U */
-   LPC_ICH7MDH,/* ICH7-M DH */
-   LPC_NM10,   /* NM10 */
-   LPC_ICH8,   /* ICH8 & ICH8R */
-   LPC_ICH8DH, /* ICH8DH */
-   LPC_ICH8DO, /* ICH8DO */
-   LPC_ICH8M,  /* ICH8M */
-   LPC_ICH8ME, /* ICH8M-E */
-   LPC_ICH9,   /* ICH9 */
-   LPC_ICH9R,  /* ICH9R */
-   LPC_ICH9DH, /* ICH9DH */
-   LPC_ICH9DO, /* ICH9DO */
-   LPC_ICH9M,  /* ICH9M */
-   LPC_ICH9ME, /* ICH9M-E */
-   LPC_ICH10,  /* ICH10 */
-   LPC_ICH10R, /* ICH10R */
-   LPC_ICH10D, /* ICH10D */
-   LPC_ICH10DO,/* ICH10DO */
-   LPC_PCH,/* PCH Desktop Full Featured */
-   LPC_PCHM,   /* PCH Mobile Full Featured */
-   LPC_P55,/* P55 */
-   LPC_PM55,   /* PM55 */
-   LPC_H55,/* H55 */
-   LPC_QM57,   /* QM57 */
-   LPC_H57,/* H57 */
-   LPC_HM55,   /* HM55 */
-   LPC_Q57,/* Q57 */
-   LPC_HM57,   /* HM57 */
-   LPC_PCHMSFF,/* PCH Mobile SFF Full Featured */
-   LPC_QS57,   /* QS57 */
-   LPC_3400,   /* 3400 */
-   LPC_3420,   /* 3420 */
-   LPC_3450,   /* 3450 */
-   LPC_EP80579,/* EP80579 */
-   LPC_CPT,/* Cougar Point */
-   LPC_CPTD,   /* Cougar Point Desktop */
-   LPC_CPTM,   /* Cougar Point Mobile */
-   LPC_PBG,/* Patsburg */
-   LPC_DH89XXCC,   /* DH89xxCC */
-   LPC_PPT,/* Panther Point */
-   LPC_LPT,/* Lynx Point */
-   LPC_LPT_LP, /* Lynx Point-LP */
-   LPC_WBG,/* Wellsburg */
-   LPC_AVN,/* Avoton SoC */
-   LPC_BAYTRAIL,   /* Bay Trail SoC */
-   LPC_COLETO, /* Coleto Creek */
-   LPC_WPT_LP, /* Wildcat Point-LP */
-   LPC_BRASWELL,   /* Braswell SoC */
-   LPC_LEWISBURG,  /* Lewisburg */
-   LPC_9S, /* 9 Series */
-};
-
 static struct lpc_ich_info lpc_chipset_info[] = {
[LPC_ICH] = {
.name = "ICH",
diff --git a/include/linux/mfd/lpc_ich.h b/include/linux/mfd/lpc_ich.h
index 2b300b4..42307ee 100644
--- a/include/linux/mfd/lpc_ich.h
+++ b/include/linux/mfd/lpc_ich.h
@@ -43,4 +43,75 @@ struct lpc_ich_info {
u8 use_gpio;
 };
 
+/* chipset related info */
+enum lpc_chipsets {
+   LPC_ICH = 0,/* ICH */
+   LPC_ICH0,   /* ICH0 */
+   LPC_ICH2,   /* ICH2 */
+   LPC_ICH2M,  /* ICH2-M */
+   LPC_ICH3,   /* ICH3-S */
+   LPC_ICH3M,  /* ICH3-M */
+   LPC_ICH4,   /* ICH4 */
+   LPC_ICH4M,  /* ICH4-M */
+   LPC_CICH,   /* C-ICH */
+   LPC_ICH5,   /* ICH5 & ICH5R */
+   LPC_6300ESB,/* 6300ESB */
+   LPC_ICH6,   /* ICH6 & ICH6R */
+   LPC_ICH6M,  /* ICH6-M */
+   LPC_ICH6W,  /* ICH6W & ICH6RW */
+   LPC_631XESB,/* 631xESB/632xESB */
+   LPC_ICH7,   /* ICH7 & ICH7R */
+   LPC_ICH7DH, /* ICH7DH */
+   LPC_ICH7M,  /* ICH7-M & ICH7-U */
+   LPC_ICH7MDH,/* ICH7-M DH */
+   LPC_NM10,   /* NM10 */
+   LPC_ICH8,   /* ICH8 & ICH8R */
+   LPC_ICH8DH, /* ICH8DH */
+   LPC_ICH8DO, /* ICH8DO */
+   LPC_ICH8M,  /* ICH8M */
+   LPC_ICH8ME, /* ICH8M-E */
+   LPC_ICH9,   /* ICH9 */
+   LPC_ICH9R,

[PATCH v10 6/6] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO pinctrl in non-ACPI system

2016-11-10 Thread Tan Jui Nee 
This driver uses the P2SB hide/unhide mechanism cooperatively
to pass the PCI BAR address to the gpio platform driver.

Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
Reviewed-by: Mika Westerberg <mika.westerb...@linux.intel.com>
---
Changes in V10:
- No change

Changes in V9:
- No change

Changes in V8:
- Rename source file lpc_ich-apl.c to lpc_ich_apl.c (suggested by Mika).

Changes in V7:
- Add author information and rewrite description of source file 
  lpc_ich-apl.c and lpc_ich_apl.h.
- Sort the header files by alphabetical order in lpc_ich-apl.c.
- Rename header file lpc_ich-apl.h to lpc_ich_apl.h (suggested by Lee).
- Remove unneeded pdata_size and platform_data from mfd_cell.
  Also, remove unneeded apl_pinctrl_pdata.
- Since variable apl_p2sb is only used once, hence switch it out for the
  PCI_DEVFN macro (suggested by Lee).
- Define APL_GPIO_COMMUNITY_MAX as total Apollo Lake GPIO communities
  supported.
- Set resources in mfd_cell for each GPIO community.
- Call p2sb_bar() function once instead of four times inside the for 
loop.
  And make p2sb_bar() function just to fill in the base address into a
  scratch "struct resource" and have the loop do the additions to 
base/end.
- Remove entire apl_pinctrl_pdata.name memory allocation since it is no
  longer needed.
- Return ret at the end of lpc_ich_add_gpio() function.

Changes in V6:
- Rename CONFIG_X86_INTEL_APL to CONFIG_X86_INTEL_IVI so that it
  relates to the actual product, as suggested by Mika.
- Rework Makefile according Andy's comments.
- Rename lpc_ich_misc() to lpc_ich_add_gpio() so that the name should 
not
  be so generic, as suggested by Andy.
- Call lpc_ich_add_gpio() via priv->chipset.
- lpc_ich_add_gpio() function will be moved from 
  .../include/linux/mfd/lpc_ich.h to
  .../drivers/mfd/lpc_ich-apl.h
  as this is a part of internal driver interface as suggested by Andy.
- Move enum lpc_chipsets from 
  .../drivers/mfd/lpc_ich-core.c to
  .../include/linux/mfd/lpc_ich.h
  as lpc_chipsets is also accessed by lpc_ich_add_gpio().
- Check if kasprintf return value for all 4 gpio controllers before
  proceed to add platform device by using mfd_add_devices().

Changes in V5:
- Split lpc-ich driver into two parts (lpc_ich-core and lpc_ich-apl).
  The file lpc_ich-apl.c introduces gpio platform driver in MFD.
- Rename Kconfig option CONFIG_X86_INTEL_NON_ACPI to 
CONFIG_X86_INTEL_APL
  so that it reflects actual product as suggested by Mika.

Changes in V4:
- Move Kconfig option CONFIG_X86_INTEL_NON_ACPI from
  [PATCH 2/3] x86/platform/p2sb: New Primary to Sideband bridge support 
driver for Intel SOC's
  to
  [PATCH 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO 
pinctrl in non-ACPI system
  since the config is used in latter patch.
- Select CONFIG_P2SB when CONFIG_LPC_ICH is enabled.
- Remove #ifdef CONFIG_X86_INTEL_NON_ACPI and use
  #if defined(CONFIG_X86_INTEL_NON_ACPI) when lpc_ich_misc is called
  as suggested by Lee Jones.
- Use single dimensional array instead of 2D array for apl_gpio_io_res
  structure and use DEFINE_RES_IRQ for its IRQ resource.

Changes in V3:
- Simplify register addresses calculation and use DEFINE_RES_MEM_NAMED
  defines for apl_gpio_io_res structure
- Define magic number for P2SB PCI ID
- Replace switch-case with if-else since currently we have only one
  use case
- Only call mfd_add_devices() once for all gpio communities

Changes in V2:
- Add new config option CONFIG_X86_INTEL_NON_ACPI and "select PINCTRL"
  to fix kbuildbot error

 drivers/mfd/Kconfig|   2 +
 drivers/mfd/Makefile   |   4 ++
 drivers/mfd/lpc_ich_apl.c  | 120 +
 drivers/mfd/lpc_ich_apl.h  |  29 +++
 drivers/mfd/lpc_ich_core.c |   5 ++
 5 files changed, 160 insertions(+)
 create mode 100644 drivers/mfd/lpc_ich_apl.c
 create mode 100644 drivers/mfd/lpc_ich_apl.h

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index c6df644..7bb2f7c 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -391,7 +391,9 @@ config MFD_INTEL_QUARK_I2C_GPIO
 config LPC_ICH
tristate "Intel ICH LPC"
depends on PCI
+   depends on X86 && PCI
select MFD_CORE
+   select P2SB
help
  The LPC bridge function of the Intel ICH provides support for
  many functional units. This driver provides needed support for
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 06a91ea..ccafdfa 100644
--- a/driv

[PATCH v10 0/6] pinctrl/broxton: enable platform device in the absent of ACPI enumeration

2016-11-10 Thread Tan Jui Nee 
ase
- Only call mfd_add_devices() once for all gpio communities

Changes in V2:
- Add new config option CONFIG_X86_INTEL_NON_ACPI and "select PINCTRL"
  to fix kbuildbot error

Andy Shevchenko (1):
  drivers/platform/x86/p2sb: New Primary to Sideband bridge support
    driver for Intel SOC's

Tan Jui Nee (5):
  mfd: lpc_ich: Rename lpc-ich driver
  x86/intel-ivi: Add Intel In-Vehicle Infotainment (IVI) systems used in
cars support
  mfd: move enum lpc_chipsets into lpc_ich.h
  mfd: lpc_ich: Add Device IDs for Intel Apollo Lake PCH
  mfd: lpc_ich: Add support for Intel Apollo Lake GPIO pinctrl in
non-ACPI system

 arch/x86/Kconfig  |   8 ++
 arch/x86/include/asm/p2sb.h   |  27 +++
 drivers/mfd/Kconfig   |   2 +
 drivers/mfd/Makefile  |   5 ++
 drivers/mfd/lpc_ich_apl.c | 120 ++
 drivers/mfd/lpc_ich_apl.h |  29 
 drivers/mfd/{lpc_ich.c => lpc_ich_core.c} |  84 +++--
 drivers/platform/x86/Kconfig  |   4 +
 drivers/platform/x86/Makefile |   1 +
 drivers/platform/x86/p2sb.c   |  98 
 include/linux/mfd/lpc_ich.h   |  72 ++
 11 files changed, 377 insertions(+), 73 deletions(-)
 create mode 100644 arch/x86/include/asm/p2sb.h
 create mode 100644 drivers/mfd/lpc_ich_apl.c
 create mode 100644 drivers/mfd/lpc_ich_apl.h
 rename drivers/mfd/{lpc_ich.c => lpc_ich_core.c} (93%)
 create mode 100644 drivers/platform/x86/p2sb.c

-- 
1.9.1

[PATCH v10 4/6] mfd: move enum lpc_chipsets into lpc_ich.h

2016-11-10 Thread Tan Jui Nee 
Move the enum's definition into a standalone header file which can be used
wherever its definition is needed.

Signed-off-by: Tan Jui Nee 
Reviewed-by: Mika Westerberg 
---
Changes in V10:
- No change

Changes in V9:
- No change

Changes in V8:
- No change

 drivers/mfd/lpc_ich_core.c  | 71 -
 include/linux/mfd/lpc_ich.h | 71 +
 2 files changed, 71 insertions(+), 71 deletions(-)

diff --git a/drivers/mfd/lpc_ich_core.c b/drivers/mfd/lpc_ich_core.c
index 7cbe037..920198a 100644
--- a/drivers/mfd/lpc_ich_core.c
+++ b/drivers/mfd/lpc_ich_core.c
@@ -145,77 +145,6 @@ struct lpc_ich_priv {
.ignore_resource_conflicts = true,
 };
 
-/* chipset related info */
-enum lpc_chipsets {
-   LPC_ICH = 0,/* ICH */
-   LPC_ICH0,   /* ICH0 */
-   LPC_ICH2,   /* ICH2 */
-   LPC_ICH2M,  /* ICH2-M */
-   LPC_ICH3,   /* ICH3-S */
-   LPC_ICH3M,  /* ICH3-M */
-   LPC_ICH4,   /* ICH4 */
-   LPC_ICH4M,  /* ICH4-M */
-   LPC_CICH,   /* C-ICH */
-   LPC_ICH5,   /* ICH5 & ICH5R */
-   LPC_6300ESB,/* 6300ESB */
-   LPC_ICH6,   /* ICH6 & ICH6R */
-   LPC_ICH6M,  /* ICH6-M */
-   LPC_ICH6W,  /* ICH6W & ICH6RW */
-   LPC_631XESB,/* 631xESB/632xESB */
-   LPC_ICH7,   /* ICH7 & ICH7R */
-   LPC_ICH7DH, /* ICH7DH */
-   LPC_ICH7M,  /* ICH7-M & ICH7-U */
-   LPC_ICH7MDH,/* ICH7-M DH */
-   LPC_NM10,   /* NM10 */
-   LPC_ICH8,   /* ICH8 & ICH8R */
-   LPC_ICH8DH, /* ICH8DH */
-   LPC_ICH8DO, /* ICH8DO */
-   LPC_ICH8M,  /* ICH8M */
-   LPC_ICH8ME, /* ICH8M-E */
-   LPC_ICH9,   /* ICH9 */
-   LPC_ICH9R,  /* ICH9R */
-   LPC_ICH9DH, /* ICH9DH */
-   LPC_ICH9DO, /* ICH9DO */
-   LPC_ICH9M,  /* ICH9M */
-   LPC_ICH9ME, /* ICH9M-E */
-   LPC_ICH10,  /* ICH10 */
-   LPC_ICH10R, /* ICH10R */
-   LPC_ICH10D, /* ICH10D */
-   LPC_ICH10DO,/* ICH10DO */
-   LPC_PCH,/* PCH Desktop Full Featured */
-   LPC_PCHM,   /* PCH Mobile Full Featured */
-   LPC_P55,/* P55 */
-   LPC_PM55,   /* PM55 */
-   LPC_H55,/* H55 */
-   LPC_QM57,   /* QM57 */
-   LPC_H57,/* H57 */
-   LPC_HM55,   /* HM55 */
-   LPC_Q57,/* Q57 */
-   LPC_HM57,   /* HM57 */
-   LPC_PCHMSFF,/* PCH Mobile SFF Full Featured */
-   LPC_QS57,   /* QS57 */
-   LPC_3400,   /* 3400 */
-   LPC_3420,   /* 3420 */
-   LPC_3450,   /* 3450 */
-   LPC_EP80579,/* EP80579 */
-   LPC_CPT,/* Cougar Point */
-   LPC_CPTD,   /* Cougar Point Desktop */
-   LPC_CPTM,   /* Cougar Point Mobile */
-   LPC_PBG,/* Patsburg */
-   LPC_DH89XXCC,   /* DH89xxCC */
-   LPC_PPT,/* Panther Point */
-   LPC_LPT,/* Lynx Point */
-   LPC_LPT_LP, /* Lynx Point-LP */
-   LPC_WBG,/* Wellsburg */
-   LPC_AVN,/* Avoton SoC */
-   LPC_BAYTRAIL,   /* Bay Trail SoC */
-   LPC_COLETO, /* Coleto Creek */
-   LPC_WPT_LP, /* Wildcat Point-LP */
-   LPC_BRASWELL,   /* Braswell SoC */
-   LPC_LEWISBURG,  /* Lewisburg */
-   LPC_9S, /* 9 Series */
-};
-
 static struct lpc_ich_info lpc_chipset_info[] = {
[LPC_ICH] = {
.name = "ICH",
diff --git a/include/linux/mfd/lpc_ich.h b/include/linux/mfd/lpc_ich.h
index 2b300b4..42307ee 100644
--- a/include/linux/mfd/lpc_ich.h
+++ b/include/linux/mfd/lpc_ich.h
@@ -43,4 +43,75 @@ struct lpc_ich_info {
u8 use_gpio;
 };
 
+/* chipset related info */
+enum lpc_chipsets {
+   LPC_ICH = 0,/* ICH */
+   LPC_ICH0,   /* ICH0 */
+   LPC_ICH2,   /* ICH2 */
+   LPC_ICH2M,  /* ICH2-M */
+   LPC_ICH3,   /* ICH3-S */
+   LPC_ICH3M,  /* ICH3-M */
+   LPC_ICH4,   /* ICH4 */
+   LPC_ICH4M,  /* ICH4-M */
+   LPC_CICH,   /* C-ICH */
+   LPC_ICH5,   /* ICH5 & ICH5R */
+   LPC_6300ESB,/* 6300ESB */
+   LPC_ICH6,   /* ICH6 & ICH6R */
+   LPC_ICH6M,  /* ICH6-M */
+   LPC_ICH6W,  /* ICH6W & ICH6RW */
+   LPC_631XESB,/* 631xESB/632xESB */
+   LPC_ICH7,   /* ICH7 & ICH7R */
+   LPC_ICH7DH, /* ICH7DH */
+   LPC_ICH7M,  /* ICH7-M & ICH7-U */
+   LPC_ICH7MDH,/* ICH7-M DH */
+   LPC_NM10,   /* NM10 */
+   LPC_ICH8,   /* ICH8 & ICH8R */
+   LPC_ICH8DH, /* ICH8DH */
+   LPC_ICH8DO, /* ICH8DO */
+   LPC_ICH8M,  /* ICH8M */
+   LPC_ICH8ME, /* ICH8M-E */
+   LPC_ICH9,   /* ICH9 */
+   LPC_ICH9R,  /* ICH9R */
+   LPC_ICH9DH, /* ICH9DH */
+   LPC

[PATCH v10 6/6] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO pinctrl in non-ACPI system

2016-11-10 Thread Tan Jui Nee 
This driver uses the P2SB hide/unhide mechanism cooperatively
to pass the PCI BAR address to the gpio platform driver.

Signed-off-by: Tan Jui Nee 
Reviewed-by: Mika Westerberg 
---
Changes in V10:
- No change

Changes in V9:
- No change

Changes in V8:
- Rename source file lpc_ich-apl.c to lpc_ich_apl.c (suggested by Mika).

Changes in V7:
- Add author information and rewrite description of source file 
  lpc_ich-apl.c and lpc_ich_apl.h.
- Sort the header files by alphabetical order in lpc_ich-apl.c.
- Rename header file lpc_ich-apl.h to lpc_ich_apl.h (suggested by Lee).
- Remove unneeded pdata_size and platform_data from mfd_cell.
  Also, remove unneeded apl_pinctrl_pdata.
- Since variable apl_p2sb is only used once, hence switch it out for the
  PCI_DEVFN macro (suggested by Lee).
- Define APL_GPIO_COMMUNITY_MAX as total Apollo Lake GPIO communities
  supported.
- Set resources in mfd_cell for each GPIO community.
- Call p2sb_bar() function once instead of four times inside the for 
loop.
  And make p2sb_bar() function just to fill in the base address into a
  scratch "struct resource" and have the loop do the additions to 
base/end.
- Remove entire apl_pinctrl_pdata.name memory allocation since it is no
  longer needed.
- Return ret at the end of lpc_ich_add_gpio() function.

Changes in V6:
- Rename CONFIG_X86_INTEL_APL to CONFIG_X86_INTEL_IVI so that it
  relates to the actual product, as suggested by Mika.
- Rework Makefile according Andy's comments.
- Rename lpc_ich_misc() to lpc_ich_add_gpio() so that the name should 
not
  be so generic, as suggested by Andy.
- Call lpc_ich_add_gpio() via priv->chipset.
- lpc_ich_add_gpio() function will be moved from 
  .../include/linux/mfd/lpc_ich.h to
  .../drivers/mfd/lpc_ich-apl.h
  as this is a part of internal driver interface as suggested by Andy.
- Move enum lpc_chipsets from 
  .../drivers/mfd/lpc_ich-core.c to
  .../include/linux/mfd/lpc_ich.h
  as lpc_chipsets is also accessed by lpc_ich_add_gpio().
- Check if kasprintf return value for all 4 gpio controllers before
  proceed to add platform device by using mfd_add_devices().

Changes in V5:
- Split lpc-ich driver into two parts (lpc_ich-core and lpc_ich-apl).
  The file lpc_ich-apl.c introduces gpio platform driver in MFD.
- Rename Kconfig option CONFIG_X86_INTEL_NON_ACPI to 
CONFIG_X86_INTEL_APL
  so that it reflects actual product as suggested by Mika.

Changes in V4:
- Move Kconfig option CONFIG_X86_INTEL_NON_ACPI from
  [PATCH 2/3] x86/platform/p2sb: New Primary to Sideband bridge support 
driver for Intel SOC's
  to
  [PATCH 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO 
pinctrl in non-ACPI system
  since the config is used in latter patch.
- Select CONFIG_P2SB when CONFIG_LPC_ICH is enabled.
- Remove #ifdef CONFIG_X86_INTEL_NON_ACPI and use
  #if defined(CONFIG_X86_INTEL_NON_ACPI) when lpc_ich_misc is called
  as suggested by Lee Jones.
- Use single dimensional array instead of 2D array for apl_gpio_io_res
  structure and use DEFINE_RES_IRQ for its IRQ resource.

Changes in V3:
- Simplify register addresses calculation and use DEFINE_RES_MEM_NAMED
  defines for apl_gpio_io_res structure
- Define magic number for P2SB PCI ID
- Replace switch-case with if-else since currently we have only one
  use case
- Only call mfd_add_devices() once for all gpio communities

Changes in V2:
- Add new config option CONFIG_X86_INTEL_NON_ACPI and "select PINCTRL"
  to fix kbuildbot error

 drivers/mfd/Kconfig|   2 +
 drivers/mfd/Makefile   |   4 ++
 drivers/mfd/lpc_ich_apl.c  | 120 +
 drivers/mfd/lpc_ich_apl.h  |  29 +++
 drivers/mfd/lpc_ich_core.c |   5 ++
 5 files changed, 160 insertions(+)
 create mode 100644 drivers/mfd/lpc_ich_apl.c
 create mode 100644 drivers/mfd/lpc_ich_apl.h

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index c6df644..7bb2f7c 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -391,7 +391,9 @@ config MFD_INTEL_QUARK_I2C_GPIO
 config LPC_ICH
tristate "Intel ICH LPC"
depends on PCI
+   depends on X86 && PCI
select MFD_CORE
+   select P2SB
help
  The LPC bridge function of the Intel ICH provides support for
  many functional units. This driver provides needed support for
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 06a91ea..ccafdfa 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -161,6 +161,10

[PATCH v10 2/6] mfd: lpc_ich: Rename lpc-ich driver

2016-11-10 Thread Tan Jui Nee 
This patch follows the example of mfd/wm831x to rename the driver
from "lpc_ich" to "lpc_ich_core".

Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
Reviewed-by: Mika Westerberg <mika.westerb...@linux.intel.com>
---
Changes in V10:
- No change

Changes in V9:
- Remove the filename from the header of lpc_ich_core.c (suggested by 
Lee).

Changes in V8:
- Update new file name with lpc_ich_core.c at description of source 
file.
- Rework Makefile with new source file name lpc_ich_apl.c.

Changes in V7:
- No change

Changes in V6:
- none, just a subject line and commit message change.

 drivers/mfd/Makefile  | 1 +
 drivers/mfd/{lpc_ich.c => lpc_ich_core.c} | 2 --
 2 files changed, 1 insertion(+), 2 deletions(-)
 rename drivers/mfd/{lpc_ich.c => lpc_ich_core.c} (99%)

diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 9834e66..06a91ea 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -159,6 +159,7 @@ obj-$(CONFIG_PMIC_ADP5520)  += adp5520.o
 obj-$(CONFIG_MFD_KEMPLD)   += kempld-core.o
 obj-$(CONFIG_MFD_INTEL_QUARK_I2C_GPIO) += intel_quark_i2c_gpio.o
 obj-$(CONFIG_LPC_SCH)  += lpc_sch.o
+lpc_ich-objs   := lpc_ich_core.o
 obj-$(CONFIG_LPC_ICH)  += lpc_ich.o
 obj-$(CONFIG_MFD_RDC321X)  += rdc321x-southbridge.o
 obj-$(CONFIG_MFD_JANZ_CMODIO)  += janz-cmodio.o
diff --git a/drivers/mfd/lpc_ich.c b/drivers/mfd/lpc_ich_core.c
similarity index 99%
rename from drivers/mfd/lpc_ich.c
rename to drivers/mfd/lpc_ich_core.c
index c8dee47..7cbe037 100644
--- a/drivers/mfd/lpc_ich.c
+++ b/drivers/mfd/lpc_ich_core.c
@@ -1,6 +1,4 @@
 /*
- *  lpc_ich.c - LPC interface for Intel ICH
- *
  *  LPC bridge function of the Intel ICH contains many other
  *  functional units, such as Interrupt controllers, Timers,
  *  Power Management, System Management, GPIO, RTC, and LPC
-- 
1.9.1

[PATCH v10 5/6] mfd: lpc_ich: Add Device IDs for Intel Apollo Lake PCH

2016-11-10 Thread Tan Jui Nee 
Adding Intel codename Apollo Lake platform device IDs for PCH.

Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
Acked-for-MFD-by: Lee Jones <lee.jo...@linaro.org>
---
Changes in V10:
- No change

Changes in V9:
- No change

Changes in V8:
- No change

 drivers/mfd/lpc_ich_core.c  | 6 ++
 include/linux/mfd/lpc_ich.h | 1 +
 2 files changed, 7 insertions(+)

diff --git a/drivers/mfd/lpc_ich_core.c b/drivers/mfd/lpc_ich_core.c
index 920198a..3bb6334 100644
--- a/drivers/mfd/lpc_ich_core.c
+++ b/drivers/mfd/lpc_ich_core.c
@@ -54,6 +54,7 @@
  * document number TBD : Wildcat Point-LP
  * document number TBD : 9 Series
  * document number TBD : Lewisburg
+ * document number TBD : Apollo Lake
  */
 
 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
@@ -458,6 +459,10 @@ struct lpc_ich_priv {
.name = "9 Series",
.iTCO_version = 2,
},
+   [LPC_APL]  = {
+   .name = "Apollo Lake SoC",
+   .iTCO_version = 5,
+   },
 };
 
 /*
@@ -606,6 +611,7 @@ struct lpc_ich_priv {
{ PCI_VDEVICE(INTEL, 0x3b14), LPC_3420},
{ PCI_VDEVICE(INTEL, 0x3b16), LPC_3450},
{ PCI_VDEVICE(INTEL, 0x5031), LPC_EP80579},
+   { PCI_VDEVICE(INTEL, 0x5ae8), LPC_APL},
{ PCI_VDEVICE(INTEL, 0x8c40), LPC_LPT},
{ PCI_VDEVICE(INTEL, 0x8c41), LPC_LPT},
{ PCI_VDEVICE(INTEL, 0x8c42), LPC_LPT},
diff --git a/include/linux/mfd/lpc_ich.h b/include/linux/mfd/lpc_ich.h
index 42307ee..397008c 100644
--- a/include/linux/mfd/lpc_ich.h
+++ b/include/linux/mfd/lpc_ich.h
@@ -112,6 +112,7 @@ enum lpc_chipsets {
LPC_BRASWELL,   /* Braswell SoC */
LPC_LEWISBURG,  /* Lewisburg */
LPC_9S, /* 9 Series */
+   LPC_APL,/* Apollo Lake SoC */
 };
 
 #endif
-- 
1.9.1

[PATCH v10 2/6] mfd: lpc_ich: Rename lpc-ich driver

2016-11-10 Thread Tan Jui Nee 
This patch follows the example of mfd/wm831x to rename the driver
from "lpc_ich" to "lpc_ich_core".

Signed-off-by: Tan Jui Nee 
Reviewed-by: Mika Westerberg 
---
Changes in V10:
- No change

Changes in V9:
- Remove the filename from the header of lpc_ich_core.c (suggested by 
Lee).

Changes in V8:
- Update new file name with lpc_ich_core.c at description of source 
file.
- Rework Makefile with new source file name lpc_ich_apl.c.

Changes in V7:
- No change

Changes in V6:
- none, just a subject line and commit message change.

 drivers/mfd/Makefile  | 1 +
 drivers/mfd/{lpc_ich.c => lpc_ich_core.c} | 2 --
 2 files changed, 1 insertion(+), 2 deletions(-)
 rename drivers/mfd/{lpc_ich.c => lpc_ich_core.c} (99%)

diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 9834e66..06a91ea 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -159,6 +159,7 @@ obj-$(CONFIG_PMIC_ADP5520)  += adp5520.o
 obj-$(CONFIG_MFD_KEMPLD)   += kempld-core.o
 obj-$(CONFIG_MFD_INTEL_QUARK_I2C_GPIO) += intel_quark_i2c_gpio.o
 obj-$(CONFIG_LPC_SCH)  += lpc_sch.o
+lpc_ich-objs   := lpc_ich_core.o
 obj-$(CONFIG_LPC_ICH)  += lpc_ich.o
 obj-$(CONFIG_MFD_RDC321X)  += rdc321x-southbridge.o
 obj-$(CONFIG_MFD_JANZ_CMODIO)  += janz-cmodio.o
diff --git a/drivers/mfd/lpc_ich.c b/drivers/mfd/lpc_ich_core.c
similarity index 99%
rename from drivers/mfd/lpc_ich.c
rename to drivers/mfd/lpc_ich_core.c
index c8dee47..7cbe037 100644
--- a/drivers/mfd/lpc_ich.c
+++ b/drivers/mfd/lpc_ich_core.c
@@ -1,6 +1,4 @@
 /*
- *  lpc_ich.c - LPC interface for Intel ICH
- *
  *  LPC bridge function of the Intel ICH contains many other
  *  functional units, such as Interrupt controllers, Timers,
  *  Power Management, System Management, GPIO, RTC, and LPC
-- 
1.9.1

[PATCH v10 5/6] mfd: lpc_ich: Add Device IDs for Intel Apollo Lake PCH

2016-11-10 Thread Tan Jui Nee 
Adding Intel codename Apollo Lake platform device IDs for PCH.

Signed-off-by: Tan Jui Nee 
Acked-for-MFD-by: Lee Jones 
---
Changes in V10:
- No change

Changes in V9:
- No change

Changes in V8:
- No change

 drivers/mfd/lpc_ich_core.c  | 6 ++
 include/linux/mfd/lpc_ich.h | 1 +
 2 files changed, 7 insertions(+)

diff --git a/drivers/mfd/lpc_ich_core.c b/drivers/mfd/lpc_ich_core.c
index 920198a..3bb6334 100644
--- a/drivers/mfd/lpc_ich_core.c
+++ b/drivers/mfd/lpc_ich_core.c
@@ -54,6 +54,7 @@
  * document number TBD : Wildcat Point-LP
  * document number TBD : 9 Series
  * document number TBD : Lewisburg
+ * document number TBD : Apollo Lake
  */
 
 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
@@ -458,6 +459,10 @@ struct lpc_ich_priv {
.name = "9 Series",
.iTCO_version = 2,
},
+   [LPC_APL]  = {
+   .name = "Apollo Lake SoC",
+   .iTCO_version = 5,
+   },
 };
 
 /*
@@ -606,6 +611,7 @@ struct lpc_ich_priv {
{ PCI_VDEVICE(INTEL, 0x3b14), LPC_3420},
{ PCI_VDEVICE(INTEL, 0x3b16), LPC_3450},
{ PCI_VDEVICE(INTEL, 0x5031), LPC_EP80579},
+   { PCI_VDEVICE(INTEL, 0x5ae8), LPC_APL},
{ PCI_VDEVICE(INTEL, 0x8c40), LPC_LPT},
{ PCI_VDEVICE(INTEL, 0x8c41), LPC_LPT},
{ PCI_VDEVICE(INTEL, 0x8c42), LPC_LPT},
diff --git a/include/linux/mfd/lpc_ich.h b/include/linux/mfd/lpc_ich.h
index 42307ee..397008c 100644
--- a/include/linux/mfd/lpc_ich.h
+++ b/include/linux/mfd/lpc_ich.h
@@ -112,6 +112,7 @@ enum lpc_chipsets {
LPC_BRASWELL,   /* Braswell SoC */
LPC_LEWISBURG,  /* Lewisburg */
LPC_9S, /* 9 Series */
+   LPC_APL,/* Apollo Lake SoC */
 };
 
 #endif
-- 
1.9.1

[PATCH v9 6/6] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO pinctrl in non-ACPI system

2016-11-08 Thread Tan Jui Nee 
This driver uses the P2SB hide/unhide mechanism cooperatively
to pass the PCI BAR address to the gpio platform driver.

Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
Changes in V9:
- No change

Changes in V8:
- Rename source file lpc_ich-apl.c to lpc_ich_apl.c (suggested by Mika).

Changes in V7:
- Add author information and rewrite description of source file 
  lpc_ich-apl.c and lpc_ich_apl.h.
- Sort the header files by alphabetical order in lpc_ich-apl.c.
- Rename header file lpc_ich-apl.h to lpc_ich_apl.h (suggested by Lee).
- Remove unneeded pdata_size and platform_data from mfd_cell.
  Also, remove unneeded apl_pinctrl_pdata.
- Since variable apl_p2sb is only used once, hence switch it out for the
  PCI_DEVFN macro (suggested by Lee).
- Define APL_GPIO_COMMUNITY_MAX as total Apollo Lake GPIO communities
  supported.
- Set resources in mfd_cell for each GPIO community.
- Call p2sb_bar() function once instead of four times inside the for 
loop.
  And make p2sb_bar() function just to fill in the base address into a
  scratch "struct resource" and have the loop do the additions to 
base/end.
- Remove entire apl_pinctrl_pdata.name memory allocation since it is no
  longer needed.
- Return ret at the end of lpc_ich_add_gpio() function.

Changes in V6:
- Rename CONFIG_X86_INTEL_APL to CONFIG_X86_INTEL_IVI so that it
  relates to the actual product, as suggested by Mika.
- Rework Makefile according Andy's comments.
- Rename lpc_ich_misc() to lpc_ich_add_gpio() so that the name should 
not
  be so generic, as suggested by Andy.
- Call lpc_ich_add_gpio() via priv->chipset.
- lpc_ich_add_gpio() function will be moved from 
  .../include/linux/mfd/lpc_ich.h to
  .../drivers/mfd/lpc_ich-apl.h
  as this is a part of internal driver interface as suggested by Andy.
- Move enum lpc_chipsets from 
  .../drivers/mfd/lpc_ich-core.c to
  .../include/linux/mfd/lpc_ich.h
  as lpc_chipsets is also accessed by lpc_ich_add_gpio().
- Check if kasprintf return value for all 4 gpio controllers before
  proceed to add platform device by using mfd_add_devices().

Changes in V5:
- Split lpc-ich driver into two parts (lpc_ich-core and lpc_ich-apl).
  The file lpc_ich-apl.c introduces gpio platform driver in MFD.
- Rename Kconfig option CONFIG_X86_INTEL_NON_ACPI to 
CONFIG_X86_INTEL_APL
  so that it reflects actual product as suggested by Mika.

Changes in V4:
- Move Kconfig option CONFIG_X86_INTEL_NON_ACPI from
  [PATCH 2/3] x86/platform/p2sb: New Primary to Sideband bridge support 
driver for Intel SOC's
  to
  [PATCH 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO 
pinctrl in non-ACPI system
  since the config is used in latter patch.
- Select CONFIG_P2SB when CONFIG_LPC_ICH is enabled.
- Remove #ifdef CONFIG_X86_INTEL_NON_ACPI and use
  #if defined(CONFIG_X86_INTEL_NON_ACPI) when lpc_ich_misc is called
  as suggested by Lee Jones.
- Use single dimensional array instead of 2D array for apl_gpio_io_res
  structure and use DEFINE_RES_IRQ for its IRQ resource.

Changes in V3:
- Simplify register addresses calculation and use DEFINE_RES_MEM_NAMED
  defines for apl_gpio_io_res structure
- Define magic number for P2SB PCI ID
- Replace switch-case with if-else since currently we have only one
  use case
- Only call mfd_add_devices() once for all gpio communities

Changes in V2:
- Add new config option CONFIG_X86_INTEL_NON_ACPI and "select PINCTRL"
  to fix kbuildbot error

 drivers/mfd/Kconfig|   2 +
 drivers/mfd/Makefile   |   4 ++
 drivers/mfd/lpc_ich_apl.c  | 120 +
 drivers/mfd/lpc_ich_apl.h  |  29 +++
 drivers/mfd/lpc_ich_core.c |   5 ++
 5 files changed, 160 insertions(+)
 create mode 100644 drivers/mfd/lpc_ich_apl.c
 create mode 100644 drivers/mfd/lpc_ich_apl.h

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index c6df644..7bb2f7c 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -391,7 +391,9 @@ config MFD_INTEL_QUARK_I2C_GPIO
 config LPC_ICH
tristate "Intel ICH LPC"
depends on PCI
+   depends on X86 && PCI
select MFD_CORE
+   select P2SB
help
  The LPC bridge function of the Intel ICH provides support for
  many functional units. This driver provides needed support for
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 06a91ea..ccafdfa 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -161,6 +161,10 @@ obj-$(CONFIG_MFD_INTEL_QUARK_I2C_GPIO) +

[PATCH v9 6/6] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO pinctrl in non-ACPI system

2016-11-08 Thread Tan Jui Nee 
This driver uses the P2SB hide/unhide mechanism cooperatively
to pass the PCI BAR address to the gpio platform driver.

Signed-off-by: Tan Jui Nee 
---
Changes in V9:
- No change

Changes in V8:
- Rename source file lpc_ich-apl.c to lpc_ich_apl.c (suggested by Mika).

Changes in V7:
- Add author information and rewrite description of source file 
  lpc_ich-apl.c and lpc_ich_apl.h.
- Sort the header files by alphabetical order in lpc_ich-apl.c.
- Rename header file lpc_ich-apl.h to lpc_ich_apl.h (suggested by Lee).
- Remove unneeded pdata_size and platform_data from mfd_cell.
  Also, remove unneeded apl_pinctrl_pdata.
- Since variable apl_p2sb is only used once, hence switch it out for the
  PCI_DEVFN macro (suggested by Lee).
- Define APL_GPIO_COMMUNITY_MAX as total Apollo Lake GPIO communities
  supported.
- Set resources in mfd_cell for each GPIO community.
- Call p2sb_bar() function once instead of four times inside the for 
loop.
  And make p2sb_bar() function just to fill in the base address into a
  scratch "struct resource" and have the loop do the additions to 
base/end.
- Remove entire apl_pinctrl_pdata.name memory allocation since it is no
  longer needed.
- Return ret at the end of lpc_ich_add_gpio() function.

Changes in V6:
- Rename CONFIG_X86_INTEL_APL to CONFIG_X86_INTEL_IVI so that it
  relates to the actual product, as suggested by Mika.
- Rework Makefile according Andy's comments.
- Rename lpc_ich_misc() to lpc_ich_add_gpio() so that the name should 
not
  be so generic, as suggested by Andy.
- Call lpc_ich_add_gpio() via priv->chipset.
- lpc_ich_add_gpio() function will be moved from 
  .../include/linux/mfd/lpc_ich.h to
  .../drivers/mfd/lpc_ich-apl.h
  as this is a part of internal driver interface as suggested by Andy.
- Move enum lpc_chipsets from 
  .../drivers/mfd/lpc_ich-core.c to
  .../include/linux/mfd/lpc_ich.h
  as lpc_chipsets is also accessed by lpc_ich_add_gpio().
- Check if kasprintf return value for all 4 gpio controllers before
  proceed to add platform device by using mfd_add_devices().

Changes in V5:
- Split lpc-ich driver into two parts (lpc_ich-core and lpc_ich-apl).
  The file lpc_ich-apl.c introduces gpio platform driver in MFD.
- Rename Kconfig option CONFIG_X86_INTEL_NON_ACPI to 
CONFIG_X86_INTEL_APL
  so that it reflects actual product as suggested by Mika.

Changes in V4:
- Move Kconfig option CONFIG_X86_INTEL_NON_ACPI from
  [PATCH 2/3] x86/platform/p2sb: New Primary to Sideband bridge support 
driver for Intel SOC's
  to
  [PATCH 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO 
pinctrl in non-ACPI system
  since the config is used in latter patch.
- Select CONFIG_P2SB when CONFIG_LPC_ICH is enabled.
- Remove #ifdef CONFIG_X86_INTEL_NON_ACPI and use
  #if defined(CONFIG_X86_INTEL_NON_ACPI) when lpc_ich_misc is called
  as suggested by Lee Jones.
- Use single dimensional array instead of 2D array for apl_gpio_io_res
  structure and use DEFINE_RES_IRQ for its IRQ resource.

Changes in V3:
- Simplify register addresses calculation and use DEFINE_RES_MEM_NAMED
  defines for apl_gpio_io_res structure
- Define magic number for P2SB PCI ID
- Replace switch-case with if-else since currently we have only one
  use case
- Only call mfd_add_devices() once for all gpio communities

Changes in V2:
- Add new config option CONFIG_X86_INTEL_NON_ACPI and "select PINCTRL"
  to fix kbuildbot error

 drivers/mfd/Kconfig|   2 +
 drivers/mfd/Makefile   |   4 ++
 drivers/mfd/lpc_ich_apl.c  | 120 +
 drivers/mfd/lpc_ich_apl.h  |  29 +++
 drivers/mfd/lpc_ich_core.c |   5 ++
 5 files changed, 160 insertions(+)
 create mode 100644 drivers/mfd/lpc_ich_apl.c
 create mode 100644 drivers/mfd/lpc_ich_apl.h

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index c6df644..7bb2f7c 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -391,7 +391,9 @@ config MFD_INTEL_QUARK_I2C_GPIO
 config LPC_ICH
tristate "Intel ICH LPC"
depends on PCI
+   depends on X86 && PCI
select MFD_CORE
+   select P2SB
help
  The LPC bridge function of the Intel ICH provides support for
  many functional units. This driver provides needed support for
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 06a91ea..ccafdfa 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -161,6 +161,10 @@ obj-$(CONFIG_MFD_INTEL_QUARK_I2C_GPIO) += 
intel_quark_i2c_gpio.o
 ob

[PATCH v9 5/6] mfd: lpc_ich: Add Device IDs for Intel Apollo Lake PCH

2016-11-08 Thread Tan Jui Nee 
Adding Intel codename Apollo Lake platform device IDs for PCH.

Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
Acked-for-MFD-by: Lee Jones <lee.jo...@linaro.org>
---
Changes in V9:
- No change

Changes in V8:
- No change

 drivers/mfd/lpc_ich_core.c  | 6 ++
 include/linux/mfd/lpc_ich.h | 1 +
 2 files changed, 7 insertions(+)

diff --git a/drivers/mfd/lpc_ich_core.c b/drivers/mfd/lpc_ich_core.c
index 920198a..3bb6334 100644
--- a/drivers/mfd/lpc_ich_core.c
+++ b/drivers/mfd/lpc_ich_core.c
@@ -54,6 +54,7 @@
  * document number TBD : Wildcat Point-LP
  * document number TBD : 9 Series
  * document number TBD : Lewisburg
+ * document number TBD : Apollo Lake
  */
 
 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
@@ -458,6 +459,10 @@ struct lpc_ich_priv {
.name = "9 Series",
.iTCO_version = 2,
},
+   [LPC_APL]  = {
+   .name = "Apollo Lake SoC",
+   .iTCO_version = 5,
+   },
 };
 
 /*
@@ -606,6 +611,7 @@ struct lpc_ich_priv {
{ PCI_VDEVICE(INTEL, 0x3b14), LPC_3420},
{ PCI_VDEVICE(INTEL, 0x3b16), LPC_3450},
{ PCI_VDEVICE(INTEL, 0x5031), LPC_EP80579},
+   { PCI_VDEVICE(INTEL, 0x5ae8), LPC_APL},
{ PCI_VDEVICE(INTEL, 0x8c40), LPC_LPT},
{ PCI_VDEVICE(INTEL, 0x8c41), LPC_LPT},
{ PCI_VDEVICE(INTEL, 0x8c42), LPC_LPT},
diff --git a/include/linux/mfd/lpc_ich.h b/include/linux/mfd/lpc_ich.h
index 42307ee..397008c 100644
--- a/include/linux/mfd/lpc_ich.h
+++ b/include/linux/mfd/lpc_ich.h
@@ -112,6 +112,7 @@ enum lpc_chipsets {
LPC_BRASWELL,   /* Braswell SoC */
LPC_LEWISBURG,  /* Lewisburg */
LPC_9S, /* 9 Series */
+   LPC_APL,/* Apollo Lake SoC */
 };
 
 #endif
-- 
1.9.1

[PATCH v9 1/6] x86/platform/p2sb: New Primary to Sideband bridge support driver for Intel SOC's

2016-11-08 Thread Tan Jui Nee 
From: Andy Shevchenko 

There is already one and at least one more user coming which
require an access to Primary to Sideband bridge (P2SB) in order
to get IO or MMIO bar hidden by BIOS.
Create a driver to access P2SB for x86 devices.

Signed-off-by: Yong, Jonathan 
Signed-off-by: Andy Shevchenko 
---
Changes in V9:
- No change

Changes in V8:
- No change

Changes in V7:
- EXPORT_SYMBOL_GPL() and MODULE_LICENSE("GPL v2") are used for new file
  p2sb.c.

Changes in V6:
- No change

Changes in V5:
- No change

Changes in V4:
- Move Kconfig option CONFIG_X86_INTEL_NON_ACPI from
  [PATCH 2/3] x86/platform/p2sb: New Primary to Sideband bridge support 
driver for Intel SOC's
  to
  [PATCH 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO 
pinctrl in non-ACPI system
  since the config is used in latter patch.

Changes in V3:
- No change

Changes in V2:
- Add new config option CONFIG_X86_INTEL_NON_ACPI and "select PINCTRL"
  to fix kbuildbot error

 arch/x86/Kconfig |  4 ++
 arch/x86/include/asm/p2sb.h  | 27 +++
 arch/x86/platform/intel/Makefile |  1 +
 arch/x86/platform/intel/p2sb.c   | 98 
 4 files changed, 130 insertions(+)
 create mode 100644 arch/x86/include/asm/p2sb.h
 create mode 100644 arch/x86/platform/intel/p2sb.c

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index bada636..e2c1dcf 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -615,6 +615,10 @@ config IOSF_MBI_DEBUG
 
  If you don't require the option or are in doubt, say N.
 
+config P2SB
+   tristate
+   depends on PCI
+
 config X86_RDC321X
bool "RDC R-321x SoC"
depends on X86_32
diff --git a/arch/x86/include/asm/p2sb.h b/arch/x86/include/asm/p2sb.h
new file mode 100644
index 000..686e07b
--- /dev/null
+++ b/arch/x86/include/asm/p2sb.h
@@ -0,0 +1,27 @@
+/*
+ * Primary to Sideband bridge (P2SB) access support
+ */
+
+#ifndef P2SB_SYMS_H
+#define P2SB_SYMS_H
+
+#include 
+#include 
+
+#if IS_ENABLED(CONFIG_P2SB)
+
+int p2sb_bar(struct pci_dev *pdev, unsigned int devfn,
+   struct resource *res);
+
+#else /* CONFIG_P2SB is not set */
+
+static inline
+int p2sb_bar(struct pci_dev *pdev, unsigned int devfn,
+   struct resource *res)
+{
+   return -ENODEV;
+}
+
+#endif /* CONFIG_P2SB */
+
+#endif /* P2SB_SYMS_H */
diff --git a/arch/x86/platform/intel/Makefile b/arch/x86/platform/intel/Makefile
index b878032..dbf9f10 100644
--- a/arch/x86/platform/intel/Makefile
+++ b/arch/x86/platform/intel/Makefile
@@ -1 +1,2 @@
 obj-$(CONFIG_IOSF_MBI) += iosf_mbi.o
+obj-$(CONFIG_P2SB) += p2sb.o
diff --git a/arch/x86/platform/intel/p2sb.c b/arch/x86/platform/intel/p2sb.c
new file mode 100644
index 000..b1d784c
--- /dev/null
+++ b/arch/x86/platform/intel/p2sb.c
@@ -0,0 +1,98 @@
+/*
+ * Primary to Sideband bridge (P2SB) driver
+ *
+ * Copyright (c) 2016, Intel Corporation.
+ *
+ * Authors: Andy Shevchenko 
+ * Jonathan Yong 
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#define SBREG_BAR  0x10
+#define SBREG_HIDE 0xe1
+
+static DEFINE_SPINLOCK(p2sb_spinlock);
+
+/*
+ * p2sb_bar - Get Primary to Sideband bridge (P2SB) BAR
+ * @pdev:  PCI device to get PCI bus to communicate with
+ * @devfn: PCI device and function to communicate with
+ * @res:   resources to be filled in
+ *
+ * The BIOS prevents the P2SB device from being enumerated by the PCI
+ * subsystem, so we need to unhide and hide it back to lookup the P2SB BAR.
+ *
+ * Locking is handled by spinlock - cannot sleep.
+ *
+ * Return:
+ * 0 on success or appropriate errno value on error.
+ */
+int p2sb_bar(struct pci_dev *pdev, unsigned int devfn,
+   struct resource *res)
+{
+   u32 base_addr;
+   u64 base64_addr;
+   unsigned long flags;
+
+   if (!res)
+   return -EINVAL;
+
+   spin_lock(_spinlock);
+
+   /* Unhide the P2SB device */
+   pci_bus_write_config_byte(pdev->bus, devfn, SBREG_HIDE, 0x00);
+
+   /* Check if device present */
+   pci_bus_read_config_dword(pdev->bus, devfn, 0, _addr);
+   if (base_addr == 0x || base_addr == 0x) {
+   spin_unlock(_spinlock);
+

[PATCH v9 5/6] mfd: lpc_ich: Add Device IDs for Intel Apollo Lake PCH

2016-11-08 Thread Tan Jui Nee 
Adding Intel codename Apollo Lake platform device IDs for PCH.

Signed-off-by: Tan Jui Nee 
Acked-for-MFD-by: Lee Jones 
---
Changes in V9:
- No change

Changes in V8:
- No change

 drivers/mfd/lpc_ich_core.c  | 6 ++
 include/linux/mfd/lpc_ich.h | 1 +
 2 files changed, 7 insertions(+)

diff --git a/drivers/mfd/lpc_ich_core.c b/drivers/mfd/lpc_ich_core.c
index 920198a..3bb6334 100644
--- a/drivers/mfd/lpc_ich_core.c
+++ b/drivers/mfd/lpc_ich_core.c
@@ -54,6 +54,7 @@
  * document number TBD : Wildcat Point-LP
  * document number TBD : 9 Series
  * document number TBD : Lewisburg
+ * document number TBD : Apollo Lake
  */
 
 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
@@ -458,6 +459,10 @@ struct lpc_ich_priv {
.name = "9 Series",
.iTCO_version = 2,
},
+   [LPC_APL]  = {
+   .name = "Apollo Lake SoC",
+   .iTCO_version = 5,
+   },
 };
 
 /*
@@ -606,6 +611,7 @@ struct lpc_ich_priv {
{ PCI_VDEVICE(INTEL, 0x3b14), LPC_3420},
{ PCI_VDEVICE(INTEL, 0x3b16), LPC_3450},
{ PCI_VDEVICE(INTEL, 0x5031), LPC_EP80579},
+   { PCI_VDEVICE(INTEL, 0x5ae8), LPC_APL},
{ PCI_VDEVICE(INTEL, 0x8c40), LPC_LPT},
{ PCI_VDEVICE(INTEL, 0x8c41), LPC_LPT},
{ PCI_VDEVICE(INTEL, 0x8c42), LPC_LPT},
diff --git a/include/linux/mfd/lpc_ich.h b/include/linux/mfd/lpc_ich.h
index 42307ee..397008c 100644
--- a/include/linux/mfd/lpc_ich.h
+++ b/include/linux/mfd/lpc_ich.h
@@ -112,6 +112,7 @@ enum lpc_chipsets {
LPC_BRASWELL,   /* Braswell SoC */
LPC_LEWISBURG,  /* Lewisburg */
LPC_9S, /* 9 Series */
+   LPC_APL,/* Apollo Lake SoC */
 };
 
 #endif
-- 
1.9.1

[PATCH v9 1/6] x86/platform/p2sb: New Primary to Sideband bridge support driver for Intel SOC's

2016-11-08 Thread Tan Jui Nee 
From: Andy Shevchenko 

There is already one and at least one more user coming which
require an access to Primary to Sideband bridge (P2SB) in order
to get IO or MMIO bar hidden by BIOS.
Create a driver to access P2SB for x86 devices.

Signed-off-by: Yong, Jonathan 
Signed-off-by: Andy Shevchenko 
---
Changes in V9:
- No change

Changes in V8:
- No change

Changes in V7:
- EXPORT_SYMBOL_GPL() and MODULE_LICENSE("GPL v2") are used for new file
  p2sb.c.

Changes in V6:
- No change

Changes in V5:
- No change

Changes in V4:
- Move Kconfig option CONFIG_X86_INTEL_NON_ACPI from
  [PATCH 2/3] x86/platform/p2sb: New Primary to Sideband bridge support 
driver for Intel SOC's
  to
  [PATCH 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO 
pinctrl in non-ACPI system
  since the config is used in latter patch.

Changes in V3:
- No change

Changes in V2:
- Add new config option CONFIG_X86_INTEL_NON_ACPI and "select PINCTRL"
  to fix kbuildbot error

 arch/x86/Kconfig |  4 ++
 arch/x86/include/asm/p2sb.h  | 27 +++
 arch/x86/platform/intel/Makefile |  1 +
 arch/x86/platform/intel/p2sb.c   | 98 
 4 files changed, 130 insertions(+)
 create mode 100644 arch/x86/include/asm/p2sb.h
 create mode 100644 arch/x86/platform/intel/p2sb.c

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index bada636..e2c1dcf 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -615,6 +615,10 @@ config IOSF_MBI_DEBUG
 
  If you don't require the option or are in doubt, say N.
 
+config P2SB
+   tristate
+   depends on PCI
+
 config X86_RDC321X
bool "RDC R-321x SoC"
depends on X86_32
diff --git a/arch/x86/include/asm/p2sb.h b/arch/x86/include/asm/p2sb.h
new file mode 100644
index 000..686e07b
--- /dev/null
+++ b/arch/x86/include/asm/p2sb.h
@@ -0,0 +1,27 @@
+/*
+ * Primary to Sideband bridge (P2SB) access support
+ */
+
+#ifndef P2SB_SYMS_H
+#define P2SB_SYMS_H
+
+#include 
+#include 
+
+#if IS_ENABLED(CONFIG_P2SB)
+
+int p2sb_bar(struct pci_dev *pdev, unsigned int devfn,
+   struct resource *res);
+
+#else /* CONFIG_P2SB is not set */
+
+static inline
+int p2sb_bar(struct pci_dev *pdev, unsigned int devfn,
+   struct resource *res)
+{
+   return -ENODEV;
+}
+
+#endif /* CONFIG_P2SB */
+
+#endif /* P2SB_SYMS_H */
diff --git a/arch/x86/platform/intel/Makefile b/arch/x86/platform/intel/Makefile
index b878032..dbf9f10 100644
--- a/arch/x86/platform/intel/Makefile
+++ b/arch/x86/platform/intel/Makefile
@@ -1 +1,2 @@
 obj-$(CONFIG_IOSF_MBI) += iosf_mbi.o
+obj-$(CONFIG_P2SB) += p2sb.o
diff --git a/arch/x86/platform/intel/p2sb.c b/arch/x86/platform/intel/p2sb.c
new file mode 100644
index 000..b1d784c
--- /dev/null
+++ b/arch/x86/platform/intel/p2sb.c
@@ -0,0 +1,98 @@
+/*
+ * Primary to Sideband bridge (P2SB) driver
+ *
+ * Copyright (c) 2016, Intel Corporation.
+ *
+ * Authors: Andy Shevchenko 
+ * Jonathan Yong 
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#define SBREG_BAR  0x10
+#define SBREG_HIDE 0xe1
+
+static DEFINE_SPINLOCK(p2sb_spinlock);
+
+/*
+ * p2sb_bar - Get Primary to Sideband bridge (P2SB) BAR
+ * @pdev:  PCI device to get PCI bus to communicate with
+ * @devfn: PCI device and function to communicate with
+ * @res:   resources to be filled in
+ *
+ * The BIOS prevents the P2SB device from being enumerated by the PCI
+ * subsystem, so we need to unhide and hide it back to lookup the P2SB BAR.
+ *
+ * Locking is handled by spinlock - cannot sleep.
+ *
+ * Return:
+ * 0 on success or appropriate errno value on error.
+ */
+int p2sb_bar(struct pci_dev *pdev, unsigned int devfn,
+   struct resource *res)
+{
+   u32 base_addr;
+   u64 base64_addr;
+   unsigned long flags;
+
+   if (!res)
+   return -EINVAL;
+
+   spin_lock(_spinlock);
+
+   /* Unhide the P2SB device */
+   pci_bus_write_config_byte(pdev->bus, devfn, SBREG_HIDE, 0x00);
+
+   /* Check if device present */
+   pci_bus_read_config_dword(pdev->bus, devfn, 0, _addr);
+   if (base_addr == 0x || base_addr == 0x) {
+   spin_unlock(_spinlock);
+   dev_warn(>dev, "P2SB device access disabled by BIOS?\n");
+   return -ENODEV;
+   }
+
+   /* Get IO or MMIO BAR */
+

[PATCH v9 0/6] pinctrl/broxton: enable platform device in the absent of ACPI enumeration

2016-11-08 Thread Tan Jui Nee 
CPI and "select PINCTRL"
  to fix kbuildbot error

Andy Shevchenko (1):
  x86/platform/p2sb: New Primary to Sideband bridge support driver for
Intel SOC's

Tan Jui Nee (5):
  mfd: lpc_ich: Rename lpc-ich driver
  x86/intel-ivi: Add Intel In-Vehicle Infotainment (IVI) systems used in
cars support
  mfd: move enum lpc_chipsets into lpc_ich.h
  mfd: lpc_ich: Add Device IDs for Intel Apollo Lake PCH
  mfd: lpc_ich: Add support for Intel Apollo Lake GPIO pinctrl in
non-ACPI system

 arch/x86/Kconfig  |  12 +++
 arch/x86/include/asm/p2sb.h   |  27 +++
 arch/x86/platform/intel/Makefile  |   1 +
 arch/x86/platform/intel/p2sb.c|  98 
 drivers/mfd/Kconfig   |   2 +
 drivers/mfd/Makefile  |   5 ++
 drivers/mfd/lpc_ich_apl.c | 120 ++
 drivers/mfd/lpc_ich_apl.h |  29 
 drivers/mfd/{lpc_ich.c => lpc_ich_core.c} |  84 +++--
 include/linux/mfd/lpc_ich.h   |  72 ++
 10 files changed, 377 insertions(+), 73 deletions(-)
 create mode 100644 arch/x86/include/asm/p2sb.h
 create mode 100644 arch/x86/platform/intel/p2sb.c
 create mode 100644 drivers/mfd/lpc_ich_apl.c
 create mode 100644 drivers/mfd/lpc_ich_apl.h
 rename drivers/mfd/{lpc_ich.c => lpc_ich_core.c} (93%)

-- 
1.9.1

[PATCH v9 2/6] mfd: lpc_ich: Rename lpc-ich driver

2016-11-08 Thread Tan Jui Nee 
This patch follows the example of mfd/wm831x to rename the driver
from "lpc_ich" to "lpc_ich_core".

Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
Changes in V9:
- Remove the filename from the header of lpc_ich_core.c (suggested by 
Lee).

Changes in V8:
- Update new file name with lpc_ich_core.c at description of source 
file.
- Rework Makefile with new source file name lpc_ich_apl.c.

Changes in V7:
- No change

Changes in V6:
- none, just a subject line and commit message change.

 drivers/mfd/Makefile  | 1 +
 drivers/mfd/{lpc_ich.c => lpc_ich_core.c} | 2 --
 2 files changed, 1 insertion(+), 2 deletions(-)
 rename drivers/mfd/{lpc_ich.c => lpc_ich_core.c} (99%)

diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 9834e66..06a91ea 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -159,6 +159,7 @@ obj-$(CONFIG_PMIC_ADP5520)  += adp5520.o
 obj-$(CONFIG_MFD_KEMPLD)   += kempld-core.o
 obj-$(CONFIG_MFD_INTEL_QUARK_I2C_GPIO) += intel_quark_i2c_gpio.o
 obj-$(CONFIG_LPC_SCH)  += lpc_sch.o
+lpc_ich-objs   := lpc_ich_core.o
 obj-$(CONFIG_LPC_ICH)  += lpc_ich.o
 obj-$(CONFIG_MFD_RDC321X)  += rdc321x-southbridge.o
 obj-$(CONFIG_MFD_JANZ_CMODIO)  += janz-cmodio.o
diff --git a/drivers/mfd/lpc_ich.c b/drivers/mfd/lpc_ich_core.c
similarity index 99%
rename from drivers/mfd/lpc_ich.c
rename to drivers/mfd/lpc_ich_core.c
index c8dee47..7cbe037 100644
--- a/drivers/mfd/lpc_ich.c
+++ b/drivers/mfd/lpc_ich_core.c
@@ -1,6 +1,4 @@
 /*
- *  lpc_ich.c - LPC interface for Intel ICH
- *
  *  LPC bridge function of the Intel ICH contains many other
  *  functional units, such as Interrupt controllers, Timers,
  *  Power Management, System Management, GPIO, RTC, and LPC
-- 
1.9.1

[PATCH v9 0/6] pinctrl/broxton: enable platform device in the absent of ACPI enumeration

2016-11-08 Thread Tan Jui Nee 
CPI and "select PINCTRL"
  to fix kbuildbot error

Andy Shevchenko (1):
  x86/platform/p2sb: New Primary to Sideband bridge support driver for
Intel SOC's

Tan Jui Nee (5):
  mfd: lpc_ich: Rename lpc-ich driver
  x86/intel-ivi: Add Intel In-Vehicle Infotainment (IVI) systems used in
cars support
  mfd: move enum lpc_chipsets into lpc_ich.h
  mfd: lpc_ich: Add Device IDs for Intel Apollo Lake PCH
  mfd: lpc_ich: Add support for Intel Apollo Lake GPIO pinctrl in
non-ACPI system

 arch/x86/Kconfig  |  12 +++
 arch/x86/include/asm/p2sb.h   |  27 +++
 arch/x86/platform/intel/Makefile  |   1 +
 arch/x86/platform/intel/p2sb.c|  98 
 drivers/mfd/Kconfig   |   2 +
 drivers/mfd/Makefile  |   5 ++
 drivers/mfd/lpc_ich_apl.c | 120 ++
 drivers/mfd/lpc_ich_apl.h |  29 
 drivers/mfd/{lpc_ich.c => lpc_ich_core.c} |  84 +++--
 include/linux/mfd/lpc_ich.h   |  72 ++
 10 files changed, 377 insertions(+), 73 deletions(-)
 create mode 100644 arch/x86/include/asm/p2sb.h
 create mode 100644 arch/x86/platform/intel/p2sb.c
 create mode 100644 drivers/mfd/lpc_ich_apl.c
 create mode 100644 drivers/mfd/lpc_ich_apl.h
 rename drivers/mfd/{lpc_ich.c => lpc_ich_core.c} (93%)

-- 
1.9.1

[PATCH v9 2/6] mfd: lpc_ich: Rename lpc-ich driver

2016-11-08 Thread Tan Jui Nee 
This patch follows the example of mfd/wm831x to rename the driver
from "lpc_ich" to "lpc_ich_core".

Signed-off-by: Tan Jui Nee 
---
Changes in V9:
- Remove the filename from the header of lpc_ich_core.c (suggested by 
Lee).

Changes in V8:
- Update new file name with lpc_ich_core.c at description of source 
file.
- Rework Makefile with new source file name lpc_ich_apl.c.

Changes in V7:
- No change

Changes in V6:
- none, just a subject line and commit message change.

 drivers/mfd/Makefile  | 1 +
 drivers/mfd/{lpc_ich.c => lpc_ich_core.c} | 2 --
 2 files changed, 1 insertion(+), 2 deletions(-)
 rename drivers/mfd/{lpc_ich.c => lpc_ich_core.c} (99%)

diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 9834e66..06a91ea 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -159,6 +159,7 @@ obj-$(CONFIG_PMIC_ADP5520)  += adp5520.o
 obj-$(CONFIG_MFD_KEMPLD)   += kempld-core.o
 obj-$(CONFIG_MFD_INTEL_QUARK_I2C_GPIO) += intel_quark_i2c_gpio.o
 obj-$(CONFIG_LPC_SCH)  += lpc_sch.o
+lpc_ich-objs   := lpc_ich_core.o
 obj-$(CONFIG_LPC_ICH)  += lpc_ich.o
 obj-$(CONFIG_MFD_RDC321X)  += rdc321x-southbridge.o
 obj-$(CONFIG_MFD_JANZ_CMODIO)  += janz-cmodio.o
diff --git a/drivers/mfd/lpc_ich.c b/drivers/mfd/lpc_ich_core.c
similarity index 99%
rename from drivers/mfd/lpc_ich.c
rename to drivers/mfd/lpc_ich_core.c
index c8dee47..7cbe037 100644
--- a/drivers/mfd/lpc_ich.c
+++ b/drivers/mfd/lpc_ich_core.c
@@ -1,6 +1,4 @@
 /*
- *  lpc_ich.c - LPC interface for Intel ICH
- *
  *  LPC bridge function of the Intel ICH contains many other
  *  functional units, such as Interrupt controllers, Timers,
  *  Power Management, System Management, GPIO, RTC, and LPC
-- 
1.9.1

[PATCH v9 4/6] mfd: move enum lpc_chipsets into lpc_ich.h

2016-11-08 Thread Tan Jui Nee 
Move the enum's definition into a standalone header file which can be used
wherever its definition is needed.

Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
Changes in V9:
- No change

Changes in V8:
- No change

 drivers/mfd/lpc_ich_core.c  | 71 -
 include/linux/mfd/lpc_ich.h | 71 +
 2 files changed, 71 insertions(+), 71 deletions(-)

diff --git a/drivers/mfd/lpc_ich_core.c b/drivers/mfd/lpc_ich_core.c
index 7cbe037..920198a 100644
--- a/drivers/mfd/lpc_ich_core.c
+++ b/drivers/mfd/lpc_ich_core.c
@@ -145,77 +145,6 @@ struct lpc_ich_priv {
.ignore_resource_conflicts = true,
 };
 
-/* chipset related info */
-enum lpc_chipsets {
-   LPC_ICH = 0,/* ICH */
-   LPC_ICH0,   /* ICH0 */
-   LPC_ICH2,   /* ICH2 */
-   LPC_ICH2M,  /* ICH2-M */
-   LPC_ICH3,   /* ICH3-S */
-   LPC_ICH3M,  /* ICH3-M */
-   LPC_ICH4,   /* ICH4 */
-   LPC_ICH4M,  /* ICH4-M */
-   LPC_CICH,   /* C-ICH */
-   LPC_ICH5,   /* ICH5 & ICH5R */
-   LPC_6300ESB,/* 6300ESB */
-   LPC_ICH6,   /* ICH6 & ICH6R */
-   LPC_ICH6M,  /* ICH6-M */
-   LPC_ICH6W,  /* ICH6W & ICH6RW */
-   LPC_631XESB,/* 631xESB/632xESB */
-   LPC_ICH7,   /* ICH7 & ICH7R */
-   LPC_ICH7DH, /* ICH7DH */
-   LPC_ICH7M,  /* ICH7-M & ICH7-U */
-   LPC_ICH7MDH,/* ICH7-M DH */
-   LPC_NM10,   /* NM10 */
-   LPC_ICH8,   /* ICH8 & ICH8R */
-   LPC_ICH8DH, /* ICH8DH */
-   LPC_ICH8DO, /* ICH8DO */
-   LPC_ICH8M,  /* ICH8M */
-   LPC_ICH8ME, /* ICH8M-E */
-   LPC_ICH9,   /* ICH9 */
-   LPC_ICH9R,  /* ICH9R */
-   LPC_ICH9DH, /* ICH9DH */
-   LPC_ICH9DO, /* ICH9DO */
-   LPC_ICH9M,  /* ICH9M */
-   LPC_ICH9ME, /* ICH9M-E */
-   LPC_ICH10,  /* ICH10 */
-   LPC_ICH10R, /* ICH10R */
-   LPC_ICH10D, /* ICH10D */
-   LPC_ICH10DO,/* ICH10DO */
-   LPC_PCH,/* PCH Desktop Full Featured */
-   LPC_PCHM,   /* PCH Mobile Full Featured */
-   LPC_P55,/* P55 */
-   LPC_PM55,   /* PM55 */
-   LPC_H55,/* H55 */
-   LPC_QM57,   /* QM57 */
-   LPC_H57,/* H57 */
-   LPC_HM55,   /* HM55 */
-   LPC_Q57,/* Q57 */
-   LPC_HM57,   /* HM57 */
-   LPC_PCHMSFF,/* PCH Mobile SFF Full Featured */
-   LPC_QS57,   /* QS57 */
-   LPC_3400,   /* 3400 */
-   LPC_3420,   /* 3420 */
-   LPC_3450,   /* 3450 */
-   LPC_EP80579,/* EP80579 */
-   LPC_CPT,/* Cougar Point */
-   LPC_CPTD,   /* Cougar Point Desktop */
-   LPC_CPTM,   /* Cougar Point Mobile */
-   LPC_PBG,/* Patsburg */
-   LPC_DH89XXCC,   /* DH89xxCC */
-   LPC_PPT,/* Panther Point */
-   LPC_LPT,/* Lynx Point */
-   LPC_LPT_LP, /* Lynx Point-LP */
-   LPC_WBG,/* Wellsburg */
-   LPC_AVN,/* Avoton SoC */
-   LPC_BAYTRAIL,   /* Bay Trail SoC */
-   LPC_COLETO, /* Coleto Creek */
-   LPC_WPT_LP, /* Wildcat Point-LP */
-   LPC_BRASWELL,   /* Braswell SoC */
-   LPC_LEWISBURG,  /* Lewisburg */
-   LPC_9S, /* 9 Series */
-};
-
 static struct lpc_ich_info lpc_chipset_info[] = {
[LPC_ICH] = {
.name = "ICH",
diff --git a/include/linux/mfd/lpc_ich.h b/include/linux/mfd/lpc_ich.h
index 2b300b4..42307ee 100644
--- a/include/linux/mfd/lpc_ich.h
+++ b/include/linux/mfd/lpc_ich.h
@@ -43,4 +43,75 @@ struct lpc_ich_info {
u8 use_gpio;
 };
 
+/* chipset related info */
+enum lpc_chipsets {
+   LPC_ICH = 0,/* ICH */
+   LPC_ICH0,   /* ICH0 */
+   LPC_ICH2,   /* ICH2 */
+   LPC_ICH2M,  /* ICH2-M */
+   LPC_ICH3,   /* ICH3-S */
+   LPC_ICH3M,  /* ICH3-M */
+   LPC_ICH4,   /* ICH4 */
+   LPC_ICH4M,  /* ICH4-M */
+   LPC_CICH,   /* C-ICH */
+   LPC_ICH5,   /* ICH5 & ICH5R */
+   LPC_6300ESB,/* 6300ESB */
+   LPC_ICH6,   /* ICH6 & ICH6R */
+   LPC_ICH6M,  /* ICH6-M */
+   LPC_ICH6W,  /* ICH6W & ICH6RW */
+   LPC_631XESB,/* 631xESB/632xESB */
+   LPC_ICH7,   /* ICH7 & ICH7R */
+   LPC_ICH7DH, /* ICH7DH */
+   LPC_ICH7M,  /* ICH7-M & ICH7-U */
+   LPC_ICH7MDH,/* ICH7-M DH */
+   LPC_NM10,   /* NM10 */
+   LPC_ICH8,   /* ICH8 & ICH8R */
+   LPC_ICH8DH, /* ICH8DH */
+   LPC_ICH8DO, /* ICH8DO */
+   LPC_ICH8M,  /* ICH8M */
+   LPC_ICH8ME, /* ICH8M-E */
+   LPC_ICH9,   /* ICH9 */
+   LPC_ICH9R,  /* ICH9R */
+   LPC_ICH9DH, /* ICH9DH */
+   LPC_ICH9DO, /* ICH9DO */
+

[PATCH v9 3/6] x86/intel-ivi: Add Intel In-Vehicle Infotainment (IVI) systems used in cars support

2016-11-08 Thread Tan Jui Nee 
Add support for non ACPI system, such as system that uses Advanced Boot
Loader (ABL) whereby a platform device has to be created in order to bind
with PINCTRL/GPIO.

At the moment, Intel Apollo Lake SoC requires P2SB driver to hide and
unhide P2SB to lookup P2SB BAR and pass the PCI BAR address to GPIO.

Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
Changes in V9:
- No change

Changes in V8:
- No change

 arch/x86/Kconfig | 8 
 1 file changed, 8 insertions(+)

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index e2c1dcf..aa8928a 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -512,6 +512,14 @@ config X86_INTEL_CE
  This option compiles in support for the CE4100 SOC for settop
  boxes and media devices.
 
+config X86_INTEL_IVI
+   bool "Intel In-Vehicle Infotainment (IVI) systems used in cars"
+   ---help---
+ Select this option to enable MMIO BAR access over the P2SB for
+ non-ACPI Intel Apollo Lake SoC platforms. This driver uses the P2SB
+ hide/unhide mechanism cooperatively to pass the PCI BAR address to
+ the platform driver, currently GPIO.
+
 config X86_INTEL_MID
bool "Intel MID platform support"
depends on X86_EXTENDED_PLATFORM
-- 
1.9.1

[PATCH v9 3/6] x86/intel-ivi: Add Intel In-Vehicle Infotainment (IVI) systems used in cars support

2016-11-08 Thread Tan Jui Nee 
Add support for non ACPI system, such as system that uses Advanced Boot
Loader (ABL) whereby a platform device has to be created in order to bind
with PINCTRL/GPIO.

At the moment, Intel Apollo Lake SoC requires P2SB driver to hide and
unhide P2SB to lookup P2SB BAR and pass the PCI BAR address to GPIO.

Signed-off-by: Tan Jui Nee 
---
Changes in V9:
- No change

Changes in V8:
- No change

 arch/x86/Kconfig | 8 
 1 file changed, 8 insertions(+)

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index e2c1dcf..aa8928a 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -512,6 +512,14 @@ config X86_INTEL_CE
  This option compiles in support for the CE4100 SOC for settop
  boxes and media devices.
 
+config X86_INTEL_IVI
+   bool "Intel In-Vehicle Infotainment (IVI) systems used in cars"
+   ---help---
+ Select this option to enable MMIO BAR access over the P2SB for
+ non-ACPI Intel Apollo Lake SoC platforms. This driver uses the P2SB
+ hide/unhide mechanism cooperatively to pass the PCI BAR address to
+ the platform driver, currently GPIO.
+
 config X86_INTEL_MID
bool "Intel MID platform support"
depends on X86_EXTENDED_PLATFORM
-- 
1.9.1

[PATCH v9 4/6] mfd: move enum lpc_chipsets into lpc_ich.h

2016-11-08 Thread Tan Jui Nee 
Move the enum's definition into a standalone header file which can be used
wherever its definition is needed.

Signed-off-by: Tan Jui Nee 
---
Changes in V9:
- No change

Changes in V8:
- No change

 drivers/mfd/lpc_ich_core.c  | 71 -
 include/linux/mfd/lpc_ich.h | 71 +
 2 files changed, 71 insertions(+), 71 deletions(-)

diff --git a/drivers/mfd/lpc_ich_core.c b/drivers/mfd/lpc_ich_core.c
index 7cbe037..920198a 100644
--- a/drivers/mfd/lpc_ich_core.c
+++ b/drivers/mfd/lpc_ich_core.c
@@ -145,77 +145,6 @@ struct lpc_ich_priv {
.ignore_resource_conflicts = true,
 };
 
-/* chipset related info */
-enum lpc_chipsets {
-   LPC_ICH = 0,/* ICH */
-   LPC_ICH0,   /* ICH0 */
-   LPC_ICH2,   /* ICH2 */
-   LPC_ICH2M,  /* ICH2-M */
-   LPC_ICH3,   /* ICH3-S */
-   LPC_ICH3M,  /* ICH3-M */
-   LPC_ICH4,   /* ICH4 */
-   LPC_ICH4M,  /* ICH4-M */
-   LPC_CICH,   /* C-ICH */
-   LPC_ICH5,   /* ICH5 & ICH5R */
-   LPC_6300ESB,/* 6300ESB */
-   LPC_ICH6,   /* ICH6 & ICH6R */
-   LPC_ICH6M,  /* ICH6-M */
-   LPC_ICH6W,  /* ICH6W & ICH6RW */
-   LPC_631XESB,/* 631xESB/632xESB */
-   LPC_ICH7,   /* ICH7 & ICH7R */
-   LPC_ICH7DH, /* ICH7DH */
-   LPC_ICH7M,  /* ICH7-M & ICH7-U */
-   LPC_ICH7MDH,/* ICH7-M DH */
-   LPC_NM10,   /* NM10 */
-   LPC_ICH8,   /* ICH8 & ICH8R */
-   LPC_ICH8DH, /* ICH8DH */
-   LPC_ICH8DO, /* ICH8DO */
-   LPC_ICH8M,  /* ICH8M */
-   LPC_ICH8ME, /* ICH8M-E */
-   LPC_ICH9,   /* ICH9 */
-   LPC_ICH9R,  /* ICH9R */
-   LPC_ICH9DH, /* ICH9DH */
-   LPC_ICH9DO, /* ICH9DO */
-   LPC_ICH9M,  /* ICH9M */
-   LPC_ICH9ME, /* ICH9M-E */
-   LPC_ICH10,  /* ICH10 */
-   LPC_ICH10R, /* ICH10R */
-   LPC_ICH10D, /* ICH10D */
-   LPC_ICH10DO,/* ICH10DO */
-   LPC_PCH,/* PCH Desktop Full Featured */
-   LPC_PCHM,   /* PCH Mobile Full Featured */
-   LPC_P55,/* P55 */
-   LPC_PM55,   /* PM55 */
-   LPC_H55,/* H55 */
-   LPC_QM57,   /* QM57 */
-   LPC_H57,/* H57 */
-   LPC_HM55,   /* HM55 */
-   LPC_Q57,/* Q57 */
-   LPC_HM57,   /* HM57 */
-   LPC_PCHMSFF,/* PCH Mobile SFF Full Featured */
-   LPC_QS57,   /* QS57 */
-   LPC_3400,   /* 3400 */
-   LPC_3420,   /* 3420 */
-   LPC_3450,   /* 3450 */
-   LPC_EP80579,/* EP80579 */
-   LPC_CPT,/* Cougar Point */
-   LPC_CPTD,   /* Cougar Point Desktop */
-   LPC_CPTM,   /* Cougar Point Mobile */
-   LPC_PBG,/* Patsburg */
-   LPC_DH89XXCC,   /* DH89xxCC */
-   LPC_PPT,/* Panther Point */
-   LPC_LPT,/* Lynx Point */
-   LPC_LPT_LP, /* Lynx Point-LP */
-   LPC_WBG,/* Wellsburg */
-   LPC_AVN,/* Avoton SoC */
-   LPC_BAYTRAIL,   /* Bay Trail SoC */
-   LPC_COLETO, /* Coleto Creek */
-   LPC_WPT_LP, /* Wildcat Point-LP */
-   LPC_BRASWELL,   /* Braswell SoC */
-   LPC_LEWISBURG,  /* Lewisburg */
-   LPC_9S, /* 9 Series */
-};
-
 static struct lpc_ich_info lpc_chipset_info[] = {
[LPC_ICH] = {
.name = "ICH",
diff --git a/include/linux/mfd/lpc_ich.h b/include/linux/mfd/lpc_ich.h
index 2b300b4..42307ee 100644
--- a/include/linux/mfd/lpc_ich.h
+++ b/include/linux/mfd/lpc_ich.h
@@ -43,4 +43,75 @@ struct lpc_ich_info {
u8 use_gpio;
 };
 
+/* chipset related info */
+enum lpc_chipsets {
+   LPC_ICH = 0,/* ICH */
+   LPC_ICH0,   /* ICH0 */
+   LPC_ICH2,   /* ICH2 */
+   LPC_ICH2M,  /* ICH2-M */
+   LPC_ICH3,   /* ICH3-S */
+   LPC_ICH3M,  /* ICH3-M */
+   LPC_ICH4,   /* ICH4 */
+   LPC_ICH4M,  /* ICH4-M */
+   LPC_CICH,   /* C-ICH */
+   LPC_ICH5,   /* ICH5 & ICH5R */
+   LPC_6300ESB,/* 6300ESB */
+   LPC_ICH6,   /* ICH6 & ICH6R */
+   LPC_ICH6M,  /* ICH6-M */
+   LPC_ICH6W,  /* ICH6W & ICH6RW */
+   LPC_631XESB,/* 631xESB/632xESB */
+   LPC_ICH7,   /* ICH7 & ICH7R */
+   LPC_ICH7DH, /* ICH7DH */
+   LPC_ICH7M,  /* ICH7-M & ICH7-U */
+   LPC_ICH7MDH,/* ICH7-M DH */
+   LPC_NM10,   /* NM10 */
+   LPC_ICH8,   /* ICH8 & ICH8R */
+   LPC_ICH8DH, /* ICH8DH */
+   LPC_ICH8DO, /* ICH8DO */
+   LPC_ICH8M,  /* ICH8M */
+   LPC_ICH8ME, /* ICH8M-E */
+   LPC_ICH9,   /* ICH9 */
+   LPC_ICH9R,  /* ICH9R */
+   LPC_ICH9DH, /* ICH9DH */
+   LPC_ICH9DO, /* ICH9DO */
+   LPC_ICH9M,  /* ICH9M */
+   LPC_

[PATCH v8 5/6] mfd: lpc_ich: Add Device IDs for Intel Apollo Lake PCH

2016-10-12 Thread Tan Jui Nee 
Adding Intel codename Apollo Lake platform device IDs for PCH.

Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
Changes in V8:
- No change

 drivers/mfd/lpc_ich_core.c  | 6 ++
 include/linux/mfd/lpc_ich.h | 1 +
 2 files changed, 7 insertions(+)

diff --git a/drivers/mfd/lpc_ich_core.c b/drivers/mfd/lpc_ich_core.c
index bfba832..27e7e63 100644
--- a/drivers/mfd/lpc_ich_core.c
+++ b/drivers/mfd/lpc_ich_core.c
@@ -56,6 +56,7 @@
  * document number TBD : Wildcat Point-LP
  * document number TBD : 9 Series
  * document number TBD : Lewisburg
+ * document number TBD : Apollo Lake
  */
 
 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
@@ -460,6 +461,10 @@ struct lpc_ich_priv {
.name = "9 Series",
.iTCO_version = 2,
},
+   [LPC_APL]  = {
+   .name = "Apollo Lake SoC",
+   .iTCO_version = 5,
+   },
 };
 
 /*
@@ -608,6 +613,7 @@ struct lpc_ich_priv {
{ PCI_VDEVICE(INTEL, 0x3b14), LPC_3420},
{ PCI_VDEVICE(INTEL, 0x3b16), LPC_3450},
{ PCI_VDEVICE(INTEL, 0x5031), LPC_EP80579},
+   { PCI_VDEVICE(INTEL, 0x5ae8), LPC_APL},
{ PCI_VDEVICE(INTEL, 0x8c40), LPC_LPT},
{ PCI_VDEVICE(INTEL, 0x8c41), LPC_LPT},
{ PCI_VDEVICE(INTEL, 0x8c42), LPC_LPT},
diff --git a/include/linux/mfd/lpc_ich.h b/include/linux/mfd/lpc_ich.h
index 42307ee..397008c 100644
--- a/include/linux/mfd/lpc_ich.h
+++ b/include/linux/mfd/lpc_ich.h
@@ -112,6 +112,7 @@ enum lpc_chipsets {
LPC_BRASWELL,   /* Braswell SoC */
LPC_LEWISBURG,  /* Lewisburg */
LPC_9S, /* 9 Series */
+   LPC_APL,/* Apollo Lake SoC */
 };
 
 #endif
-- 
1.9.1

[PATCH v8 5/6] mfd: lpc_ich: Add Device IDs for Intel Apollo Lake PCH

2016-10-12 Thread Tan Jui Nee 
Adding Intel codename Apollo Lake platform device IDs for PCH.

Signed-off-by: Tan Jui Nee 
---
Changes in V8:
- No change

 drivers/mfd/lpc_ich_core.c  | 6 ++
 include/linux/mfd/lpc_ich.h | 1 +
 2 files changed, 7 insertions(+)

diff --git a/drivers/mfd/lpc_ich_core.c b/drivers/mfd/lpc_ich_core.c
index bfba832..27e7e63 100644
--- a/drivers/mfd/lpc_ich_core.c
+++ b/drivers/mfd/lpc_ich_core.c
@@ -56,6 +56,7 @@
  * document number TBD : Wildcat Point-LP
  * document number TBD : 9 Series
  * document number TBD : Lewisburg
+ * document number TBD : Apollo Lake
  */
 
 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
@@ -460,6 +461,10 @@ struct lpc_ich_priv {
.name = "9 Series",
.iTCO_version = 2,
},
+   [LPC_APL]  = {
+   .name = "Apollo Lake SoC",
+   .iTCO_version = 5,
+   },
 };
 
 /*
@@ -608,6 +613,7 @@ struct lpc_ich_priv {
{ PCI_VDEVICE(INTEL, 0x3b14), LPC_3420},
{ PCI_VDEVICE(INTEL, 0x3b16), LPC_3450},
{ PCI_VDEVICE(INTEL, 0x5031), LPC_EP80579},
+   { PCI_VDEVICE(INTEL, 0x5ae8), LPC_APL},
{ PCI_VDEVICE(INTEL, 0x8c40), LPC_LPT},
{ PCI_VDEVICE(INTEL, 0x8c41), LPC_LPT},
{ PCI_VDEVICE(INTEL, 0x8c42), LPC_LPT},
diff --git a/include/linux/mfd/lpc_ich.h b/include/linux/mfd/lpc_ich.h
index 42307ee..397008c 100644
--- a/include/linux/mfd/lpc_ich.h
+++ b/include/linux/mfd/lpc_ich.h
@@ -112,6 +112,7 @@ enum lpc_chipsets {
LPC_BRASWELL,   /* Braswell SoC */
LPC_LEWISBURG,  /* Lewisburg */
LPC_9S, /* 9 Series */
+   LPC_APL,/* Apollo Lake SoC */
 };
 
 #endif
-- 
1.9.1

[PATCH v8 3/6] x86/intel-ivi: Add Intel In-Vehicle Infotainment (IVI) systems used in cars support

2016-10-12 Thread Tan Jui Nee 
Add support for non ACPI system, such as system that uses Advanced Boot
Loader (ABL) whereby a platform device has to be created in order to bind
with PINCTRL/GPIO.

At the moment, Intel Apollo Lake SoC requires P2SB driver to hide and
unhide P2SB to lookup P2SB BAR and pass the PCI BAR address to GPIO.

Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
Changes in V8:
- No change

 arch/x86/Kconfig | 8 
 1 file changed, 8 insertions(+)

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index e2c1dcf..aa8928a 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -512,6 +512,14 @@ config X86_INTEL_CE
  This option compiles in support for the CE4100 SOC for settop
  boxes and media devices.
 
+config X86_INTEL_IVI
+   bool "Intel In-Vehicle Infotainment (IVI) systems used in cars"
+   ---help---
+ Select this option to enable MMIO BAR access over the P2SB for
+ non-ACPI Intel Apollo Lake SoC platforms. This driver uses the P2SB
+ hide/unhide mechanism cooperatively to pass the PCI BAR address to
+ the platform driver, currently GPIO.
+
 config X86_INTEL_MID
bool "Intel MID platform support"
depends on X86_EXTENDED_PLATFORM
-- 
1.9.1

[PATCH v8 4/6] mfd: move enum lpc_chipsets into lpc_ich.h

2016-10-12 Thread Tan Jui Nee 
Move the enum's definition into a standalone header file which can be used
wherever its definition is needed.

Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
Changes in V8:
- No change

 drivers/mfd/lpc_ich_core.c  | 71 -
 include/linux/mfd/lpc_ich.h | 71 +
 2 files changed, 71 insertions(+), 71 deletions(-)

diff --git a/drivers/mfd/lpc_ich_core.c b/drivers/mfd/lpc_ich_core.c
index 01d8d9e..bfba832 100644
--- a/drivers/mfd/lpc_ich_core.c
+++ b/drivers/mfd/lpc_ich_core.c
@@ -147,77 +147,6 @@ struct lpc_ich_priv {
.ignore_resource_conflicts = true,
 };
 
-/* chipset related info */
-enum lpc_chipsets {
-   LPC_ICH = 0,/* ICH */
-   LPC_ICH0,   /* ICH0 */
-   LPC_ICH2,   /* ICH2 */
-   LPC_ICH2M,  /* ICH2-M */
-   LPC_ICH3,   /* ICH3-S */
-   LPC_ICH3M,  /* ICH3-M */
-   LPC_ICH4,   /* ICH4 */
-   LPC_ICH4M,  /* ICH4-M */
-   LPC_CICH,   /* C-ICH */
-   LPC_ICH5,   /* ICH5 & ICH5R */
-   LPC_6300ESB,/* 6300ESB */
-   LPC_ICH6,   /* ICH6 & ICH6R */
-   LPC_ICH6M,  /* ICH6-M */
-   LPC_ICH6W,  /* ICH6W & ICH6RW */
-   LPC_631XESB,/* 631xESB/632xESB */
-   LPC_ICH7,   /* ICH7 & ICH7R */
-   LPC_ICH7DH, /* ICH7DH */
-   LPC_ICH7M,  /* ICH7-M & ICH7-U */
-   LPC_ICH7MDH,/* ICH7-M DH */
-   LPC_NM10,   /* NM10 */
-   LPC_ICH8,   /* ICH8 & ICH8R */
-   LPC_ICH8DH, /* ICH8DH */
-   LPC_ICH8DO, /* ICH8DO */
-   LPC_ICH8M,  /* ICH8M */
-   LPC_ICH8ME, /* ICH8M-E */
-   LPC_ICH9,   /* ICH9 */
-   LPC_ICH9R,  /* ICH9R */
-   LPC_ICH9DH, /* ICH9DH */
-   LPC_ICH9DO, /* ICH9DO */
-   LPC_ICH9M,  /* ICH9M */
-   LPC_ICH9ME, /* ICH9M-E */
-   LPC_ICH10,  /* ICH10 */
-   LPC_ICH10R, /* ICH10R */
-   LPC_ICH10D, /* ICH10D */
-   LPC_ICH10DO,/* ICH10DO */
-   LPC_PCH,/* PCH Desktop Full Featured */
-   LPC_PCHM,   /* PCH Mobile Full Featured */
-   LPC_P55,/* P55 */
-   LPC_PM55,   /* PM55 */
-   LPC_H55,/* H55 */
-   LPC_QM57,   /* QM57 */
-   LPC_H57,/* H57 */
-   LPC_HM55,   /* HM55 */
-   LPC_Q57,/* Q57 */
-   LPC_HM57,   /* HM57 */
-   LPC_PCHMSFF,/* PCH Mobile SFF Full Featured */
-   LPC_QS57,   /* QS57 */
-   LPC_3400,   /* 3400 */
-   LPC_3420,   /* 3420 */
-   LPC_3450,   /* 3450 */
-   LPC_EP80579,/* EP80579 */
-   LPC_CPT,/* Cougar Point */
-   LPC_CPTD,   /* Cougar Point Desktop */
-   LPC_CPTM,   /* Cougar Point Mobile */
-   LPC_PBG,/* Patsburg */
-   LPC_DH89XXCC,   /* DH89xxCC */
-   LPC_PPT,/* Panther Point */
-   LPC_LPT,/* Lynx Point */
-   LPC_LPT_LP, /* Lynx Point-LP */
-   LPC_WBG,/* Wellsburg */
-   LPC_AVN,/* Avoton SoC */
-   LPC_BAYTRAIL,   /* Bay Trail SoC */
-   LPC_COLETO, /* Coleto Creek */
-   LPC_WPT_LP, /* Wildcat Point-LP */
-   LPC_BRASWELL,   /* Braswell SoC */
-   LPC_LEWISBURG,  /* Lewisburg */
-   LPC_9S, /* 9 Series */
-};
-
 static struct lpc_ich_info lpc_chipset_info[] = {
[LPC_ICH] = {
.name = "ICH",
diff --git a/include/linux/mfd/lpc_ich.h b/include/linux/mfd/lpc_ich.h
index 2b300b4..42307ee 100644
--- a/include/linux/mfd/lpc_ich.h
+++ b/include/linux/mfd/lpc_ich.h
@@ -43,4 +43,75 @@ struct lpc_ich_info {
u8 use_gpio;
 };
 
+/* chipset related info */
+enum lpc_chipsets {
+   LPC_ICH = 0,/* ICH */
+   LPC_ICH0,   /* ICH0 */
+   LPC_ICH2,   /* ICH2 */
+   LPC_ICH2M,  /* ICH2-M */
+   LPC_ICH3,   /* ICH3-S */
+   LPC_ICH3M,  /* ICH3-M */
+   LPC_ICH4,   /* ICH4 */
+   LPC_ICH4M,  /* ICH4-M */
+   LPC_CICH,   /* C-ICH */
+   LPC_ICH5,   /* ICH5 & ICH5R */
+   LPC_6300ESB,/* 6300ESB */
+   LPC_ICH6,   /* ICH6 & ICH6R */
+   LPC_ICH6M,  /* ICH6-M */
+   LPC_ICH6W,  /* ICH6W & ICH6RW */
+   LPC_631XESB,/* 631xESB/632xESB */
+   LPC_ICH7,   /* ICH7 & ICH7R */
+   LPC_ICH7DH, /* ICH7DH */
+   LPC_ICH7M,  /* ICH7-M & ICH7-U */
+   LPC_ICH7MDH,/* ICH7-M DH */
+   LPC_NM10,   /* NM10 */
+   LPC_ICH8,   /* ICH8 & ICH8R */
+   LPC_ICH8DH, /* ICH8DH */
+   LPC_ICH8DO, /* ICH8DO */
+   LPC_ICH8M,  /* ICH8M */
+   LPC_ICH8ME, /* ICH8M-E */
+   LPC_ICH9,   /* ICH9 */
+   LPC_ICH9R,  /* ICH9R */
+   LPC_ICH9DH, /* ICH9DH */
+   LPC_ICH9DO, /* ICH9DO */
+   LPC_ICH9M,  /* ICH9M */
+

[PATCH v8 6/6] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO pinctrl in non-ACPI system

2016-10-12 Thread Tan Jui Nee 
This driver uses the P2SB hide/unhide mechanism cooperatively
to pass the PCI BAR address to the gpio platform driver.

Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
Changes in V8:
- Rename source file lpc_ich-apl.c to lpc_ich_apl.c (suggested by Mika).

Changes in V7:
- Add author information and rewrite description of source file 
  lpc_ich-apl.c and lpc_ich_apl.h.
- Sort the header files by alphabetical order in lpc_ich-apl.c.
- Rename header file lpc_ich-apl.h to lpc_ich_apl.h (suggested by Lee).
- Remove unneeded pdata_size and platform_data from mfd_cell.
  Also, remove unneeded apl_pinctrl_pdata.
- Since variable apl_p2sb is only used once, hence switch it out for the
  PCI_DEVFN macro (suggested by Lee).
- Define APL_GPIO_COMMUNITY_MAX as total Apollo Lake GPIO communities
  supported.
- Set resources in mfd_cell for each GPIO community.
- Call p2sb_bar() function once instead of four times inside the for 
loop.
  And make p2sb_bar() function just to fill in the base address into a
  scratch "struct resource" and have the loop do the additions to 
base/end.
- Remove entire apl_pinctrl_pdata.name memory allocation since it is no
  longer needed.
- Return ret at the end of lpc_ich_add_gpio() function.

Changes in V6:
- Rename CONFIG_X86_INTEL_APL to CONFIG_X86_INTEL_IVI so that it
  relates to the actual product, as suggested by Mika.
- Rework Makefile according Andy's comments.
- Rename lpc_ich_misc() to lpc_ich_add_gpio() so that the name should 
not
  be so generic, as suggested by Andy.
- Call lpc_ich_add_gpio() via priv->chipset.
- lpc_ich_add_gpio() function will be moved from 
  .../include/linux/mfd/lpc_ich.h to
  .../drivers/mfd/lpc_ich-apl.h
  as this is a part of internal driver interface as suggested by Andy.
- Move enum lpc_chipsets from 
  .../drivers/mfd/lpc_ich-core.c to
  .../include/linux/mfd/lpc_ich.h
  as lpc_chipsets is also accessed by lpc_ich_add_gpio().
- Check if kasprintf return value for all 4 gpio controllers before
  proceed to add platform device by using mfd_add_devices().

Changes in V5:
- Split lpc-ich driver into two parts (lpc_ich-core and lpc_ich-apl).
  The file lpc_ich-apl.c introduces gpio platform driver in MFD.
- Rename Kconfig option CONFIG_X86_INTEL_NON_ACPI to 
CONFIG_X86_INTEL_APL
  so that it reflects actual product as suggested by Mika.

Changes in V4:
- Move Kconfig option CONFIG_X86_INTEL_NON_ACPI from
  [PATCH 2/3] x86/platform/p2sb: New Primary to Sideband bridge support 
driver for Intel SOC's
  to
  [PATCH 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO 
pinctrl in non-ACPI system
  since the config is used in latter patch.
- Select CONFIG_P2SB when CONFIG_LPC_ICH is enabled.
- Remove #ifdef CONFIG_X86_INTEL_NON_ACPI and use
  #if defined(CONFIG_X86_INTEL_NON_ACPI) when lpc_ich_misc is called
  as suggested by Lee Jones.
- Use single dimensional array instead of 2D array for apl_gpio_io_res
  structure and use DEFINE_RES_IRQ for its IRQ resource.

Changes in V3:
- Simplify register addresses calculation and use DEFINE_RES_MEM_NAMED
  defines for apl_gpio_io_res structure
- Define magic number for P2SB PCI ID
- Replace switch-case with if-else since currently we have only one
  use case
- Only call mfd_add_devices() once for all gpio communities

Changes in V2:
- Add new config option CONFIG_X86_INTEL_NON_ACPI and "select PINCTRL"
  to fix kbuildbot error

 drivers/mfd/Kconfig|   2 +
 drivers/mfd/Makefile   |   4 ++
 drivers/mfd/lpc_ich_apl.c  | 120 +
 drivers/mfd/lpc_ich_apl.h  |  29 +++
 drivers/mfd/lpc_ich_core.c |   5 ++
 5 files changed, 160 insertions(+)
 create mode 100644 drivers/mfd/lpc_ich_apl.c
 create mode 100644 drivers/mfd/lpc_ich_apl.h

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index c6df644..7bb2f7c 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -391,7 +391,9 @@ config MFD_INTEL_QUARK_I2C_GPIO
 config LPC_ICH
tristate "Intel ICH LPC"
depends on PCI
+   depends on X86 && PCI
select MFD_CORE
+   select P2SB
help
  The LPC bridge function of the Intel ICH provides support for
  many functional units. This driver provides needed support for
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 06a91ea..ccafdfa 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -161,6 +161,10 @@ obj-$(CONFIG_MFD_INTEL_QUARK_I2C_GPIO) += 
intel_quark_i2c_gpio.o
 obj-$(CONF

[PATCH v8 3/6] x86/intel-ivi: Add Intel In-Vehicle Infotainment (IVI) systems used in cars support

2016-10-12 Thread Tan Jui Nee 
Add support for non ACPI system, such as system that uses Advanced Boot
Loader (ABL) whereby a platform device has to be created in order to bind
with PINCTRL/GPIO.

At the moment, Intel Apollo Lake SoC requires P2SB driver to hide and
unhide P2SB to lookup P2SB BAR and pass the PCI BAR address to GPIO.

Signed-off-by: Tan Jui Nee 
---
Changes in V8:
- No change

 arch/x86/Kconfig | 8 
 1 file changed, 8 insertions(+)

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index e2c1dcf..aa8928a 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -512,6 +512,14 @@ config X86_INTEL_CE
  This option compiles in support for the CE4100 SOC for settop
  boxes and media devices.
 
+config X86_INTEL_IVI
+   bool "Intel In-Vehicle Infotainment (IVI) systems used in cars"
+   ---help---
+ Select this option to enable MMIO BAR access over the P2SB for
+ non-ACPI Intel Apollo Lake SoC platforms. This driver uses the P2SB
+ hide/unhide mechanism cooperatively to pass the PCI BAR address to
+ the platform driver, currently GPIO.
+
 config X86_INTEL_MID
bool "Intel MID platform support"
depends on X86_EXTENDED_PLATFORM
-- 
1.9.1

[PATCH v8 4/6] mfd: move enum lpc_chipsets into lpc_ich.h

2016-10-12 Thread Tan Jui Nee 
Move the enum's definition into a standalone header file which can be used
wherever its definition is needed.

Signed-off-by: Tan Jui Nee 
---
Changes in V8:
- No change

 drivers/mfd/lpc_ich_core.c  | 71 -
 include/linux/mfd/lpc_ich.h | 71 +
 2 files changed, 71 insertions(+), 71 deletions(-)

diff --git a/drivers/mfd/lpc_ich_core.c b/drivers/mfd/lpc_ich_core.c
index 01d8d9e..bfba832 100644
--- a/drivers/mfd/lpc_ich_core.c
+++ b/drivers/mfd/lpc_ich_core.c
@@ -147,77 +147,6 @@ struct lpc_ich_priv {
.ignore_resource_conflicts = true,
 };
 
-/* chipset related info */
-enum lpc_chipsets {
-   LPC_ICH = 0,/* ICH */
-   LPC_ICH0,   /* ICH0 */
-   LPC_ICH2,   /* ICH2 */
-   LPC_ICH2M,  /* ICH2-M */
-   LPC_ICH3,   /* ICH3-S */
-   LPC_ICH3M,  /* ICH3-M */
-   LPC_ICH4,   /* ICH4 */
-   LPC_ICH4M,  /* ICH4-M */
-   LPC_CICH,   /* C-ICH */
-   LPC_ICH5,   /* ICH5 & ICH5R */
-   LPC_6300ESB,/* 6300ESB */
-   LPC_ICH6,   /* ICH6 & ICH6R */
-   LPC_ICH6M,  /* ICH6-M */
-   LPC_ICH6W,  /* ICH6W & ICH6RW */
-   LPC_631XESB,/* 631xESB/632xESB */
-   LPC_ICH7,   /* ICH7 & ICH7R */
-   LPC_ICH7DH, /* ICH7DH */
-   LPC_ICH7M,  /* ICH7-M & ICH7-U */
-   LPC_ICH7MDH,/* ICH7-M DH */
-   LPC_NM10,   /* NM10 */
-   LPC_ICH8,   /* ICH8 & ICH8R */
-   LPC_ICH8DH, /* ICH8DH */
-   LPC_ICH8DO, /* ICH8DO */
-   LPC_ICH8M,  /* ICH8M */
-   LPC_ICH8ME, /* ICH8M-E */
-   LPC_ICH9,   /* ICH9 */
-   LPC_ICH9R,  /* ICH9R */
-   LPC_ICH9DH, /* ICH9DH */
-   LPC_ICH9DO, /* ICH9DO */
-   LPC_ICH9M,  /* ICH9M */
-   LPC_ICH9ME, /* ICH9M-E */
-   LPC_ICH10,  /* ICH10 */
-   LPC_ICH10R, /* ICH10R */
-   LPC_ICH10D, /* ICH10D */
-   LPC_ICH10DO,/* ICH10DO */
-   LPC_PCH,/* PCH Desktop Full Featured */
-   LPC_PCHM,   /* PCH Mobile Full Featured */
-   LPC_P55,/* P55 */
-   LPC_PM55,   /* PM55 */
-   LPC_H55,/* H55 */
-   LPC_QM57,   /* QM57 */
-   LPC_H57,/* H57 */
-   LPC_HM55,   /* HM55 */
-   LPC_Q57,/* Q57 */
-   LPC_HM57,   /* HM57 */
-   LPC_PCHMSFF,/* PCH Mobile SFF Full Featured */
-   LPC_QS57,   /* QS57 */
-   LPC_3400,   /* 3400 */
-   LPC_3420,   /* 3420 */
-   LPC_3450,   /* 3450 */
-   LPC_EP80579,/* EP80579 */
-   LPC_CPT,/* Cougar Point */
-   LPC_CPTD,   /* Cougar Point Desktop */
-   LPC_CPTM,   /* Cougar Point Mobile */
-   LPC_PBG,/* Patsburg */
-   LPC_DH89XXCC,   /* DH89xxCC */
-   LPC_PPT,/* Panther Point */
-   LPC_LPT,/* Lynx Point */
-   LPC_LPT_LP, /* Lynx Point-LP */
-   LPC_WBG,/* Wellsburg */
-   LPC_AVN,/* Avoton SoC */
-   LPC_BAYTRAIL,   /* Bay Trail SoC */
-   LPC_COLETO, /* Coleto Creek */
-   LPC_WPT_LP, /* Wildcat Point-LP */
-   LPC_BRASWELL,   /* Braswell SoC */
-   LPC_LEWISBURG,  /* Lewisburg */
-   LPC_9S, /* 9 Series */
-};
-
 static struct lpc_ich_info lpc_chipset_info[] = {
[LPC_ICH] = {
.name = "ICH",
diff --git a/include/linux/mfd/lpc_ich.h b/include/linux/mfd/lpc_ich.h
index 2b300b4..42307ee 100644
--- a/include/linux/mfd/lpc_ich.h
+++ b/include/linux/mfd/lpc_ich.h
@@ -43,4 +43,75 @@ struct lpc_ich_info {
u8 use_gpio;
 };
 
+/* chipset related info */
+enum lpc_chipsets {
+   LPC_ICH = 0,/* ICH */
+   LPC_ICH0,   /* ICH0 */
+   LPC_ICH2,   /* ICH2 */
+   LPC_ICH2M,  /* ICH2-M */
+   LPC_ICH3,   /* ICH3-S */
+   LPC_ICH3M,  /* ICH3-M */
+   LPC_ICH4,   /* ICH4 */
+   LPC_ICH4M,  /* ICH4-M */
+   LPC_CICH,   /* C-ICH */
+   LPC_ICH5,   /* ICH5 & ICH5R */
+   LPC_6300ESB,/* 6300ESB */
+   LPC_ICH6,   /* ICH6 & ICH6R */
+   LPC_ICH6M,  /* ICH6-M */
+   LPC_ICH6W,  /* ICH6W & ICH6RW */
+   LPC_631XESB,/* 631xESB/632xESB */
+   LPC_ICH7,   /* ICH7 & ICH7R */
+   LPC_ICH7DH, /* ICH7DH */
+   LPC_ICH7M,  /* ICH7-M & ICH7-U */
+   LPC_ICH7MDH,/* ICH7-M DH */
+   LPC_NM10,   /* NM10 */
+   LPC_ICH8,   /* ICH8 & ICH8R */
+   LPC_ICH8DH, /* ICH8DH */
+   LPC_ICH8DO, /* ICH8DO */
+   LPC_ICH8M,  /* ICH8M */
+   LPC_ICH8ME, /* ICH8M-E */
+   LPC_ICH9,   /* ICH9 */
+   LPC_ICH9R,  /* ICH9R */
+   LPC_ICH9DH, /* ICH9DH */
+   LPC_ICH9DO, /* ICH9DO */
+   LPC_ICH9M,  /* ICH9M */
+   LPC_ICH9ME, /* ICH9M-E */
+   LPC

[PATCH v8 6/6] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO pinctrl in non-ACPI system

2016-10-12 Thread Tan Jui Nee 
This driver uses the P2SB hide/unhide mechanism cooperatively
to pass the PCI BAR address to the gpio platform driver.

Signed-off-by: Tan Jui Nee 
---
Changes in V8:
- Rename source file lpc_ich-apl.c to lpc_ich_apl.c (suggested by Mika).

Changes in V7:
- Add author information and rewrite description of source file 
  lpc_ich-apl.c and lpc_ich_apl.h.
- Sort the header files by alphabetical order in lpc_ich-apl.c.
- Rename header file lpc_ich-apl.h to lpc_ich_apl.h (suggested by Lee).
- Remove unneeded pdata_size and platform_data from mfd_cell.
  Also, remove unneeded apl_pinctrl_pdata.
- Since variable apl_p2sb is only used once, hence switch it out for the
  PCI_DEVFN macro (suggested by Lee).
- Define APL_GPIO_COMMUNITY_MAX as total Apollo Lake GPIO communities
  supported.
- Set resources in mfd_cell for each GPIO community.
- Call p2sb_bar() function once instead of four times inside the for 
loop.
  And make p2sb_bar() function just to fill in the base address into a
  scratch "struct resource" and have the loop do the additions to 
base/end.
- Remove entire apl_pinctrl_pdata.name memory allocation since it is no
  longer needed.
- Return ret at the end of lpc_ich_add_gpio() function.

Changes in V6:
- Rename CONFIG_X86_INTEL_APL to CONFIG_X86_INTEL_IVI so that it
  relates to the actual product, as suggested by Mika.
- Rework Makefile according Andy's comments.
- Rename lpc_ich_misc() to lpc_ich_add_gpio() so that the name should 
not
  be so generic, as suggested by Andy.
- Call lpc_ich_add_gpio() via priv->chipset.
- lpc_ich_add_gpio() function will be moved from 
  .../include/linux/mfd/lpc_ich.h to
  .../drivers/mfd/lpc_ich-apl.h
  as this is a part of internal driver interface as suggested by Andy.
- Move enum lpc_chipsets from 
  .../drivers/mfd/lpc_ich-core.c to
  .../include/linux/mfd/lpc_ich.h
  as lpc_chipsets is also accessed by lpc_ich_add_gpio().
- Check if kasprintf return value for all 4 gpio controllers before
  proceed to add platform device by using mfd_add_devices().

Changes in V5:
- Split lpc-ich driver into two parts (lpc_ich-core and lpc_ich-apl).
  The file lpc_ich-apl.c introduces gpio platform driver in MFD.
- Rename Kconfig option CONFIG_X86_INTEL_NON_ACPI to 
CONFIG_X86_INTEL_APL
  so that it reflects actual product as suggested by Mika.

Changes in V4:
- Move Kconfig option CONFIG_X86_INTEL_NON_ACPI from
  [PATCH 2/3] x86/platform/p2sb: New Primary to Sideband bridge support 
driver for Intel SOC's
  to
  [PATCH 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO 
pinctrl in non-ACPI system
  since the config is used in latter patch.
- Select CONFIG_P2SB when CONFIG_LPC_ICH is enabled.
- Remove #ifdef CONFIG_X86_INTEL_NON_ACPI and use
  #if defined(CONFIG_X86_INTEL_NON_ACPI) when lpc_ich_misc is called
  as suggested by Lee Jones.
- Use single dimensional array instead of 2D array for apl_gpio_io_res
  structure and use DEFINE_RES_IRQ for its IRQ resource.

Changes in V3:
- Simplify register addresses calculation and use DEFINE_RES_MEM_NAMED
  defines for apl_gpio_io_res structure
- Define magic number for P2SB PCI ID
- Replace switch-case with if-else since currently we have only one
  use case
- Only call mfd_add_devices() once for all gpio communities

Changes in V2:
- Add new config option CONFIG_X86_INTEL_NON_ACPI and "select PINCTRL"
  to fix kbuildbot error

 drivers/mfd/Kconfig|   2 +
 drivers/mfd/Makefile   |   4 ++
 drivers/mfd/lpc_ich_apl.c  | 120 +
 drivers/mfd/lpc_ich_apl.h  |  29 +++
 drivers/mfd/lpc_ich_core.c |   5 ++
 5 files changed, 160 insertions(+)
 create mode 100644 drivers/mfd/lpc_ich_apl.c
 create mode 100644 drivers/mfd/lpc_ich_apl.h

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index c6df644..7bb2f7c 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -391,7 +391,9 @@ config MFD_INTEL_QUARK_I2C_GPIO
 config LPC_ICH
tristate "Intel ICH LPC"
depends on PCI
+   depends on X86 && PCI
select MFD_CORE
+   select P2SB
help
  The LPC bridge function of the Intel ICH provides support for
  many functional units. This driver provides needed support for
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 06a91ea..ccafdfa 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -161,6 +161,10 @@ obj-$(CONFIG_MFD_INTEL_QUARK_I2C_GPIO) += 
intel_quark_i2c_gpio.o
 obj-$(CONFIG_LPC

[PATCH v8 0/6] inctrl/broxton: enable platform device in the absent of ACPI enumeration

2016-10-12 Thread Tan Jui Nee 
b: New Primary to Sideband bridge support driver for
Intel SOC's

Tan Jui Nee (5):
  mfd: lpc_ich: Rename lpc-ich driver
  x86/intel-ivi: Add Intel In-Vehicle Infotainment (IVI) systems used in
cars support
  mfd: move enum lpc_chipsets into lpc_ich.h
  mfd: lpc_ich: Add Device IDs for Intel Apollo Lake PCH
  mfd: lpc_ich: Add support for Intel Apollo Lake GPIO pinctrl in
non-ACPI system

 arch/x86/Kconfig  |  12 +++
 arch/x86/include/asm/p2sb.h   |  27 +++
 arch/x86/platform/intel/Makefile  |   1 +
 arch/x86/platform/intel/p2sb.c|  98 
 drivers/mfd/Kconfig   |   2 +
 drivers/mfd/Makefile  |   5 ++
 drivers/mfd/lpc_ich_apl.c | 120 ++
 drivers/mfd/lpc_ich_apl.h |  29 
 drivers/mfd/{lpc_ich.c => lpc_ich_core.c} |  84 +++--
 include/linux/mfd/lpc_ich.h   |  72 ++
 10 files changed, 378 insertions(+), 72 deletions(-)
 create mode 100644 arch/x86/include/asm/p2sb.h
 create mode 100644 arch/x86/platform/intel/p2sb.c
 create mode 100644 drivers/mfd/lpc_ich_apl.c
 create mode 100644 drivers/mfd/lpc_ich_apl.h
 rename drivers/mfd/{lpc_ich.c => lpc_ich_core.c} (93%)

-- 
1.9.1

[PATCH v8 0/6] inctrl/broxton: enable platform device in the absent of ACPI enumeration

2016-10-12 Thread Tan Jui Nee 
b: New Primary to Sideband bridge support driver for
Intel SOC's

Tan Jui Nee (5):
  mfd: lpc_ich: Rename lpc-ich driver
  x86/intel-ivi: Add Intel In-Vehicle Infotainment (IVI) systems used in
cars support
  mfd: move enum lpc_chipsets into lpc_ich.h
  mfd: lpc_ich: Add Device IDs for Intel Apollo Lake PCH
  mfd: lpc_ich: Add support for Intel Apollo Lake GPIO pinctrl in
non-ACPI system

 arch/x86/Kconfig  |  12 +++
 arch/x86/include/asm/p2sb.h   |  27 +++
 arch/x86/platform/intel/Makefile  |   1 +
 arch/x86/platform/intel/p2sb.c|  98 
 drivers/mfd/Kconfig   |   2 +
 drivers/mfd/Makefile  |   5 ++
 drivers/mfd/lpc_ich_apl.c | 120 ++
 drivers/mfd/lpc_ich_apl.h |  29 
 drivers/mfd/{lpc_ich.c => lpc_ich_core.c} |  84 +++--
 include/linux/mfd/lpc_ich.h   |  72 ++
 10 files changed, 378 insertions(+), 72 deletions(-)
 create mode 100644 arch/x86/include/asm/p2sb.h
 create mode 100644 arch/x86/platform/intel/p2sb.c
 create mode 100644 drivers/mfd/lpc_ich_apl.c
 create mode 100644 drivers/mfd/lpc_ich_apl.h
 rename drivers/mfd/{lpc_ich.c => lpc_ich_core.c} (93%)

-- 
1.9.1

[PATCH v8 1/6] x86/platform/p2sb: New Primary to Sideband bridge support driver for Intel SOC's

2016-10-12 Thread Tan Jui Nee 
From: Andy Shevchenko 

There is already one and at least one more user coming which
require an access to Primary to Sideband bridge (P2SB) in order
to get IO or MMIO bar hidden by BIOS.
Create a driver to access P2SB for x86 devices.

Signed-off-by: Yong, Jonathan 
Signed-off-by: Andy Shevchenko 
---
Changes in V8:
- No change

Changes in V7:
- EXPORT_SYMBOL_GPL() and MODULE_LICENSE("GPL v2") are used for new file
  p2sb.c.

Changes in V6:
- No change

Changes in V5:
- No change

Changes in V4:
- Move Kconfig option CONFIG_X86_INTEL_NON_ACPI from
  [PATCH 2/3] x86/platform/p2sb: New Primary to Sideband bridge support 
driver for Intel SOC's
  to
  [PATCH 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO 
pinctrl in non-ACPI system
  since the config is used in latter patch.

Changes in V3:
- No change

Changes in V2:
- Add new config option CONFIG_X86_INTEL_NON_ACPI and "select PINCTRL"
  to fix kbuildbot error

 arch/x86/Kconfig |  4 ++
 arch/x86/include/asm/p2sb.h  | 27 +++
 arch/x86/platform/intel/Makefile |  1 +
 arch/x86/platform/intel/p2sb.c   | 98 
 4 files changed, 130 insertions(+)
 create mode 100644 arch/x86/include/asm/p2sb.h
 create mode 100644 arch/x86/platform/intel/p2sb.c

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index bada636..e2c1dcf 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -615,6 +615,10 @@ config IOSF_MBI_DEBUG
 
  If you don't require the option or are in doubt, say N.
 
+config P2SB
+   tristate
+   depends on PCI
+
 config X86_RDC321X
bool "RDC R-321x SoC"
depends on X86_32
diff --git a/arch/x86/include/asm/p2sb.h b/arch/x86/include/asm/p2sb.h
new file mode 100644
index 000..686e07b
--- /dev/null
+++ b/arch/x86/include/asm/p2sb.h
@@ -0,0 +1,27 @@
+/*
+ * Primary to Sideband bridge (P2SB) access support
+ */
+
+#ifndef P2SB_SYMS_H
+#define P2SB_SYMS_H
+
+#include 
+#include 
+
+#if IS_ENABLED(CONFIG_P2SB)
+
+int p2sb_bar(struct pci_dev *pdev, unsigned int devfn,
+   struct resource *res);
+
+#else /* CONFIG_P2SB is not set */
+
+static inline
+int p2sb_bar(struct pci_dev *pdev, unsigned int devfn,
+   struct resource *res)
+{
+   return -ENODEV;
+}
+
+#endif /* CONFIG_P2SB */
+
+#endif /* P2SB_SYMS_H */
diff --git a/arch/x86/platform/intel/Makefile b/arch/x86/platform/intel/Makefile
index b878032..dbf9f10 100644
--- a/arch/x86/platform/intel/Makefile
+++ b/arch/x86/platform/intel/Makefile
@@ -1 +1,2 @@
 obj-$(CONFIG_IOSF_MBI) += iosf_mbi.o
+obj-$(CONFIG_P2SB) += p2sb.o
diff --git a/arch/x86/platform/intel/p2sb.c b/arch/x86/platform/intel/p2sb.c
new file mode 100644
index 000..b1d784c
--- /dev/null
+++ b/arch/x86/platform/intel/p2sb.c
@@ -0,0 +1,98 @@
+/*
+ * Primary to Sideband bridge (P2SB) driver
+ *
+ * Copyright (c) 2016, Intel Corporation.
+ *
+ * Authors: Andy Shevchenko 
+ * Jonathan Yong 
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#define SBREG_BAR  0x10
+#define SBREG_HIDE 0xe1
+
+static DEFINE_SPINLOCK(p2sb_spinlock);
+
+/*
+ * p2sb_bar - Get Primary to Sideband bridge (P2SB) BAR
+ * @pdev:  PCI device to get PCI bus to communicate with
+ * @devfn: PCI device and function to communicate with
+ * @res:   resources to be filled in
+ *
+ * The BIOS prevents the P2SB device from being enumerated by the PCI
+ * subsystem, so we need to unhide and hide it back to lookup the P2SB BAR.
+ *
+ * Locking is handled by spinlock - cannot sleep.
+ *
+ * Return:
+ * 0 on success or appropriate errno value on error.
+ */
+int p2sb_bar(struct pci_dev *pdev, unsigned int devfn,
+   struct resource *res)
+{
+   u32 base_addr;
+   u64 base64_addr;
+   unsigned long flags;
+
+   if (!res)
+   return -EINVAL;
+
+   spin_lock(_spinlock);
+
+   /* Unhide the P2SB device */
+   pci_bus_write_config_byte(pdev->bus, devfn, SBREG_HIDE, 0x00);
+
+   /* Check if device present */
+   pci_bus_read_config_dword(pdev->bus, devfn, 0, _addr);
+   if (base_addr == 0x || base_addr == 0x) {
+   spin_unlock(_spinlock);
+   dev_warn(>dev, "P2SB device access

[PATCH v8 2/6] mfd: lpc_ich: Rename lpc-ich driver

2016-10-12 Thread Tan Jui Nee 
This patch follows the example of mfd/wm831x to rename the driver
from "lpc_ich" to "lpc_ich_core".

Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
Changes in V8:
- Update new file name with lpc_ich_core.c at description of source 
file.
- Rework Makefile with new source file name lpc_ich_apl.c.

Changes in V7:
- No change

Changes in V6:
- none, just a subject line and commit message change.

 drivers/mfd/Makefile  | 1 +
 drivers/mfd/{lpc_ich.c => lpc_ich_core.c} | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)
 rename drivers/mfd/{lpc_ich.c => lpc_ich_core.c} (99%)

diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 9834e66..06a91ea 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -159,6 +159,7 @@ obj-$(CONFIG_PMIC_ADP5520)  += adp5520.o
 obj-$(CONFIG_MFD_KEMPLD)   += kempld-core.o
 obj-$(CONFIG_MFD_INTEL_QUARK_I2C_GPIO) += intel_quark_i2c_gpio.o
 obj-$(CONFIG_LPC_SCH)  += lpc_sch.o
+lpc_ich-objs   := lpc_ich_core.o
 obj-$(CONFIG_LPC_ICH)  += lpc_ich.o
 obj-$(CONFIG_MFD_RDC321X)  += rdc321x-southbridge.o
 obj-$(CONFIG_MFD_JANZ_CMODIO)  += janz-cmodio.o
diff --git a/drivers/mfd/lpc_ich.c b/drivers/mfd/lpc_ich_core.c
similarity index 99%
rename from drivers/mfd/lpc_ich.c
rename to drivers/mfd/lpc_ich_core.c
index c8dee47..01d8d9e 100644
--- a/drivers/mfd/lpc_ich.c
+++ b/drivers/mfd/lpc_ich_core.c
@@ -1,5 +1,5 @@
 /*
- *  lpc_ich.c - LPC interface for Intel ICH
+ *  lpc_ich_core.c - LPC interface for Intel ICH
  *
  *  LPC bridge function of the Intel ICH contains many other
  *  functional units, such as Interrupt controllers, Timers,
-- 
1.9.1

[PATCH v8 1/6] x86/platform/p2sb: New Primary to Sideband bridge support driver for Intel SOC's

2016-10-12 Thread Tan Jui Nee 
From: Andy Shevchenko 

There is already one and at least one more user coming which
require an access to Primary to Sideband bridge (P2SB) in order
to get IO or MMIO bar hidden by BIOS.
Create a driver to access P2SB for x86 devices.

Signed-off-by: Yong, Jonathan 
Signed-off-by: Andy Shevchenko 
---
Changes in V8:
- No change

Changes in V7:
- EXPORT_SYMBOL_GPL() and MODULE_LICENSE("GPL v2") are used for new file
  p2sb.c.

Changes in V6:
- No change

Changes in V5:
- No change

Changes in V4:
- Move Kconfig option CONFIG_X86_INTEL_NON_ACPI from
  [PATCH 2/3] x86/platform/p2sb: New Primary to Sideband bridge support 
driver for Intel SOC's
  to
  [PATCH 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO 
pinctrl in non-ACPI system
  since the config is used in latter patch.

Changes in V3:
- No change

Changes in V2:
- Add new config option CONFIG_X86_INTEL_NON_ACPI and "select PINCTRL"
  to fix kbuildbot error

 arch/x86/Kconfig |  4 ++
 arch/x86/include/asm/p2sb.h  | 27 +++
 arch/x86/platform/intel/Makefile |  1 +
 arch/x86/platform/intel/p2sb.c   | 98 
 4 files changed, 130 insertions(+)
 create mode 100644 arch/x86/include/asm/p2sb.h
 create mode 100644 arch/x86/platform/intel/p2sb.c

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index bada636..e2c1dcf 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -615,6 +615,10 @@ config IOSF_MBI_DEBUG
 
  If you don't require the option or are in doubt, say N.
 
+config P2SB
+   tristate
+   depends on PCI
+
 config X86_RDC321X
bool "RDC R-321x SoC"
depends on X86_32
diff --git a/arch/x86/include/asm/p2sb.h b/arch/x86/include/asm/p2sb.h
new file mode 100644
index 000..686e07b
--- /dev/null
+++ b/arch/x86/include/asm/p2sb.h
@@ -0,0 +1,27 @@
+/*
+ * Primary to Sideband bridge (P2SB) access support
+ */
+
+#ifndef P2SB_SYMS_H
+#define P2SB_SYMS_H
+
+#include 
+#include 
+
+#if IS_ENABLED(CONFIG_P2SB)
+
+int p2sb_bar(struct pci_dev *pdev, unsigned int devfn,
+   struct resource *res);
+
+#else /* CONFIG_P2SB is not set */
+
+static inline
+int p2sb_bar(struct pci_dev *pdev, unsigned int devfn,
+   struct resource *res)
+{
+   return -ENODEV;
+}
+
+#endif /* CONFIG_P2SB */
+
+#endif /* P2SB_SYMS_H */
diff --git a/arch/x86/platform/intel/Makefile b/arch/x86/platform/intel/Makefile
index b878032..dbf9f10 100644
--- a/arch/x86/platform/intel/Makefile
+++ b/arch/x86/platform/intel/Makefile
@@ -1 +1,2 @@
 obj-$(CONFIG_IOSF_MBI) += iosf_mbi.o
+obj-$(CONFIG_P2SB) += p2sb.o
diff --git a/arch/x86/platform/intel/p2sb.c b/arch/x86/platform/intel/p2sb.c
new file mode 100644
index 000..b1d784c
--- /dev/null
+++ b/arch/x86/platform/intel/p2sb.c
@@ -0,0 +1,98 @@
+/*
+ * Primary to Sideband bridge (P2SB) driver
+ *
+ * Copyright (c) 2016, Intel Corporation.
+ *
+ * Authors: Andy Shevchenko 
+ * Jonathan Yong 
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#define SBREG_BAR  0x10
+#define SBREG_HIDE 0xe1
+
+static DEFINE_SPINLOCK(p2sb_spinlock);
+
+/*
+ * p2sb_bar - Get Primary to Sideband bridge (P2SB) BAR
+ * @pdev:  PCI device to get PCI bus to communicate with
+ * @devfn: PCI device and function to communicate with
+ * @res:   resources to be filled in
+ *
+ * The BIOS prevents the P2SB device from being enumerated by the PCI
+ * subsystem, so we need to unhide and hide it back to lookup the P2SB BAR.
+ *
+ * Locking is handled by spinlock - cannot sleep.
+ *
+ * Return:
+ * 0 on success or appropriate errno value on error.
+ */
+int p2sb_bar(struct pci_dev *pdev, unsigned int devfn,
+   struct resource *res)
+{
+   u32 base_addr;
+   u64 base64_addr;
+   unsigned long flags;
+
+   if (!res)
+   return -EINVAL;
+
+   spin_lock(_spinlock);
+
+   /* Unhide the P2SB device */
+   pci_bus_write_config_byte(pdev->bus, devfn, SBREG_HIDE, 0x00);
+
+   /* Check if device present */
+   pci_bus_read_config_dword(pdev->bus, devfn, 0, _addr);
+   if (base_addr == 0x || base_addr == 0x) {
+   spin_unlock(_spinlock);
+   dev_warn(>dev, "P2SB device access disabled by BIOS?\n");
+   return -ENODEV;
+   }
+
+   /* Get IO or MMIO BAR */
+   pci_bus_read_config_dword(pdev->bus, devfn,

[PATCH v8 2/6] mfd: lpc_ich: Rename lpc-ich driver

2016-10-12 Thread Tan Jui Nee 
This patch follows the example of mfd/wm831x to rename the driver
from "lpc_ich" to "lpc_ich_core".

Signed-off-by: Tan Jui Nee 
---
Changes in V8:
- Update new file name with lpc_ich_core.c at description of source 
file.
- Rework Makefile with new source file name lpc_ich_apl.c.

Changes in V7:
- No change

Changes in V6:
- none, just a subject line and commit message change.

 drivers/mfd/Makefile  | 1 +
 drivers/mfd/{lpc_ich.c => lpc_ich_core.c} | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)
 rename drivers/mfd/{lpc_ich.c => lpc_ich_core.c} (99%)

diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 9834e66..06a91ea 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -159,6 +159,7 @@ obj-$(CONFIG_PMIC_ADP5520)  += adp5520.o
 obj-$(CONFIG_MFD_KEMPLD)   += kempld-core.o
 obj-$(CONFIG_MFD_INTEL_QUARK_I2C_GPIO) += intel_quark_i2c_gpio.o
 obj-$(CONFIG_LPC_SCH)  += lpc_sch.o
+lpc_ich-objs   := lpc_ich_core.o
 obj-$(CONFIG_LPC_ICH)  += lpc_ich.o
 obj-$(CONFIG_MFD_RDC321X)  += rdc321x-southbridge.o
 obj-$(CONFIG_MFD_JANZ_CMODIO)  += janz-cmodio.o
diff --git a/drivers/mfd/lpc_ich.c b/drivers/mfd/lpc_ich_core.c
similarity index 99%
rename from drivers/mfd/lpc_ich.c
rename to drivers/mfd/lpc_ich_core.c
index c8dee47..01d8d9e 100644
--- a/drivers/mfd/lpc_ich.c
+++ b/drivers/mfd/lpc_ich_core.c
@@ -1,5 +1,5 @@
 /*
- *  lpc_ich.c - LPC interface for Intel ICH
+ *  lpc_ich_core.c - LPC interface for Intel ICH
  *
  *  LPC bridge function of the Intel ICH contains many other
  *  functional units, such as Interrupt controllers, Timers,
-- 
1.9.1

RE: [PATCH v7 5/6] mfd: lpc_ich: Add Device IDs for Intel Apollo Lake PCH

2016-10-07 Thread Tan, Jui Nee 


> -Original Message-
> From: Mika Westerberg [mailto:mika.westerb...@linux.intel.com]
> Sent: Thursday, September 29, 2016 7:09 PM
> To: Tan, Jui Nee <jui.nee@intel.com>
> Cc: heikki.kroge...@linux.intel.com; andriy.shevche...@linux.intel.com;
> t...@linutronix.de; mi...@redhat.com; h...@zytor.com; x...@kernel.org;
> pty...@xes-inc.com; lee.jo...@linaro.org; linus.wall...@linaro.org; linux-
> g...@vger.kernel.org; linux-kernel@vger.kernel.org; Yong, Jonathan
> <jonathan.y...@intel.com>; Yu, Ong Hock <ong.hock...@intel.com>; Luck,
> Tony <tony.l...@intel.com>; Wan Mohamad, Wan Ahmad Zainie
> <wan.ahmad.zainie.wan.moha...@intel.com>
> Subject: Re: [PATCH v7 5/6] mfd: lpc_ich: Add Device IDs for Intel Apollo
> Lake PCH
> 
> On Wed, Sep 28, 2016 at 05:52:22PM +0800, Tan Jui Nee wrote:
> > Adding Intel codename Apollo Lake platform device IDs for PCH.
> >
> > Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
> > ---
> >  drivers/mfd/lpc_ich-core.c  | 6 ++
> 
> It should be either lpc_ich_core.c or lpc-ich-core.c. Ditto for -apl.c
> thing.
Thanks for your comment. I will send out another patch-set with filename 
lpc_ich_core.c and lpc_ich_apl.c.

RE: [PATCH v7 5/6] mfd: lpc_ich: Add Device IDs for Intel Apollo Lake PCH

2016-10-07 Thread Tan, Jui Nee 


> -Original Message-
> From: Mika Westerberg [mailto:mika.westerb...@linux.intel.com]
> Sent: Thursday, September 29, 2016 7:09 PM
> To: Tan, Jui Nee 
> Cc: heikki.kroge...@linux.intel.com; andriy.shevche...@linux.intel.com;
> t...@linutronix.de; mi...@redhat.com; h...@zytor.com; x...@kernel.org;
> pty...@xes-inc.com; lee.jo...@linaro.org; linus.wall...@linaro.org; linux-
> g...@vger.kernel.org; linux-kernel@vger.kernel.org; Yong, Jonathan
> ; Yu, Ong Hock ; Luck,
> Tony ; Wan Mohamad, Wan Ahmad Zainie
> 
> Subject: Re: [PATCH v7 5/6] mfd: lpc_ich: Add Device IDs for Intel Apollo
> Lake PCH
> 
> On Wed, Sep 28, 2016 at 05:52:22PM +0800, Tan Jui Nee wrote:
> > Adding Intel codename Apollo Lake platform device IDs for PCH.
> >
> > Signed-off-by: Tan Jui Nee 
> > ---
> >  drivers/mfd/lpc_ich-core.c  | 6 ++
> 
> It should be either lpc_ich_core.c or lpc-ich-core.c. Ditto for -apl.c
> thing.
Thanks for your comment. I will send out another patch-set with filename 
lpc_ich_core.c and lpc_ich_apl.c.

RE: [PATCH v7 4/6] mfd: move enum lpc_chipsets into lpc_ich.h

2016-10-07 Thread Tan, Jui Nee 


> -Original Message-
> From: Lee Jones [mailto:lee.jo...@linaro.org]
> Sent: Friday, September 30, 2016 8:33 AM
> To: Tan, Jui Nee <jui.nee@intel.com>
> Cc: mika.westerb...@linux.intel.com; heikki.kroge...@linux.intel.com;
> andriy.shevche...@linux.intel.com; t...@linutronix.de; mi...@redhat.com;
> h...@zytor.com; x...@kernel.org; pty...@xes-inc.com;
> linus.wall...@linaro.org; linux-g...@vger.kernel.org; linux-
> ker...@vger.kernel.org; Yong, Jonathan <jonathan.y...@intel.com>; Yu, Ong
> Hock <ong.hock...@intel.com>; Luck, Tony <tony.l...@intel.com>; Wan
> Mohamad, Wan Ahmad Zainie <wan.ahmad.zainie.wan.moha...@intel.com>
> Subject: Re: [PATCH v7 4/6] mfd: move enum lpc_chipsets into lpc_ich.h
> 
> On Wed, 28 Sep 2016, Tan Jui Nee wrote:
> 
> > Move the enum's definition into a standalone header file which can be
> > used wherever its definition is needed.
> >
> > Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
> > ---
> >  drivers/mfd/lpc_ich-core.c  | 71
> > -
> >  include/linux/mfd/lpc_ich.h | 71
> > +
> >  2 files changed, 71 insertions(+), 71 deletions(-)
> 
> Did you use -M when creating this patch?
> 
This patch is to move part of the file and not the entire file to lpc_ich.h. It 
will not show similarity % info even I have used -M option when creating the 
patch.
> > diff --git a/drivers/mfd/lpc_ich-core.c b/drivers/mfd/lpc_ich-core.c
> > index bd3aa45..05ed985 100644
> > --- a/drivers/mfd/lpc_ich-core.c
> > +++ b/drivers/mfd/lpc_ich-core.c
> > @@ -147,77 +147,6 @@ static struct mfd_cell lpc_ich_gpio_cell = {
> > .ignore_resource_conflicts = true,
> >  };
> >
> > -/* chipset related info */
> > -enum lpc_chipsets {
> > -   LPC_ICH = 0,/* ICH */
> > -   LPC_ICH0,   /* ICH0 */
> > -   LPC_ICH2,   /* ICH2 */
> > -   LPC_ICH2M,  /* ICH2-M */
> > -   LPC_ICH3,   /* ICH3-S */
> > -   LPC_ICH3M,  /* ICH3-M */
> > -   LPC_ICH4,   /* ICH4 */
> > -   LPC_ICH4M,  /* ICH4-M */
> > -   LPC_CICH,   /* C-ICH */
> > -   LPC_ICH5,   /* ICH5 & ICH5R */
> > -   LPC_6300ESB,/* 6300ESB */
> > -   LPC_ICH6,   /* ICH6 & ICH6R */
> > -   LPC_ICH6M,  /* ICH6-M */
> > -   LPC_ICH6W,  /* ICH6W & ICH6RW */
> > -   LPC_631XESB,/* 631xESB/632xESB */
> > -   LPC_ICH7,   /* ICH7 & ICH7R */
> > -   LPC_ICH7DH, /* ICH7DH */
> > -   LPC_ICH7M,  /* ICH7-M & ICH7-U */
> > -   LPC_ICH7MDH,/* ICH7-M DH */
> > -   LPC_NM10,   /* NM10 */
> > -   LPC_ICH8,   /* ICH8 & ICH8R */
> > -   LPC_ICH8DH, /* ICH8DH */
> > -   LPC_ICH8DO, /* ICH8DO */
> > -   LPC_ICH8M,  /* ICH8M */
> > -   LPC_ICH8ME, /* ICH8M-E */
> > -   LPC_ICH9,   /* ICH9 */
> > -   LPC_ICH9R,  /* ICH9R */
> > -   LPC_ICH9DH, /* ICH9DH */
> > -   LPC_ICH9DO, /* ICH9DO */
> > -   LPC_ICH9M,  /* ICH9M */
> > -   LPC_ICH9ME, /* ICH9M-E */
> > -   LPC_ICH10,  /* ICH10 */
> > -   LPC_ICH10R, /* ICH10R */
> > -   LPC_ICH10D, /* ICH10D */
> > -   LPC_ICH10DO,/* ICH10DO */
> > -   LPC_PCH,/* PCH Desktop Full Featured */
> > -   LPC_PCHM,   /* PCH Mobile Full Featured */
> > -   LPC_P55,/* P55 */
> > -   LPC_PM55,   /* PM55 */
> > -   LPC_H55,/* H55 */
> > -   LPC_QM57,   /* QM57 */
> > -   LPC_H57,/* H57 */
> > -   LPC_HM55,   /* HM55 */
> > -   LPC_Q57,/* Q57 */
> > -   LPC_HM57,   /* HM57 */
> > -   LPC_PCHMSFF,/* PCH Mobile SFF Full Featured */
> > -   LPC_QS57,   /* QS57 */
> > -   LPC_3400,   /* 3400 */
> > -   LPC_3420,   /* 3420 */
> > -   LPC_3450,   /* 3450 */
> > -   LPC_EP80579,/* EP80579 */
> > -   LPC_CPT,/* Cougar Point */
> > -   LPC_CPTD,   /* Cougar Point Desktop */
> > -   LPC_CPTM,   /* Cougar Point Mobile */
> > -   LPC_PBG,/* Patsburg */
> > -   LPC_DH89XXCC,   /* DH89xxCC */
> > -   LPC_PPT,/* Panther Point */
> > -   LPC_LPT,/* Lynx Point */
> > -   LPC_LPT_LP, /* Lynx Point-LP */
> > -   LPC_WBG,/* Wellsburg */
> > -   LPC_AVN,/* Avoton SoC */
> > -   LPC_BAYTRAIL,   /* Bay Trail SoC */
> > -   LPC_COLETO, /* Coleto Creek */
> > -   LPC_WPT_LP, /* Wildcat Point-LP */
> > -   LPC_BRASWELL,   /* Braswell SoC */
> > -   LPC_LEWISBURG,  /* L

RE: [PATCH v7 4/6] mfd: move enum lpc_chipsets into lpc_ich.h

2016-10-07 Thread Tan, Jui Nee 


> -Original Message-
> From: Lee Jones [mailto:lee.jo...@linaro.org]
> Sent: Friday, September 30, 2016 8:33 AM
> To: Tan, Jui Nee 
> Cc: mika.westerb...@linux.intel.com; heikki.kroge...@linux.intel.com;
> andriy.shevche...@linux.intel.com; t...@linutronix.de; mi...@redhat.com;
> h...@zytor.com; x...@kernel.org; pty...@xes-inc.com;
> linus.wall...@linaro.org; linux-g...@vger.kernel.org; linux-
> ker...@vger.kernel.org; Yong, Jonathan ; Yu, Ong
> Hock ; Luck, Tony ; Wan
> Mohamad, Wan Ahmad Zainie 
> Subject: Re: [PATCH v7 4/6] mfd: move enum lpc_chipsets into lpc_ich.h
> 
> On Wed, 28 Sep 2016, Tan Jui Nee wrote:
> 
> > Move the enum's definition into a standalone header file which can be
> > used wherever its definition is needed.
> >
> > Signed-off-by: Tan Jui Nee 
> > ---
> >  drivers/mfd/lpc_ich-core.c  | 71
> > -
> >  include/linux/mfd/lpc_ich.h | 71
> > +
> >  2 files changed, 71 insertions(+), 71 deletions(-)
> 
> Did you use -M when creating this patch?
> 
This patch is to move part of the file and not the entire file to lpc_ich.h. It 
will not show similarity % info even I have used -M option when creating the 
patch.
> > diff --git a/drivers/mfd/lpc_ich-core.c b/drivers/mfd/lpc_ich-core.c
> > index bd3aa45..05ed985 100644
> > --- a/drivers/mfd/lpc_ich-core.c
> > +++ b/drivers/mfd/lpc_ich-core.c
> > @@ -147,77 +147,6 @@ static struct mfd_cell lpc_ich_gpio_cell = {
> > .ignore_resource_conflicts = true,
> >  };
> >
> > -/* chipset related info */
> > -enum lpc_chipsets {
> > -   LPC_ICH = 0,/* ICH */
> > -   LPC_ICH0,   /* ICH0 */
> > -   LPC_ICH2,   /* ICH2 */
> > -   LPC_ICH2M,  /* ICH2-M */
> > -   LPC_ICH3,   /* ICH3-S */
> > -   LPC_ICH3M,  /* ICH3-M */
> > -   LPC_ICH4,   /* ICH4 */
> > -   LPC_ICH4M,  /* ICH4-M */
> > -   LPC_CICH,   /* C-ICH */
> > -   LPC_ICH5,   /* ICH5 & ICH5R */
> > -   LPC_6300ESB,/* 6300ESB */
> > -   LPC_ICH6,   /* ICH6 & ICH6R */
> > -   LPC_ICH6M,  /* ICH6-M */
> > -   LPC_ICH6W,  /* ICH6W & ICH6RW */
> > -   LPC_631XESB,/* 631xESB/632xESB */
> > -   LPC_ICH7,   /* ICH7 & ICH7R */
> > -   LPC_ICH7DH, /* ICH7DH */
> > -   LPC_ICH7M,  /* ICH7-M & ICH7-U */
> > -   LPC_ICH7MDH,/* ICH7-M DH */
> > -   LPC_NM10,   /* NM10 */
> > -   LPC_ICH8,   /* ICH8 & ICH8R */
> > -   LPC_ICH8DH, /* ICH8DH */
> > -   LPC_ICH8DO, /* ICH8DO */
> > -   LPC_ICH8M,  /* ICH8M */
> > -   LPC_ICH8ME, /* ICH8M-E */
> > -   LPC_ICH9,   /* ICH9 */
> > -   LPC_ICH9R,  /* ICH9R */
> > -   LPC_ICH9DH, /* ICH9DH */
> > -   LPC_ICH9DO, /* ICH9DO */
> > -   LPC_ICH9M,  /* ICH9M */
> > -   LPC_ICH9ME, /* ICH9M-E */
> > -   LPC_ICH10,  /* ICH10 */
> > -   LPC_ICH10R, /* ICH10R */
> > -   LPC_ICH10D, /* ICH10D */
> > -   LPC_ICH10DO,/* ICH10DO */
> > -   LPC_PCH,/* PCH Desktop Full Featured */
> > -   LPC_PCHM,   /* PCH Mobile Full Featured */
> > -   LPC_P55,/* P55 */
> > -   LPC_PM55,   /* PM55 */
> > -   LPC_H55,/* H55 */
> > -   LPC_QM57,   /* QM57 */
> > -   LPC_H57,/* H57 */
> > -   LPC_HM55,   /* HM55 */
> > -   LPC_Q57,/* Q57 */
> > -   LPC_HM57,   /* HM57 */
> > -   LPC_PCHMSFF,/* PCH Mobile SFF Full Featured */
> > -   LPC_QS57,   /* QS57 */
> > -   LPC_3400,   /* 3400 */
> > -   LPC_3420,   /* 3420 */
> > -   LPC_3450,   /* 3450 */
> > -   LPC_EP80579,/* EP80579 */
> > -   LPC_CPT,/* Cougar Point */
> > -   LPC_CPTD,   /* Cougar Point Desktop */
> > -   LPC_CPTM,   /* Cougar Point Mobile */
> > -   LPC_PBG,/* Patsburg */
> > -   LPC_DH89XXCC,   /* DH89xxCC */
> > -   LPC_PPT,/* Panther Point */
> > -   LPC_LPT,/* Lynx Point */
> > -   LPC_LPT_LP, /* Lynx Point-LP */
> > -   LPC_WBG,/* Wellsburg */
> > -   LPC_AVN,/* Avoton SoC */
> > -   LPC_BAYTRAIL,   /* Bay Trail SoC */
> > -   LPC_COLETO, /* Coleto Creek */
> > -   LPC_WPT_LP, /* Wildcat Point-LP */
> > -   LPC_BRASWELL,   /* Braswell SoC */
> > -   LPC_LEWISBURG,  /* Lewisburg */
> > -   LPC_9S, /* 9 Series */
> > -};
> > -
> >  static struct lpc_ich_info lpc_chipset_info[] = {
> > [LPC_ICH] = {
> > .name =

RE: [PATCH v7 2/6] mfd: lpc_ich: Rename lpc-ich driver

2016-10-07 Thread Tan, Jui Nee 


> -Original Message-
> From: Lee Jones [mailto:lee.jo...@linaro.org]
> Sent: Friday, September 30, 2016 8:31 AM
> To: Tan, Jui Nee <jui.nee@intel.com>
> Cc: mika.westerb...@linux.intel.com; heikki.kroge...@linux.intel.com;
> andriy.shevche...@linux.intel.com; t...@linutronix.de; mi...@redhat.com;
> h...@zytor.com; x...@kernel.org; pty...@xes-inc.com;
> linus.wall...@linaro.org; linux-g...@vger.kernel.org; linux-
> ker...@vger.kernel.org; Yong, Jonathan <jonathan.y...@intel.com>; Yu, Ong
> Hock <ong.hock...@intel.com>; Luck, Tony <tony.l...@intel.com>; Wan
> Mohamad, Wan Ahmad Zainie <wan.ahmad.zainie.wan.moha...@intel.com>
> Subject: Re: [PATCH v7 2/6] mfd: lpc_ich: Rename lpc-ich driver
> 
> On Wed, 28 Sep 2016, Tan Jui Nee wrote:
> 
> > This patch follows the example of mfd/wm831x to rename the driver from
> > "lpc_ich" to "lpc_ich-core".
> >
> > Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
> > ---
> > Changes in V7:
> > - No change
> >
> > Changes in V6:
> > - none, just a subject line and commit message change.
> >
> >  drivers/mfd/Makefile  | 1 +
> >  drivers/mfd/{lpc_ich.c => lpc_ich-core.c} | 0
> >  2 files changed, 1 insertion(+)
> >  rename drivers/mfd/{lpc_ich.c => lpc_ich-core.c} (100%)
> >
> > diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index
> > 2ba3ba3..260f46f 100644
> > --- a/drivers/mfd/Makefile
> > +++ b/drivers/mfd/Makefile
> > @@ -155,6 +155,7 @@ obj-$(CONFIG_PMIC_ADP5520)  += adp5520.o
> >  obj-$(CONFIG_MFD_KEMPLD)   += kempld-core.o
> >  obj-$(CONFIG_MFD_INTEL_QUARK_I2C_GPIO) += intel_quark_i2c_gpio.o
> >  obj-$(CONFIG_LPC_SCH)  += lpc_sch.o
> > +lpc_ich-objs   := lpc_ich-core.o
> 
> Please use underscores OR obliques, not both.
> 
Noted. I will send out another patch-set with filename lpc_ich_core.
> >  obj-$(CONFIG_LPC_ICH)  += lpc_ich.o
> >  obj-$(CONFIG_MFD_RDC321X)  += rdc321x-southbridge.o
> >  obj-$(CONFIG_MFD_JANZ_CMODIO)  += janz-cmodio.o
> > diff --git a/drivers/mfd/lpc_ich.c b/drivers/mfd/lpc_ich-core.c
> > similarity index 100% rename from drivers/mfd/lpc_ich.c rename to
> > drivers/mfd/lpc_ich-core.c
> 
> --
> Lee Jones
> Linaro STMicroelectronics Landing Team Lead Linaro.org │ Open source
> software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog

RE: [PATCH v7 2/6] mfd: lpc_ich: Rename lpc-ich driver

2016-10-07 Thread Tan, Jui Nee 


> -Original Message-
> From: Lee Jones [mailto:lee.jo...@linaro.org]
> Sent: Friday, September 30, 2016 8:31 AM
> To: Tan, Jui Nee 
> Cc: mika.westerb...@linux.intel.com; heikki.kroge...@linux.intel.com;
> andriy.shevche...@linux.intel.com; t...@linutronix.de; mi...@redhat.com;
> h...@zytor.com; x...@kernel.org; pty...@xes-inc.com;
> linus.wall...@linaro.org; linux-g...@vger.kernel.org; linux-
> ker...@vger.kernel.org; Yong, Jonathan ; Yu, Ong
> Hock ; Luck, Tony ; Wan
> Mohamad, Wan Ahmad Zainie 
> Subject: Re: [PATCH v7 2/6] mfd: lpc_ich: Rename lpc-ich driver
> 
> On Wed, 28 Sep 2016, Tan Jui Nee wrote:
> 
> > This patch follows the example of mfd/wm831x to rename the driver from
> > "lpc_ich" to "lpc_ich-core".
> >
> > Signed-off-by: Tan Jui Nee 
> > ---
> > Changes in V7:
> > - No change
> >
> > Changes in V6:
> > - none, just a subject line and commit message change.
> >
> >  drivers/mfd/Makefile  | 1 +
> >  drivers/mfd/{lpc_ich.c => lpc_ich-core.c} | 0
> >  2 files changed, 1 insertion(+)
> >  rename drivers/mfd/{lpc_ich.c => lpc_ich-core.c} (100%)
> >
> > diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index
> > 2ba3ba3..260f46f 100644
> > --- a/drivers/mfd/Makefile
> > +++ b/drivers/mfd/Makefile
> > @@ -155,6 +155,7 @@ obj-$(CONFIG_PMIC_ADP5520)  += adp5520.o
> >  obj-$(CONFIG_MFD_KEMPLD)   += kempld-core.o
> >  obj-$(CONFIG_MFD_INTEL_QUARK_I2C_GPIO) += intel_quark_i2c_gpio.o
> >  obj-$(CONFIG_LPC_SCH)  += lpc_sch.o
> > +lpc_ich-objs   := lpc_ich-core.o
> 
> Please use underscores OR obliques, not both.
> 
Noted. I will send out another patch-set with filename lpc_ich_core.
> >  obj-$(CONFIG_LPC_ICH)  += lpc_ich.o
> >  obj-$(CONFIG_MFD_RDC321X)  += rdc321x-southbridge.o
> >  obj-$(CONFIG_MFD_JANZ_CMODIO)  += janz-cmodio.o
> > diff --git a/drivers/mfd/lpc_ich.c b/drivers/mfd/lpc_ich-core.c
> > similarity index 100% rename from drivers/mfd/lpc_ich.c rename to
> > drivers/mfd/lpc_ich-core.c
> 
> --
> Lee Jones
> Linaro STMicroelectronics Landing Team Lead Linaro.org │ Open source
> software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog

[PATCH v7 6/6] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO pinctrl in non-ACPI system

2016-09-28 Thread Tan Jui Nee 
This driver uses the P2SB hide/unhide mechanism cooperatively
to pass the PCI BAR address to the gpio platform driver.

Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
Changes in V7:
- Add author information and rewrite description of source file 
  lpc_ich-apl.c and lpc_ich_apl.h.
- Sort the header files by alphabetical order in lpc_ich-apl.c.
- Rename header file lpc_ich-apl.h to lpc_ich_apl.h (suggested by Lee).
- Remove unneeded pdata_size and platform_data from mfd_cell.
  Also, remove unneeded apl_pinctrl_pdata.
- Since variable apl_p2sb is only used once, hence switch it out for the
  PCI_DEVFN macro (suggested by Lee).
- Define APL_GPIO_COMMUNITY_MAX as total Apollo Lake GPIO communities
  supported.
- Set resources in mfd_cell for each GPIO community.
- Call p2sb_bar() function once instead of four times inside the for 
loop.
  And make p2sb_bar() function just to fill in the base address into a
  scratch "struct resource" and have the loop do the additions to 
base/end.
- Remove entire apl_pinctrl_pdata.name memory allocation since it is no
  longer needed.
- Return ret at the end of lpc_ich_add_gpio() function.

Changes in V6:
- Rename CONFIG_X86_INTEL_APL to CONFIG_X86_INTEL_IVI so that it
  relates to the actual product, as suggested by Mika.
- Rework Makefile according Andy's comments.
- Rename lpc_ich_misc() to lpc_ich_add_gpio() so that the name should 
not
  be so generic, as suggested by Andy.
- Call lpc_ich_add_gpio() via priv->chipset.
- lpc_ich_add_gpio() function will be moved from 
  .../include/linux/mfd/lpc_ich.h to
  .../drivers/mfd/lpc_ich-apl.h
  as this is a part of internal driver interface as suggested by Andy.
- Move enum lpc_chipsets from 
  .../drivers/mfd/lpc_ich-core.c to
  .../include/linux/mfd/lpc_ich.h
  as lpc_chipsets is also accessed by lpc_ich_add_gpio().
- Check if kasprintf return value for all 4 gpio controllers before
  proceed to add platform device by using mfd_add_devices().

Changes in V5:
- Split lpc-ich driver into two parts (lpc_ich-core and lpc_ich-apl).
  The file lpc_ich-apl.c introduces gpio platform driver in MFD.
- Rename Kconfig option CONFIG_X86_INTEL_NON_ACPI to 
CONFIG_X86_INTEL_APL
  so that it reflects actual product as suggested by Mika.

Changes in V4:
- Move Kconfig option CONFIG_X86_INTEL_NON_ACPI from
  [PATCH 2/3] x86/platform/p2sb: New Primary to Sideband bridge support 
driver for Intel SOC's
  to
  [PATCH 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO 
pinctrl in non-ACPI system
  since the config is used in latter patch.
- Select CONFIG_P2SB when CONFIG_LPC_ICH is enabled.
- Remove #ifdef CONFIG_X86_INTEL_NON_ACPI and use
  #if defined(CONFIG_X86_INTEL_NON_ACPI) when lpc_ich_misc is called
  as suggested by Lee Jones.
- Use single dimensional array instead of 2D array for apl_gpio_io_res
  structure and use DEFINE_RES_IRQ for its IRQ resource.

Changes in V3:
- Simplify register addresses calculation and use DEFINE_RES_MEM_NAMED
  defines for apl_gpio_io_res structure
- Define magic number for P2SB PCI ID
- Replace switch-case with if-else since currently we have only one
  use case
- Only call mfd_add_devices() once for all gpio communities

Changes in V2:
- Add new config option CONFIG_X86_INTEL_NON_ACPI and "select PINCTRL"
  to fix kbuildbot error

 drivers/mfd/Kconfig|   3 +-
 drivers/mfd/Makefile   |   5 +-
 drivers/mfd/lpc_ich-apl.c  | 120 +
 drivers/mfd/lpc_ich-core.c |   5 ++
 drivers/mfd/lpc_ich_apl.h  |  29 +++
 5 files changed, 160 insertions(+), 2 deletions(-)
 create mode 100644 drivers/mfd/lpc_ich-apl.c
 create mode 100644 drivers/mfd/lpc_ich_apl.h

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 2d1fb64..8838e55 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -380,8 +380,9 @@ config MFD_INTEL_QUARK_I2C_GPIO
 
 config LPC_ICH
tristate "Intel ICH LPC"
-   depends on PCI
+   depends on X86 && PCI
select MFD_CORE
+   select P2SB
help
  The LPC bridge function of the Intel ICH provides support for
  many functional units. This driver provides needed support for
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 260f46f..3ad16c9 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -155,8 +155,11 @@ obj-$(CONFIG_PMIC_ADP5520) += adp5520.o
 obj-$(CONFIG_MFD_KEMPLD)   += kempld-core.o
 obj-$(CONFIG_MFD_INTEL_QUARK_I2C_GPIO) += intel_quark_i2c_gpio

[PATCH v7 2/6] mfd: lpc_ich: Rename lpc-ich driver

2016-09-28 Thread Tan Jui Nee 
This patch follows the example of mfd/wm831x to rename the driver
from "lpc_ich" to "lpc_ich-core".

Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
Changes in V7:
- No change

Changes in V6:
- none, just a subject line and commit message change.

 drivers/mfd/Makefile  | 1 +
 drivers/mfd/{lpc_ich.c => lpc_ich-core.c} | 0
 2 files changed, 1 insertion(+)
 rename drivers/mfd/{lpc_ich.c => lpc_ich-core.c} (100%)

diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 2ba3ba3..260f46f 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -155,6 +155,7 @@ obj-$(CONFIG_PMIC_ADP5520)  += adp5520.o
 obj-$(CONFIG_MFD_KEMPLD)   += kempld-core.o
 obj-$(CONFIG_MFD_INTEL_QUARK_I2C_GPIO) += intel_quark_i2c_gpio.o
 obj-$(CONFIG_LPC_SCH)  += lpc_sch.o
+lpc_ich-objs   := lpc_ich-core.o
 obj-$(CONFIG_LPC_ICH)  += lpc_ich.o
 obj-$(CONFIG_MFD_RDC321X)  += rdc321x-southbridge.o
 obj-$(CONFIG_MFD_JANZ_CMODIO)  += janz-cmodio.o
diff --git a/drivers/mfd/lpc_ich.c b/drivers/mfd/lpc_ich-core.c
similarity index 100%
rename from drivers/mfd/lpc_ich.c
rename to drivers/mfd/lpc_ich-core.c
-- 
1.9.1

[PATCH v7 1/6] x86/platform/p2sb: New Primary to Sideband bridge support driver for Intel SOC's

2016-09-28 Thread Tan Jui Nee 
From: Andy Shevchenko 

There is already one and at least one more user coming which
require an access to Primary to Sideband bridge (P2SB) in order
to get IO or MMIO bar hidden by BIOS.
Create a driver to access P2SB for x86 devices.

Signed-off-by: Yong, Jonathan 
Signed-off-by: Andy Shevchenko 
---
Changes in V7:
- EXPORT_SYMBOL_GPL() and MODULE_LICENSE("GPL v2") are used for new file
  p2sb.c.

Changes in V6:
- No change

Changes in V5:
- No change

Changes in V4:
- Move Kconfig option CONFIG_X86_INTEL_NON_ACPI from
  [PATCH 2/3] x86/platform/p2sb: New Primary to Sideband bridge support 
driver for Intel SOC's
  to
  [PATCH 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO 
pinctrl in non-ACPI system
  since the config is used in latter patch.

Changes in V3:
- No change

Changes in V2:
- Add new config option CONFIG_X86_INTEL_NON_ACPI and "select PINCTRL"
  to fix kbuildbot error

 arch/x86/Kconfig |  4 ++
 arch/x86/include/asm/p2sb.h  | 27 +++
 arch/x86/platform/intel/Makefile |  1 +
 arch/x86/platform/intel/p2sb.c   | 98 
 4 files changed, 130 insertions(+)
 create mode 100644 arch/x86/include/asm/p2sb.h
 create mode 100644 arch/x86/platform/intel/p2sb.c

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 2a1f0ce..edc0313 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -602,6 +602,10 @@ config IOSF_MBI_DEBUG
 
  If you don't require the option or are in doubt, say N.
 
+config P2SB
+   tristate
+   depends on PCI
+
 config X86_RDC321X
bool "RDC R-321x SoC"
depends on X86_32
diff --git a/arch/x86/include/asm/p2sb.h b/arch/x86/include/asm/p2sb.h
new file mode 100644
index 000..686e07b
--- /dev/null
+++ b/arch/x86/include/asm/p2sb.h
@@ -0,0 +1,27 @@
+/*
+ * Primary to Sideband bridge (P2SB) access support
+ */
+
+#ifndef P2SB_SYMS_H
+#define P2SB_SYMS_H
+
+#include 
+#include 
+
+#if IS_ENABLED(CONFIG_P2SB)
+
+int p2sb_bar(struct pci_dev *pdev, unsigned int devfn,
+   struct resource *res);
+
+#else /* CONFIG_P2SB is not set */
+
+static inline
+int p2sb_bar(struct pci_dev *pdev, unsigned int devfn,
+   struct resource *res)
+{
+   return -ENODEV;
+}
+
+#endif /* CONFIG_P2SB */
+
+#endif /* P2SB_SYMS_H */
diff --git a/arch/x86/platform/intel/Makefile b/arch/x86/platform/intel/Makefile
index b878032..dbf9f10 100644
--- a/arch/x86/platform/intel/Makefile
+++ b/arch/x86/platform/intel/Makefile
@@ -1 +1,2 @@
 obj-$(CONFIG_IOSF_MBI) += iosf_mbi.o
+obj-$(CONFIG_P2SB) += p2sb.o
diff --git a/arch/x86/platform/intel/p2sb.c b/arch/x86/platform/intel/p2sb.c
new file mode 100644
index 000..b1d784c
--- /dev/null
+++ b/arch/x86/platform/intel/p2sb.c
@@ -0,0 +1,98 @@
+/*
+ * Primary to Sideband bridge (P2SB) driver
+ *
+ * Copyright (c) 2016, Intel Corporation.
+ *
+ * Authors: Andy Shevchenko 
+ * Jonathan Yong 
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#define SBREG_BAR  0x10
+#define SBREG_HIDE 0xe1
+
+static DEFINE_SPINLOCK(p2sb_spinlock);
+
+/*
+ * p2sb_bar - Get Primary to Sideband bridge (P2SB) BAR
+ * @pdev:  PCI device to get PCI bus to communicate with
+ * @devfn: PCI device and function to communicate with
+ * @res:   resources to be filled in
+ *
+ * The BIOS prevents the P2SB device from being enumerated by the PCI
+ * subsystem, so we need to unhide and hide it back to lookup the P2SB BAR.
+ *
+ * Locking is handled by spinlock - cannot sleep.
+ *
+ * Return:
+ * 0 on success or appropriate errno value on error.
+ */
+int p2sb_bar(struct pci_dev *pdev, unsigned int devfn,
+   struct resource *res)
+{
+   u32 base_addr;
+   u64 base64_addr;
+   unsigned long flags;
+
+   if (!res)
+   return -EINVAL;
+
+   spin_lock(_spinlock);
+
+   /* Unhide the P2SB device */
+   pci_bus_write_config_byte(pdev->bus, devfn, SBREG_HIDE, 0x00);
+
+   /* Check if device present */
+   pci_bus_read_config_dword(pdev->bus, devfn, 0, _addr);
+   if (base_addr == 0x || base_addr == 0x) {
+   spin_unlock(_spinlock);
+   dev_warn(>dev, "P2SB device access disabled by BIOS?\n");
+

[PATCH v7 5/6] mfd: lpc_ich: Add Device IDs for Intel Apollo Lake PCH

2016-09-28 Thread Tan Jui Nee 
Adding Intel codename Apollo Lake platform device IDs for PCH.

Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
 drivers/mfd/lpc_ich-core.c  | 6 ++
 include/linux/mfd/lpc_ich.h | 1 +
 2 files changed, 7 insertions(+)

diff --git a/drivers/mfd/lpc_ich-core.c b/drivers/mfd/lpc_ich-core.c
index 05ed985..589155c 100644
--- a/drivers/mfd/lpc_ich-core.c
+++ b/drivers/mfd/lpc_ich-core.c
@@ -56,6 +56,7 @@
  * document number TBD : Wildcat Point-LP
  * document number TBD : 9 Series
  * document number TBD : Lewisburg
+ * document number TBD : Apollo Lake
  */
 
 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
@@ -460,6 +461,10 @@ static struct lpc_ich_info lpc_chipset_info[] = {
.name = "9 Series",
.iTCO_version = 2,
},
+   [LPC_APL]  = {
+   .name = "Apollo Lake SoC",
+   .iTCO_version = 5,
+   },
 };
 
 /*
@@ -608,6 +613,7 @@ static const struct pci_device_id lpc_ich_ids[] = {
{ PCI_VDEVICE(INTEL, 0x3b14), LPC_3420},
{ PCI_VDEVICE(INTEL, 0x3b16), LPC_3450},
{ PCI_VDEVICE(INTEL, 0x5031), LPC_EP80579},
+   { PCI_VDEVICE(INTEL, 0x5ae8), LPC_APL},
{ PCI_VDEVICE(INTEL, 0x8c40), LPC_LPT},
{ PCI_VDEVICE(INTEL, 0x8c41), LPC_LPT},
{ PCI_VDEVICE(INTEL, 0x8c42), LPC_LPT},
diff --git a/include/linux/mfd/lpc_ich.h b/include/linux/mfd/lpc_ich.h
index 42307ee..397008c 100644
--- a/include/linux/mfd/lpc_ich.h
+++ b/include/linux/mfd/lpc_ich.h
@@ -112,6 +112,7 @@ enum lpc_chipsets {
LPC_BRASWELL,   /* Braswell SoC */
LPC_LEWISBURG,  /* Lewisburg */
LPC_9S, /* 9 Series */
+   LPC_APL,/* Apollo Lake SoC */
 };
 
 #endif
-- 
1.9.1

[PATCH v7 6/6] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO pinctrl in non-ACPI system

2016-09-28 Thread Tan Jui Nee 
This driver uses the P2SB hide/unhide mechanism cooperatively
to pass the PCI BAR address to the gpio platform driver.

Signed-off-by: Tan Jui Nee 
---
Changes in V7:
- Add author information and rewrite description of source file 
  lpc_ich-apl.c and lpc_ich_apl.h.
- Sort the header files by alphabetical order in lpc_ich-apl.c.
- Rename header file lpc_ich-apl.h to lpc_ich_apl.h (suggested by Lee).
- Remove unneeded pdata_size and platform_data from mfd_cell.
  Also, remove unneeded apl_pinctrl_pdata.
- Since variable apl_p2sb is only used once, hence switch it out for the
  PCI_DEVFN macro (suggested by Lee).
- Define APL_GPIO_COMMUNITY_MAX as total Apollo Lake GPIO communities
  supported.
- Set resources in mfd_cell for each GPIO community.
- Call p2sb_bar() function once instead of four times inside the for 
loop.
  And make p2sb_bar() function just to fill in the base address into a
  scratch "struct resource" and have the loop do the additions to 
base/end.
- Remove entire apl_pinctrl_pdata.name memory allocation since it is no
  longer needed.
- Return ret at the end of lpc_ich_add_gpio() function.

Changes in V6:
- Rename CONFIG_X86_INTEL_APL to CONFIG_X86_INTEL_IVI so that it
  relates to the actual product, as suggested by Mika.
- Rework Makefile according Andy's comments.
- Rename lpc_ich_misc() to lpc_ich_add_gpio() so that the name should 
not
  be so generic, as suggested by Andy.
- Call lpc_ich_add_gpio() via priv->chipset.
- lpc_ich_add_gpio() function will be moved from 
  .../include/linux/mfd/lpc_ich.h to
  .../drivers/mfd/lpc_ich-apl.h
  as this is a part of internal driver interface as suggested by Andy.
- Move enum lpc_chipsets from 
  .../drivers/mfd/lpc_ich-core.c to
  .../include/linux/mfd/lpc_ich.h
  as lpc_chipsets is also accessed by lpc_ich_add_gpio().
- Check if kasprintf return value for all 4 gpio controllers before
  proceed to add platform device by using mfd_add_devices().

Changes in V5:
- Split lpc-ich driver into two parts (lpc_ich-core and lpc_ich-apl).
  The file lpc_ich-apl.c introduces gpio platform driver in MFD.
- Rename Kconfig option CONFIG_X86_INTEL_NON_ACPI to 
CONFIG_X86_INTEL_APL
  so that it reflects actual product as suggested by Mika.

Changes in V4:
- Move Kconfig option CONFIG_X86_INTEL_NON_ACPI from
  [PATCH 2/3] x86/platform/p2sb: New Primary to Sideband bridge support 
driver for Intel SOC's
  to
  [PATCH 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO 
pinctrl in non-ACPI system
  since the config is used in latter patch.
- Select CONFIG_P2SB when CONFIG_LPC_ICH is enabled.
- Remove #ifdef CONFIG_X86_INTEL_NON_ACPI and use
  #if defined(CONFIG_X86_INTEL_NON_ACPI) when lpc_ich_misc is called
  as suggested by Lee Jones.
- Use single dimensional array instead of 2D array for apl_gpio_io_res
  structure and use DEFINE_RES_IRQ for its IRQ resource.

Changes in V3:
- Simplify register addresses calculation and use DEFINE_RES_MEM_NAMED
  defines for apl_gpio_io_res structure
- Define magic number for P2SB PCI ID
- Replace switch-case with if-else since currently we have only one
  use case
- Only call mfd_add_devices() once for all gpio communities

Changes in V2:
- Add new config option CONFIG_X86_INTEL_NON_ACPI and "select PINCTRL"
  to fix kbuildbot error

 drivers/mfd/Kconfig|   3 +-
 drivers/mfd/Makefile   |   5 +-
 drivers/mfd/lpc_ich-apl.c  | 120 +
 drivers/mfd/lpc_ich-core.c |   5 ++
 drivers/mfd/lpc_ich_apl.h  |  29 +++
 5 files changed, 160 insertions(+), 2 deletions(-)
 create mode 100644 drivers/mfd/lpc_ich-apl.c
 create mode 100644 drivers/mfd/lpc_ich_apl.h

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 2d1fb64..8838e55 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -380,8 +380,9 @@ config MFD_INTEL_QUARK_I2C_GPIO
 
 config LPC_ICH
tristate "Intel ICH LPC"
-   depends on PCI
+   depends on X86 && PCI
select MFD_CORE
+   select P2SB
help
  The LPC bridge function of the Intel ICH provides support for
  many functional units. This driver provides needed support for
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 260f46f..3ad16c9 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -155,8 +155,11 @@ obj-$(CONFIG_PMIC_ADP5520) += adp5520.o
 obj-$(CONFIG_MFD_KEMPLD)   += kempld-core.o
 obj-$(CONFIG_MFD_INTEL_QUARK_I2C_GPIO) += intel_quark_i2c_gpio.o
 obj-$(CONFIG_LPC

[PATCH v7 2/6] mfd: lpc_ich: Rename lpc-ich driver

2016-09-28 Thread Tan Jui Nee 
This patch follows the example of mfd/wm831x to rename the driver
from "lpc_ich" to "lpc_ich-core".

Signed-off-by: Tan Jui Nee 
---
Changes in V7:
- No change

Changes in V6:
- none, just a subject line and commit message change.

 drivers/mfd/Makefile  | 1 +
 drivers/mfd/{lpc_ich.c => lpc_ich-core.c} | 0
 2 files changed, 1 insertion(+)
 rename drivers/mfd/{lpc_ich.c => lpc_ich-core.c} (100%)

diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 2ba3ba3..260f46f 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -155,6 +155,7 @@ obj-$(CONFIG_PMIC_ADP5520)  += adp5520.o
 obj-$(CONFIG_MFD_KEMPLD)   += kempld-core.o
 obj-$(CONFIG_MFD_INTEL_QUARK_I2C_GPIO) += intel_quark_i2c_gpio.o
 obj-$(CONFIG_LPC_SCH)  += lpc_sch.o
+lpc_ich-objs   := lpc_ich-core.o
 obj-$(CONFIG_LPC_ICH)  += lpc_ich.o
 obj-$(CONFIG_MFD_RDC321X)  += rdc321x-southbridge.o
 obj-$(CONFIG_MFD_JANZ_CMODIO)  += janz-cmodio.o
diff --git a/drivers/mfd/lpc_ich.c b/drivers/mfd/lpc_ich-core.c
similarity index 100%
rename from drivers/mfd/lpc_ich.c
rename to drivers/mfd/lpc_ich-core.c
-- 
1.9.1

[PATCH v7 1/6] x86/platform/p2sb: New Primary to Sideband bridge support driver for Intel SOC's

2016-09-28 Thread Tan Jui Nee 
From: Andy Shevchenko 

There is already one and at least one more user coming which
require an access to Primary to Sideband bridge (P2SB) in order
to get IO or MMIO bar hidden by BIOS.
Create a driver to access P2SB for x86 devices.

Signed-off-by: Yong, Jonathan 
Signed-off-by: Andy Shevchenko 
---
Changes in V7:
- EXPORT_SYMBOL_GPL() and MODULE_LICENSE("GPL v2") are used for new file
  p2sb.c.

Changes in V6:
- No change

Changes in V5:
- No change

Changes in V4:
- Move Kconfig option CONFIG_X86_INTEL_NON_ACPI from
  [PATCH 2/3] x86/platform/p2sb: New Primary to Sideband bridge support 
driver for Intel SOC's
  to
  [PATCH 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO 
pinctrl in non-ACPI system
  since the config is used in latter patch.

Changes in V3:
- No change

Changes in V2:
- Add new config option CONFIG_X86_INTEL_NON_ACPI and "select PINCTRL"
  to fix kbuildbot error

 arch/x86/Kconfig |  4 ++
 arch/x86/include/asm/p2sb.h  | 27 +++
 arch/x86/platform/intel/Makefile |  1 +
 arch/x86/platform/intel/p2sb.c   | 98 
 4 files changed, 130 insertions(+)
 create mode 100644 arch/x86/include/asm/p2sb.h
 create mode 100644 arch/x86/platform/intel/p2sb.c

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 2a1f0ce..edc0313 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -602,6 +602,10 @@ config IOSF_MBI_DEBUG
 
  If you don't require the option or are in doubt, say N.
 
+config P2SB
+   tristate
+   depends on PCI
+
 config X86_RDC321X
bool "RDC R-321x SoC"
depends on X86_32
diff --git a/arch/x86/include/asm/p2sb.h b/arch/x86/include/asm/p2sb.h
new file mode 100644
index 000..686e07b
--- /dev/null
+++ b/arch/x86/include/asm/p2sb.h
@@ -0,0 +1,27 @@
+/*
+ * Primary to Sideband bridge (P2SB) access support
+ */
+
+#ifndef P2SB_SYMS_H
+#define P2SB_SYMS_H
+
+#include 
+#include 
+
+#if IS_ENABLED(CONFIG_P2SB)
+
+int p2sb_bar(struct pci_dev *pdev, unsigned int devfn,
+   struct resource *res);
+
+#else /* CONFIG_P2SB is not set */
+
+static inline
+int p2sb_bar(struct pci_dev *pdev, unsigned int devfn,
+   struct resource *res)
+{
+   return -ENODEV;
+}
+
+#endif /* CONFIG_P2SB */
+
+#endif /* P2SB_SYMS_H */
diff --git a/arch/x86/platform/intel/Makefile b/arch/x86/platform/intel/Makefile
index b878032..dbf9f10 100644
--- a/arch/x86/platform/intel/Makefile
+++ b/arch/x86/platform/intel/Makefile
@@ -1 +1,2 @@
 obj-$(CONFIG_IOSF_MBI) += iosf_mbi.o
+obj-$(CONFIG_P2SB) += p2sb.o
diff --git a/arch/x86/platform/intel/p2sb.c b/arch/x86/platform/intel/p2sb.c
new file mode 100644
index 000..b1d784c
--- /dev/null
+++ b/arch/x86/platform/intel/p2sb.c
@@ -0,0 +1,98 @@
+/*
+ * Primary to Sideband bridge (P2SB) driver
+ *
+ * Copyright (c) 2016, Intel Corporation.
+ *
+ * Authors: Andy Shevchenko 
+ * Jonathan Yong 
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#define SBREG_BAR  0x10
+#define SBREG_HIDE 0xe1
+
+static DEFINE_SPINLOCK(p2sb_spinlock);
+
+/*
+ * p2sb_bar - Get Primary to Sideband bridge (P2SB) BAR
+ * @pdev:  PCI device to get PCI bus to communicate with
+ * @devfn: PCI device and function to communicate with
+ * @res:   resources to be filled in
+ *
+ * The BIOS prevents the P2SB device from being enumerated by the PCI
+ * subsystem, so we need to unhide and hide it back to lookup the P2SB BAR.
+ *
+ * Locking is handled by spinlock - cannot sleep.
+ *
+ * Return:
+ * 0 on success or appropriate errno value on error.
+ */
+int p2sb_bar(struct pci_dev *pdev, unsigned int devfn,
+   struct resource *res)
+{
+   u32 base_addr;
+   u64 base64_addr;
+   unsigned long flags;
+
+   if (!res)
+   return -EINVAL;
+
+   spin_lock(_spinlock);
+
+   /* Unhide the P2SB device */
+   pci_bus_write_config_byte(pdev->bus, devfn, SBREG_HIDE, 0x00);
+
+   /* Check if device present */
+   pci_bus_read_config_dword(pdev->bus, devfn, 0, _addr);
+   if (base_addr == 0x || base_addr == 0x) {
+   spin_unlock(_spinlock);
+   dev_warn(>dev, "P2SB device access disabled by BIOS?\n");
+   return -ENODEV;
+   }
+
+   /* Get IO or MMIO BAR */
+   pci_bus_read_config_dword(pdev->bus, devfn, SBREG_BAR, _addr);
+   if ((base_addr &

[PATCH v7 5/6] mfd: lpc_ich: Add Device IDs for Intel Apollo Lake PCH

2016-09-28 Thread Tan Jui Nee 
Adding Intel codename Apollo Lake platform device IDs for PCH.

Signed-off-by: Tan Jui Nee 
---
 drivers/mfd/lpc_ich-core.c  | 6 ++
 include/linux/mfd/lpc_ich.h | 1 +
 2 files changed, 7 insertions(+)

diff --git a/drivers/mfd/lpc_ich-core.c b/drivers/mfd/lpc_ich-core.c
index 05ed985..589155c 100644
--- a/drivers/mfd/lpc_ich-core.c
+++ b/drivers/mfd/lpc_ich-core.c
@@ -56,6 +56,7 @@
  * document number TBD : Wildcat Point-LP
  * document number TBD : 9 Series
  * document number TBD : Lewisburg
+ * document number TBD : Apollo Lake
  */
 
 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
@@ -460,6 +461,10 @@ static struct lpc_ich_info lpc_chipset_info[] = {
.name = "9 Series",
.iTCO_version = 2,
},
+   [LPC_APL]  = {
+   .name = "Apollo Lake SoC",
+   .iTCO_version = 5,
+   },
 };
 
 /*
@@ -608,6 +613,7 @@ static const struct pci_device_id lpc_ich_ids[] = {
{ PCI_VDEVICE(INTEL, 0x3b14), LPC_3420},
{ PCI_VDEVICE(INTEL, 0x3b16), LPC_3450},
{ PCI_VDEVICE(INTEL, 0x5031), LPC_EP80579},
+   { PCI_VDEVICE(INTEL, 0x5ae8), LPC_APL},
{ PCI_VDEVICE(INTEL, 0x8c40), LPC_LPT},
{ PCI_VDEVICE(INTEL, 0x8c41), LPC_LPT},
{ PCI_VDEVICE(INTEL, 0x8c42), LPC_LPT},
diff --git a/include/linux/mfd/lpc_ich.h b/include/linux/mfd/lpc_ich.h
index 42307ee..397008c 100644
--- a/include/linux/mfd/lpc_ich.h
+++ b/include/linux/mfd/lpc_ich.h
@@ -112,6 +112,7 @@ enum lpc_chipsets {
LPC_BRASWELL,   /* Braswell SoC */
LPC_LEWISBURG,  /* Lewisburg */
LPC_9S, /* 9 Series */
+   LPC_APL,/* Apollo Lake SoC */
 };
 
 #endif
-- 
1.9.1

[PATCH v7 4/6] mfd: move enum lpc_chipsets into lpc_ich.h

2016-09-28 Thread Tan Jui Nee 
Move the enum's definition into a standalone header file which can be used
wherever its definition is needed.

Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
 drivers/mfd/lpc_ich-core.c  | 71 -
 include/linux/mfd/lpc_ich.h | 71 +
 2 files changed, 71 insertions(+), 71 deletions(-)

diff --git a/drivers/mfd/lpc_ich-core.c b/drivers/mfd/lpc_ich-core.c
index bd3aa45..05ed985 100644
--- a/drivers/mfd/lpc_ich-core.c
+++ b/drivers/mfd/lpc_ich-core.c
@@ -147,77 +147,6 @@ static struct mfd_cell lpc_ich_gpio_cell = {
.ignore_resource_conflicts = true,
 };
 
-/* chipset related info */
-enum lpc_chipsets {
-   LPC_ICH = 0,/* ICH */
-   LPC_ICH0,   /* ICH0 */
-   LPC_ICH2,   /* ICH2 */
-   LPC_ICH2M,  /* ICH2-M */
-   LPC_ICH3,   /* ICH3-S */
-   LPC_ICH3M,  /* ICH3-M */
-   LPC_ICH4,   /* ICH4 */
-   LPC_ICH4M,  /* ICH4-M */
-   LPC_CICH,   /* C-ICH */
-   LPC_ICH5,   /* ICH5 & ICH5R */
-   LPC_6300ESB,/* 6300ESB */
-   LPC_ICH6,   /* ICH6 & ICH6R */
-   LPC_ICH6M,  /* ICH6-M */
-   LPC_ICH6W,  /* ICH6W & ICH6RW */
-   LPC_631XESB,/* 631xESB/632xESB */
-   LPC_ICH7,   /* ICH7 & ICH7R */
-   LPC_ICH7DH, /* ICH7DH */
-   LPC_ICH7M,  /* ICH7-M & ICH7-U */
-   LPC_ICH7MDH,/* ICH7-M DH */
-   LPC_NM10,   /* NM10 */
-   LPC_ICH8,   /* ICH8 & ICH8R */
-   LPC_ICH8DH, /* ICH8DH */
-   LPC_ICH8DO, /* ICH8DO */
-   LPC_ICH8M,  /* ICH8M */
-   LPC_ICH8ME, /* ICH8M-E */
-   LPC_ICH9,   /* ICH9 */
-   LPC_ICH9R,  /* ICH9R */
-   LPC_ICH9DH, /* ICH9DH */
-   LPC_ICH9DO, /* ICH9DO */
-   LPC_ICH9M,  /* ICH9M */
-   LPC_ICH9ME, /* ICH9M-E */
-   LPC_ICH10,  /* ICH10 */
-   LPC_ICH10R, /* ICH10R */
-   LPC_ICH10D, /* ICH10D */
-   LPC_ICH10DO,/* ICH10DO */
-   LPC_PCH,/* PCH Desktop Full Featured */
-   LPC_PCHM,   /* PCH Mobile Full Featured */
-   LPC_P55,/* P55 */
-   LPC_PM55,   /* PM55 */
-   LPC_H55,/* H55 */
-   LPC_QM57,   /* QM57 */
-   LPC_H57,/* H57 */
-   LPC_HM55,   /* HM55 */
-   LPC_Q57,/* Q57 */
-   LPC_HM57,   /* HM57 */
-   LPC_PCHMSFF,/* PCH Mobile SFF Full Featured */
-   LPC_QS57,   /* QS57 */
-   LPC_3400,   /* 3400 */
-   LPC_3420,   /* 3420 */
-   LPC_3450,   /* 3450 */
-   LPC_EP80579,/* EP80579 */
-   LPC_CPT,/* Cougar Point */
-   LPC_CPTD,   /* Cougar Point Desktop */
-   LPC_CPTM,   /* Cougar Point Mobile */
-   LPC_PBG,/* Patsburg */
-   LPC_DH89XXCC,   /* DH89xxCC */
-   LPC_PPT,/* Panther Point */
-   LPC_LPT,/* Lynx Point */
-   LPC_LPT_LP, /* Lynx Point-LP */
-   LPC_WBG,/* Wellsburg */
-   LPC_AVN,/* Avoton SoC */
-   LPC_BAYTRAIL,   /* Bay Trail SoC */
-   LPC_COLETO, /* Coleto Creek */
-   LPC_WPT_LP, /* Wildcat Point-LP */
-   LPC_BRASWELL,   /* Braswell SoC */
-   LPC_LEWISBURG,  /* Lewisburg */
-   LPC_9S, /* 9 Series */
-};
-
 static struct lpc_ich_info lpc_chipset_info[] = {
[LPC_ICH] = {
.name = "ICH",
diff --git a/include/linux/mfd/lpc_ich.h b/include/linux/mfd/lpc_ich.h
index 2b300b4..42307ee 100644
--- a/include/linux/mfd/lpc_ich.h
+++ b/include/linux/mfd/lpc_ich.h
@@ -43,4 +43,75 @@ struct lpc_ich_info {
u8 use_gpio;
 };
 
+/* chipset related info */
+enum lpc_chipsets {
+   LPC_ICH = 0,/* ICH */
+   LPC_ICH0,   /* ICH0 */
+   LPC_ICH2,   /* ICH2 */
+   LPC_ICH2M,  /* ICH2-M */
+   LPC_ICH3,   /* ICH3-S */
+   LPC_ICH3M,  /* ICH3-M */
+   LPC_ICH4,   /* ICH4 */
+   LPC_ICH4M,  /* ICH4-M */
+   LPC_CICH,   /* C-ICH */
+   LPC_ICH5,   /* ICH5 & ICH5R */
+   LPC_6300ESB,/* 6300ESB */
+   LPC_ICH6,   /* ICH6 & ICH6R */
+   LPC_ICH6M,  /* ICH6-M */
+   LPC_ICH6W,  /* ICH6W & ICH6RW */
+   LPC_631XESB,/* 631xESB/632xESB */
+   LPC_ICH7,   /* ICH7 & ICH7R */
+   LPC_ICH7DH, /* ICH7DH */
+   LPC_ICH7M,  /* ICH7-M & ICH7-U */
+   LPC_ICH7MDH,/* ICH7-M DH */
+   LPC_NM10,   /* NM10 */
+   LPC_ICH8,   /* ICH8 & ICH8R */
+   LPC_ICH8DH, /* ICH8DH */
+   LPC_ICH8DO, /* ICH8DO */
+   LPC_ICH8M,  /* ICH8M */
+   LPC_ICH8ME, /* ICH8M-E */
+   LPC_ICH9,   /* ICH9 */
+   LPC_ICH9R,  /* ICH9R */
+   LPC_ICH9DH, /* ICH9DH */
+   LPC_ICH9DO, /* ICH9DO */
+   LPC_ICH9M,  /* ICH9M */
+   LPC_ICH9ME, /* I

[PATCH v7 4/6] mfd: move enum lpc_chipsets into lpc_ich.h

2016-09-28 Thread Tan Jui Nee 
Move the enum's definition into a standalone header file which can be used
wherever its definition is needed.

Signed-off-by: Tan Jui Nee 
---
 drivers/mfd/lpc_ich-core.c  | 71 -
 include/linux/mfd/lpc_ich.h | 71 +
 2 files changed, 71 insertions(+), 71 deletions(-)

diff --git a/drivers/mfd/lpc_ich-core.c b/drivers/mfd/lpc_ich-core.c
index bd3aa45..05ed985 100644
--- a/drivers/mfd/lpc_ich-core.c
+++ b/drivers/mfd/lpc_ich-core.c
@@ -147,77 +147,6 @@ static struct mfd_cell lpc_ich_gpio_cell = {
.ignore_resource_conflicts = true,
 };
 
-/* chipset related info */
-enum lpc_chipsets {
-   LPC_ICH = 0,/* ICH */
-   LPC_ICH0,   /* ICH0 */
-   LPC_ICH2,   /* ICH2 */
-   LPC_ICH2M,  /* ICH2-M */
-   LPC_ICH3,   /* ICH3-S */
-   LPC_ICH3M,  /* ICH3-M */
-   LPC_ICH4,   /* ICH4 */
-   LPC_ICH4M,  /* ICH4-M */
-   LPC_CICH,   /* C-ICH */
-   LPC_ICH5,   /* ICH5 & ICH5R */
-   LPC_6300ESB,/* 6300ESB */
-   LPC_ICH6,   /* ICH6 & ICH6R */
-   LPC_ICH6M,  /* ICH6-M */
-   LPC_ICH6W,  /* ICH6W & ICH6RW */
-   LPC_631XESB,/* 631xESB/632xESB */
-   LPC_ICH7,   /* ICH7 & ICH7R */
-   LPC_ICH7DH, /* ICH7DH */
-   LPC_ICH7M,  /* ICH7-M & ICH7-U */
-   LPC_ICH7MDH,/* ICH7-M DH */
-   LPC_NM10,   /* NM10 */
-   LPC_ICH8,   /* ICH8 & ICH8R */
-   LPC_ICH8DH, /* ICH8DH */
-   LPC_ICH8DO, /* ICH8DO */
-   LPC_ICH8M,  /* ICH8M */
-   LPC_ICH8ME, /* ICH8M-E */
-   LPC_ICH9,   /* ICH9 */
-   LPC_ICH9R,  /* ICH9R */
-   LPC_ICH9DH, /* ICH9DH */
-   LPC_ICH9DO, /* ICH9DO */
-   LPC_ICH9M,  /* ICH9M */
-   LPC_ICH9ME, /* ICH9M-E */
-   LPC_ICH10,  /* ICH10 */
-   LPC_ICH10R, /* ICH10R */
-   LPC_ICH10D, /* ICH10D */
-   LPC_ICH10DO,/* ICH10DO */
-   LPC_PCH,/* PCH Desktop Full Featured */
-   LPC_PCHM,   /* PCH Mobile Full Featured */
-   LPC_P55,/* P55 */
-   LPC_PM55,   /* PM55 */
-   LPC_H55,/* H55 */
-   LPC_QM57,   /* QM57 */
-   LPC_H57,/* H57 */
-   LPC_HM55,   /* HM55 */
-   LPC_Q57,/* Q57 */
-   LPC_HM57,   /* HM57 */
-   LPC_PCHMSFF,/* PCH Mobile SFF Full Featured */
-   LPC_QS57,   /* QS57 */
-   LPC_3400,   /* 3400 */
-   LPC_3420,   /* 3420 */
-   LPC_3450,   /* 3450 */
-   LPC_EP80579,/* EP80579 */
-   LPC_CPT,/* Cougar Point */
-   LPC_CPTD,   /* Cougar Point Desktop */
-   LPC_CPTM,   /* Cougar Point Mobile */
-   LPC_PBG,/* Patsburg */
-   LPC_DH89XXCC,   /* DH89xxCC */
-   LPC_PPT,/* Panther Point */
-   LPC_LPT,/* Lynx Point */
-   LPC_LPT_LP, /* Lynx Point-LP */
-   LPC_WBG,/* Wellsburg */
-   LPC_AVN,/* Avoton SoC */
-   LPC_BAYTRAIL,   /* Bay Trail SoC */
-   LPC_COLETO, /* Coleto Creek */
-   LPC_WPT_LP, /* Wildcat Point-LP */
-   LPC_BRASWELL,   /* Braswell SoC */
-   LPC_LEWISBURG,  /* Lewisburg */
-   LPC_9S, /* 9 Series */
-};
-
 static struct lpc_ich_info lpc_chipset_info[] = {
[LPC_ICH] = {
.name = "ICH",
diff --git a/include/linux/mfd/lpc_ich.h b/include/linux/mfd/lpc_ich.h
index 2b300b4..42307ee 100644
--- a/include/linux/mfd/lpc_ich.h
+++ b/include/linux/mfd/lpc_ich.h
@@ -43,4 +43,75 @@ struct lpc_ich_info {
u8 use_gpio;
 };
 
+/* chipset related info */
+enum lpc_chipsets {
+   LPC_ICH = 0,/* ICH */
+   LPC_ICH0,   /* ICH0 */
+   LPC_ICH2,   /* ICH2 */
+   LPC_ICH2M,  /* ICH2-M */
+   LPC_ICH3,   /* ICH3-S */
+   LPC_ICH3M,  /* ICH3-M */
+   LPC_ICH4,   /* ICH4 */
+   LPC_ICH4M,  /* ICH4-M */
+   LPC_CICH,   /* C-ICH */
+   LPC_ICH5,   /* ICH5 & ICH5R */
+   LPC_6300ESB,/* 6300ESB */
+   LPC_ICH6,   /* ICH6 & ICH6R */
+   LPC_ICH6M,  /* ICH6-M */
+   LPC_ICH6W,  /* ICH6W & ICH6RW */
+   LPC_631XESB,/* 631xESB/632xESB */
+   LPC_ICH7,   /* ICH7 & ICH7R */
+   LPC_ICH7DH, /* ICH7DH */
+   LPC_ICH7M,  /* ICH7-M & ICH7-U */
+   LPC_ICH7MDH,/* ICH7-M DH */
+   LPC_NM10,   /* NM10 */
+   LPC_ICH8,   /* ICH8 & ICH8R */
+   LPC_ICH8DH, /* ICH8DH */
+   LPC_ICH8DO, /* ICH8DO */
+   LPC_ICH8M,  /* ICH8M */
+   LPC_ICH8ME, /* ICH8M-E */
+   LPC_ICH9,   /* ICH9 */
+   LPC_ICH9R,  /* ICH9R */
+   LPC_ICH9DH, /* ICH9DH */
+   LPC_ICH9DO, /* ICH9DO */
+   LPC_ICH9M,  /* ICH9M */
+   LPC_ICH9ME, /* ICH9M-E */
+   LPC

[PATCH v7 3/6] x86/intel-ivi: Add Intel In-Vehicle Infotainment (IVI) systems used in cars support

2016-09-28 Thread Tan Jui Nee 
Add support for non ACPI system, such as system that uses Advanced Boot
Loader (ABL) whereby a platform device has to be created in order to bind
with PINCTRL/GPIO.

At the moment, Intel Apollo Lake SoC requires P2SB driver to hide and
unhide P2SB to lookup P2SB BAR and pass the PCI BAR address to GPIO.

Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
 arch/x86/Kconfig | 8 
 1 file changed, 8 insertions(+)

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index edc0313..ce5a048 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -511,6 +511,14 @@ config X86_INTEL_CE
  This option compiles in support for the CE4100 SOC for settop
  boxes and media devices.
 
+config X86_INTEL_IVI
+   bool "Intel In-Vehicle Infotainment (IVI) systems used in cars"
+   ---help---
+ Select this option to enable MMIO BAR access over the P2SB for
+ non-ACPI Intel Apollo Lake SoC platforms. This driver uses the P2SB
+ hide/unhide mechanism cooperatively to pass the PCI BAR address to
+ the platform driver, currently GPIO.
+
 config X86_INTEL_MID
bool "Intel MID platform support"
depends on X86_EXTENDED_PLATFORM
-- 
1.9.1

[PATCH v7 3/6] x86/intel-ivi: Add Intel In-Vehicle Infotainment (IVI) systems used in cars support

2016-09-28 Thread Tan Jui Nee 
Add support for non ACPI system, such as system that uses Advanced Boot
Loader (ABL) whereby a platform device has to be created in order to bind
with PINCTRL/GPIO.

At the moment, Intel Apollo Lake SoC requires P2SB driver to hide and
unhide P2SB to lookup P2SB BAR and pass the PCI BAR address to GPIO.

Signed-off-by: Tan Jui Nee 
---
 arch/x86/Kconfig | 8 
 1 file changed, 8 insertions(+)

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index edc0313..ce5a048 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -511,6 +511,14 @@ config X86_INTEL_CE
  This option compiles in support for the CE4100 SOC for settop
  boxes and media devices.
 
+config X86_INTEL_IVI
+   bool "Intel In-Vehicle Infotainment (IVI) systems used in cars"
+   ---help---
+ Select this option to enable MMIO BAR access over the P2SB for
+ non-ACPI Intel Apollo Lake SoC platforms. This driver uses the P2SB
+ hide/unhide mechanism cooperatively to pass the PCI BAR address to
+ the platform driver, currently GPIO.
+
 config X86_INTEL_MID
bool "Intel MID platform support"
depends on X86_EXTENDED_PLATFORM
-- 
1.9.1

[PATCH v7 0/6] pinctrl/broxton: enable platform device in the absent of ACPI enumeration

2016-09-28 Thread Tan Jui Nee 
Hi,
The patches are to cater the need for non-ACPI system whereby
a platform device has to be created in order to bind with
Apollo Lake Pinctrl GPIO platform driver.

The MMIO BAR is accessed over the Primary to Sideband bridge
(P2SB). Since the BIOS prevents the P2SB device from being
enumerated by the PCI subsystem, so we need to hide/unhide P2SB
to lookup the P2SB BAR and pass the PCI BAR address to the gpio
platform driver.

All these three patches have dependencies on each other.

Changes in V7:
- EXPORT_SYMBOL_GPL() and MODULE_LICENSE("GPL v2") are used for new file
  p2sb.c.
- Split Kconfig option CONFIG_X86_INTEL_IVI to separate patch 
(suggested by
  Lee).
- Split new platform enabling into a separate patch.
- Move lpc_chipsets enum's definition into a standalone header file 
which
  can be used wherever its definition is needed.
- Add author information and rewrite description of source file 
  lpc_ich-apl.c and lpc_ich_apl.h.
- Sort the header files by alphabetical order in lpc_ich-apl.c.
- Rename header file lpc_ich-apl.h to lpc_ich_apl.h (suggested by Lee).
- Remove unneeded pdata_size and platform_data from mfd_cell.
  Also, remove unneeded apl_pinctrl_pdata.
- Since variable apl_p2sb is only used once, hence switch it out for the
  PCI_DEVFN macro (suggested by Lee).
- Define APL_GPIO_COMMUNITY_MAX as total Apollo Lake GPIO communities
  supported.
- Set resources in mfd_cell for each GPIO community.
- Call p2sb_bar() function once instead of four times inside the for 
loop.
  And make p2sb_bar() function just to fill in the base address into a
  scratch "struct resource" and have the loop do the additions to 
base/end.
- Remove entire apl_pinctrl_pdata.name memory allocation since it is no
  longer needed.
- Return ret at the end of lpc_ich_add_gpio() function.

Changes in V6:
- Rename CONFIG_X86_INTEL_APL to CONFIG_X86_INTEL_IVI so that it
  relates to the actual product, as suggested by Mika.
- Rework Makefile according Andy's comments.
- Rename lpc_ich_misc() to lpc_ich_add_gpio() so that the name should 
not
  be so generic, as suggested by Andy.
- Call lpc_ich_add_gpio() via priv->chipset.
- lpc_ich_add_gpio() function will be moved from 
  .../include/linux/mfd/lpc_ich.h to
  .../drivers/mfd/lpc_ich-apl.h
  as this is a part of internal driver interface as suggested by Andy.
- Move enum lpc_chipsets from 
  .../drivers/mfd/lpc_ich-core.c to
  .../include/linux/mfd/lpc_ich.h
  as lpc_chipsets is also accessed by lpc_ich_add_gpio().
- Check if kasprintf return value for all 4 gpio controllers before
  proceed to add platform device by using mfd_add_devices().

Changes in V5:
- Split lpc-ich driver into two parts (lpc_ich-core and lpc_ich-apl).
  The file lpc_ich-apl.c introduces gpio platform driver in MFD.
- Rename Kconfig option CONFIG_X86_INTEL_NON_ACPI to 
CONFIG_X86_INTEL_APL
  so that it reflects actual product as suggested by Mika.
- The patch: 
  [PATCH] pinctrl/broxton: enable platform device in the absent of ACPI 
enumeration
  is removed in V5 patch-set as the patch is already applied in Linus' 
pinctrl tree.

Changes in V4:
- Move Kconfig option CONFIG_X86_INTEL_NON_ACPI from
  [PATCH 2/3] x86/platform/p2sb: New Primary to Sideband bridge support 
driver for Intel SOC's
  to
  [PATCH 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO 
pinctrl in non-ACPI system
  since the config is used in latter patch.
- Select CONFIG_P2SB when CONFIG_LPC_ICH is enabled.
- Remove #ifdef CONFIG_X86_INTEL_NON_ACPI and use
  #if defined(CONFIG_X86_INTEL_NON_ACPI) when lpc_ich_misc is called
  as suggested by Lee Jones.
- Use single dimensional array instead of 2D array for apl_gpio_io_res
  structure and use DEFINE_RES_IRQ for its IRQ resource.

Changes in V3:
- Simplify register addresses calculation and use DEFINE_RES_MEM_NAMED
  defines for apl_gpio_io_res structure
- Define magic number for P2SB PCI ID
- Replace switch-case with if-else since currently we have only one
  use case
- Only call mfd_add_devices() once for all gpio communities

Changes in V2:
- Add new config option CONFIG_X86_INTEL_NON_ACPI and "select PINCTRL"
  to fix kbuildbot error

Andy Shevchenko (1):
  x86/platform/p2sb: New Primary to Sideband bridge support driver for
Intel SOC's

Tan Jui Nee (5):
  mfd: lpc_ich: Rename lpc-ich driver
  x86/intel-ivi: Add Intel In-Vehicle Infotainment (IVI) systems used in
cars support
  mfd: move enum lpc_chipsets i

[PATCH v7 0/6] pinctrl/broxton: enable platform device in the absent of ACPI enumeration

2016-09-28 Thread Tan Jui Nee 
Hi,
The patches are to cater the need for non-ACPI system whereby
a platform device has to be created in order to bind with
Apollo Lake Pinctrl GPIO platform driver.

The MMIO BAR is accessed over the Primary to Sideband bridge
(P2SB). Since the BIOS prevents the P2SB device from being
enumerated by the PCI subsystem, so we need to hide/unhide P2SB
to lookup the P2SB BAR and pass the PCI BAR address to the gpio
platform driver.

All these three patches have dependencies on each other.

Changes in V7:
- EXPORT_SYMBOL_GPL() and MODULE_LICENSE("GPL v2") are used for new file
  p2sb.c.
- Split Kconfig option CONFIG_X86_INTEL_IVI to separate patch 
(suggested by
  Lee).
- Split new platform enabling into a separate patch.
- Move lpc_chipsets enum's definition into a standalone header file 
which
  can be used wherever its definition is needed.
- Add author information and rewrite description of source file 
  lpc_ich-apl.c and lpc_ich_apl.h.
- Sort the header files by alphabetical order in lpc_ich-apl.c.
- Rename header file lpc_ich-apl.h to lpc_ich_apl.h (suggested by Lee).
- Remove unneeded pdata_size and platform_data from mfd_cell.
  Also, remove unneeded apl_pinctrl_pdata.
- Since variable apl_p2sb is only used once, hence switch it out for the
  PCI_DEVFN macro (suggested by Lee).
- Define APL_GPIO_COMMUNITY_MAX as total Apollo Lake GPIO communities
  supported.
- Set resources in mfd_cell for each GPIO community.
- Call p2sb_bar() function once instead of four times inside the for 
loop.
  And make p2sb_bar() function just to fill in the base address into a
  scratch "struct resource" and have the loop do the additions to 
base/end.
- Remove entire apl_pinctrl_pdata.name memory allocation since it is no
  longer needed.
- Return ret at the end of lpc_ich_add_gpio() function.

Changes in V6:
- Rename CONFIG_X86_INTEL_APL to CONFIG_X86_INTEL_IVI so that it
  relates to the actual product, as suggested by Mika.
- Rework Makefile according Andy's comments.
- Rename lpc_ich_misc() to lpc_ich_add_gpio() so that the name should 
not
  be so generic, as suggested by Andy.
- Call lpc_ich_add_gpio() via priv->chipset.
- lpc_ich_add_gpio() function will be moved from 
  .../include/linux/mfd/lpc_ich.h to
  .../drivers/mfd/lpc_ich-apl.h
  as this is a part of internal driver interface as suggested by Andy.
- Move enum lpc_chipsets from 
  .../drivers/mfd/lpc_ich-core.c to
  .../include/linux/mfd/lpc_ich.h
  as lpc_chipsets is also accessed by lpc_ich_add_gpio().
- Check if kasprintf return value for all 4 gpio controllers before
  proceed to add platform device by using mfd_add_devices().

Changes in V5:
- Split lpc-ich driver into two parts (lpc_ich-core and lpc_ich-apl).
  The file lpc_ich-apl.c introduces gpio platform driver in MFD.
- Rename Kconfig option CONFIG_X86_INTEL_NON_ACPI to 
CONFIG_X86_INTEL_APL
  so that it reflects actual product as suggested by Mika.
- The patch: 
  [PATCH] pinctrl/broxton: enable platform device in the absent of ACPI 
enumeration
  is removed in V5 patch-set as the patch is already applied in Linus' 
pinctrl tree.

Changes in V4:
- Move Kconfig option CONFIG_X86_INTEL_NON_ACPI from
  [PATCH 2/3] x86/platform/p2sb: New Primary to Sideband bridge support 
driver for Intel SOC's
  to
  [PATCH 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO 
pinctrl in non-ACPI system
  since the config is used in latter patch.
- Select CONFIG_P2SB when CONFIG_LPC_ICH is enabled.
- Remove #ifdef CONFIG_X86_INTEL_NON_ACPI and use
  #if defined(CONFIG_X86_INTEL_NON_ACPI) when lpc_ich_misc is called
  as suggested by Lee Jones.
- Use single dimensional array instead of 2D array for apl_gpio_io_res
  structure and use DEFINE_RES_IRQ for its IRQ resource.

Changes in V3:
- Simplify register addresses calculation and use DEFINE_RES_MEM_NAMED
  defines for apl_gpio_io_res structure
- Define magic number for P2SB PCI ID
- Replace switch-case with if-else since currently we have only one
  use case
- Only call mfd_add_devices() once for all gpio communities

Changes in V2:
- Add new config option CONFIG_X86_INTEL_NON_ACPI and "select PINCTRL"
  to fix kbuildbot error

Andy Shevchenko (1):
  x86/platform/p2sb: New Primary to Sideband bridge support driver for
Intel SOC's

Tan Jui Nee (5):
  mfd: lpc_ich: Rename lpc-ich driver
  x86/intel-ivi: Add Intel In-Vehicle Infotainment (IVI) systems used in
cars support
  mfd: move enum lpc_chipsets i

RE: [PATCH v6 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO pinctrl in non-ACPI system

2016-09-28 Thread Tan, Jui Nee 


> -Original Message-
> From: Lee Jones [mailto:lee.jo...@linaro.org]
> Sent: Tuesday, August 9, 2016 3:16 PM
> To: Tan, Jui Nee <jui.nee@intel.com>
> Cc: mika.westerb...@linux.intel.com; heikki.kroge...@linux.intel.com;
> andriy.shevche...@linux.intel.com; t...@linutronix.de;
> mi...@redhat.com; h...@zytor.com; x...@kernel.org; pty...@xes-inc.com;
> linus.wall...@linaro.org; linux-g...@vger.kernel.org; linux-
> ker...@vger.kernel.org; Yong, Jonathan <jonathan.y...@intel.com>; Yu,
> Ong Hock <ong.hock...@intel.com>; Voon, Weifeng
> <weifeng.v...@intel.com>; Wan Mohamad, Wan Ahmad Zainie
> <wan.ahmad.zainie.wan.moha...@intel.com>
> Subject: Re: [PATCH v6 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake
> GPIO pinctrl in non-ACPI system
> 
> On Thu, 14 Jul 2016, Tan Jui Nee wrote:
> 
> > This driver uses the P2SB hide/unhide mechanism cooperatively to pass
> > the PCI BAR address to the gpio platform driver.
> >
> > Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
> > ---
> > Changes in V6:
> > - Rename CONFIG_X86_INTEL_APL to CONFIG_X86_INTEL_IVI so
> that it
> >   relates to the actual product, as suggested by Mika.
> > - Rework Makefile according Andy's comments.
> > - Rename lpc_ich_misc() to lpc_ich_add_gpio() so that the name
> should not
> >   be so generic, as suggested by Andy.
> > - Call lpc_ich_add_gpio() via priv->chipset.
> > - lpc_ich_add_gpio() function will be moved from
> >   .../include/linux/mfd/lpc_ich.h to
> >   .../drivers/mfd/lpc_ich-apl.h
> >   as this is a part of internal driver interface as suggested by Andy.
> > - Move enum lpc_chipsets from
> >   .../drivers/mfd/lpc_ich-core.c to
> >   .../include/linux/mfd/lpc_ich.h
> >   as lpc_chipsets is also accessed by lpc_ich_add_gpio().
> > - Check if kasprintf return value for all 4 gpio controllers before
> >   proceed to add platform device by using mfd_add_devices().
> >
> > Changes in V5:
> > - Split lpc-ich driver into two parts (lpc_ich-core and lpc_ich-apl).
> >   The file lpc_ich-apl.c introduces gpio platform driver in MFD.
> > - Rename Kconfig option CONFIG_X86_INTEL_NON_ACPI to
> CONFIG_X86_INTEL_APL
> >   so that it reflects actual product as suggested by Mika.
> >
> > Changes in V4:
> > - Move Kconfig option CONFIG_X86_INTEL_NON_ACPI from
> >   [PATCH 2/3] x86/platform/p2sb: New Primary to Sideband bridge
> support driver for Intel SOC's
> >   to
> >   [PATCH 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO
> pinctrl in non-ACPI system
> >   since the config is used in latter patch.
> > - Select CONFIG_P2SB when CONFIG_LPC_ICH is enabled.
> > - Remove #ifdef CONFIG_X86_INTEL_NON_ACPI and use
> >   #if defined(CONFIG_X86_INTEL_NON_ACPI) when lpc_ich_misc is
> called
> >   as suggested by Lee Jones.
> > - Use single dimensional array instead of 2D array for apl_gpio_io_res
> >   structure and use DEFINE_RES_IRQ for its IRQ resource.
> >
> > Changes in V3:
> > - Simplify register addresses calculation and use
> DEFINE_RES_MEM_NAMED
> >   defines for apl_gpio_io_res structure
> > - Define magic number for P2SB PCI ID
> > - Replace switch-case with if-else since currently we have only one
> >   use case
> > - Only call mfd_add_devices() once for all gpio communities
> >
> > Changes in V2:
> > - Add new config option CONFIG_X86_INTEL_NON_ACPI and "select
> PINCTRL"
> >   to fix kbuildbot error
> >
> >  arch/x86/Kconfig|   9 +++
> >  drivers/mfd/Kconfig |   3 +-
> >  drivers/mfd/Makefile|   5 +-
> >  drivers/mfd/lpc_ich-apl.c   | 130
> 
> >  drivers/mfd/lpc_ich-apl.h   |  28 ++
> >  drivers/mfd/lpc_ich-core.c  |  81 ---
> > include/linux/mfd/lpc_ich.h |  73 +
> >  7 files changed, 256 insertions(+), 73 deletions(-)  create mode
> > 100644 drivers/mfd/lpc_ich-apl.c  create mode 100644
> > drivers/mfd/lpc_ich-apl.h
> >
> > diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index
> > d305d81..c0b427b 100644
> > --- a/arch/x86/Kconfig
> > +++ b/arch/x86/Kconfig
> > @@ -513,6 +513,15 @@ config X86_INTEL_CE
> >   This option compiles in support for the CE4100 SOC for settop
> >   boxes and media devices.
> >
> > +config X86_INTEL_IVI
> > +   bool &qu

RE: [PATCH v6 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO pinctrl in non-ACPI system

2016-09-28 Thread Tan, Jui Nee 


> -Original Message-
> From: Lee Jones [mailto:lee.jo...@linaro.org]
> Sent: Tuesday, August 9, 2016 3:16 PM
> To: Tan, Jui Nee 
> Cc: mika.westerb...@linux.intel.com; heikki.kroge...@linux.intel.com;
> andriy.shevche...@linux.intel.com; t...@linutronix.de;
> mi...@redhat.com; h...@zytor.com; x...@kernel.org; pty...@xes-inc.com;
> linus.wall...@linaro.org; linux-g...@vger.kernel.org; linux-
> ker...@vger.kernel.org; Yong, Jonathan ; Yu,
> Ong Hock ; Voon, Weifeng
> ; Wan Mohamad, Wan Ahmad Zainie
> 
> Subject: Re: [PATCH v6 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake
> GPIO pinctrl in non-ACPI system
> 
> On Thu, 14 Jul 2016, Tan Jui Nee wrote:
> 
> > This driver uses the P2SB hide/unhide mechanism cooperatively to pass
> > the PCI BAR address to the gpio platform driver.
> >
> > Signed-off-by: Tan Jui Nee 
> > ---
> > Changes in V6:
> > - Rename CONFIG_X86_INTEL_APL to CONFIG_X86_INTEL_IVI so
> that it
> >   relates to the actual product, as suggested by Mika.
> > - Rework Makefile according Andy's comments.
> > - Rename lpc_ich_misc() to lpc_ich_add_gpio() so that the name
> should not
> >   be so generic, as suggested by Andy.
> > - Call lpc_ich_add_gpio() via priv->chipset.
> > - lpc_ich_add_gpio() function will be moved from
> >   .../include/linux/mfd/lpc_ich.h to
> >   .../drivers/mfd/lpc_ich-apl.h
> >   as this is a part of internal driver interface as suggested by Andy.
> > - Move enum lpc_chipsets from
> >   .../drivers/mfd/lpc_ich-core.c to
> >   .../include/linux/mfd/lpc_ich.h
> >   as lpc_chipsets is also accessed by lpc_ich_add_gpio().
> > - Check if kasprintf return value for all 4 gpio controllers before
> >   proceed to add platform device by using mfd_add_devices().
> >
> > Changes in V5:
> > - Split lpc-ich driver into two parts (lpc_ich-core and lpc_ich-apl).
> >   The file lpc_ich-apl.c introduces gpio platform driver in MFD.
> > - Rename Kconfig option CONFIG_X86_INTEL_NON_ACPI to
> CONFIG_X86_INTEL_APL
> >   so that it reflects actual product as suggested by Mika.
> >
> > Changes in V4:
> > - Move Kconfig option CONFIG_X86_INTEL_NON_ACPI from
> >   [PATCH 2/3] x86/platform/p2sb: New Primary to Sideband bridge
> support driver for Intel SOC's
> >   to
> >   [PATCH 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO
> pinctrl in non-ACPI system
> >   since the config is used in latter patch.
> > - Select CONFIG_P2SB when CONFIG_LPC_ICH is enabled.
> > - Remove #ifdef CONFIG_X86_INTEL_NON_ACPI and use
> >   #if defined(CONFIG_X86_INTEL_NON_ACPI) when lpc_ich_misc is
> called
> >   as suggested by Lee Jones.
> > - Use single dimensional array instead of 2D array for apl_gpio_io_res
> >   structure and use DEFINE_RES_IRQ for its IRQ resource.
> >
> > Changes in V3:
> > - Simplify register addresses calculation and use
> DEFINE_RES_MEM_NAMED
> >   defines for apl_gpio_io_res structure
> > - Define magic number for P2SB PCI ID
> > - Replace switch-case with if-else since currently we have only one
> >   use case
> > - Only call mfd_add_devices() once for all gpio communities
> >
> > Changes in V2:
> > - Add new config option CONFIG_X86_INTEL_NON_ACPI and "select
> PINCTRL"
> >   to fix kbuildbot error
> >
> >  arch/x86/Kconfig|   9 +++
> >  drivers/mfd/Kconfig |   3 +-
> >  drivers/mfd/Makefile|   5 +-
> >  drivers/mfd/lpc_ich-apl.c   | 130
> 
> >  drivers/mfd/lpc_ich-apl.h   |  28 ++
> >  drivers/mfd/lpc_ich-core.c  |  81 ---
> > include/linux/mfd/lpc_ich.h |  73 +
> >  7 files changed, 256 insertions(+), 73 deletions(-)  create mode
> > 100644 drivers/mfd/lpc_ich-apl.c  create mode 100644
> > drivers/mfd/lpc_ich-apl.h
> >
> > diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index
> > d305d81..c0b427b 100644
> > --- a/arch/x86/Kconfig
> > +++ b/arch/x86/Kconfig
> > @@ -513,6 +513,15 @@ config X86_INTEL_CE
> >   This option compiles in support for the CE4100 SOC for settop
> >   boxes and media devices.
> >
> > +config X86_INTEL_IVI
> > +   bool "Intel in-vehicle infotainment (IVI) systems used in cars"
> > +   select PINCTRL
> > +   ---help---
> > + Select this option to enable MMIO BAR access over the P2SB for
>

RE: [PATCH v6 1/3] x86/platform/p2sb: New Primary to Sideband bridge support driver for Intel SOC's

2016-07-17 Thread Tan, Jui Nee 


> -Original Message-
> From: Tan, Jui Nee
> Sent: Monday, July 18, 2016 11:35 AM
> To: 'Paul Gortmaker' <paul.gortma...@windriver.com>;
> andriy.shevche...@linux.intel.com
> Cc: mika.westerb...@linux.intel.com; heikki.kroge...@linux.intel.com;
> t...@linutronix.de; mi...@redhat.com; H. Peter Anvin <h...@zytor.com>;
> X86 ML <x...@kernel.org>; pty...@xes-inc.com; Lee Jones
> <lee.jo...@linaro.org>; Linus Walleij <linus.wall...@linaro.org>; linux-
> g...@vger.kernel.org; LKML <linux-kernel@vger.kernel.org>; Yong,
> Jonathan <jonathan.y...@intel.com>; Yu, Ong Hock
> <ong.hock...@intel.com>; Voon, Weifeng <weifeng.v...@intel.com>; Wan
> Mohamad, Wan Ahmad Zainie
> <wan.ahmad.zainie.wan.moha...@intel.com>
> Subject: RE: [PATCH v6 1/3] x86/platform/p2sb: New Primary to Sideband
> bridge support driver for Intel SOC's
> 
> 
> 
> > -Original Message-
> > From: paul.gortma...@gmail.com [mailto:paul.gortma...@gmail.com] On
> > Behalf Of Paul Gortmaker
> > Sent: Friday, July 15, 2016 8:01 AM
> > To: Tan, Jui Nee <jui.nee@intel.com>
> > Cc: mika.westerb...@linux.intel.com; heikki.kroge...@linux.intel.com;
> > andriy.shevche...@linux.intel.com; t...@linutronix.de;
> > mi...@redhat.com; H. Peter Anvin <h...@zytor.com>; X86 ML
> > <x...@kernel.org>; pty...@xes-inc.com; Lee Jones
> <lee.jo...@linaro.org>;
> > Linus Walleij <linus.wall...@linaro.org>; linux-g...@vger.kernel.org; LKML
> > <linux-kernel@vger.kernel.org>; Yong, Jonathan
> > <jonathan.y...@intel.com>; Yu, Ong Hock <ong.hock...@intel.com>;
> Voon,
> > Weifeng <weifeng.v...@intel.com>; Wan Mohamad, Wan Ahmad Zainie
> > <wan.ahmad.zainie.wan.moha...@intel.com>
> > Subject: Re: [PATCH v6 1/3] x86/platform/p2sb: New Primary to Sideband
> > bridge support driver for Intel SOC's
> >
> > On Thu, Jul 14, 2016 at 4:11 AM, Tan Jui Nee <jui.nee@intel.com>
> wrote:
> > > From: Andy Shevchenko <andriy.shevche...@linux.intel.com>
> > >
> > > There is already one and at least one more user coming which require
> > > an access to Primary to Sideband bridge (P2SB) in order to get IO or
> > > MMIO bar hidden by BIOS.
> > > Create a driver to access P2SB for x86 devices.
> > >
> > > Signed-off-by: Yong, Jonathan <jonathan.y...@intel.com>
> > > Signed-off-by: Andy Shevchenko <andriy.shevche...@linux.intel.com>
> > > ---
> > > Changes in V6:
> > > - No change
> > >
> > > Changes in V5:
> > > - No change
> > >
> > > Changes in V4:
> > > - Move Kconfig option CONFIG_X86_INTEL_NON_ACPI from
> > >   [PATCH 2/3] x86/platform/p2sb: New Primary to Sideband bridge
> > support driver for Intel SOC's
> > >   to
> > >   [PATCH 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO
> > pinctrl in non-ACPI system
> > >   since the config is used in latter patch.
> > >
> > > Changes in V3:
> > > - No change
> > >
> > > Changes in V2:
> > > - Add new config option CONFIG_X86_INTEL_NON_ACPI and "select
> > PINCTRL"
> > >   to fix kbuildbot error
> > >
> > >  arch/x86/Kconfig |  4 ++
> > >  arch/x86/include/asm/p2sb.h  | 27 +++
> > >  arch/x86/platform/intel/Makefile |  1 +
> > >  arch/x86/platform/intel/p2sb.c   | 99
> > 
> > >  4 files changed, 131 insertions(+)
> > >  create mode 100644 arch/x86/include/asm/p2sb.h  create mode 100644
> > > arch/x86/platform/intel/p2sb.c
> > >
> > > diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index
> > > d9a94da..d305d81 100644
> > > --- a/arch/x86/Kconfig
> > > +++ b/arch/x86/Kconfig
> > > @@ -604,6 +604,10 @@ config IOSF_MBI_DEBUG
> > >
> > >   If you don't require the option or are in doubt, say N.
> > >
> > > +config P2SB
> > > +   tristate
> >
> > OK, this is tristate, but then
> >
> P2SB is tristate as currently it is only used by LPC_ICH that is tristate too.
> ...
> config LPC_ICH
>   tristate "Intel ICH LPC"
>   depends on X86 && PCI
>   select MFD_CORE
>   select P2SB
> ...
> > > +   depends on PCI
> > > +
> > >  config X86_RDC321X
> > > bool "RDC R-321x SoC&

RE: [PATCH v6 1/3] x86/platform/p2sb: New Primary to Sideband bridge support driver for Intel SOC's

2016-07-17 Thread Tan, Jui Nee 


> -Original Message-
> From: Tan, Jui Nee
> Sent: Monday, July 18, 2016 11:35 AM
> To: 'Paul Gortmaker' ;
> andriy.shevche...@linux.intel.com
> Cc: mika.westerb...@linux.intel.com; heikki.kroge...@linux.intel.com;
> t...@linutronix.de; mi...@redhat.com; H. Peter Anvin ;
> X86 ML ; pty...@xes-inc.com; Lee Jones
> ; Linus Walleij ; linux-
> g...@vger.kernel.org; LKML ; Yong,
> Jonathan ; Yu, Ong Hock
> ; Voon, Weifeng ; Wan
> Mohamad, Wan Ahmad Zainie
> 
> Subject: RE: [PATCH v6 1/3] x86/platform/p2sb: New Primary to Sideband
> bridge support driver for Intel SOC's
> 
> 
> 
> > -Original Message-
> > From: paul.gortma...@gmail.com [mailto:paul.gortma...@gmail.com] On
> > Behalf Of Paul Gortmaker
> > Sent: Friday, July 15, 2016 8:01 AM
> > To: Tan, Jui Nee 
> > Cc: mika.westerb...@linux.intel.com; heikki.kroge...@linux.intel.com;
> > andriy.shevche...@linux.intel.com; t...@linutronix.de;
> > mi...@redhat.com; H. Peter Anvin ; X86 ML
> > ; pty...@xes-inc.com; Lee Jones
> ;
> > Linus Walleij ; linux-g...@vger.kernel.org; LKML
> > ; Yong, Jonathan
> > ; Yu, Ong Hock ;
> Voon,
> > Weifeng ; Wan Mohamad, Wan Ahmad Zainie
> > 
> > Subject: Re: [PATCH v6 1/3] x86/platform/p2sb: New Primary to Sideband
> > bridge support driver for Intel SOC's
> >
> > On Thu, Jul 14, 2016 at 4:11 AM, Tan Jui Nee 
> wrote:
> > > From: Andy Shevchenko 
> > >
> > > There is already one and at least one more user coming which require
> > > an access to Primary to Sideband bridge (P2SB) in order to get IO or
> > > MMIO bar hidden by BIOS.
> > > Create a driver to access P2SB for x86 devices.
> > >
> > > Signed-off-by: Yong, Jonathan 
> > > Signed-off-by: Andy Shevchenko 
> > > ---
> > > Changes in V6:
> > > - No change
> > >
> > > Changes in V5:
> > > - No change
> > >
> > > Changes in V4:
> > > - Move Kconfig option CONFIG_X86_INTEL_NON_ACPI from
> > >   [PATCH 2/3] x86/platform/p2sb: New Primary to Sideband bridge
> > support driver for Intel SOC's
> > >   to
> > >   [PATCH 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO
> > pinctrl in non-ACPI system
> > >   since the config is used in latter patch.
> > >
> > > Changes in V3:
> > > - No change
> > >
> > > Changes in V2:
> > > - Add new config option CONFIG_X86_INTEL_NON_ACPI and "select
> > PINCTRL"
> > >   to fix kbuildbot error
> > >
> > >  arch/x86/Kconfig |  4 ++
> > >  arch/x86/include/asm/p2sb.h  | 27 +++
> > >  arch/x86/platform/intel/Makefile |  1 +
> > >  arch/x86/platform/intel/p2sb.c   | 99
> > 
> > >  4 files changed, 131 insertions(+)
> > >  create mode 100644 arch/x86/include/asm/p2sb.h  create mode 100644
> > > arch/x86/platform/intel/p2sb.c
> > >
> > > diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index
> > > d9a94da..d305d81 100644
> > > --- a/arch/x86/Kconfig
> > > +++ b/arch/x86/Kconfig
> > > @@ -604,6 +604,10 @@ config IOSF_MBI_DEBUG
> > >
> > >   If you don't require the option or are in doubt, say N.
> > >
> > > +config P2SB
> > > +   tristate
> >
> > OK, this is tristate, but then
> >
> P2SB is tristate as currently it is only used by LPC_ICH that is tristate too.
> ...
> config LPC_ICH
>   tristate "Intel ICH LPC"
>   depends on X86 && PCI
>   select MFD_CORE
>   select P2SB
> ...
> > > +   depends on PCI
> > > +
> > >  config X86_RDC321X
> > > bool "RDC R-321x SoC"
> > > depends on X86_32
> > > diff --git a/arch/x86/include/asm/p2sb.h b/arch/x86/include/asm/p2sb.h
> > > new file mode 100644 index 000..686e07b
> > > --- /dev/null
> > > +++ b/arch/x86/include/asm/p2sb.h
> > > @@ -0,0 +1,27 @@
> > > +/*
> > > + * Primary to Sideband bridge (P2SB) access support  */
> > > +
> > > +#ifndef P2SB_SYMS_H
> > > +#define P2SB_SYMS_H
> > > +
> > > +#include 
> > > +#include 
> > > +
> > > +#if IS_ENABLED(CONFIG_P2SB)
> > > +
> > > +int p2sb_bar(struct pci_dev *pdev, unsigned int devfn,
> > > +   struct resource *res);
> > >

RE: [PATCH v6 1/3] x86/platform/p2sb: New Primary to Sideband bridge support driver for Intel SOC's

2016-07-17 Thread Tan, Jui Nee 


> -Original Message-
> From: paul.gortma...@gmail.com [mailto:paul.gortma...@gmail.com] On
> Behalf Of Paul Gortmaker
> Sent: Friday, July 15, 2016 8:01 AM
> To: Tan, Jui Nee <jui.nee@intel.com>
> Cc: mika.westerb...@linux.intel.com; heikki.kroge...@linux.intel.com;
> andriy.shevche...@linux.intel.com; t...@linutronix.de;
> mi...@redhat.com; H. Peter Anvin <h...@zytor.com>; X86 ML
> <x...@kernel.org>; pty...@xes-inc.com; Lee Jones <lee.jo...@linaro.org>;
> Linus Walleij <linus.wall...@linaro.org>; linux-g...@vger.kernel.org; LKML
> <linux-kernel@vger.kernel.org>; Yong, Jonathan
> <jonathan.y...@intel.com>; Yu, Ong Hock <ong.hock...@intel.com>; Voon,
> Weifeng <weifeng.v...@intel.com>; Wan Mohamad, Wan Ahmad Zainie
> <wan.ahmad.zainie.wan.moha...@intel.com>
> Subject: Re: [PATCH v6 1/3] x86/platform/p2sb: New Primary to Sideband
> bridge support driver for Intel SOC's
> 
> On Thu, Jul 14, 2016 at 4:11 AM, Tan Jui Nee <jui.nee@intel.com> wrote:
> > From: Andy Shevchenko <andriy.shevche...@linux.intel.com>
> >
> > There is already one and at least one more user coming which require
> > an access to Primary to Sideband bridge (P2SB) in order to get IO or
> > MMIO bar hidden by BIOS.
> > Create a driver to access P2SB for x86 devices.
> >
> > Signed-off-by: Yong, Jonathan <jonathan.y...@intel.com>
> > Signed-off-by: Andy Shevchenko <andriy.shevche...@linux.intel.com>
> > ---
> > Changes in V6:
> > - No change
> >
> > Changes in V5:
> > - No change
> >
> > Changes in V4:
> > - Move Kconfig option CONFIG_X86_INTEL_NON_ACPI from
> >   [PATCH 2/3] x86/platform/p2sb: New Primary to Sideband bridge
> support driver for Intel SOC's
> >   to
> >   [PATCH 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO
> pinctrl in non-ACPI system
> >   since the config is used in latter patch.
> >
> > Changes in V3:
> > - No change
> >
> > Changes in V2:
> > - Add new config option CONFIG_X86_INTEL_NON_ACPI and "select
> PINCTRL"
> >   to fix kbuildbot error
> >
> >  arch/x86/Kconfig |  4 ++
> >  arch/x86/include/asm/p2sb.h  | 27 +++
> >  arch/x86/platform/intel/Makefile |  1 +
> >  arch/x86/platform/intel/p2sb.c   | 99
> 
> >  4 files changed, 131 insertions(+)
> >  create mode 100644 arch/x86/include/asm/p2sb.h  create mode 100644
> > arch/x86/platform/intel/p2sb.c
> >
> > diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index
> > d9a94da..d305d81 100644
> > --- a/arch/x86/Kconfig
> > +++ b/arch/x86/Kconfig
> > @@ -604,6 +604,10 @@ config IOSF_MBI_DEBUG
> >
> >   If you don't require the option or are in doubt, say N.
> >
> > +config P2SB
> > +   tristate
> 
> OK, this is tristate, but then
> 
P2SB is tristate as currently it is only used by LPC_ICH that is tristate too.
...
config LPC_ICH
tristate "Intel ICH LPC"
depends on X86 && PCI
select MFD_CORE
select P2SB
...
> > +   depends on PCI
> > +
> >  config X86_RDC321X
> > bool "RDC R-321x SoC"
> > depends on X86_32
> > diff --git a/arch/x86/include/asm/p2sb.h b/arch/x86/include/asm/p2sb.h
> > new file mode 100644 index 000..686e07b
> > --- /dev/null
> > +++ b/arch/x86/include/asm/p2sb.h
> > @@ -0,0 +1,27 @@
> > +/*
> > + * Primary to Sideband bridge (P2SB) access support  */
> > +
> > +#ifndef P2SB_SYMS_H
> > +#define P2SB_SYMS_H
> > +
> > +#include 
> > +#include 
> > +
> > +#if IS_ENABLED(CONFIG_P2SB)
> > +
> > +int p2sb_bar(struct pci_dev *pdev, unsigned int devfn,
> > +   struct resource *res);
> > +
> > +#else /* CONFIG_P2SB is not set */
> > +
> > +static inline
> > +int p2sb_bar(struct pci_dev *pdev, unsigned int devfn,
> > +   struct resource *res)
> > +{
> > +   return -ENODEV;
> > +}
> > +
> > +#endif /* CONFIG_P2SB */
> > +
> > +#endif /* P2SB_SYMS_H */
> > diff --git a/arch/x86/platform/intel/Makefile
> > b/arch/x86/platform/intel/Makefile
> > index b878032..dbf9f10 100644
> > --- a/arch/x86/platform/intel/Makefile
> > +++ b/arch/x86/platform/intel/Makefile
> > @@ -1 +1,2 @@
> >  obj-$(CONFIG_IOSF_MBI) += iosf_mbi.o
> > +obj-$(CONFIG_P2SB)

RE: [PATCH v6 1/3] x86/platform/p2sb: New Primary to Sideband bridge support driver for Intel SOC's

2016-07-17 Thread Tan, Jui Nee 


> -Original Message-
> From: paul.gortma...@gmail.com [mailto:paul.gortma...@gmail.com] On
> Behalf Of Paul Gortmaker
> Sent: Friday, July 15, 2016 8:01 AM
> To: Tan, Jui Nee 
> Cc: mika.westerb...@linux.intel.com; heikki.kroge...@linux.intel.com;
> andriy.shevche...@linux.intel.com; t...@linutronix.de;
> mi...@redhat.com; H. Peter Anvin ; X86 ML
> ; pty...@xes-inc.com; Lee Jones ;
> Linus Walleij ; linux-g...@vger.kernel.org; LKML
> ; Yong, Jonathan
> ; Yu, Ong Hock ; Voon,
> Weifeng ; Wan Mohamad, Wan Ahmad Zainie
> 
> Subject: Re: [PATCH v6 1/3] x86/platform/p2sb: New Primary to Sideband
> bridge support driver for Intel SOC's
> 
> On Thu, Jul 14, 2016 at 4:11 AM, Tan Jui Nee  wrote:
> > From: Andy Shevchenko 
> >
> > There is already one and at least one more user coming which require
> > an access to Primary to Sideband bridge (P2SB) in order to get IO or
> > MMIO bar hidden by BIOS.
> > Create a driver to access P2SB for x86 devices.
> >
> > Signed-off-by: Yong, Jonathan 
> > Signed-off-by: Andy Shevchenko 
> > ---
> > Changes in V6:
> > - No change
> >
> > Changes in V5:
> > - No change
> >
> > Changes in V4:
> > - Move Kconfig option CONFIG_X86_INTEL_NON_ACPI from
> >   [PATCH 2/3] x86/platform/p2sb: New Primary to Sideband bridge
> support driver for Intel SOC's
> >   to
> >   [PATCH 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO
> pinctrl in non-ACPI system
> >   since the config is used in latter patch.
> >
> > Changes in V3:
> > - No change
> >
> > Changes in V2:
> > - Add new config option CONFIG_X86_INTEL_NON_ACPI and "select
> PINCTRL"
> >   to fix kbuildbot error
> >
> >  arch/x86/Kconfig |  4 ++
> >  arch/x86/include/asm/p2sb.h  | 27 +++
> >  arch/x86/platform/intel/Makefile |  1 +
> >  arch/x86/platform/intel/p2sb.c   | 99
> 
> >  4 files changed, 131 insertions(+)
> >  create mode 100644 arch/x86/include/asm/p2sb.h  create mode 100644
> > arch/x86/platform/intel/p2sb.c
> >
> > diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index
> > d9a94da..d305d81 100644
> > --- a/arch/x86/Kconfig
> > +++ b/arch/x86/Kconfig
> > @@ -604,6 +604,10 @@ config IOSF_MBI_DEBUG
> >
> >   If you don't require the option or are in doubt, say N.
> >
> > +config P2SB
> > +   tristate
> 
> OK, this is tristate, but then
> 
P2SB is tristate as currently it is only used by LPC_ICH that is tristate too.
...
config LPC_ICH
tristate "Intel ICH LPC"
depends on X86 && PCI
select MFD_CORE
select P2SB
...
> > +   depends on PCI
> > +
> >  config X86_RDC321X
> > bool "RDC R-321x SoC"
> > depends on X86_32
> > diff --git a/arch/x86/include/asm/p2sb.h b/arch/x86/include/asm/p2sb.h
> > new file mode 100644 index 000..686e07b
> > --- /dev/null
> > +++ b/arch/x86/include/asm/p2sb.h
> > @@ -0,0 +1,27 @@
> > +/*
> > + * Primary to Sideband bridge (P2SB) access support  */
> > +
> > +#ifndef P2SB_SYMS_H
> > +#define P2SB_SYMS_H
> > +
> > +#include 
> > +#include 
> > +
> > +#if IS_ENABLED(CONFIG_P2SB)
> > +
> > +int p2sb_bar(struct pci_dev *pdev, unsigned int devfn,
> > +   struct resource *res);
> > +
> > +#else /* CONFIG_P2SB is not set */
> > +
> > +static inline
> > +int p2sb_bar(struct pci_dev *pdev, unsigned int devfn,
> > +   struct resource *res)
> > +{
> > +   return -ENODEV;
> > +}
> > +
> > +#endif /* CONFIG_P2SB */
> > +
> > +#endif /* P2SB_SYMS_H */
> > diff --git a/arch/x86/platform/intel/Makefile
> > b/arch/x86/platform/intel/Makefile
> > index b878032..dbf9f10 100644
> > --- a/arch/x86/platform/intel/Makefile
> > +++ b/arch/x86/platform/intel/Makefile
> > @@ -1 +1,2 @@
> >  obj-$(CONFIG_IOSF_MBI) += iosf_mbi.o
> > +obj-$(CONFIG_P2SB) += p2sb.o
> > diff --git a/arch/x86/platform/intel/p2sb.c
> > b/arch/x86/platform/intel/p2sb.c new file mode 100644 index
> > 000..8be47a4
> > --- /dev/null
> > +++ b/arch/x86/platform/intel/p2sb.c
> > @@ -0,0 +1,99 @@
> > +/*
> > + * Primary to Sideband bridge (P2SB) driver
> > + *
> > + * Copyright (c) 2016, Intel Corporation.
> > + *
> > + * Authors: Andy Shevchenko 
>

RE: [PATCH v5 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO pinctrl in non-ACPI system

2016-07-14 Thread Tan, Jui Nee 


> -Original Message-
> From: Mika Westerberg [mailto:mika.westerb...@linux.intel.com]
> Sent: Tuesday, June 28, 2016 4:19 PM
> To: Tan, Jui Nee <jui.nee@intel.com>
> Cc: heikki.kroge...@linux.intel.com; andriy.shevche...@linux.intel.com;
> t...@linutronix.de; mi...@redhat.com; h...@zytor.com; x...@kernel.org;
> pty...@xes-inc.com; lee.jo...@linaro.org; linus.wall...@linaro.org; linux-
> g...@vger.kernel.org; linux-kernel@vger.kernel.org; Yong, Jonathan
> <jonathan.y...@intel.com>; Yu, Ong Hock <ong.hock...@intel.com>; Voon,
> Weifeng <weifeng.v...@intel.com>; Wan Mohamad, Wan Ahmad Zainie
> <wan.ahmad.zainie.wan.moha...@intel.com>
> Subject: Re: [PATCH v5 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake
> GPIO pinctrl in non-ACPI system
> 
> On Tue, Jun 28, 2016 at 03:56:48PM +0800, Tan Jui Nee wrote:
> > +config X86_INTEL_APL
> > +   bool "Non-ACPI support for Intel Apollo Lake platforms"
> > +   select PINCTRL
> > +   ---help---
> > + Select this option to enable MMIO BAR access over the P2SB for
> > + non-ACPI Intel Apollo Lake SoC platforms. This driver uses the P2SB
> > + hide/unhide mechanism cooperatively to pass the PCI BAR address
> to
> > + the platform driver, currently GPIO.
> > +
> 
> Sorry but IMHO this still does not explain the option clearly enough.
> You are using this in some automotive IVI system with specialized
> bootloader, correct? Why not use that here instead?
> 
> Something along the lines of
> 
>   config X86_INTEL_IVI
>   bool "Intel in-vehicle infotainment (IVI) systems used in cars"
Thanks for your comments. The changes will be applied in next patch-set.

RE: [PATCH v5 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO pinctrl in non-ACPI system

2016-07-14 Thread Tan, Jui Nee 


> -Original Message-
> From: Mika Westerberg [mailto:mika.westerb...@linux.intel.com]
> Sent: Tuesday, June 28, 2016 4:19 PM
> To: Tan, Jui Nee 
> Cc: heikki.kroge...@linux.intel.com; andriy.shevche...@linux.intel.com;
> t...@linutronix.de; mi...@redhat.com; h...@zytor.com; x...@kernel.org;
> pty...@xes-inc.com; lee.jo...@linaro.org; linus.wall...@linaro.org; linux-
> g...@vger.kernel.org; linux-kernel@vger.kernel.org; Yong, Jonathan
> ; Yu, Ong Hock ; Voon,
> Weifeng ; Wan Mohamad, Wan Ahmad Zainie
> 
> Subject: Re: [PATCH v5 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake
> GPIO pinctrl in non-ACPI system
> 
> On Tue, Jun 28, 2016 at 03:56:48PM +0800, Tan Jui Nee wrote:
> > +config X86_INTEL_APL
> > +   bool "Non-ACPI support for Intel Apollo Lake platforms"
> > +   select PINCTRL
> > +   ---help---
> > + Select this option to enable MMIO BAR access over the P2SB for
> > + non-ACPI Intel Apollo Lake SoC platforms. This driver uses the P2SB
> > + hide/unhide mechanism cooperatively to pass the PCI BAR address
> to
> > + the platform driver, currently GPIO.
> > +
> 
> Sorry but IMHO this still does not explain the option clearly enough.
> You are using this in some automotive IVI system with specialized
> bootloader, correct? Why not use that here instead?
> 
> Something along the lines of
> 
>   config X86_INTEL_IVI
>   bool "Intel in-vehicle infotainment (IVI) systems used in cars"
Thanks for your comments. The changes will be applied in next patch-set.

[PATCH v6 1/3] x86/platform/p2sb: New Primary to Sideband bridge support driver for Intel SOC's

2016-07-14 Thread Tan Jui Nee 
From: Andy Shevchenko 

There is already one and at least one more user coming which
require an access to Primary to Sideband bridge (P2SB) in order
to get IO or MMIO bar hidden by BIOS.
Create a driver to access P2SB for x86 devices.

Signed-off-by: Yong, Jonathan 
Signed-off-by: Andy Shevchenko 
---
Changes in V6:
- No change

Changes in V5:
- No change

Changes in V4:
- Move Kconfig option CONFIG_X86_INTEL_NON_ACPI from
  [PATCH 2/3] x86/platform/p2sb: New Primary to Sideband bridge support 
driver for Intel SOC's
  to
  [PATCH 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO 
pinctrl in non-ACPI system
  since the config is used in latter patch.

Changes in V3:
- No change

Changes in V2:
- Add new config option CONFIG_X86_INTEL_NON_ACPI and "select PINCTRL"
  to fix kbuildbot error

 arch/x86/Kconfig |  4 ++
 arch/x86/include/asm/p2sb.h  | 27 +++
 arch/x86/platform/intel/Makefile |  1 +
 arch/x86/platform/intel/p2sb.c   | 99 
 4 files changed, 131 insertions(+)
 create mode 100644 arch/x86/include/asm/p2sb.h
 create mode 100644 arch/x86/platform/intel/p2sb.c

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index d9a94da..d305d81 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -604,6 +604,10 @@ config IOSF_MBI_DEBUG
 
  If you don't require the option or are in doubt, say N.
 
+config P2SB
+   tristate
+   depends on PCI
+
 config X86_RDC321X
bool "RDC R-321x SoC"
depends on X86_32
diff --git a/arch/x86/include/asm/p2sb.h b/arch/x86/include/asm/p2sb.h
new file mode 100644
index 000..686e07b
--- /dev/null
+++ b/arch/x86/include/asm/p2sb.h
@@ -0,0 +1,27 @@
+/*
+ * Primary to Sideband bridge (P2SB) access support
+ */
+
+#ifndef P2SB_SYMS_H
+#define P2SB_SYMS_H
+
+#include 
+#include 
+
+#if IS_ENABLED(CONFIG_P2SB)
+
+int p2sb_bar(struct pci_dev *pdev, unsigned int devfn,
+   struct resource *res);
+
+#else /* CONFIG_P2SB is not set */
+
+static inline
+int p2sb_bar(struct pci_dev *pdev, unsigned int devfn,
+   struct resource *res)
+{
+   return -ENODEV;
+}
+
+#endif /* CONFIG_P2SB */
+
+#endif /* P2SB_SYMS_H */
diff --git a/arch/x86/platform/intel/Makefile b/arch/x86/platform/intel/Makefile
index b878032..dbf9f10 100644
--- a/arch/x86/platform/intel/Makefile
+++ b/arch/x86/platform/intel/Makefile
@@ -1 +1,2 @@
 obj-$(CONFIG_IOSF_MBI) += iosf_mbi.o
+obj-$(CONFIG_P2SB) += p2sb.o
diff --git a/arch/x86/platform/intel/p2sb.c b/arch/x86/platform/intel/p2sb.c
new file mode 100644
index 000..8be47a4
--- /dev/null
+++ b/arch/x86/platform/intel/p2sb.c
@@ -0,0 +1,99 @@
+/*
+ * Primary to Sideband bridge (P2SB) driver
+ *
+ * Copyright (c) 2016, Intel Corporation.
+ *
+ * Authors: Andy Shevchenko 
+ * Jonathan Yong 
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#define SBREG_BAR  0x10
+#define SBREG_HIDE 0xe1
+
+static DEFINE_SPINLOCK(p2sb_spinlock);
+
+/*
+ * p2sb_bar - Get Primary to Sideband bridge (P2SB) BAR
+ * @pdev:  PCI device to get PCI bus to communicate with
+ * @devfn: PCI device and function to communicate with
+ * @res:   resources to be filled in
+ *
+ * The BIOS prevents the P2SB device from being enumerated by the PCI
+ * subsystem, so we need to unhide and hide it back to lookup the P2SB BAR.
+ *
+ * Locking is handled by spinlock - cannot sleep.
+ *
+ * Return:
+ * 0 on success or appropriate errno value on error.
+ */
+int p2sb_bar(struct pci_dev *pdev, unsigned int devfn,
+   struct resource *res)
+{
+   u32 base_addr;
+   u64 base64_addr;
+   unsigned long flags;
+
+   if (!res)
+   return -EINVAL;
+
+   spin_lock(_spinlock);
+
+   /* Unhide the P2SB device */
+   pci_bus_write_config_byte(pdev->bus, devfn, SBREG_HIDE, 0x00);
+
+   /* Check if device present */
+   pci_bus_read_config_dword(pdev->bus, devfn, 0, _addr);
+   if (base_addr == 0x || base_addr == 0x) {
+   spin_unlock(_spinlock);
+   dev_warn(>dev, "P2SB device access disabled by BIOS?\n");
+   return -ENODEV;
+   }
+
+   /* Get IO or MMIO BAR */
+   pci_bus_read_config_dword(pdev->bus, devfn,

[PATCH v6 1/3] x86/platform/p2sb: New Primary to Sideband bridge support driver for Intel SOC's

2016-07-14 Thread Tan Jui Nee 
From: Andy Shevchenko 

There is already one and at least one more user coming which
require an access to Primary to Sideband bridge (P2SB) in order
to get IO or MMIO bar hidden by BIOS.
Create a driver to access P2SB for x86 devices.

Signed-off-by: Yong, Jonathan 
Signed-off-by: Andy Shevchenko 
---
Changes in V6:
- No change

Changes in V5:
- No change

Changes in V4:
- Move Kconfig option CONFIG_X86_INTEL_NON_ACPI from
  [PATCH 2/3] x86/platform/p2sb: New Primary to Sideband bridge support 
driver for Intel SOC's
  to
  [PATCH 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO 
pinctrl in non-ACPI system
  since the config is used in latter patch.

Changes in V3:
- No change

Changes in V2:
- Add new config option CONFIG_X86_INTEL_NON_ACPI and "select PINCTRL"
  to fix kbuildbot error

 arch/x86/Kconfig |  4 ++
 arch/x86/include/asm/p2sb.h  | 27 +++
 arch/x86/platform/intel/Makefile |  1 +
 arch/x86/platform/intel/p2sb.c   | 99 
 4 files changed, 131 insertions(+)
 create mode 100644 arch/x86/include/asm/p2sb.h
 create mode 100644 arch/x86/platform/intel/p2sb.c

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index d9a94da..d305d81 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -604,6 +604,10 @@ config IOSF_MBI_DEBUG
 
  If you don't require the option or are in doubt, say N.
 
+config P2SB
+   tristate
+   depends on PCI
+
 config X86_RDC321X
bool "RDC R-321x SoC"
depends on X86_32
diff --git a/arch/x86/include/asm/p2sb.h b/arch/x86/include/asm/p2sb.h
new file mode 100644
index 000..686e07b
--- /dev/null
+++ b/arch/x86/include/asm/p2sb.h
@@ -0,0 +1,27 @@
+/*
+ * Primary to Sideband bridge (P2SB) access support
+ */
+
+#ifndef P2SB_SYMS_H
+#define P2SB_SYMS_H
+
+#include 
+#include 
+
+#if IS_ENABLED(CONFIG_P2SB)
+
+int p2sb_bar(struct pci_dev *pdev, unsigned int devfn,
+   struct resource *res);
+
+#else /* CONFIG_P2SB is not set */
+
+static inline
+int p2sb_bar(struct pci_dev *pdev, unsigned int devfn,
+   struct resource *res)
+{
+   return -ENODEV;
+}
+
+#endif /* CONFIG_P2SB */
+
+#endif /* P2SB_SYMS_H */
diff --git a/arch/x86/platform/intel/Makefile b/arch/x86/platform/intel/Makefile
index b878032..dbf9f10 100644
--- a/arch/x86/platform/intel/Makefile
+++ b/arch/x86/platform/intel/Makefile
@@ -1 +1,2 @@
 obj-$(CONFIG_IOSF_MBI) += iosf_mbi.o
+obj-$(CONFIG_P2SB) += p2sb.o
diff --git a/arch/x86/platform/intel/p2sb.c b/arch/x86/platform/intel/p2sb.c
new file mode 100644
index 000..8be47a4
--- /dev/null
+++ b/arch/x86/platform/intel/p2sb.c
@@ -0,0 +1,99 @@
+/*
+ * Primary to Sideband bridge (P2SB) driver
+ *
+ * Copyright (c) 2016, Intel Corporation.
+ *
+ * Authors: Andy Shevchenko 
+ * Jonathan Yong 
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#define SBREG_BAR  0x10
+#define SBREG_HIDE 0xe1
+
+static DEFINE_SPINLOCK(p2sb_spinlock);
+
+/*
+ * p2sb_bar - Get Primary to Sideband bridge (P2SB) BAR
+ * @pdev:  PCI device to get PCI bus to communicate with
+ * @devfn: PCI device and function to communicate with
+ * @res:   resources to be filled in
+ *
+ * The BIOS prevents the P2SB device from being enumerated by the PCI
+ * subsystem, so we need to unhide and hide it back to lookup the P2SB BAR.
+ *
+ * Locking is handled by spinlock - cannot sleep.
+ *
+ * Return:
+ * 0 on success or appropriate errno value on error.
+ */
+int p2sb_bar(struct pci_dev *pdev, unsigned int devfn,
+   struct resource *res)
+{
+   u32 base_addr;
+   u64 base64_addr;
+   unsigned long flags;
+
+   if (!res)
+   return -EINVAL;
+
+   spin_lock(_spinlock);
+
+   /* Unhide the P2SB device */
+   pci_bus_write_config_byte(pdev->bus, devfn, SBREG_HIDE, 0x00);
+
+   /* Check if device present */
+   pci_bus_read_config_dword(pdev->bus, devfn, 0, _addr);
+   if (base_addr == 0x || base_addr == 0x) {
+   spin_unlock(_spinlock);
+   dev_warn(>dev, "P2SB device access disabled by BIOS?\n");
+   return -ENODEV;
+   }
+
+   /* Get IO or MMIO BAR */
+   pci_bus_read_config_dword(pdev->bus, devfn, SBREG_BAR, _addr);
+   if ((base_addr & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
+   flags = IORESOURCE_IO;
+

[PATCH v6 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO pinctrl in non-ACPI system

2016-07-14 Thread Tan Jui Nee 
This driver uses the P2SB hide/unhide mechanism cooperatively
to pass the PCI BAR address to the gpio platform driver.

Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
Changes in V6:
- Rename CONFIG_X86_INTEL_APL to CONFIG_X86_INTEL_IVI so that it
  relates to the actual product, as suggested by Mika.
- Rework Makefile according Andy's comments.
- Rename lpc_ich_misc() to lpc_ich_add_gpio() so that the name should 
not
  be so generic, as suggested by Andy.
- Call lpc_ich_add_gpio() via priv->chipset.
- lpc_ich_add_gpio() function will be moved from 
  .../include/linux/mfd/lpc_ich.h to
  .../drivers/mfd/lpc_ich-apl.h
  as this is a part of internal driver interface as suggested by Andy.
- Move enum lpc_chipsets from 
  .../drivers/mfd/lpc_ich-core.c to
  .../include/linux/mfd/lpc_ich.h
  as lpc_chipsets is also accessed by lpc_ich_add_gpio().
- Check if kasprintf return value for all 4 gpio controllers before
  proceed to add platform device by using mfd_add_devices().

Changes in V5:
- Split lpc-ich driver into two parts (lpc_ich-core and lpc_ich-apl).
  The file lpc_ich-apl.c introduces gpio platform driver in MFD.
- Rename Kconfig option CONFIG_X86_INTEL_NON_ACPI to 
CONFIG_X86_INTEL_APL
  so that it reflects actual product as suggested by Mika.

Changes in V4:
- Move Kconfig option CONFIG_X86_INTEL_NON_ACPI from
  [PATCH 2/3] x86/platform/p2sb: New Primary to Sideband bridge support 
driver for Intel SOC's
  to
  [PATCH 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO 
pinctrl in non-ACPI system
  since the config is used in latter patch.
- Select CONFIG_P2SB when CONFIG_LPC_ICH is enabled.
- Remove #ifdef CONFIG_X86_INTEL_NON_ACPI and use
  #if defined(CONFIG_X86_INTEL_NON_ACPI) when lpc_ich_misc is called
  as suggested by Lee Jones.
- Use single dimensional array instead of 2D array for apl_gpio_io_res
  structure and use DEFINE_RES_IRQ for its IRQ resource.

Changes in V3:
- Simplify register addresses calculation and use DEFINE_RES_MEM_NAMED
  defines for apl_gpio_io_res structure
- Define magic number for P2SB PCI ID
- Replace switch-case with if-else since currently we have only one
  use case
- Only call mfd_add_devices() once for all gpio communities

Changes in V2:
- Add new config option CONFIG_X86_INTEL_NON_ACPI and "select PINCTRL"
  to fix kbuildbot error

 arch/x86/Kconfig|   9 +++
 drivers/mfd/Kconfig |   3 +-
 drivers/mfd/Makefile|   5 +-
 drivers/mfd/lpc_ich-apl.c   | 130 
 drivers/mfd/lpc_ich-apl.h   |  28 ++
 drivers/mfd/lpc_ich-core.c  |  81 ---
 include/linux/mfd/lpc_ich.h |  73 +
 7 files changed, 256 insertions(+), 73 deletions(-)
 create mode 100644 drivers/mfd/lpc_ich-apl.c
 create mode 100644 drivers/mfd/lpc_ich-apl.h

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index d305d81..c0b427b 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -513,6 +513,15 @@ config X86_INTEL_CE
  This option compiles in support for the CE4100 SOC for settop
  boxes and media devices.
 
+config X86_INTEL_IVI
+   bool "Intel in-vehicle infotainment (IVI) systems used in cars"
+   select PINCTRL
+   ---help---
+ Select this option to enable MMIO BAR access over the P2SB for
+ non-ACPI Intel Apollo Lake SoC platforms. This driver uses the P2SB
+ hide/unhide mechanism cooperatively to pass the PCI BAR address to
+ the platform driver, currently GPIO.
+
 config X86_INTEL_MID
bool "Intel MID platform support"
depends on X86_EXTENDED_PLATFORM
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 1bcf601..dc4e543 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -369,8 +369,9 @@ config MFD_INTEL_QUARK_I2C_GPIO
 
 config LPC_ICH
tristate "Intel ICH LPC"
-   depends on PCI
+   depends on X86 && PCI
select MFD_CORE
+   select P2SB
help
  The LPC bridge function of the Intel ICH provides support for
  many functional units. This driver provides needed support for
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 1dfe5fb..0aa3e1f 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -155,8 +155,11 @@ obj-$(CONFIG_PMIC_ADP5520) += adp5520.o
 obj-$(CONFIG_MFD_KEMPLD)   += kempld-core.o
 obj-$(CONFIG_MFD_INTEL_QUARK_I2C_GPIO) += intel_quark_i2c_gpio.o
 obj-$(CONFIG_LPC_SCH)  += lpc_sch.o
-lpc_ich-objs   := lpc_ich-core.o
 obj-$(CONFIG_LPC_ICH)  += lpc_ich.o
+lpc_ich-objs   := lpc_ich-core.o
+ifeq (

[PATCH v6 2/3] mfd: lpc_ich: Rename lpc-ich driver

2016-07-14 Thread Tan Jui Nee 
This patch follows the example of mfd/wm831x to rename the driver
from "lpc_ich" to "lpc_ich-core".

Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
Changes in V6:
- none, just a subject line and commit message change.

 drivers/mfd/Makefile  | 1 +
 drivers/mfd/{lpc_ich.c => lpc_ich-core.c} | 0
 2 files changed, 1 insertion(+)
 rename drivers/mfd/{lpc_ich.c => lpc_ich-core.c} (100%)

diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 42a66e1..1dfe5fb 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -155,6 +155,7 @@ obj-$(CONFIG_PMIC_ADP5520)  += adp5520.o
 obj-$(CONFIG_MFD_KEMPLD)   += kempld-core.o
 obj-$(CONFIG_MFD_INTEL_QUARK_I2C_GPIO) += intel_quark_i2c_gpio.o
 obj-$(CONFIG_LPC_SCH)  += lpc_sch.o
+lpc_ich-objs   := lpc_ich-core.o
 obj-$(CONFIG_LPC_ICH)  += lpc_ich.o
 obj-$(CONFIG_MFD_RDC321X)  += rdc321x-southbridge.o
 obj-$(CONFIG_MFD_JANZ_CMODIO)  += janz-cmodio.o
diff --git a/drivers/mfd/lpc_ich.c b/drivers/mfd/lpc_ich-core.c
similarity index 100%
rename from drivers/mfd/lpc_ich.c
rename to drivers/mfd/lpc_ich-core.c
-- 
1.9.1

[PATCH v6 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO pinctrl in non-ACPI system

2016-07-14 Thread Tan Jui Nee 
This driver uses the P2SB hide/unhide mechanism cooperatively
to pass the PCI BAR address to the gpio platform driver.

Signed-off-by: Tan Jui Nee 
---
Changes in V6:
- Rename CONFIG_X86_INTEL_APL to CONFIG_X86_INTEL_IVI so that it
  relates to the actual product, as suggested by Mika.
- Rework Makefile according Andy's comments.
- Rename lpc_ich_misc() to lpc_ich_add_gpio() so that the name should 
not
  be so generic, as suggested by Andy.
- Call lpc_ich_add_gpio() via priv->chipset.
- lpc_ich_add_gpio() function will be moved from 
  .../include/linux/mfd/lpc_ich.h to
  .../drivers/mfd/lpc_ich-apl.h
  as this is a part of internal driver interface as suggested by Andy.
- Move enum lpc_chipsets from 
  .../drivers/mfd/lpc_ich-core.c to
  .../include/linux/mfd/lpc_ich.h
  as lpc_chipsets is also accessed by lpc_ich_add_gpio().
- Check if kasprintf return value for all 4 gpio controllers before
  proceed to add platform device by using mfd_add_devices().

Changes in V5:
- Split lpc-ich driver into two parts (lpc_ich-core and lpc_ich-apl).
  The file lpc_ich-apl.c introduces gpio platform driver in MFD.
- Rename Kconfig option CONFIG_X86_INTEL_NON_ACPI to 
CONFIG_X86_INTEL_APL
  so that it reflects actual product as suggested by Mika.

Changes in V4:
- Move Kconfig option CONFIG_X86_INTEL_NON_ACPI from
  [PATCH 2/3] x86/platform/p2sb: New Primary to Sideband bridge support 
driver for Intel SOC's
  to
  [PATCH 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO 
pinctrl in non-ACPI system
  since the config is used in latter patch.
- Select CONFIG_P2SB when CONFIG_LPC_ICH is enabled.
- Remove #ifdef CONFIG_X86_INTEL_NON_ACPI and use
  #if defined(CONFIG_X86_INTEL_NON_ACPI) when lpc_ich_misc is called
  as suggested by Lee Jones.
- Use single dimensional array instead of 2D array for apl_gpio_io_res
  structure and use DEFINE_RES_IRQ for its IRQ resource.

Changes in V3:
- Simplify register addresses calculation and use DEFINE_RES_MEM_NAMED
  defines for apl_gpio_io_res structure
- Define magic number for P2SB PCI ID
- Replace switch-case with if-else since currently we have only one
  use case
- Only call mfd_add_devices() once for all gpio communities

Changes in V2:
- Add new config option CONFIG_X86_INTEL_NON_ACPI and "select PINCTRL"
  to fix kbuildbot error

 arch/x86/Kconfig|   9 +++
 drivers/mfd/Kconfig |   3 +-
 drivers/mfd/Makefile|   5 +-
 drivers/mfd/lpc_ich-apl.c   | 130 
 drivers/mfd/lpc_ich-apl.h   |  28 ++
 drivers/mfd/lpc_ich-core.c  |  81 ---
 include/linux/mfd/lpc_ich.h |  73 +
 7 files changed, 256 insertions(+), 73 deletions(-)
 create mode 100644 drivers/mfd/lpc_ich-apl.c
 create mode 100644 drivers/mfd/lpc_ich-apl.h

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index d305d81..c0b427b 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -513,6 +513,15 @@ config X86_INTEL_CE
  This option compiles in support for the CE4100 SOC for settop
  boxes and media devices.
 
+config X86_INTEL_IVI
+   bool "Intel in-vehicle infotainment (IVI) systems used in cars"
+   select PINCTRL
+   ---help---
+ Select this option to enable MMIO BAR access over the P2SB for
+ non-ACPI Intel Apollo Lake SoC platforms. This driver uses the P2SB
+ hide/unhide mechanism cooperatively to pass the PCI BAR address to
+ the platform driver, currently GPIO.
+
 config X86_INTEL_MID
bool "Intel MID platform support"
depends on X86_EXTENDED_PLATFORM
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 1bcf601..dc4e543 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -369,8 +369,9 @@ config MFD_INTEL_QUARK_I2C_GPIO
 
 config LPC_ICH
tristate "Intel ICH LPC"
-   depends on PCI
+   depends on X86 && PCI
select MFD_CORE
+   select P2SB
help
  The LPC bridge function of the Intel ICH provides support for
  many functional units. This driver provides needed support for
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 1dfe5fb..0aa3e1f 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -155,8 +155,11 @@ obj-$(CONFIG_PMIC_ADP5520) += adp5520.o
 obj-$(CONFIG_MFD_KEMPLD)   += kempld-core.o
 obj-$(CONFIG_MFD_INTEL_QUARK_I2C_GPIO) += intel_quark_i2c_gpio.o
 obj-$(CONFIG_LPC_SCH)  += lpc_sch.o
-lpc_ich-objs   := lpc_ich-core.o
 obj-$(CONFIG_LPC_ICH)  += lpc_ich.o
+lpc_ich-objs   := lpc_ich-core.o
+ifeq ($(CONFIG_X86_INTEL

[PATCH v6 2/3] mfd: lpc_ich: Rename lpc-ich driver

2016-07-14 Thread Tan Jui Nee 
This patch follows the example of mfd/wm831x to rename the driver
from "lpc_ich" to "lpc_ich-core".

Signed-off-by: Tan Jui Nee 
---
Changes in V6:
- none, just a subject line and commit message change.

 drivers/mfd/Makefile  | 1 +
 drivers/mfd/{lpc_ich.c => lpc_ich-core.c} | 0
 2 files changed, 1 insertion(+)
 rename drivers/mfd/{lpc_ich.c => lpc_ich-core.c} (100%)

diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 42a66e1..1dfe5fb 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -155,6 +155,7 @@ obj-$(CONFIG_PMIC_ADP5520)  += adp5520.o
 obj-$(CONFIG_MFD_KEMPLD)   += kempld-core.o
 obj-$(CONFIG_MFD_INTEL_QUARK_I2C_GPIO) += intel_quark_i2c_gpio.o
 obj-$(CONFIG_LPC_SCH)  += lpc_sch.o
+lpc_ich-objs   := lpc_ich-core.o
 obj-$(CONFIG_LPC_ICH)  += lpc_ich.o
 obj-$(CONFIG_MFD_RDC321X)  += rdc321x-southbridge.o
 obj-$(CONFIG_MFD_JANZ_CMODIO)  += janz-cmodio.o
diff --git a/drivers/mfd/lpc_ich.c b/drivers/mfd/lpc_ich-core.c
similarity index 100%
rename from drivers/mfd/lpc_ich.c
rename to drivers/mfd/lpc_ich-core.c
-- 
1.9.1

[PATCH v6 0/3] pinctrl/broxton: enable platform device in the absent of ACPI enumeration

2016-07-14 Thread Tan Jui Nee 
Hi,
The patches are to cater the need for non-ACPI system whereby
a platform device has to be created in order to bind with
Apollo Lake Pinctrl GPIO platform driver.

The MMIO BAR is accessed over the Primary to Sideband bridge
(P2SB). Since the BIOS prevents the P2SB device from being
enumerated by the PCI subsystem, so we need to hide/unhide P2SB
to lookup the P2SB BAR and pass the PCI BAR address to the gpio
platform driver.

All these three patches have dependencies on each other.

Changes in V6:
- Rename CONFIG_X86_INTEL_APL to CONFIG_X86_INTEL_IVI so that it
  relates to the actual product, as suggested by Mika.
- Rework Makefile according Andy's comments.
- Rename lpc_ich_misc() to lpc_ich_add_gpio() so that the name should 
not
  be so generic, as suggested by Andy.
- Call lpc_ich_add_gpio() via priv->chipset.
- lpc_ich_add_gpio() function will be moved from 
  .../include/linux/mfd/lpc_ich.h to
  .../drivers/mfd/lpc_ich-apl.h
  as this is a part of internal driver interface as suggested by Andy.
- Move enum lpc_chipsets from 
  .../drivers/mfd/lpc_ich-core.c to
  .../include/linux/mfd/lpc_ich.h
  as lpc_chipsets is also accessed by lpc_ich_add_gpio().
- Check if kasprintf return value for all 4 gpio controllers before
  proceed to add platform device by using mfd_add_devices().

Changes in V5:
- Split lpc-ich driver into two parts (lpc_ich-core and lpc_ich-apl).
  The file lpc_ich-apl.c introduces gpio platform driver in MFD.
- Rename Kconfig option CONFIG_X86_INTEL_NON_ACPI to 
CONFIG_X86_INTEL_APL
  so that it reflects actual product as suggested by Mika.
- The patch: 
  [PATCH] pinctrl/broxton: enable platform device in the absent of ACPI 
enumeration
  is removed in V5 patch-set as the patch is already applied in Linus' 
pinctrl tree.

Changes in V4:
- Move Kconfig option CONFIG_X86_INTEL_NON_ACPI from
  [PATCH 2/3] x86/platform/p2sb: New Primary to Sideband bridge support 
driver for Intel SOC's
  to
  [PATCH 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO 
pinctrl in non-ACPI system
  since the config is used in latter patch.
- Select CONFIG_P2SB when CONFIG_LPC_ICH is enabled.
- Remove #ifdef CONFIG_X86_INTEL_NON_ACPI and use
  #if defined(CONFIG_X86_INTEL_NON_ACPI) when lpc_ich_misc is called
  as suggested by Lee Jones.
- Use single dimensional array instead of 2D array for apl_gpio_io_res
  structure and use DEFINE_RES_IRQ for its IRQ resource.

Changes in V3:
- Simplify register addresses calculation and use DEFINE_RES_MEM_NAMED
  defines for apl_gpio_io_res structure
- Define magic number for P2SB PCI ID
- Replace switch-case with if-else since currently we have only one
  use case
- Only call mfd_add_devices() once for all gpio communities

Changes in V2:
- Add new config option CONFIG_X86_INTEL_NON_ACPI and "select PINCTRL"
  to fix kbuildbot error

Andy Shevchenko (1):
  x86/platform/p2sb: New Primary to Sideband bridge support driver for
Intel SOC's

Tan Jui Nee (2):
  mfd: lpc_ich: Rename lpc-ich driver
  mfd: lpc_ich: Add support for Intel Apollo Lake GPIO pinctrl in
non-ACPI system

 arch/x86/Kconfig  |  13 +++
 arch/x86/include/asm/p2sb.h   |  27 +++
 arch/x86/platform/intel/Makefile  |   1 +
 arch/x86/platform/intel/p2sb.c|  99 +++
 drivers/mfd/Kconfig   |   3 +-
 drivers/mfd/Makefile  |   4 +
 drivers/mfd/lpc_ich-apl.c | 130 ++
 drivers/mfd/lpc_ich-apl.h |  28 +++
 drivers/mfd/{lpc_ich.c => lpc_ich-core.c} |  81 +++
 include/linux/mfd/lpc_ich.h   |  73 +
 10 files changed, 387 insertions(+), 72 deletions(-)
 create mode 100644 arch/x86/include/asm/p2sb.h
 create mode 100644 arch/x86/platform/intel/p2sb.c
 create mode 100644 drivers/mfd/lpc_ich-apl.c
 create mode 100644 drivers/mfd/lpc_ich-apl.h
 rename drivers/mfd/{lpc_ich.c => lpc_ich-core.c} (94%)

-- 
1.9.1

[PATCH v6 0/3] pinctrl/broxton: enable platform device in the absent of ACPI enumeration

2016-07-14 Thread Tan Jui Nee 
Hi,
The patches are to cater the need for non-ACPI system whereby
a platform device has to be created in order to bind with
Apollo Lake Pinctrl GPIO platform driver.

The MMIO BAR is accessed over the Primary to Sideband bridge
(P2SB). Since the BIOS prevents the P2SB device from being
enumerated by the PCI subsystem, so we need to hide/unhide P2SB
to lookup the P2SB BAR and pass the PCI BAR address to the gpio
platform driver.

All these three patches have dependencies on each other.

Changes in V6:
- Rename CONFIG_X86_INTEL_APL to CONFIG_X86_INTEL_IVI so that it
  relates to the actual product, as suggested by Mika.
- Rework Makefile according Andy's comments.
- Rename lpc_ich_misc() to lpc_ich_add_gpio() so that the name should 
not
  be so generic, as suggested by Andy.
- Call lpc_ich_add_gpio() via priv->chipset.
- lpc_ich_add_gpio() function will be moved from 
  .../include/linux/mfd/lpc_ich.h to
  .../drivers/mfd/lpc_ich-apl.h
  as this is a part of internal driver interface as suggested by Andy.
- Move enum lpc_chipsets from 
  .../drivers/mfd/lpc_ich-core.c to
  .../include/linux/mfd/lpc_ich.h
  as lpc_chipsets is also accessed by lpc_ich_add_gpio().
- Check if kasprintf return value for all 4 gpio controllers before
  proceed to add platform device by using mfd_add_devices().

Changes in V5:
- Split lpc-ich driver into two parts (lpc_ich-core and lpc_ich-apl).
  The file lpc_ich-apl.c introduces gpio platform driver in MFD.
- Rename Kconfig option CONFIG_X86_INTEL_NON_ACPI to 
CONFIG_X86_INTEL_APL
  so that it reflects actual product as suggested by Mika.
- The patch: 
  [PATCH] pinctrl/broxton: enable platform device in the absent of ACPI 
enumeration
  is removed in V5 patch-set as the patch is already applied in Linus' 
pinctrl tree.

Changes in V4:
- Move Kconfig option CONFIG_X86_INTEL_NON_ACPI from
  [PATCH 2/3] x86/platform/p2sb: New Primary to Sideband bridge support 
driver for Intel SOC's
  to
  [PATCH 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO 
pinctrl in non-ACPI system
  since the config is used in latter patch.
- Select CONFIG_P2SB when CONFIG_LPC_ICH is enabled.
- Remove #ifdef CONFIG_X86_INTEL_NON_ACPI and use
  #if defined(CONFIG_X86_INTEL_NON_ACPI) when lpc_ich_misc is called
  as suggested by Lee Jones.
- Use single dimensional array instead of 2D array for apl_gpio_io_res
  structure and use DEFINE_RES_IRQ for its IRQ resource.

Changes in V3:
- Simplify register addresses calculation and use DEFINE_RES_MEM_NAMED
  defines for apl_gpio_io_res structure
- Define magic number for P2SB PCI ID
- Replace switch-case with if-else since currently we have only one
  use case
- Only call mfd_add_devices() once for all gpio communities

Changes in V2:
- Add new config option CONFIG_X86_INTEL_NON_ACPI and "select PINCTRL"
  to fix kbuildbot error

Andy Shevchenko (1):
  x86/platform/p2sb: New Primary to Sideband bridge support driver for
Intel SOC's

Tan Jui Nee (2):
  mfd: lpc_ich: Rename lpc-ich driver
  mfd: lpc_ich: Add support for Intel Apollo Lake GPIO pinctrl in
non-ACPI system

 arch/x86/Kconfig  |  13 +++
 arch/x86/include/asm/p2sb.h   |  27 +++
 arch/x86/platform/intel/Makefile  |   1 +
 arch/x86/platform/intel/p2sb.c|  99 +++
 drivers/mfd/Kconfig   |   3 +-
 drivers/mfd/Makefile  |   4 +
 drivers/mfd/lpc_ich-apl.c | 130 ++
 drivers/mfd/lpc_ich-apl.h |  28 +++
 drivers/mfd/{lpc_ich.c => lpc_ich-core.c} |  81 +++
 include/linux/mfd/lpc_ich.h   |  73 +
 10 files changed, 387 insertions(+), 72 deletions(-)
 create mode 100644 arch/x86/include/asm/p2sb.h
 create mode 100644 arch/x86/platform/intel/p2sb.c
 create mode 100644 drivers/mfd/lpc_ich-apl.c
 create mode 100644 drivers/mfd/lpc_ich-apl.h
 rename drivers/mfd/{lpc_ich.c => lpc_ich-core.c} (94%)

-- 
1.9.1

RE: [PATCH v5 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO pinctrl in non-ACPI system

2016-07-14 Thread Tan, Jui Nee 


> -Original Message-
> From: Lee Jones [mailto:lee.jo...@linaro.org]
> Sent: Tuesday, June 28, 2016 5:15 PM
> To: Andy Shevchenko <andy.shevche...@gmail.com>
> Cc: Tan, Jui Nee <jui.nee@intel.com>; Mika Westerberg
> <mika.westerb...@linux.intel.com>; Krogerus, Heikki
> <heikki.kroge...@linux.intel.com>; Andy Shevchenko
> <andriy.shevche...@linux.intel.com>; Thomas Gleixner
> <t...@linutronix.de>; Ingo Molnar <mi...@redhat.com>; H. Peter Anvin
> <h...@zytor.com>; x...@kernel.org; pty...@xes-inc.com; Linus Walleij
> <linus.wall...@linaro.org>; linux-g...@vger.kernel.org; linux-
> ker...@vger.kernel.org; Yong, Jonathan <jonathan.y...@intel.com>; Yu,
> Ong Hock <ong.hock...@intel.com>; Voon, Weifeng
> <weifeng.v...@intel.com>; Wan Mohamad, Wan Ahmad Zainie
> <wan.ahmad.zainie.wan.moha...@intel.com>
> Subject: Re: [PATCH v5 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake
> GPIO pinctrl in non-ACPI system
> 
> On Tue, 28 Jun 2016, Andy Shevchenko wrote:
> 
> > On Tue, Jun 28, 2016 at 10:56 AM, Tan Jui Nee <jui.nee@intel.com>
> wrote:
> > > This driver uses the P2SB hide/unhide mechanism cooperatively to
> > > pass the PCI BAR address to the gpio platform driver.
> >
> > > --- a/drivers/mfd/Kconfig
> > > +++ b/drivers/mfd/Kconfig
> > > @@ -369,8 +369,9 @@ config MFD_INTEL_QUARK_I2C_GPIO
> > >
> > >  config LPC_ICH
> > > tristate "Intel ICH LPC"
> > > -   depends on PCI
> > > +   depends on X86 && PCI
> >
> > This might deserve to be a separate change. Lee, what is your opinion?
> 
> I have no strong opinion.  Keep it in if you like.
> 
> [...]
> 
> > > @@ -155,7 +155,7 @@ obj-$(CONFIG_PMIC_ADP5520)  += adp5520.o
> > >  obj-$(CONFIG_MFD_KEMPLD)   += kempld-core.o
> > >  obj-$(CONFIG_MFD_INTEL_QUARK_I2C_GPIO) +=
> intel_quark_i2c_gpio.o
> > >  obj-$(CONFIG_LPC_SCH)  += lpc_sch.o
> >
> > > -lpc_ich-objs   := lpc_ich-core.o
> > > +lpc_ich-objs   := lpc_ich-core.o lpc_ich-apl.o
> > >  obj-$(CONFIG_LPC_ICH)  += lpc_ich.o
> >
> > I don't know if there is any requirement, but what I see in other
> > Makefiles is
> >
> > obj-$(CONFIG_DRV_OPTION) = drv_name.o
> > drv_name-objs := main.o aux1.o
> 
> Yes, this is nicer.
> 
> > Perhaps you may do the same.
> 
Thanks for your comment. The changes will be applied in next patch-set.
> > > +++ b/drivers/mfd/lpc_ich-apl.c
> > > @@ -0,0 +1,126 @@
> > > +/*
> > > + * Purpose: Create a platform device to bind with Intel Apollo Lake
> > > + * Pinctrl GPIO platform driver
> > > + * Copyright (C) 2016 Intel Corporation
> > > + *
> > > + * This program is free software; you can redistribute it and/or
> > > +modify
> > > + * it under the terms of the GNU General Public License version 2
> > > +as
> > > + * published by the Free Software Foundation.
> > > + */
> > > +
> > > +#include 
> > > +#include 
> > > +#include 
> > > +#include 
> > > +
> >
> > > +#if defined(CONFIG_X86_INTEL_APL)
> 
> I'm not accepting this kind of #ifery in *.c files.
> 
> > And why you can't use
> >
> > ifeq ($(CONFIG_...,y))
> > lpc_ich-objs += ...
> > endif
> >
> > in the Makefile?
> 
> [...]
> 
Applied with Andy's suggestion and #ifery in *.c files will be removed in
next patch-set.
> > > +int lpc_ich_misc(struct pci_dev *dev) {
> > > +   unsigned int apl_p2sb = PCI_DEVFN(PCI_IDSEL_P2SB, 0);
> > > +   unsigned int i;
> > > +   int ret;
> > > +
> > > +   /*
> > > +* Apollo lake, has not 1, but 4 gpio controllers,
> > > +* handle it a bit differently.
> > > +*/
> > > +
> > > +   for (i = 0; i < ARRAY_SIZE(apl_gpio_io_res)-1; i++) {
> > > +   struct resource *res = _gpio_io_res[i];
> > > +
> > > +   apl_gpio_devices[i].resources = res;
> > > +
> > > +   /* Fill MEM resource */
> > > +   ret = p2sb_bar(dev, apl_p2sb, res++);
> > > +   if (ret)
> > > +   goto warn_continue;
> > > +
> > > +   apl_pinctrl_pdata.name = kasprintf(GFP_KERNEL, "%u",
> > > +   i + 1);
> > > +   }
> > > +
> > > +

RE: [PATCH v5 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO pinctrl in non-ACPI system

2016-07-14 Thread Tan, Jui Nee 


> -Original Message-
> From: Lee Jones [mailto:lee.jo...@linaro.org]
> Sent: Tuesday, June 28, 2016 5:15 PM
> To: Andy Shevchenko 
> Cc: Tan, Jui Nee ; Mika Westerberg
> ; Krogerus, Heikki
> ; Andy Shevchenko
> ; Thomas Gleixner
> ; Ingo Molnar ; H. Peter Anvin
> ; x...@kernel.org; pty...@xes-inc.com; Linus Walleij
> ; linux-g...@vger.kernel.org; linux-
> ker...@vger.kernel.org; Yong, Jonathan ; Yu,
> Ong Hock ; Voon, Weifeng
> ; Wan Mohamad, Wan Ahmad Zainie
> 
> Subject: Re: [PATCH v5 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake
> GPIO pinctrl in non-ACPI system
> 
> On Tue, 28 Jun 2016, Andy Shevchenko wrote:
> 
> > On Tue, Jun 28, 2016 at 10:56 AM, Tan Jui Nee 
> wrote:
> > > This driver uses the P2SB hide/unhide mechanism cooperatively to
> > > pass the PCI BAR address to the gpio platform driver.
> >
> > > --- a/drivers/mfd/Kconfig
> > > +++ b/drivers/mfd/Kconfig
> > > @@ -369,8 +369,9 @@ config MFD_INTEL_QUARK_I2C_GPIO
> > >
> > >  config LPC_ICH
> > > tristate "Intel ICH LPC"
> > > -   depends on PCI
> > > +   depends on X86 && PCI
> >
> > This might deserve to be a separate change. Lee, what is your opinion?
> 
> I have no strong opinion.  Keep it in if you like.
> 
> [...]
> 
> > > @@ -155,7 +155,7 @@ obj-$(CONFIG_PMIC_ADP5520)  += adp5520.o
> > >  obj-$(CONFIG_MFD_KEMPLD)   += kempld-core.o
> > >  obj-$(CONFIG_MFD_INTEL_QUARK_I2C_GPIO) +=
> intel_quark_i2c_gpio.o
> > >  obj-$(CONFIG_LPC_SCH)  += lpc_sch.o
> >
> > > -lpc_ich-objs   := lpc_ich-core.o
> > > +lpc_ich-objs   := lpc_ich-core.o lpc_ich-apl.o
> > >  obj-$(CONFIG_LPC_ICH)  += lpc_ich.o
> >
> > I don't know if there is any requirement, but what I see in other
> > Makefiles is
> >
> > obj-$(CONFIG_DRV_OPTION) = drv_name.o
> > drv_name-objs := main.o aux1.o
> 
> Yes, this is nicer.
> 
> > Perhaps you may do the same.
> 
Thanks for your comment. The changes will be applied in next patch-set.
> > > +++ b/drivers/mfd/lpc_ich-apl.c
> > > @@ -0,0 +1,126 @@
> > > +/*
> > > + * Purpose: Create a platform device to bind with Intel Apollo Lake
> > > + * Pinctrl GPIO platform driver
> > > + * Copyright (C) 2016 Intel Corporation
> > > + *
> > > + * This program is free software; you can redistribute it and/or
> > > +modify
> > > + * it under the terms of the GNU General Public License version 2
> > > +as
> > > + * published by the Free Software Foundation.
> > > + */
> > > +
> > > +#include 
> > > +#include 
> > > +#include 
> > > +#include 
> > > +
> >
> > > +#if defined(CONFIG_X86_INTEL_APL)
> 
> I'm not accepting this kind of #ifery in *.c files.
> 
> > And why you can't use
> >
> > ifeq ($(CONFIG_...,y))
> > lpc_ich-objs += ...
> > endif
> >
> > in the Makefile?
> 
> [...]
> 
Applied with Andy's suggestion and #ifery in *.c files will be removed in
next patch-set.
> > > +int lpc_ich_misc(struct pci_dev *dev) {
> > > +   unsigned int apl_p2sb = PCI_DEVFN(PCI_IDSEL_P2SB, 0);
> > > +   unsigned int i;
> > > +   int ret;
> > > +
> > > +   /*
> > > +* Apollo lake, has not 1, but 4 gpio controllers,
> > > +* handle it a bit differently.
> > > +*/
> > > +
> > > +   for (i = 0; i < ARRAY_SIZE(apl_gpio_io_res)-1; i++) {
> > > +   struct resource *res = _gpio_io_res[i];
> > > +
> > > +   apl_gpio_devices[i].resources = res;
> > > +
> > > +   /* Fill MEM resource */
> > > +   ret = p2sb_bar(dev, apl_p2sb, res++);
> > > +   if (ret)
> > > +   goto warn_continue;
> > > +
> > > +   apl_pinctrl_pdata.name = kasprintf(GFP_KERNEL, "%u",
> > > +   i + 1);
> > > +   }
> > > +
> > > +   if (apl_pinctrl_pdata.name)
> > > +   ret = mfd_add_devices(>dev, apl_gpio_devices->id,
> > > +   apl_gpio_devices, ARRAY_SIZE(apl_gpio_devices),
> > > +   NULL, 0, NULL);
> > > +   else
> > > +   ret = -ENOMEM;
> > > +
> > > +warn_continue:
> > > +   if (ret)
> > > +

[PATCH v5 2/3] mfd: lpc_ich: Prepare to split lpc-ich driver

2016-06-28 Thread Tan Jui Nee 
This patch follows the example of mfd/wm831x and splits it into an
interface independent core since it is growing quite fast with
many table entries.

Signed-off-by: Tan Jui Nee <jui.nee@intel.com>
---
 drivers/mfd/Makefile   |1 +
 drivers/mfd/lpc_ich-core.c | 1126 
 drivers/mfd/lpc_ich.c  | 1126 
 3 files changed, 1127 insertions(+), 1126 deletions(-)
 create mode 100644 drivers/mfd/lpc_ich-core.c
 delete mode 100644 drivers/mfd/lpc_ich.c

diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 42a66e1..1dfe5fb 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -155,6 +155,7 @@ obj-$(CONFIG_PMIC_ADP5520)  += adp5520.o
 obj-$(CONFIG_MFD_KEMPLD)   += kempld-core.o
 obj-$(CONFIG_MFD_INTEL_QUARK_I2C_GPIO) += intel_quark_i2c_gpio.o
 obj-$(CONFIG_LPC_SCH)  += lpc_sch.o
+lpc_ich-objs   := lpc_ich-core.o
 obj-$(CONFIG_LPC_ICH)  += lpc_ich.o
 obj-$(CONFIG_MFD_RDC321X)  += rdc321x-southbridge.o
 obj-$(CONFIG_MFD_JANZ_CMODIO)  += janz-cmodio.o
diff --git a/drivers/mfd/lpc_ich-core.c b/drivers/mfd/lpc_ich-core.c
new file mode 100644
index 000..bd3aa45
--- /dev/null
+++ b/drivers/mfd/lpc_ich-core.c
@@ -0,0 +1,1126 @@
+/*
+ *  lpc_ich.c - LPC interface for Intel ICH
+ *
+ *  LPC bridge function of the Intel ICH contains many other
+ *  functional units, such as Interrupt controllers, Timers,
+ *  Power Management, System Management, GPIO, RTC, and LPC
+ *  Configuration Registers.
+ *
+ *  This driver is derived from lpc_sch.
+
+ *  Copyright (c) 2011 Extreme Engineering Solution, Inc.
+ *  Author: Aaron Sierra <asie...@xes-inc.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; see the file COPYING.  If not, write to
+ *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *  This driver supports the following I/O Controller hubs:
+ * (See the intel documentation on http://developer.intel.com.)
+ * document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
+ * document number 290687-002, 298242-027: 82801BA (ICH2)
+ * document number 290733-003, 290739-013: 82801CA (ICH3-S)
+ * document number 290716-001, 290718-007: 82801CAM (ICH3-M)
+ * document number 290744-001, 290745-025: 82801DB (ICH4)
+ * document number 252337-001, 252663-008: 82801DBM (ICH4-M)
+ * document number 273599-001, 273645-002: 82801E (C-ICH)
+ * document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
+ * document number 300641-004, 300884-013: 6300ESB
+ * document number 301473-002, 301474-026: 82801F (ICH6)
+ * document number 313082-001, 313075-006: 631xESB, 632xESB
+ * document number 307013-003, 307014-024: 82801G (ICH7)
+ * document number 322896-001, 322897-001: NM10
+ * document number 313056-003, 313057-017: 82801H (ICH8)
+ * document number 316972-004, 316973-012: 82801I (ICH9)
+ * document number 319973-002, 319974-002: 82801J (ICH10)
+ * document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
+ * document number 320066-003, 320257-008: EP80597 (IICH)
+ * document number 324645-001, 324646-001: Cougar Point (CPT)
+ * document number TBD : Patsburg (PBG)
+ * document number TBD : DH89xxCC
+ * document number TBD : Panther Point
+ * document number TBD : Lynx Point
+ * document number TBD : Lynx Point-LP
+ * document number TBD : Wellsburg
+ * document number TBD : Avoton SoC
+ * document number TBD : Coleto Creek
+ * document number TBD : Wildcat Point-LP
+ * document number TBD : 9 Series
+ * document number TBD : Lewisburg
+ */
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define ACPIBASE   0x40
+#define ACPIBASE_GPE_OFF   0x28
+#define ACPIBASE_GPE_END   0x2f
+#define ACPIBASE_SMI_OFF   0x30
+#define ACPIBASE_SMI_END   0x33
+#define ACPIBASE_PMC_OFF   0x08
+#define ACPIBASE_PMC_END   0x0c
+#define ACPIBASE_TCO_OFF   0x60
+#define ACPIBASE_TCO_END   0x7f
+#define ACPICTRL_PMCBASE   0x44
+
+#define ACPIBASE_GCS_OFF   0x3410
+#define ACPIBASE_GCS_END   0x3414
+
+#define GPIOBASE_ICH0  0x58
+#define GPIOCTRL_ICH0  0x5C
+#define GPIOBASE_ICH6  0x48
+#define GPIOCTRL_ICH6  0x4C
+
+#define RCBABASE

[PATCH v5 2/3] mfd: lpc_ich: Prepare to split lpc-ich driver

2016-06-28 Thread Tan Jui Nee 
This patch follows the example of mfd/wm831x and splits it into an
interface independent core since it is growing quite fast with
many table entries.

Signed-off-by: Tan Jui Nee 
---
 drivers/mfd/Makefile   |1 +
 drivers/mfd/lpc_ich-core.c | 1126 
 drivers/mfd/lpc_ich.c  | 1126 
 3 files changed, 1127 insertions(+), 1126 deletions(-)
 create mode 100644 drivers/mfd/lpc_ich-core.c
 delete mode 100644 drivers/mfd/lpc_ich.c

diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 42a66e1..1dfe5fb 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -155,6 +155,7 @@ obj-$(CONFIG_PMIC_ADP5520)  += adp5520.o
 obj-$(CONFIG_MFD_KEMPLD)   += kempld-core.o
 obj-$(CONFIG_MFD_INTEL_QUARK_I2C_GPIO) += intel_quark_i2c_gpio.o
 obj-$(CONFIG_LPC_SCH)  += lpc_sch.o
+lpc_ich-objs   := lpc_ich-core.o
 obj-$(CONFIG_LPC_ICH)  += lpc_ich.o
 obj-$(CONFIG_MFD_RDC321X)  += rdc321x-southbridge.o
 obj-$(CONFIG_MFD_JANZ_CMODIO)  += janz-cmodio.o
diff --git a/drivers/mfd/lpc_ich-core.c b/drivers/mfd/lpc_ich-core.c
new file mode 100644
index 000..bd3aa45
--- /dev/null
+++ b/drivers/mfd/lpc_ich-core.c
@@ -0,0 +1,1126 @@
+/*
+ *  lpc_ich.c - LPC interface for Intel ICH
+ *
+ *  LPC bridge function of the Intel ICH contains many other
+ *  functional units, such as Interrupt controllers, Timers,
+ *  Power Management, System Management, GPIO, RTC, and LPC
+ *  Configuration Registers.
+ *
+ *  This driver is derived from lpc_sch.
+
+ *  Copyright (c) 2011 Extreme Engineering Solution, Inc.
+ *  Author: Aaron Sierra 
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; see the file COPYING.  If not, write to
+ *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *  This driver supports the following I/O Controller hubs:
+ * (See the intel documentation on http://developer.intel.com.)
+ * document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
+ * document number 290687-002, 298242-027: 82801BA (ICH2)
+ * document number 290733-003, 290739-013: 82801CA (ICH3-S)
+ * document number 290716-001, 290718-007: 82801CAM (ICH3-M)
+ * document number 290744-001, 290745-025: 82801DB (ICH4)
+ * document number 252337-001, 252663-008: 82801DBM (ICH4-M)
+ * document number 273599-001, 273645-002: 82801E (C-ICH)
+ * document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
+ * document number 300641-004, 300884-013: 6300ESB
+ * document number 301473-002, 301474-026: 82801F (ICH6)
+ * document number 313082-001, 313075-006: 631xESB, 632xESB
+ * document number 307013-003, 307014-024: 82801G (ICH7)
+ * document number 322896-001, 322897-001: NM10
+ * document number 313056-003, 313057-017: 82801H (ICH8)
+ * document number 316972-004, 316973-012: 82801I (ICH9)
+ * document number 319973-002, 319974-002: 82801J (ICH10)
+ * document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
+ * document number 320066-003, 320257-008: EP80597 (IICH)
+ * document number 324645-001, 324646-001: Cougar Point (CPT)
+ * document number TBD : Patsburg (PBG)
+ * document number TBD : DH89xxCC
+ * document number TBD : Panther Point
+ * document number TBD : Lynx Point
+ * document number TBD : Lynx Point-LP
+ * document number TBD : Wellsburg
+ * document number TBD : Avoton SoC
+ * document number TBD : Coleto Creek
+ * document number TBD : Wildcat Point-LP
+ * document number TBD : 9 Series
+ * document number TBD : Lewisburg
+ */
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define ACPIBASE   0x40
+#define ACPIBASE_GPE_OFF   0x28
+#define ACPIBASE_GPE_END   0x2f
+#define ACPIBASE_SMI_OFF   0x30
+#define ACPIBASE_SMI_END   0x33
+#define ACPIBASE_PMC_OFF   0x08
+#define ACPIBASE_PMC_END   0x0c
+#define ACPIBASE_TCO_OFF   0x60
+#define ACPIBASE_TCO_END   0x7f
+#define ACPICTRL_PMCBASE   0x44
+
+#define ACPIBASE_GCS_OFF   0x3410
+#define ACPIBASE_GCS_END   0x3414
+
+#define GPIOBASE_ICH0  0x58
+#define GPIOCTRL_ICH0  0x5C
+#define GPIOBASE_ICH6  0x48
+#define GPIOCTRL_ICH6  0x4C
+
+#define RCBABASE   0xf0
+
+#define wdt_io_res(i) wdt_res(0, i

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