Re: [PATCH 2/2] mfd: sec: Add support for S2MPS15 PMIC

[Thomas Abraham]

On Tue, Oct 14, 2014 at 2:11 PM, Krzysztof Kozłowski
 wrote:
> On 14.10.2014 10:14, Thomas Abraham wrote:
>> Add support for S2MPS15 PMIC which is similar to S2MPS11 PMIC. The S2MPS15
>> PMIC supports 27 LDO regulators, 10 buck regulators, RTC, three 32.768KHz
>> clock outputs and battery charger. This patch adds initial support for
>> LDO and buck regulators of S2MPS15 device.
>>
>> Signed-off-by: Thomas Abraham 
>
> Quite nice and small diff stat for adding new chip support. Looks good.
> I assume that RTC/clock will be handled in later submissions.

Yes, it will be posted later after testing these features.

>
> Reviewed-by: Krzysztof Kozlowski 

Thanks!

Regards,
Thomas.

>
> Best regards,
> Krzysztof
>
>> ---
>>  drivers/mfd/sec-core.c  |   26 ++
>>  include/linux/mfd/samsung/core.h|1 +
>>  include/linux/mfd/samsung/s2mps15.h |  161 
>> +++
>>  3 files changed, 188 insertions(+), 0 deletions(-)
>>  create mode 100644 include/linux/mfd/samsung/s2mps15.h
>>
>> diff --git a/drivers/mfd/sec-core.c b/drivers/mfd/sec-core.c
>> index dba7e2b..6f33c2b 100644
>> --- a/drivers/mfd/sec-core.c
>> +++ b/drivers/mfd/sec-core.c
>> @@ -28,6 +28,7 @@
>>  #include 
>>  #include 
>>  #include 
>> +#include 
>>  #include 
>>  #include 
>>  #include 
>> @@ -85,6 +86,12 @@ static const struct mfd_cell s2mps14_devs[] = {
>>   }
>>  };
>>
>> +static const struct mfd_cell s2mps15_devs[] = {
>> + {
>> + .name = "s2mps15-pmic",
>> + },
>> +};
>> +
>>  static const struct mfd_cell s2mpa01_devs[] = {
>>   {
>>   .name = "s2mpa01-pmic",
>> @@ -111,6 +118,9 @@ static const struct of_device_id sec_dt_match[] = {
>>   .compatible = "samsung,s2mps14-pmic",
>>   .data = (void *)S2MPS14X,
>>   }, {
>> + .compatible = "samsung,s2mps15-pmic",
>> + .data = (void *)S2MPS15X,
>> + }, {
>>   .compatible = "samsung,s2mpa01-pmic",
>>   .data = (void *)S2MPA01,
>>   }, {
>> @@ -203,6 +213,15 @@ static const struct regmap_config s2mps14_regmap_config 
>> = {
>>   .cache_type = REGCACHE_FLAT,
>>  };
>>
>> +static const struct regmap_config s2mps15_regmap_config = {
>> + .reg_bits = 8,
>> + .val_bits = 8,
>> +
>> + .max_register = S2MPS15_REG_LDODSCH4,
>> + .volatile_reg = s2mps11_volatile,
>> + .cache_type = REGCACHE_FLAT,
>> +};
>> +
>>  static const struct regmap_config s2mpu02_regmap_config = {
>>   .reg_bits = 8,
>>   .val_bits = 8,
>> @@ -328,6 +347,9 @@ static int sec_pmic_probe(struct i2c_client *i2c,
>>   case S2MPS14X:
>>   regmap = _regmap_config;
>>   break;
>> + case S2MPS15X:
>> + regmap = _regmap_config;
>> + break;
>>   case S5M8763X:
>>   regmap = _regmap_config;
>>   break;
>> @@ -382,6 +404,10 @@ static int sec_pmic_probe(struct i2c_client *i2c,
>>   sec_devs = s2mps14_devs;
>>   num_sec_devs = ARRAY_SIZE(s2mps14_devs);
>>   break;
>> + case S2MPS15X:
>> + sec_devs = s2mps15_devs;
>> + num_sec_devs = ARRAY_SIZE(s2mps15_devs);
>> + break;
>>   case S2MPU02:
>>   sec_devs = s2mpu02_devs;
>>   num_sec_devs = ARRAY_SIZE(s2mpu02_devs);
>> diff --git a/include/linux/mfd/samsung/core.h 
>> b/include/linux/mfd/samsung/core.h
>> index 1825eda..49ef612 100644
>> --- a/include/linux/mfd/samsung/core.h
>> +++ b/include/linux/mfd/samsung/core.h
>> @@ -42,6 +42,7 @@ enum sec_device_type {
>>   S2MPA01,
>>   S2MPS11X,
>>   S2MPS14X,
>> + S2MPS15X,
>>   S2MPU02,
>>  };
>>
>> diff --git a/include/linux/mfd/samsung/s2mps15.h 
>> b/include/linux/mfd/samsung/s2mps15.h
>> new file mode 100644
>> index 000..e82549a
>> --- /dev/null
>> +++ b/include/linux/mfd/samsung/s2mps15.h
>> @@ -0,0 +1,161 @@
>> +/*
>> + * s2mps15.h
>> + *
>> + * Copyright (c) 2014 Samsung Electronics Co., Ltd
>> + *  http://www.samsung.com
>> + *
>> + * This program is free software; you can redistribute  it and/or modify it
>> + * under  the terms of  the GNU General  Public

Re: [PATCH 1/2] dt-bindings: mfd: s2mps11: add documentation for s2mps15 PMIC

[Thomas Abraham]

On Tue, Oct 14, 2014 at 2:13 PM, Krzysztof Kozłowski
 wrote:
> On 14.10.2014 10:14, Thomas Abraham wrote:
>> Add dt-binding documentation for s2mps15 PMIC device. The s2mps15 device
>> is similar to s2mps11/14 PMIC device and has 27 LDO and 10 buck regulators.
>>
>> Cc: devicet...@vger.kernel.org
>> Signed-off-by: Thomas Abraham 
>> ---
>>  Documentation/devicetree/bindings/mfd/s2mps11.txt |   11 ---
>>  1 files changed, 8 insertions(+), 3 deletions(-)
>
> Looks good.
> Reviewed-by: Krzysztof Kozlowski 
>
> P.S. Wrong devicetree-disc...@lists.ozlabs.org list? I receive bounces.

Yes, that was wrong. Thanks for correcting it.

Regards,
Thomas.

>
> Best regards,
> Krzysztof
>
>
>>
>> diff --git a/Documentation/devicetree/bindings/mfd/s2mps11.txt 
>> b/Documentation/devicetree/bindings/mfd/s2mps11.txt
>> index 0e4026a..41ee3f5 100644
>> --- a/Documentation/devicetree/bindings/mfd/s2mps11.txt
>> +++ b/Documentation/devicetree/bindings/mfd/s2mps11.txt
>> @@ -1,5 +1,5 @@
>>
>> -* Samsung S2MPS11, S2MPS14 and S2MPU02 Voltage and Current Regulator
>> +* Samsung S2MPS11/14/15 and S2MPU02 Voltage and Current Regulator
>>
>>  The Samsung S2MPS11 is a multi-function device which includes voltage and
>>  current regulators, RTC, charger controller and other sub-blocks. It is
>> @@ -7,8 +7,11 @@ interfaced to the host controller using an I2C interface. 
>> Each sub-block is
>>  addressed by the host system using different I2C slave addresses.
>>
>>  Required properties:
>> -- compatible: Should be "samsung,s2mps11-pmic" or "samsung,s2mps14-pmic"
>> -  or "samsung,s2mpu02-pmic".
>> +- compatible: Should be one of the following
>> + - "samsung,s2mps11-pmic"
>> + - "samsung,s2mps14-pmic"
>> + - "samsung,s2mps15-pmic"
>> + - "samsung,s2mpu02-pmic"
>>  - reg: Specifies the I2C slave address of the pmic block. It should be 0x66.
>>
>>  Optional properties:
>> @@ -82,12 +85,14 @@ as per the datasheet of s2mps11.
>> - valid values for n are:
>>   - S2MPS11: 1 to 38
>>   - S2MPS14: 1 to 25
>> + - S2MPS15: 1 to 27
>>   - S2MPU02: 1 to 28
>> - Example: LDO1, LDO2, LDO28
>>   - BUCKn
>> - valid values for n are:
>>   - S2MPS11: 1 to 10
>>   - S2MPS14: 1 to 5
>> + - S2MPS15: 1 to 10
>>   - S2MPU02: 1 to 7
>> - Example: BUCK1, BUCK2, BUCK9
>>
>>
>
> --
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Re: [PATCH] regulator: s2mps11: add support for S2MPS15 regulators

[Thomas Abraham]

On Tue, Oct 14, 2014 at 2:18 PM, Krzysztof Kozłowski
 wrote:
> On 14.10.2014 10:17, Thomas Abraham wrote:
>> The S2MPS15 PMIC is similar in functionality to S2MPS11/14 PMIC. It contains
>> 27 LDO and 10 Buck regulators and allows programming these regulators via a
>> I2C interface. This patch adds initial support for LDO/Buck regulators of
>> S2MPS15 PMIC.
>>
>> Signed-off-by: Thomas Abraham 
>
> Just two questions/ideas:
> 1. No specific steps for suspend?

Yes, it is required but I have not tested it yet. I will post the
suspend related changes when it has been tested.

> 2. Maybe add S2MPS15 to MODULE_DESCRIPTION and Kconfig?

Okay, I will do that along in the next set of update patches for s2mps15.

>
> Anyway rest looks fine.
> Reviewed-by: Krzysztof Kozlowski 

Thanks Krzysztof.

Regards,
Thomas.

>
> Best regards,
> Krzysztof
>
>> ---
>>  drivers/regulator/s2mps11.c |  133 
>> +++
>>  1 files changed, 133 insertions(+), 0 deletions(-)
>>
>> diff --git a/drivers/regulator/s2mps11.c b/drivers/regulator/s2mps11.c
>> index adab82d..e176fbb 100644
>> --- a/drivers/regulator/s2mps11.c
>> +++ b/drivers/regulator/s2mps11.c
>> @@ -31,6 +31,7 @@
>>  #include 
>>  #include 
>>  #include 
>> +#include 
>>  #include 
>>
>>  struct s2mps11_info {
>> @@ -529,6 +530,133 @@ static const struct regulator_desc 
>> s2mps14_regulators[] = {
>>   regulator_desc_s2mps14_buck(5, MIN_600_MV, STEP_6_25_MV),
>>  };
>>
>> +static struct regulator_ops s2mps15_reg_ldo_ops = {
>> + .list_voltage   = regulator_list_voltage_linear_range,
>> + .map_voltage= regulator_map_voltage_linear_range,
>> + .is_enabled = regulator_is_enabled_regmap,
>> + .enable = regulator_enable_regmap,
>> + .disable= regulator_disable_regmap,
>> + .get_voltage_sel= regulator_get_voltage_sel_regmap,
>> + .set_voltage_sel= regulator_set_voltage_sel_regmap,
>> +};
>> +
>> +static struct regulator_ops s2mps15_reg_buck_ops = {
>> + .list_voltage   = regulator_list_voltage_linear_range,
>> + .map_voltage= regulator_map_voltage_linear_range,
>> + .is_enabled = regulator_is_enabled_regmap,
>> + .enable = regulator_enable_regmap,
>> + .disable= regulator_disable_regmap,
>> + .get_voltage_sel= regulator_get_voltage_sel_regmap,
>> + .set_voltage_sel= regulator_set_voltage_sel_regmap,
>> + .set_voltage_time_sel   = regulator_set_voltage_time_sel,
>> +};
>> +
>> +#define regulator_desc_s2mps15_ldo(num, range) { \
>> + .name   = "LDO"#num,\
>> + .id = S2MPS15_LDO##num, \
>> + .ops= _reg_ldo_ops, \
>> + .type   = REGULATOR_VOLTAGE,\
>> + .owner  = THIS_MODULE,  \
>> + .linear_ranges  = range,\
>> + .n_linear_ranges = ARRAY_SIZE(range),   \
>> + .n_voltages = S2MPS15_LDO_N_VOLTAGES,   \
>> + .vsel_reg   = S2MPS15_REG_L1CTRL + num - 1, \
>> + .vsel_mask  = S2MPS15_LDO_VSEL_MASK,\
>> + .enable_reg = S2MPS15_REG_L1CTRL + num - 1, \
>> + .enable_mask= S2MPS15_ENABLE_MASK   \
>> +}
>> +
>> +#define regulator_desc_s2mps15_buck(num, range) {\
>> + .name   = "BUCK"#num,   \
>> + .id = S2MPS15_BUCK##num,\
>> + .ops= _reg_buck_ops,\
>> + .type   = REGULATOR_VOLTAGE,\
>> + .owner  = THIS_MODULE,  \
>> + .linear_ranges  = range,\
>> + .n_linear_ranges = ARRAY_SIZE(range),   \
>> + .ramp_delay = 12500,\
>> + .n_voltages = S2MPS15_BUCK_N_VOLTAGES,  \
>> + .vsel_reg   = S2MPS15_REG_B1CTRL2 + ((num - 1) * 2),\
>> + .vsel_mask  = S2MPS15_BUCK_VSEL_MASK,   \
>> + .enable_reg = S2MPS15_REG_B1CTRL1 + ((num - 1) * 2),\
>> + .enable_mask= S2MPS14_ENABLE_MASK   \
>> +}
>> +
>> +/* voltage rang

[PATCH] regulator: s2mps11: add support for S2MPS15 regulators

[Thomas Abraham]

The S2MPS15 PMIC is similar in functionality to S2MPS11/14 PMIC. It contains
27 LDO and 10 Buck regulators and allows programming these regulators via a
I2C interface. This patch adds initial support for LDO/Buck regulators of
S2MPS15 PMIC.

Signed-off-by: Thomas Abraham 
---
 drivers/regulator/s2mps11.c |  133 +++
 1 files changed, 133 insertions(+), 0 deletions(-)

diff --git a/drivers/regulator/s2mps11.c b/drivers/regulator/s2mps11.c
index adab82d..e176fbb 100644
--- a/drivers/regulator/s2mps11.c
+++ b/drivers/regulator/s2mps11.c
@@ -31,6 +31,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 struct s2mps11_info {
@@ -529,6 +530,133 @@ static const struct regulator_desc s2mps14_regulators[] = 
{
regulator_desc_s2mps14_buck(5, MIN_600_MV, STEP_6_25_MV),
 };
 
+static struct regulator_ops s2mps15_reg_ldo_ops = {
+   .list_voltage   = regulator_list_voltage_linear_range,
+   .map_voltage= regulator_map_voltage_linear_range,
+   .is_enabled = regulator_is_enabled_regmap,
+   .enable = regulator_enable_regmap,
+   .disable= regulator_disable_regmap,
+   .get_voltage_sel= regulator_get_voltage_sel_regmap,
+   .set_voltage_sel= regulator_set_voltage_sel_regmap,
+};
+
+static struct regulator_ops s2mps15_reg_buck_ops = {
+   .list_voltage   = regulator_list_voltage_linear_range,
+   .map_voltage= regulator_map_voltage_linear_range,
+   .is_enabled = regulator_is_enabled_regmap,
+   .enable = regulator_enable_regmap,
+   .disable= regulator_disable_regmap,
+   .get_voltage_sel= regulator_get_voltage_sel_regmap,
+   .set_voltage_sel= regulator_set_voltage_sel_regmap,
+   .set_voltage_time_sel   = regulator_set_voltage_time_sel,
+};
+
+#define regulator_desc_s2mps15_ldo(num, range) {   \
+   .name   = "LDO"#num,\
+   .id = S2MPS15_LDO##num, \
+   .ops= _reg_ldo_ops, \
+   .type   = REGULATOR_VOLTAGE,\
+   .owner  = THIS_MODULE,  \
+   .linear_ranges  = range,\
+   .n_linear_ranges = ARRAY_SIZE(range),   \
+   .n_voltages = S2MPS15_LDO_N_VOLTAGES,   \
+   .vsel_reg   = S2MPS15_REG_L1CTRL + num - 1, \
+   .vsel_mask  = S2MPS15_LDO_VSEL_MASK,\
+   .enable_reg = S2MPS15_REG_L1CTRL + num - 1, \
+   .enable_mask= S2MPS15_ENABLE_MASK   \
+}
+
+#define regulator_desc_s2mps15_buck(num, range) {  \
+   .name   = "BUCK"#num,   \
+   .id = S2MPS15_BUCK##num,\
+   .ops= _reg_buck_ops,\
+   .type   = REGULATOR_VOLTAGE,\
+   .owner  = THIS_MODULE,  \
+   .linear_ranges  = range,\
+   .n_linear_ranges = ARRAY_SIZE(range),   \
+   .ramp_delay = 12500,\
+   .n_voltages = S2MPS15_BUCK_N_VOLTAGES,  \
+   .vsel_reg   = S2MPS15_REG_B1CTRL2 + ((num - 1) * 2),\
+   .vsel_mask  = S2MPS15_BUCK_VSEL_MASK,   \
+   .enable_reg = S2MPS15_REG_B1CTRL1 + ((num - 1) * 2),\
+   .enable_mask= S2MPS14_ENABLE_MASK   \
+}
+
+/* voltage range for s2mps15 LDO 3, 5, 15, 16, 18, 20, 23 and 27 */
+static const struct regulator_linear_range s2mps15_ldo_voltage_ranges1[] = {
+   REGULATOR_LINEAR_RANGE(100, 0xc, 0x38, 25000),
+};
+
+/* voltage range for s2mps15 LDO 2, 6, 14, 17, 19, 21, 24 and 25 */
+static const struct regulator_linear_range s2mps15_ldo_voltage_ranges2[] = {
+   REGULATOR_LINEAR_RANGE(180, 0x0, 0x3f, 25000),
+};
+
+/* voltage range for s2mps15 LDO 4, 11, 12, 13, 22 and 26 */
+static const struct regulator_linear_range s2mps15_ldo_voltage_ranges3[] = {
+   REGULATOR_LINEAR_RANGE(70, 0x0, 0x34, 12500),
+};
+
+/* voltage range for s2mps15 LDO 7, 8, 9 and 10 */
+static const struct regulator_linear_range s2mps15_ldo_voltage_ranges4[] = {
+   REGULATOR_LINEAR_RANGE(70, 0xc, 0x18, 25000),
+};
+
+/* voltage range for s2mps15 LDO 1 */
+static const struct regulator_linear_range s2mps15_ldo_voltage_ranges5[] = {
+   REGULATOR_LINEAR_RANGE(50, 0x0, 0x20, 12500),
+};
+
+/* voltage range for s2mps15 BUCK 1, 2, 3, 4, 5, 6 and 7 */
+static const struct regulator_linear_range s2mps15_buck_voltage_ranges1[] = {
+   REGULATOR_LINEAR_RANGE(50, 0x10, 0xb0, 6250),
+};
+
+/* voltage range for s2mps15 BUCK 8, 9 and 10 */

[PATCH 0/2] mfd: sec: add S2MPS15 PMIC support

[Thomas Abraham]

Samsung's S2MPS15 PMIC is targetted to be used with Samsung's Exynos7 SoC.
The S2MPS15 PMIC is similar in functionality to S2MPS11/14 PMIC. It contains
27 LDO and 10 Buck regulators, RTC, three 32.768 KHz clock outputs and allows
programming these blocks via a I2C interface. This patch series adds initial
support for LDO/Buck regulators of S2MPS15 PMIC.

Thomas Abraham (2):
  dt-bindings: mfd: s2mps11: add documentation for s2mps15 PMIC
  mfd: sec: Add support for S2MPS15 PMIC

 Documentation/devicetree/bindings/mfd/s2mps11.txt |   11 +-
 drivers/mfd/sec-core.c|   26 
 include/linux/mfd/samsung/core.h  |1 +
 include/linux/mfd/samsung/s2mps15.h   |  161 +
 4 files changed, 196 insertions(+), 3 deletions(-)
 create mode 100644 include/linux/mfd/samsung/s2mps15.h

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[PATCH 1/2] dt-bindings: mfd: s2mps11: add documentation for s2mps15 PMIC

[Thomas Abraham]

Add dt-binding documentation for s2mps15 PMIC device. The s2mps15 device
is similar to s2mps11/14 PMIC device and has 27 LDO and 10 buck regulators.

Cc: devicet...@vger.kernel.org
Signed-off-by: Thomas Abraham 
---
 Documentation/devicetree/bindings/mfd/s2mps11.txt |   11 ---
 1 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/mfd/s2mps11.txt 
b/Documentation/devicetree/bindings/mfd/s2mps11.txt
index 0e4026a..41ee3f5 100644
--- a/Documentation/devicetree/bindings/mfd/s2mps11.txt
+++ b/Documentation/devicetree/bindings/mfd/s2mps11.txt
@@ -1,5 +1,5 @@
 
-* Samsung S2MPS11, S2MPS14 and S2MPU02 Voltage and Current Regulator
+* Samsung S2MPS11/14/15 and S2MPU02 Voltage and Current Regulator
 
 The Samsung S2MPS11 is a multi-function device which includes voltage and
 current regulators, RTC, charger controller and other sub-blocks. It is
@@ -7,8 +7,11 @@ interfaced to the host controller using an I2C interface. Each 
sub-block is
 addressed by the host system using different I2C slave addresses.
 
 Required properties:
-- compatible: Should be "samsung,s2mps11-pmic" or "samsung,s2mps14-pmic"
-  or "samsung,s2mpu02-pmic".
+- compatible: Should be one of the following
+   - "samsung,s2mps11-pmic"
+   - "samsung,s2mps14-pmic"
+   - "samsung,s2mps15-pmic"
+   - "samsung,s2mpu02-pmic"
 - reg: Specifies the I2C slave address of the pmic block. It should be 0x66.
 
 Optional properties:
@@ -82,12 +85,14 @@ as per the datasheet of s2mps11.
  - valid values for n are:
- S2MPS11: 1 to 38
- S2MPS14: 1 to 25
+   - S2MPS15: 1 to 27
- S2MPU02: 1 to 28
  - Example: LDO1, LDO2, LDO28
- BUCKn
  - valid values for n are:
- S2MPS11: 1 to 10
- S2MPS14: 1 to 5
+   - S2MPS15: 1 to 10
- S2MPU02: 1 to 7
  - Example: BUCK1, BUCK2, BUCK9
 
-- 
1.6.6.rc2

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[PATCH 2/2] mfd: sec: Add support for S2MPS15 PMIC

[Thomas Abraham]

Add support for S2MPS15 PMIC which is similar to S2MPS11 PMIC. The S2MPS15
PMIC supports 27 LDO regulators, 10 buck regulators, RTC, three 32.768KHz
clock outputs and battery charger. This patch adds initial support for
LDO and buck regulators of S2MPS15 device.

Signed-off-by: Thomas Abraham 
---
 drivers/mfd/sec-core.c  |   26 ++
 include/linux/mfd/samsung/core.h|1 +
 include/linux/mfd/samsung/s2mps15.h |  161 +++
 3 files changed, 188 insertions(+), 0 deletions(-)
 create mode 100644 include/linux/mfd/samsung/s2mps15.h

diff --git a/drivers/mfd/sec-core.c b/drivers/mfd/sec-core.c
index dba7e2b..6f33c2b 100644
--- a/drivers/mfd/sec-core.c
+++ b/drivers/mfd/sec-core.c
@@ -28,6 +28,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -85,6 +86,12 @@ static const struct mfd_cell s2mps14_devs[] = {
}
 };
 
+static const struct mfd_cell s2mps15_devs[] = {
+   {
+   .name = "s2mps15-pmic",
+   },
+};
+
 static const struct mfd_cell s2mpa01_devs[] = {
{
.name = "s2mpa01-pmic",
@@ -111,6 +118,9 @@ static const struct of_device_id sec_dt_match[] = {
.compatible = "samsung,s2mps14-pmic",
.data = (void *)S2MPS14X,
}, {
+   .compatible = "samsung,s2mps15-pmic",
+   .data = (void *)S2MPS15X,
+   }, {
.compatible = "samsung,s2mpa01-pmic",
.data = (void *)S2MPA01,
}, {
@@ -203,6 +213,15 @@ static const struct regmap_config s2mps14_regmap_config = {
.cache_type = REGCACHE_FLAT,
 };
 
+static const struct regmap_config s2mps15_regmap_config = {
+   .reg_bits = 8,
+   .val_bits = 8,
+
+   .max_register = S2MPS15_REG_LDODSCH4,
+   .volatile_reg = s2mps11_volatile,
+   .cache_type = REGCACHE_FLAT,
+};
+
 static const struct regmap_config s2mpu02_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
@@ -328,6 +347,9 @@ static int sec_pmic_probe(struct i2c_client *i2c,
case S2MPS14X:
regmap = _regmap_config;
break;
+   case S2MPS15X:
+   regmap = _regmap_config;
+   break;
case S5M8763X:
regmap = _regmap_config;
break;
@@ -382,6 +404,10 @@ static int sec_pmic_probe(struct i2c_client *i2c,
sec_devs = s2mps14_devs;
num_sec_devs = ARRAY_SIZE(s2mps14_devs);
break;
+   case S2MPS15X:
+   sec_devs = s2mps15_devs;
+   num_sec_devs = ARRAY_SIZE(s2mps15_devs);
+   break;
case S2MPU02:
sec_devs = s2mpu02_devs;
num_sec_devs = ARRAY_SIZE(s2mpu02_devs);
diff --git a/include/linux/mfd/samsung/core.h b/include/linux/mfd/samsung/core.h
index 1825eda..49ef612 100644
--- a/include/linux/mfd/samsung/core.h
+++ b/include/linux/mfd/samsung/core.h
@@ -42,6 +42,7 @@ enum sec_device_type {
S2MPA01,
S2MPS11X,
S2MPS14X,
+   S2MPS15X,
S2MPU02,
 };
 
diff --git a/include/linux/mfd/samsung/s2mps15.h 
b/include/linux/mfd/samsung/s2mps15.h
new file mode 100644
index 000..e82549a
--- /dev/null
+++ b/include/linux/mfd/samsung/s2mps15.h
@@ -0,0 +1,161 @@
+/*
+ * s2mps15.h
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd
+ *  http://www.samsung.com
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __LINUX_MFD_S2MPS15_H
+#define __LINUX_MFD_S2MPS15_H
+
+/* S2MPS15 registers */
+enum s2mps15_reg {
+   S2MPS15_REG_ID,
+   S2MPS15_REG_INT1,
+   S2MPS15_REG_INT2,
+   S2MPS15_REG_INT3,
+   S2MPS15_REG_INT1M,
+   S2MPS15_REG_INT2M,
+   S2MPS15_REG_INT3M,
+   S2MPS15_REG_ST1,
+   S2MPS15_REG_ST2,
+   S2MPS15_REG_PWRONSRC,
+   S2MPS15_REG_OFFSRC,
+   S2MPS15_REG_BU_CHG,
+   S2MPS15_REG_RTCCTRL,
+   S2MPS15_REG_CTRL1,
+   S2MPS15_REG_CTRL2,
+   S2MPS15_REG_RSVD1,
+   S2MPS15_REG_RSVD2,
+   S2MPS15_REG_RSVD3,
+   S2MPS15_REG_RSVD4,
+   S2MPS15_REG_RSVD5,
+   S2MPS15_REG_RSVD6,
+   S2MPS15_REG_CTRL3,
+   S2MPS15_REG_RSVD7,
+   S2MPS15_REG_RSVD8,
+   S2MPS15_REG_WRSTBI,
+   S2MPS15_REG_B1CTRL1,
+   S2MPS15_REG_B1CTRL2,
+   S2MPS15_REG_B2CTRL1,
+   S2MPS15_REG_B2CTRL2,
+   S2MPS15_REG_B3CTRL1,
+   S2MPS15_REG_B3CTRL2,
+ 

[PATCH 2/2] mfd: sec: Add support for S2MPS15 PMIC

[Thomas Abraham]

Add support for S2MPS15 PMIC which is similar to S2MPS11 PMIC. The S2MPS15
PMIC supports 27 LDO regulators, 10 buck regulators, RTC, three 32.768KHz
clock outputs and battery charger. This patch adds initial support for
LDO and buck regulators of S2MPS15 device.

Signed-off-by: Thomas Abraham thomas...@samsung.com
---
 drivers/mfd/sec-core.c  |   26 ++
 include/linux/mfd/samsung/core.h|1 +
 include/linux/mfd/samsung/s2mps15.h |  161 +++
 3 files changed, 188 insertions(+), 0 deletions(-)
 create mode 100644 include/linux/mfd/samsung/s2mps15.h

diff --git a/drivers/mfd/sec-core.c b/drivers/mfd/sec-core.c
index dba7e2b..6f33c2b 100644
--- a/drivers/mfd/sec-core.c
+++ b/drivers/mfd/sec-core.c
@@ -28,6 +28,7 @@
 #include linux/mfd/samsung/s2mpa01.h
 #include linux/mfd/samsung/s2mps11.h
 #include linux/mfd/samsung/s2mps14.h
+#include linux/mfd/samsung/s2mps15.h
 #include linux/mfd/samsung/s2mpu02.h
 #include linux/mfd/samsung/s5m8763.h
 #include linux/mfd/samsung/s5m8767.h
@@ -85,6 +86,12 @@ static const struct mfd_cell s2mps14_devs[] = {
}
 };
 
+static const struct mfd_cell s2mps15_devs[] = {
+   {
+   .name = s2mps15-pmic,
+   },
+};
+
 static const struct mfd_cell s2mpa01_devs[] = {
{
.name = s2mpa01-pmic,
@@ -111,6 +118,9 @@ static const struct of_device_id sec_dt_match[] = {
.compatible = samsung,s2mps14-pmic,
.data = (void *)S2MPS14X,
}, {
+   .compatible = samsung,s2mps15-pmic,
+   .data = (void *)S2MPS15X,
+   }, {
.compatible = samsung,s2mpa01-pmic,
.data = (void *)S2MPA01,
}, {
@@ -203,6 +213,15 @@ static const struct regmap_config s2mps14_regmap_config = {
.cache_type = REGCACHE_FLAT,
 };
 
+static const struct regmap_config s2mps15_regmap_config = {
+   .reg_bits = 8,
+   .val_bits = 8,
+
+   .max_register = S2MPS15_REG_LDODSCH4,
+   .volatile_reg = s2mps11_volatile,
+   .cache_type = REGCACHE_FLAT,
+};
+
 static const struct regmap_config s2mpu02_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
@@ -328,6 +347,9 @@ static int sec_pmic_probe(struct i2c_client *i2c,
case S2MPS14X:
regmap = s2mps14_regmap_config;
break;
+   case S2MPS15X:
+   regmap = s2mps15_regmap_config;
+   break;
case S5M8763X:
regmap = s5m8763_regmap_config;
break;
@@ -382,6 +404,10 @@ static int sec_pmic_probe(struct i2c_client *i2c,
sec_devs = s2mps14_devs;
num_sec_devs = ARRAY_SIZE(s2mps14_devs);
break;
+   case S2MPS15X:
+   sec_devs = s2mps15_devs;
+   num_sec_devs = ARRAY_SIZE(s2mps15_devs);
+   break;
case S2MPU02:
sec_devs = s2mpu02_devs;
num_sec_devs = ARRAY_SIZE(s2mpu02_devs);
diff --git a/include/linux/mfd/samsung/core.h b/include/linux/mfd/samsung/core.h
index 1825eda..49ef612 100644
--- a/include/linux/mfd/samsung/core.h
+++ b/include/linux/mfd/samsung/core.h
@@ -42,6 +42,7 @@ enum sec_device_type {
S2MPA01,
S2MPS11X,
S2MPS14X,
+   S2MPS15X,
S2MPU02,
 };
 
diff --git a/include/linux/mfd/samsung/s2mps15.h 
b/include/linux/mfd/samsung/s2mps15.h
new file mode 100644
index 000..e82549a
--- /dev/null
+++ b/include/linux/mfd/samsung/s2mps15.h
@@ -0,0 +1,161 @@
+/*
+ * s2mps15.h
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd
+ *  http://www.samsung.com
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __LINUX_MFD_S2MPS15_H
+#define __LINUX_MFD_S2MPS15_H
+
+/* S2MPS15 registers */
+enum s2mps15_reg {
+   S2MPS15_REG_ID,
+   S2MPS15_REG_INT1,
+   S2MPS15_REG_INT2,
+   S2MPS15_REG_INT3,
+   S2MPS15_REG_INT1M,
+   S2MPS15_REG_INT2M,
+   S2MPS15_REG_INT3M,
+   S2MPS15_REG_ST1,
+   S2MPS15_REG_ST2,
+   S2MPS15_REG_PWRONSRC,
+   S2MPS15_REG_OFFSRC,
+   S2MPS15_REG_BU_CHG,
+   S2MPS15_REG_RTCCTRL,
+   S2MPS15_REG_CTRL1,
+   S2MPS15_REG_CTRL2,
+   S2MPS15_REG_RSVD1,
+   S2MPS15_REG_RSVD2,
+   S2MPS15_REG_RSVD3,
+   S2MPS15_REG_RSVD4,
+   S2MPS15_REG_RSVD5,
+   S2MPS15_REG_RSVD6,
+   S2MPS15_REG_CTRL3,
+   S2MPS15_REG_RSVD7,
+   S2MPS15_REG_RSVD8,
+   S2MPS15_REG_WRSTBI,
+   S2MPS15_REG_B1CTRL1

[PATCH 1/2] dt-bindings: mfd: s2mps11: add documentation for s2mps15 PMIC

[Thomas Abraham]

Add dt-binding documentation for s2mps15 PMIC device. The s2mps15 device
is similar to s2mps11/14 PMIC device and has 27 LDO and 10 buck regulators.

Cc: devicet...@vger.kernel.org
Signed-off-by: Thomas Abraham thomas...@samsung.com
---
 Documentation/devicetree/bindings/mfd/s2mps11.txt |   11 ---
 1 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/mfd/s2mps11.txt 
b/Documentation/devicetree/bindings/mfd/s2mps11.txt
index 0e4026a..41ee3f5 100644
--- a/Documentation/devicetree/bindings/mfd/s2mps11.txt
+++ b/Documentation/devicetree/bindings/mfd/s2mps11.txt
@@ -1,5 +1,5 @@
 
-* Samsung S2MPS11, S2MPS14 and S2MPU02 Voltage and Current Regulator
+* Samsung S2MPS11/14/15 and S2MPU02 Voltage and Current Regulator
 
 The Samsung S2MPS11 is a multi-function device which includes voltage and
 current regulators, RTC, charger controller and other sub-blocks. It is
@@ -7,8 +7,11 @@ interfaced to the host controller using an I2C interface. Each 
sub-block is
 addressed by the host system using different I2C slave addresses.
 
 Required properties:
-- compatible: Should be samsung,s2mps11-pmic or samsung,s2mps14-pmic
-  or samsung,s2mpu02-pmic.
+- compatible: Should be one of the following
+   - samsung,s2mps11-pmic
+   - samsung,s2mps14-pmic
+   - samsung,s2mps15-pmic
+   - samsung,s2mpu02-pmic
 - reg: Specifies the I2C slave address of the pmic block. It should be 0x66.
 
 Optional properties:
@@ -82,12 +85,14 @@ as per the datasheet of s2mps11.
  - valid values for n are:
- S2MPS11: 1 to 38
- S2MPS14: 1 to 25
+   - S2MPS15: 1 to 27
- S2MPU02: 1 to 28
  - Example: LDO1, LDO2, LDO28
- BUCKn
  - valid values for n are:
- S2MPS11: 1 to 10
- S2MPS14: 1 to 5
+   - S2MPS15: 1 to 10
- S2MPU02: 1 to 7
  - Example: BUCK1, BUCK2, BUCK9
 
-- 
1.6.6.rc2

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[PATCH 0/2] mfd: sec: add S2MPS15 PMIC support

[Thomas Abraham]

Samsung's S2MPS15 PMIC is targetted to be used with Samsung's Exynos7 SoC.
The S2MPS15 PMIC is similar in functionality to S2MPS11/14 PMIC. It contains
27 LDO and 10 Buck regulators, RTC, three 32.768 KHz clock outputs and allows
programming these blocks via a I2C interface. This patch series adds initial
support for LDO/Buck regulators of S2MPS15 PMIC.

Thomas Abraham (2):
  dt-bindings: mfd: s2mps11: add documentation for s2mps15 PMIC
  mfd: sec: Add support for S2MPS15 PMIC

 Documentation/devicetree/bindings/mfd/s2mps11.txt |   11 +-
 drivers/mfd/sec-core.c|   26 
 include/linux/mfd/samsung/core.h  |1 +
 include/linux/mfd/samsung/s2mps15.h   |  161 +
 4 files changed, 196 insertions(+), 3 deletions(-)
 create mode 100644 include/linux/mfd/samsung/s2mps15.h

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[PATCH] regulator: s2mps11: add support for S2MPS15 regulators

[Thomas Abraham]

The S2MPS15 PMIC is similar in functionality to S2MPS11/14 PMIC. It contains
27 LDO and 10 Buck regulators and allows programming these regulators via a
I2C interface. This patch adds initial support for LDO/Buck regulators of
S2MPS15 PMIC.

Signed-off-by: Thomas Abraham thomas...@samsung.com
---
 drivers/regulator/s2mps11.c |  133 +++
 1 files changed, 133 insertions(+), 0 deletions(-)

diff --git a/drivers/regulator/s2mps11.c b/drivers/regulator/s2mps11.c
index adab82d..e176fbb 100644
--- a/drivers/regulator/s2mps11.c
+++ b/drivers/regulator/s2mps11.c
@@ -31,6 +31,7 @@
 #include linux/mfd/samsung/core.h
 #include linux/mfd/samsung/s2mps11.h
 #include linux/mfd/samsung/s2mps14.h
+#include linux/mfd/samsung/s2mps15.h
 #include linux/mfd/samsung/s2mpu02.h
 
 struct s2mps11_info {
@@ -529,6 +530,133 @@ static const struct regulator_desc s2mps14_regulators[] = 
{
regulator_desc_s2mps14_buck(5, MIN_600_MV, STEP_6_25_MV),
 };
 
+static struct regulator_ops s2mps15_reg_ldo_ops = {
+   .list_voltage   = regulator_list_voltage_linear_range,
+   .map_voltage= regulator_map_voltage_linear_range,
+   .is_enabled = regulator_is_enabled_regmap,
+   .enable = regulator_enable_regmap,
+   .disable= regulator_disable_regmap,
+   .get_voltage_sel= regulator_get_voltage_sel_regmap,
+   .set_voltage_sel= regulator_set_voltage_sel_regmap,
+};
+
+static struct regulator_ops s2mps15_reg_buck_ops = {
+   .list_voltage   = regulator_list_voltage_linear_range,
+   .map_voltage= regulator_map_voltage_linear_range,
+   .is_enabled = regulator_is_enabled_regmap,
+   .enable = regulator_enable_regmap,
+   .disable= regulator_disable_regmap,
+   .get_voltage_sel= regulator_get_voltage_sel_regmap,
+   .set_voltage_sel= regulator_set_voltage_sel_regmap,
+   .set_voltage_time_sel   = regulator_set_voltage_time_sel,
+};
+
+#define regulator_desc_s2mps15_ldo(num, range) {   \
+   .name   = LDO#num,\
+   .id = S2MPS15_LDO##num, \
+   .ops= s2mps15_reg_ldo_ops, \
+   .type   = REGULATOR_VOLTAGE,\
+   .owner  = THIS_MODULE,  \
+   .linear_ranges  = range,\
+   .n_linear_ranges = ARRAY_SIZE(range),   \
+   .n_voltages = S2MPS15_LDO_N_VOLTAGES,   \
+   .vsel_reg   = S2MPS15_REG_L1CTRL + num - 1, \
+   .vsel_mask  = S2MPS15_LDO_VSEL_MASK,\
+   .enable_reg = S2MPS15_REG_L1CTRL + num - 1, \
+   .enable_mask= S2MPS15_ENABLE_MASK   \
+}
+
+#define regulator_desc_s2mps15_buck(num, range) {  \
+   .name   = BUCK#num,   \
+   .id = S2MPS15_BUCK##num,\
+   .ops= s2mps15_reg_buck_ops,\
+   .type   = REGULATOR_VOLTAGE,\
+   .owner  = THIS_MODULE,  \
+   .linear_ranges  = range,\
+   .n_linear_ranges = ARRAY_SIZE(range),   \
+   .ramp_delay = 12500,\
+   .n_voltages = S2MPS15_BUCK_N_VOLTAGES,  \
+   .vsel_reg   = S2MPS15_REG_B1CTRL2 + ((num - 1) * 2),\
+   .vsel_mask  = S2MPS15_BUCK_VSEL_MASK,   \
+   .enable_reg = S2MPS15_REG_B1CTRL1 + ((num - 1) * 2),\
+   .enable_mask= S2MPS14_ENABLE_MASK   \
+}
+
+/* voltage range for s2mps15 LDO 3, 5, 15, 16, 18, 20, 23 and 27 */
+static const struct regulator_linear_range s2mps15_ldo_voltage_ranges1[] = {
+   REGULATOR_LINEAR_RANGE(100, 0xc, 0x38, 25000),
+};
+
+/* voltage range for s2mps15 LDO 2, 6, 14, 17, 19, 21, 24 and 25 */
+static const struct regulator_linear_range s2mps15_ldo_voltage_ranges2[] = {
+   REGULATOR_LINEAR_RANGE(180, 0x0, 0x3f, 25000),
+};
+
+/* voltage range for s2mps15 LDO 4, 11, 12, 13, 22 and 26 */
+static const struct regulator_linear_range s2mps15_ldo_voltage_ranges3[] = {
+   REGULATOR_LINEAR_RANGE(70, 0x0, 0x34, 12500),
+};
+
+/* voltage range for s2mps15 LDO 7, 8, 9 and 10 */
+static const struct regulator_linear_range s2mps15_ldo_voltage_ranges4[] = {
+   REGULATOR_LINEAR_RANGE(70, 0xc, 0x18, 25000),
+};
+
+/* voltage range for s2mps15 LDO 1 */
+static const struct regulator_linear_range s2mps15_ldo_voltage_ranges5[] = {
+   REGULATOR_LINEAR_RANGE(50, 0x0, 0x20, 12500),
+};
+
+/* voltage range for s2mps15 BUCK 1, 2, 3, 4, 5, 6 and 7 */
+static const struct regulator_linear_range

Re: [PATCH] regulator: s2mps11: add support for S2MPS15 regulators

[Thomas Abraham]

On Tue, Oct 14, 2014 at 2:18 PM, Krzysztof Kozłowski
k.kozlow...@samsung.com wrote:
 On 14.10.2014 10:17, Thomas Abraham wrote:
 The S2MPS15 PMIC is similar in functionality to S2MPS11/14 PMIC. It contains
 27 LDO and 10 Buck regulators and allows programming these regulators via a
 I2C interface. This patch adds initial support for LDO/Buck regulators of
 S2MPS15 PMIC.

 Signed-off-by: Thomas Abraham thomas...@samsung.com

 Just two questions/ideas:
 1. No specific steps for suspend?

Yes, it is required but I have not tested it yet. I will post the
suspend related changes when it has been tested.

 2. Maybe add S2MPS15 to MODULE_DESCRIPTION and Kconfig?

Okay, I will do that along in the next set of update patches for s2mps15.


 Anyway rest looks fine.
 Reviewed-by: Krzysztof Kozlowski k.kozlow...@samsung.com

Thanks Krzysztof.

Regards,
Thomas.


 Best regards,
 Krzysztof

 ---
  drivers/regulator/s2mps11.c |  133 
 +++
  1 files changed, 133 insertions(+), 0 deletions(-)

 diff --git a/drivers/regulator/s2mps11.c b/drivers/regulator/s2mps11.c
 index adab82d..e176fbb 100644
 --- a/drivers/regulator/s2mps11.c
 +++ b/drivers/regulator/s2mps11.c
 @@ -31,6 +31,7 @@
  #include linux/mfd/samsung/core.h
  #include linux/mfd/samsung/s2mps11.h
  #include linux/mfd/samsung/s2mps14.h
 +#include linux/mfd/samsung/s2mps15.h
  #include linux/mfd/samsung/s2mpu02.h

  struct s2mps11_info {
 @@ -529,6 +530,133 @@ static const struct regulator_desc 
 s2mps14_regulators[] = {
   regulator_desc_s2mps14_buck(5, MIN_600_MV, STEP_6_25_MV),
  };

 +static struct regulator_ops s2mps15_reg_ldo_ops = {
 + .list_voltage   = regulator_list_voltage_linear_range,
 + .map_voltage= regulator_map_voltage_linear_range,
 + .is_enabled = regulator_is_enabled_regmap,
 + .enable = regulator_enable_regmap,
 + .disable= regulator_disable_regmap,
 + .get_voltage_sel= regulator_get_voltage_sel_regmap,
 + .set_voltage_sel= regulator_set_voltage_sel_regmap,
 +};
 +
 +static struct regulator_ops s2mps15_reg_buck_ops = {
 + .list_voltage   = regulator_list_voltage_linear_range,
 + .map_voltage= regulator_map_voltage_linear_range,
 + .is_enabled = regulator_is_enabled_regmap,
 + .enable = regulator_enable_regmap,
 + .disable= regulator_disable_regmap,
 + .get_voltage_sel= regulator_get_voltage_sel_regmap,
 + .set_voltage_sel= regulator_set_voltage_sel_regmap,
 + .set_voltage_time_sel   = regulator_set_voltage_time_sel,
 +};
 +
 +#define regulator_desc_s2mps15_ldo(num, range) { \
 + .name   = LDO#num,\
 + .id = S2MPS15_LDO##num, \
 + .ops= s2mps15_reg_ldo_ops, \
 + .type   = REGULATOR_VOLTAGE,\
 + .owner  = THIS_MODULE,  \
 + .linear_ranges  = range,\
 + .n_linear_ranges = ARRAY_SIZE(range),   \
 + .n_voltages = S2MPS15_LDO_N_VOLTAGES,   \
 + .vsel_reg   = S2MPS15_REG_L1CTRL + num - 1, \
 + .vsel_mask  = S2MPS15_LDO_VSEL_MASK,\
 + .enable_reg = S2MPS15_REG_L1CTRL + num - 1, \
 + .enable_mask= S2MPS15_ENABLE_MASK   \
 +}
 +
 +#define regulator_desc_s2mps15_buck(num, range) {\
 + .name   = BUCK#num,   \
 + .id = S2MPS15_BUCK##num,\
 + .ops= s2mps15_reg_buck_ops,\
 + .type   = REGULATOR_VOLTAGE,\
 + .owner  = THIS_MODULE,  \
 + .linear_ranges  = range,\
 + .n_linear_ranges = ARRAY_SIZE(range),   \
 + .ramp_delay = 12500,\
 + .n_voltages = S2MPS15_BUCK_N_VOLTAGES,  \
 + .vsel_reg   = S2MPS15_REG_B1CTRL2 + ((num - 1) * 2),\
 + .vsel_mask  = S2MPS15_BUCK_VSEL_MASK,   \
 + .enable_reg = S2MPS15_REG_B1CTRL1 + ((num - 1) * 2),\
 + .enable_mask= S2MPS14_ENABLE_MASK   \
 +}
 +
 +/* voltage range for s2mps15 LDO 3, 5, 15, 16, 18, 20, 23 and 27 */
 +static const struct regulator_linear_range s2mps15_ldo_voltage_ranges1[] = {
 + REGULATOR_LINEAR_RANGE(100, 0xc, 0x38, 25000),
 +};
 +
 +/* voltage range for s2mps15 LDO 2, 6, 14, 17, 19, 21, 24 and 25 */
 +static const struct regulator_linear_range s2mps15_ldo_voltage_ranges2[] = {
 + REGULATOR_LINEAR_RANGE(180, 0x0, 0x3f, 25000),
 +};
 +
 +/* voltage range for s2mps15 LDO 4, 11, 12, 13, 22 and 26 */
 +static const struct

Re: [PATCH 1/2] dt-bindings: mfd: s2mps11: add documentation for s2mps15 PMIC

[Thomas Abraham]

On Tue, Oct 14, 2014 at 2:13 PM, Krzysztof Kozłowski
k.kozlow...@samsung.com wrote:
 On 14.10.2014 10:14, Thomas Abraham wrote:
 Add dt-binding documentation for s2mps15 PMIC device. The s2mps15 device
 is similar to s2mps11/14 PMIC device and has 27 LDO and 10 buck regulators.

 Cc: devicet...@vger.kernel.org
 Signed-off-by: Thomas Abraham thomas...@samsung.com
 ---
  Documentation/devicetree/bindings/mfd/s2mps11.txt |   11 ---
  1 files changed, 8 insertions(+), 3 deletions(-)

 Looks good.
 Reviewed-by: Krzysztof Kozlowski k.kozlow...@samsung.com

 P.S. Wrong devicetree-disc...@lists.ozlabs.org list? I receive bounces.

Yes, that was wrong. Thanks for correcting it.

Regards,
Thomas.


 Best regards,
 Krzysztof



 diff --git a/Documentation/devicetree/bindings/mfd/s2mps11.txt 
 b/Documentation/devicetree/bindings/mfd/s2mps11.txt
 index 0e4026a..41ee3f5 100644
 --- a/Documentation/devicetree/bindings/mfd/s2mps11.txt
 +++ b/Documentation/devicetree/bindings/mfd/s2mps11.txt
 @@ -1,5 +1,5 @@

 -* Samsung S2MPS11, S2MPS14 and S2MPU02 Voltage and Current Regulator
 +* Samsung S2MPS11/14/15 and S2MPU02 Voltage and Current Regulator

  The Samsung S2MPS11 is a multi-function device which includes voltage and
  current regulators, RTC, charger controller and other sub-blocks. It is
 @@ -7,8 +7,11 @@ interfaced to the host controller using an I2C interface. 
 Each sub-block is
  addressed by the host system using different I2C slave addresses.

  Required properties:
 -- compatible: Should be samsung,s2mps11-pmic or samsung,s2mps14-pmic
 -  or samsung,s2mpu02-pmic.
 +- compatible: Should be one of the following
 + - samsung,s2mps11-pmic
 + - samsung,s2mps14-pmic
 + - samsung,s2mps15-pmic
 + - samsung,s2mpu02-pmic
  - reg: Specifies the I2C slave address of the pmic block. It should be 0x66.

  Optional properties:
 @@ -82,12 +85,14 @@ as per the datasheet of s2mps11.
 - valid values for n are:
   - S2MPS11: 1 to 38
   - S2MPS14: 1 to 25
 + - S2MPS15: 1 to 27
   - S2MPU02: 1 to 28
 - Example: LDO1, LDO2, LDO28
   - BUCKn
 - valid values for n are:
   - S2MPS11: 1 to 10
   - S2MPS14: 1 to 5
 + - S2MPS15: 1 to 10
   - S2MPU02: 1 to 7
 - Example: BUCK1, BUCK2, BUCK9



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Re: [PATCH 2/2] mfd: sec: Add support for S2MPS15 PMIC

[Thomas Abraham]

On Tue, Oct 14, 2014 at 2:11 PM, Krzysztof Kozłowski
k.kozlow...@samsung.com wrote:
 On 14.10.2014 10:14, Thomas Abraham wrote:
 Add support for S2MPS15 PMIC which is similar to S2MPS11 PMIC. The S2MPS15
 PMIC supports 27 LDO regulators, 10 buck regulators, RTC, three 32.768KHz
 clock outputs and battery charger. This patch adds initial support for
 LDO and buck regulators of S2MPS15 device.

 Signed-off-by: Thomas Abraham thomas...@samsung.com

 Quite nice and small diff stat for adding new chip support. Looks good.
 I assume that RTC/clock will be handled in later submissions.

Yes, it will be posted later after testing these features.


 Reviewed-by: Krzysztof Kozlowski k.kozlow...@samsung.com

Thanks!

Regards,
Thomas.


 Best regards,
 Krzysztof

 ---
  drivers/mfd/sec-core.c  |   26 ++
  include/linux/mfd/samsung/core.h|1 +
  include/linux/mfd/samsung/s2mps15.h |  161 
 +++
  3 files changed, 188 insertions(+), 0 deletions(-)
  create mode 100644 include/linux/mfd/samsung/s2mps15.h

 diff --git a/drivers/mfd/sec-core.c b/drivers/mfd/sec-core.c
 index dba7e2b..6f33c2b 100644
 --- a/drivers/mfd/sec-core.c
 +++ b/drivers/mfd/sec-core.c
 @@ -28,6 +28,7 @@
  #include linux/mfd/samsung/s2mpa01.h
  #include linux/mfd/samsung/s2mps11.h
  #include linux/mfd/samsung/s2mps14.h
 +#include linux/mfd/samsung/s2mps15.h
  #include linux/mfd/samsung/s2mpu02.h
  #include linux/mfd/samsung/s5m8763.h
  #include linux/mfd/samsung/s5m8767.h
 @@ -85,6 +86,12 @@ static const struct mfd_cell s2mps14_devs[] = {
   }
  };

 +static const struct mfd_cell s2mps15_devs[] = {
 + {
 + .name = s2mps15-pmic,
 + },
 +};
 +
  static const struct mfd_cell s2mpa01_devs[] = {
   {
   .name = s2mpa01-pmic,
 @@ -111,6 +118,9 @@ static const struct of_device_id sec_dt_match[] = {
   .compatible = samsung,s2mps14-pmic,
   .data = (void *)S2MPS14X,
   }, {
 + .compatible = samsung,s2mps15-pmic,
 + .data = (void *)S2MPS15X,
 + }, {
   .compatible = samsung,s2mpa01-pmic,
   .data = (void *)S2MPA01,
   }, {
 @@ -203,6 +213,15 @@ static const struct regmap_config s2mps14_regmap_config 
 = {
   .cache_type = REGCACHE_FLAT,
  };

 +static const struct regmap_config s2mps15_regmap_config = {
 + .reg_bits = 8,
 + .val_bits = 8,
 +
 + .max_register = S2MPS15_REG_LDODSCH4,
 + .volatile_reg = s2mps11_volatile,
 + .cache_type = REGCACHE_FLAT,
 +};
 +
  static const struct regmap_config s2mpu02_regmap_config = {
   .reg_bits = 8,
   .val_bits = 8,
 @@ -328,6 +347,9 @@ static int sec_pmic_probe(struct i2c_client *i2c,
   case S2MPS14X:
   regmap = s2mps14_regmap_config;
   break;
 + case S2MPS15X:
 + regmap = s2mps15_regmap_config;
 + break;
   case S5M8763X:
   regmap = s5m8763_regmap_config;
   break;
 @@ -382,6 +404,10 @@ static int sec_pmic_probe(struct i2c_client *i2c,
   sec_devs = s2mps14_devs;
   num_sec_devs = ARRAY_SIZE(s2mps14_devs);
   break;
 + case S2MPS15X:
 + sec_devs = s2mps15_devs;
 + num_sec_devs = ARRAY_SIZE(s2mps15_devs);
 + break;
   case S2MPU02:
   sec_devs = s2mpu02_devs;
   num_sec_devs = ARRAY_SIZE(s2mpu02_devs);
 diff --git a/include/linux/mfd/samsung/core.h 
 b/include/linux/mfd/samsung/core.h
 index 1825eda..49ef612 100644
 --- a/include/linux/mfd/samsung/core.h
 +++ b/include/linux/mfd/samsung/core.h
 @@ -42,6 +42,7 @@ enum sec_device_type {
   S2MPA01,
   S2MPS11X,
   S2MPS14X,
 + S2MPS15X,
   S2MPU02,
  };

 diff --git a/include/linux/mfd/samsung/s2mps15.h 
 b/include/linux/mfd/samsung/s2mps15.h
 new file mode 100644
 index 000..e82549a
 --- /dev/null
 +++ b/include/linux/mfd/samsung/s2mps15.h
 @@ -0,0 +1,161 @@
 +/*
 + * s2mps15.h
 + *
 + * Copyright (c) 2014 Samsung Electronics Co., Ltd
 + *  http://www.samsung.com
 + *
 + * This program is free software; you can redistribute  it and/or modify it
 + * under  the terms of  the GNU General  Public License as published by the
 + * Free Software Foundation;  either version 2 of the  License, or (at your
 + * option) any later version.
 + *
 + * This program is distributed in the hope that it will be useful,
 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 + * GNU General Public License for more details.
 + *
 + */
 +
 +#ifndef __LINUX_MFD_S2MPS15_H
 +#define __LINUX_MFD_S2MPS15_H
 +
 +/* S2MPS15 registers */
 +enum s2mps15_reg {
 + S2MPS15_REG_ID,
 + S2MPS15_REG_INT1,
 + S2MPS15_REG_INT2,
 + S2MPS15_REG_INT3,
 + S2MPS15_REG_INT1M,
 + S2MPS15_REG_INT2M,
 + S2MPS15_REG_INT3M,
 + S2MPS15_REG_ST1,
 + S2MPS15_REG_ST2

Re: [RFC/PATCH 02/12] clk: Add safe switch hook

[Thomas Abraham]

On Tue, Jul 29, 2014 at 11:35 AM, Mike Turquette  wrote:
> Quoting Stephen Boyd (2014-06-24 17:06:13)
>> Sometimes clocks can't accept their parent source turning off
>> while the source is reprogrammed to a different rate. Most
>> notably some CPU clocks require a way to switch away from the
>> current PLL they're running on, reprogram that PLL to a new rate,
>> and then switch back to the PLL with the new rate once they're
>> done.  Add a hook that drivers can implement allowing them to
>> return a 'safe parent' that they can switch their parent to while
>> the upstream source is reprogrammed.
>
> Adding Thomas to Cc.
>
> Thomas,
>
> Does this generic hook help you out at all with your CPU frequency
> transitions? I remember in my discussions with Chander K. that you have
> something like safe dividers, safe parents and safe voltages to take
> into account (but I might be misremembering some of that).

Hi Mike,

Samsung CPU clock implementation divides the alternate parent clock to
lower permissible speeds when the old clock rate of the primary parent
(PLL) is lower than the speed of the alternate parent. This step has
to be completed prior to hook gets called.

So though this hook takes care of re-parenting the clock, which is one
of the steps handled in Samsung CPU clock, it is not a alternative to
the current implementation of the Samsung CPU clock.

Thanks,
Thomas.

>
> Stephen,
>
> For reference, recent patches from Samsung to introduce cpu clocks[1]
> which I am not wild about, but the generic infrastructure isn't really
> there yet in the framework core to manage complex, pre-defined,
> multi-clock transitions gracefully.
>
> Regards,
> Mike
>
> [1] http://www.spinics.net/lists/arm-kernel/msg351137.html
>
>>
>> Signed-off-by: Stephen Boyd 
>> ---
>>  drivers/clk/clk.c| 53 
>> ++--
>>  include/linux/clk-private.h  |  2 ++
>>  include/linux/clk-provider.h |  1 +
>>  3 files changed, 49 insertions(+), 7 deletions(-)
>>
>> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
>> index 8b73edef151d..5e32fa55032b 100644
>> --- a/drivers/clk/clk.c
>> +++ b/drivers/clk/clk.c
>> @@ -1367,6 +1367,7 @@ static void clk_calc_subtree(struct clk *clk, unsigned 
>> long new_rate,
>>  struct clk *new_parent, u8 p_index)
>>  {
>> struct clk *child;
>> +   struct clk *parent;
>>
>> clk->new_rate = new_rate;
>> clk->new_parent = new_parent;
>> @@ -1376,6 +1377,17 @@ static void clk_calc_subtree(struct clk *clk, 
>> unsigned long new_rate,
>> if (new_parent && new_parent != clk->parent)
>> new_parent->new_child = clk;
>>
>> +   if (clk->ops->get_safe_parent) {
>> +   parent = clk->ops->get_safe_parent(clk->hw);
>> +   if (parent) {
>> +   p_index = clk_fetch_parent_index(clk, parent);
>> +   clk->safe_parent_index = p_index;
>> +   clk->safe_parent = parent;
>> +   }
>> +   } else {
>> +   clk->safe_parent = NULL;
>> +   }
>> +
>> hlist_for_each_entry(child, >children, child_node) {
>> child->new_rate = clk_recalc(child, new_rate);
>> clk_calc_subtree(child, child->new_rate, NULL, 0);
>> @@ -1458,14 +1470,42 @@ out:
>>  static struct clk *clk_propagate_rate_change(struct clk *clk, unsigned long 
>> event)
>>  {
>> struct clk *child, *tmp_clk, *fail_clk = NULL;
>> +   struct clk *old_parent;
>> int ret = NOTIFY_DONE;
>>
>> -   if (clk->rate == clk->new_rate)
>> +   if (clk->rate == clk->new_rate && event != POST_RATE_CHANGE)
>> return NULL;
>>
>> +   switch (event) {
>> +   case PRE_RATE_CHANGE:
>> +   if (clk->safe_parent)
>> +   clk->ops->set_parent(clk->hw, 
>> clk->safe_parent_index);
>> +   break;
>> +   case POST_RATE_CHANGE:
>> +   if (clk->safe_parent) {
>> +   old_parent = __clk_set_parent_before(clk,
>> +
>> clk->new_parent);
>> +   if (clk->ops->set_rate_and_parent) {
>> +   clk->ops->set_rate_and_parent(clk->hw,
>> +   clk->new_rate,
>> +   clk->new_parent ?
>> +   clk->new_parent->rate : 0,
>> +   clk->new_parent_index);
>> +   } else if (clk->ops->set_parent) {
>> +   clk->ops->set_parent(clk->hw,
>> +   clk->new_parent_index);
>> +   }
>> +   __clk_set_parent_after(clk, clk->new_parent,
>> +  old_parent);
>> +   }
>> +  

Re: [RFC/PATCH 02/12] clk: Add safe switch hook

[Thomas Abraham]

On Tue, Jul 29, 2014 at 11:35 AM, Mike Turquette mturque...@linaro.org wrote:
 Quoting Stephen Boyd (2014-06-24 17:06:13)
 Sometimes clocks can't accept their parent source turning off
 while the source is reprogrammed to a different rate. Most
 notably some CPU clocks require a way to switch away from the
 current PLL they're running on, reprogram that PLL to a new rate,
 and then switch back to the PLL with the new rate once they're
 done.  Add a hook that drivers can implement allowing them to
 return a 'safe parent' that they can switch their parent to while
 the upstream source is reprogrammed.

 Adding Thomas to Cc.

 Thomas,

 Does this generic hook help you out at all with your CPU frequency
 transitions? I remember in my discussions with Chander K. that you have
 something like safe dividers, safe parents and safe voltages to take
 into account (but I might be misremembering some of that).

Hi Mike,

Samsung CPU clock implementation divides the alternate parent clock to
lower permissible speeds when the old clock rate of the primary parent
(PLL) is lower than the speed of the alternate parent. This step has
to be completed prior to hook gets called.

So though this hook takes care of re-parenting the clock, which is one
of the steps handled in Samsung CPU clock, it is not a alternative to
the current implementation of the Samsung CPU clock.

Thanks,
Thomas.


 Stephen,

 For reference, recent patches from Samsung to introduce cpu clocks[1]
 which I am not wild about, but the generic infrastructure isn't really
 there yet in the framework core to manage complex, pre-defined,
 multi-clock transitions gracefully.

 Regards,
 Mike

 [1] http://www.spinics.net/lists/arm-kernel/msg351137.html


 Signed-off-by: Stephen Boyd sb...@codeaurora.org
 ---
  drivers/clk/clk.c| 53 
 ++--
  include/linux/clk-private.h  |  2 ++
  include/linux/clk-provider.h |  1 +
  3 files changed, 49 insertions(+), 7 deletions(-)

 diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
 index 8b73edef151d..5e32fa55032b 100644
 --- a/drivers/clk/clk.c
 +++ b/drivers/clk/clk.c
 @@ -1367,6 +1367,7 @@ static void clk_calc_subtree(struct clk *clk, unsigned 
 long new_rate,
  struct clk *new_parent, u8 p_index)
  {
 struct clk *child;
 +   struct clk *parent;

 clk-new_rate = new_rate;
 clk-new_parent = new_parent;
 @@ -1376,6 +1377,17 @@ static void clk_calc_subtree(struct clk *clk, 
 unsigned long new_rate,
 if (new_parent  new_parent != clk-parent)
 new_parent-new_child = clk;

 +   if (clk-ops-get_safe_parent) {
 +   parent = clk-ops-get_safe_parent(clk-hw);
 +   if (parent) {
 +   p_index = clk_fetch_parent_index(clk, parent);
 +   clk-safe_parent_index = p_index;
 +   clk-safe_parent = parent;
 +   }
 +   } else {
 +   clk-safe_parent = NULL;
 +   }
 +
 hlist_for_each_entry(child, clk-children, child_node) {
 child-new_rate = clk_recalc(child, new_rate);
 clk_calc_subtree(child, child-new_rate, NULL, 0);
 @@ -1458,14 +1470,42 @@ out:
  static struct clk *clk_propagate_rate_change(struct clk *clk, unsigned long 
 event)
  {
 struct clk *child, *tmp_clk, *fail_clk = NULL;
 +   struct clk *old_parent;
 int ret = NOTIFY_DONE;

 -   if (clk-rate == clk-new_rate)
 +   if (clk-rate == clk-new_rate  event != POST_RATE_CHANGE)
 return NULL;

 +   switch (event) {
 +   case PRE_RATE_CHANGE:
 +   if (clk-safe_parent)
 +   clk-ops-set_parent(clk-hw, 
 clk-safe_parent_index);
 +   break;
 +   case POST_RATE_CHANGE:
 +   if (clk-safe_parent) {
 +   old_parent = __clk_set_parent_before(clk,
 +
 clk-new_parent);
 +   if (clk-ops-set_rate_and_parent) {
 +   clk-ops-set_rate_and_parent(clk-hw,
 +   clk-new_rate,
 +   clk-new_parent ?
 +   clk-new_parent-rate : 0,
 +   clk-new_parent_index);
 +   } else if (clk-ops-set_parent) {
 +   clk-ops-set_parent(clk-hw,
 +   clk-new_parent_index);
 +   }
 +   __clk_set_parent_after(clk, clk-new_parent,
 +  old_parent);
 +   }
 +   break;
 +   }
 +
 if (clk-notifier_count) {
 -   ret = __clk_notify(clk, event, clk-rate, clk-new_rate);
 -   if (ret  NOTIFY_STOP_MASK)
 +   

Re: [PATCH] ARM: dts: add CPU nodes for Exynos4 SoCs

[Thomas Abraham]

On Mon, Jul 21, 2014 at 6:40 PM, Bartlomiej Zolnierkiewicz
 wrote:
>
> Hi,
>
> On Monday, July 21, 2014 01:43:53 PM Daniel Drake wrote:
>> On Fri, Jul 18, 2014 at 5:00 PM, Bartlomiej Zolnierkiewicz
>>  wrote:
>> > Recent patch by Tomasz Figa ("irqchip: gic: Fix core ID calculation
>> > when topology is read from DT") fixed GIC driver to filter cluster ID
>> > from values returned by cpu_logical_map() for SoCs having registers
>> > mapped without per-CPU banking making it is possible to add CPU nodes
>> > for Exynos4 SoCs.  In case of Exynos SoCs these CPU nodes are also
>> > required by future changes adding initialization of cpuidle states in
>> > Exynos cpuidle driver through DT.
>>
>> This conflicts with work in the thread "cpufreq: use generic cpufreq
>> drivers for exynos platforms" which is already in its 7th iteration.
>> Perhaps best to work directly with Thomas to help him finish that series?
>
> Patch "[PATCH v7 4/6] ARM: dts: Exynos: add cpu nodes, opp and cpu clock
> configuration data" from Thomas needs another revision anyway since it lacks
> cluster ID in Exynos4210 CPU node.  It also mixes addition of CPU nodes
> with cpufreq specific changes and IMHO addition of CPU nodes should be in
> separate patch to ease bisection if any later problems turn up.  Therefore
> I think that it would be the best if Thomas would rebase his work on top of
> "irqchip: gic: Fix core ID calculation when topology is read from DT" patch
> and this one.  Thomas, are you okay with this?

Hi Bartlomiej,

Yes, I am okay with this.

Regards,
Thomas.

>
> Best regards,
> --
> Bartlomiej Zolnierkiewicz
> Samsung R Institute Poland
> Samsung Electronics
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" 
> in
> the body of a message to majord...@vger.kernel.org
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Re: [PATCH] ARM: dts: add CPU nodes for Exynos4 SoCs

[Thomas Abraham]

On Mon, Jul 21, 2014 at 6:40 PM, Bartlomiej Zolnierkiewicz
b.zolnier...@samsung.com wrote:

 Hi,

 On Monday, July 21, 2014 01:43:53 PM Daniel Drake wrote:
 On Fri, Jul 18, 2014 at 5:00 PM, Bartlomiej Zolnierkiewicz
 b.zolnier...@samsung.com wrote:
  Recent patch by Tomasz Figa (irqchip: gic: Fix core ID calculation
  when topology is read from DT) fixed GIC driver to filter cluster ID
  from values returned by cpu_logical_map() for SoCs having registers
  mapped without per-CPU banking making it is possible to add CPU nodes
  for Exynos4 SoCs.  In case of Exynos SoCs these CPU nodes are also
  required by future changes adding initialization of cpuidle states in
  Exynos cpuidle driver through DT.

 This conflicts with work in the thread cpufreq: use generic cpufreq
 drivers for exynos platforms which is already in its 7th iteration.
 Perhaps best to work directly with Thomas to help him finish that series?

 Patch [PATCH v7 4/6] ARM: dts: Exynos: add cpu nodes, opp and cpu clock
 configuration data from Thomas needs another revision anyway since it lacks
 cluster ID in Exynos4210 CPU node.  It also mixes addition of CPU nodes
 with cpufreq specific changes and IMHO addition of CPU nodes should be in
 separate patch to ease bisection if any later problems turn up.  Therefore
 I think that it would be the best if Thomas would rebase his work on top of
 irqchip: gic: Fix core ID calculation when topology is read from DT patch
 and this one.  Thomas, are you okay with this?

Hi Bartlomiej,

Yes, I am okay with this.

Regards,
Thomas.


 Best regards,
 --
 Bartlomiej Zolnierkiewicz
 Samsung RD Institute Poland
 Samsung Electronics

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Re: [PATCHv2 0/3] cpufreq: Use cpufreq-cpu0 driver for Exynos3250

[Thomas Abraham]

On Wed, Jun 18, 2014 at 2:09 PM, Chanwoo Choi  wrote:
> This patchset use cpufreq-cpu0 driver to support Exynos3250 cpufreq. So, this
> patchset is based on following patchset[1] by Thomas Abraham.
>  [1] http://www.spinics.net/lists/arm-kernel/msg339392.html
>
> Changes from v1:
> - Rebased on new patchset[1] by Thomas Abraham
> - Modify clk-cpu.c to support Exynos3250
> - Drop documentation patch on previous patchset[2]
>  [2] http://www.spinics.net/lists/cpufreq/msg10265.html
> - Add only operating-points for Exynos3250 without armclk-divider-table
>
> Chanwoo Choi (3):
>   clk: samsung: cpu: Add support for cpu clocks of Exynos3250
>   clk: samsung: exynos3250: Use cpu-clock provider type to support cpufreq
>   ARM: dts: Exynos: Add cpu clock table for Exynos3250
>
>  arch/arm/boot/dts/exynos3250.dtsi| 15 +++
>  drivers/clk/samsung/clk-cpu.c| 31 +++
>  drivers/clk/samsung/clk-exynos3250.c | 14 ++
>  3 files changed, 56 insertions(+), 4 deletions(-)

Hi Chanwoo,

I have reviewed this series and it looks fine. If the cpu clock type
is merged without any further changes, please add
Reviewed-by: Thomas Abraham 

Thanks,
Thomas.

>
> --
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Re: [PATCHv2 0/3] cpufreq: Use cpufreq-cpu0 driver for Exynos3250

[Thomas Abraham]

On Wed, Jun 18, 2014 at 2:09 PM, Chanwoo Choi cw00.c...@samsung.com wrote:
 This patchset use cpufreq-cpu0 driver to support Exynos3250 cpufreq. So, this
 patchset is based on following patchset[1] by Thomas Abraham.
  [1] http://www.spinics.net/lists/arm-kernel/msg339392.html

 Changes from v1:
 - Rebased on new patchset[1] by Thomas Abraham
 - Modify clk-cpu.c to support Exynos3250
 - Drop documentation patch on previous patchset[2]
  [2] http://www.spinics.net/lists/cpufreq/msg10265.html
 - Add only operating-points for Exynos3250 without armclk-divider-table

 Chanwoo Choi (3):
   clk: samsung: cpu: Add support for cpu clocks of Exynos3250
   clk: samsung: exynos3250: Use cpu-clock provider type to support cpufreq
   ARM: dts: Exynos: Add cpu clock table for Exynos3250

  arch/arm/boot/dts/exynos3250.dtsi| 15 +++
  drivers/clk/samsung/clk-cpu.c| 31 +++
  drivers/clk/samsung/clk-exynos3250.c | 14 ++
  3 files changed, 56 insertions(+), 4 deletions(-)

Hi Chanwoo,

I have reviewed this series and it looks fine. If the cpu clock type
is merged without any further changes, please add
Reviewed-by: Thomas Abraham thomas...@samsung.com

Thanks,
Thomas.


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Re: [PATCH V2 0/3] cpufreq: add support for intermediate (stable)

[Thomas Abraham]

On Fri, May 16, 2014 at 2:33 PM, Viresh Kumar  wrote:
> Douglas Anderson, recently pointed out an interesting problem due to which
> udelay() was expiring earlier than it should.
>
> While transitioning between frequencies few platforms may temporarily switch 
> to
> a stable frequency, waiting for the main PLL to stabilize.
>
> For example: When we transition between very low frequencies on exynos, like
> between 200MHz and 300MHz, we may temporarily switch to a PLL running at 
> 800MHz.
> No CPUFREQ notification is sent for that. That means there's a period of time
> when we're running at 800MHz but loops_per_jiffy is calibrated at between 
> 200MHz
> and 300MHz. And so udelay behaves badly.

Hi Viresh,

In the given example above, the reworked implementation of cpufreq for
exynos maintains the transition frequency at 800MHz / 4 = 200MHz by
using a clock divider. So the transition frequency is ensured to be
less than or equal to the pre-transition cpu clock frequency.

Thanks,
Thomas.

>
> To get this fixed in a generic way, lets introduce another set of callbacks
> get_intermediate() and target_intermediate(), only for drivers with
> target_index() and CPUFREQ_ASYNC_NOTIFICATION unset.
>
> get_intermediate should return a stable intermediate frequency platform wants 
> to
> switch to, and target_intermediate() should set CPU to to that frequency, 
> before
> jumping to the frequency corresponding to 'index'. Core will take care of
> sending notifications and driver doesn't have to handle them in
> target_intermediate() or target_index().
>
> This patchset also update Tegra to use this new infrastructure.
>
> NOTE: Once set to intermediate frequency, driver isn't expected to fail for 
> the
> following ->target_index() call, if it fails core will issue a WARN().
>
> @Stephen: Can you please test this? I haven't as I didn't had a board. :)
>
> V1-V2: Almost changed completely, V1 was here: 
> https://lkml.org/lkml/2014/5/15/40
>
> Viresh Kumar (3):
>   cpufreq: handle calls to ->target_index() in separate routine
>   cpufreq: add support for intermediate (stable) frequencies
>   cpufreq: Tegra: implement intermediate frequency callbacks
>
>  Documentation/cpu-freq/cpu-drivers.txt | 19 +++-
>  drivers/cpufreq/cpufreq.c  | 82 
> --
>  drivers/cpufreq/tegra-cpufreq.c| 81 -
>  include/linux/cpufreq.h| 15 +++
>  4 files changed, 128 insertions(+), 69 deletions(-)
>
> --
> 2.0.0.rc2
>
>
> ___
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> http://lists.linaro.org/mailman/listinfo/linaro-kernel
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Re: [PATCH V2 0/3] cpufreq: add support for intermediate (stable)

[Thomas Abraham]

On Fri, May 16, 2014 at 2:33 PM, Viresh Kumar viresh.ku...@linaro.org wrote:
 Douglas Anderson, recently pointed out an interesting problem due to which
 udelay() was expiring earlier than it should.

 While transitioning between frequencies few platforms may temporarily switch 
 to
 a stable frequency, waiting for the main PLL to stabilize.

 For example: When we transition between very low frequencies on exynos, like
 between 200MHz and 300MHz, we may temporarily switch to a PLL running at 
 800MHz.
 No CPUFREQ notification is sent for that. That means there's a period of time
 when we're running at 800MHz but loops_per_jiffy is calibrated at between 
 200MHz
 and 300MHz. And so udelay behaves badly.

Hi Viresh,

In the given example above, the reworked implementation of cpufreq for
exynos maintains the transition frequency at 800MHz / 4 = 200MHz by
using a clock divider. So the transition frequency is ensured to be
less than or equal to the pre-transition cpu clock frequency.

Thanks,
Thomas.


 To get this fixed in a generic way, lets introduce another set of callbacks
 get_intermediate() and target_intermediate(), only for drivers with
 target_index() and CPUFREQ_ASYNC_NOTIFICATION unset.

 get_intermediate should return a stable intermediate frequency platform wants 
 to
 switch to, and target_intermediate() should set CPU to to that frequency, 
 before
 jumping to the frequency corresponding to 'index'. Core will take care of
 sending notifications and driver doesn't have to handle them in
 target_intermediate() or target_index().

 This patchset also update Tegra to use this new infrastructure.

 NOTE: Once set to intermediate frequency, driver isn't expected to fail for 
 the
 following -target_index() call, if it fails core will issue a WARN().

 @Stephen: Can you please test this? I haven't as I didn't had a board. :)

 V1-V2: Almost changed completely, V1 was here: 
 https://lkml.org/lkml/2014/5/15/40

 Viresh Kumar (3):
   cpufreq: handle calls to -target_index() in separate routine
   cpufreq: add support for intermediate (stable) frequencies
   cpufreq: Tegra: implement intermediate frequency callbacks

  Documentation/cpu-freq/cpu-drivers.txt | 19 +++-
  drivers/cpufreq/cpufreq.c  | 82 
 --
  drivers/cpufreq/tegra-cpufreq.c| 81 -
  include/linux/cpufreq.h| 15 +++
  4 files changed, 128 insertions(+), 69 deletions(-)

 --
 2.0.0.rc2


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Re: [PATCH 0/2] PM / OPP: move cpufreq specific helpers out of OPP layer

[Thomas Abraham]

On Mon, May 5, 2014 at 7:03 PM, Nishanth Menon  wrote:
> CPUFreq usage of OPP should be independent of the ordering of type of
> data storage inside OPP layer. The current operations can equally be
> performed by generic operations.
>
> [RFC]: https://patchwork.kernel.org/patch/4100811/
>
> Series based on: v3.15-rc1
>
> Nishanth Menon (2):
>   PM / OPP: Remove cpufreq wrapper dependency on internal data
> organization
>   PM / OPP: Move cpufreq specific OPP functions out of generic OPP
> library
>
>  Documentation/cpu-freq/core.txt |   29 +++
>  Documentation/power/opp.txt |   40 ++
>  drivers/base/power/opp.c|   91 
>  drivers/cpufreq/Makefile|2 +
>  drivers/cpufreq/cpufreq_opp.c   |  110 
> +++
>  include/linux/cpufreq.h |   21 
>  include/linux/pm_opp.h  |   20 ---
>  7 files changed, 167 insertions(+), 146 deletions(-)
>  create mode 100644 drivers/cpufreq/cpufreq_opp.c

Works fine on Exynos.
Tested-by: Thomas Abraham 

>
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Re: [PATCH 0/2] PM / OPP: move cpufreq specific helpers out of OPP layer

[Thomas Abraham]

On Mon, May 5, 2014 at 7:03 PM, Nishanth Menon n...@ti.com wrote:
 CPUFreq usage of OPP should be independent of the ordering of type of
 data storage inside OPP layer. The current operations can equally be
 performed by generic operations.

 [RFC]: https://patchwork.kernel.org/patch/4100811/

 Series based on: v3.15-rc1

 Nishanth Menon (2):
   PM / OPP: Remove cpufreq wrapper dependency on internal data
 organization
   PM / OPP: Move cpufreq specific OPP functions out of generic OPP
 library

  Documentation/cpu-freq/core.txt |   29 +++
  Documentation/power/opp.txt |   40 ++
  drivers/base/power/opp.c|   91 
  drivers/cpufreq/Makefile|2 +
  drivers/cpufreq/cpufreq_opp.c   |  110 
 +++
  include/linux/cpufreq.h |   21 
  include/linux/pm_opp.h  |   20 ---
  7 files changed, 167 insertions(+), 146 deletions(-)
  create mode 100644 drivers/cpufreq/cpufreq_opp.c

Works fine on Exynos.
Tested-by: Thomas Abraham thomas...@samsung.com


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Re: [PATCH v2] USB: ehci-s5p: Fix phy reset

[Thomas Abraham]

On 14 March 2013 17:31, Alexander Graf  wrote:
>
> On 14.03.2013, at 05:19, Thomas Abraham wrote:
>
>> On 14 March 2013 05:29, Alexander Graf  wrote:
>>> On my Exynos 5 based Arndale system, I need to pull the reset line down
>>> and then let it go up again to actually perform a reset. Without that
>>> reset, I can't find any USB hubs on my bus, rendering the USB controller
>>> useless.
>>>
>>> We also only need to reset the line after the phy node has been found.
>>> This way we don't accidently reserve the vbus GPIO pin, but later on
>>> defer the creation of our controller, because the phy device tree node
>>> hasn't been probed yet.
>>>
>>> This patch implements the above logic, making EHCI and OHCI work on
>>> Arndale systems for me.
>>>
>>> Signed-off-by: Alexander Graf 
>>> CC: Vivek Gautam 
>>> CC: Jingoo Han 
>>> CC: Alan Stern 
>>> CC: Kukjin Kim 
>>> CC: Felipe Balbi 
>>> CC: Greg Kroah-Hartman 
>>> CC: Doug Anderson 
>>>
>>> ---
>>>
>>> v1 -> v2:
>>>
>>>  - remove gpio_free call
>>>  - move reset logic after phy node search
>>>
>>> diff --git a/drivers/usb/host/ehci-s5p.c b/drivers/usb/host/ehci-s5p.c
>>> index 20ebf6a..b29b2b8 100644
>>> --- a/drivers/usb/host/ehci-s5p.c
>>> +++ b/drivers/usb/host/ehci-s5p.c
>>> @@ -103,9 +103,14 @@ static void s5p_setup_vbus_gpio(struct platform_device 
>>> *pdev)
>>>if (!gpio_is_valid(gpio))
>>>return;
>>>
>>> -   err = gpio_request_one(gpio, GPIOF_OUT_INIT_HIGH, "ehci_vbus_gpio");
>>> -   if (err)
>>> +   /* reset pulls the line down, then up again */
>>> +   err = gpio_request_one(gpio, GPIOF_OUT_INIT_LOW, "ehci_vbus_gpio");
>>> +   if (err) {
>>>dev_err(>dev, "can't request ehci vbus gpio %d", gpio);
>>> +   return;
>>> +   }
>>> +   mdelay(1);
>>> +   __gpio_set_value(gpio, 1);
>>> }
>>>
>>> static u64 ehci_s5p_dma_mask = DMA_BIT_MASK(32);
>>> @@ -131,8 +136,6 @@ static int s5p_ehci_probe(struct platform_device *pdev)
>>>if (!pdev->dev.coherent_dma_mask)
>>>pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
>>>
>>> -   s5p_setup_vbus_gpio(pdev);
>>> -
>>>s5p_ehci = devm_kzalloc(>dev, sizeof(struct s5p_ehci_hcd),
>>>GFP_KERNEL);
>>>if (!s5p_ehci)
>>> @@ -152,6 +155,8 @@ static int s5p_ehci_probe(struct platform_device *pdev)
>>>s5p_ehci->otg = phy->otg;
>>>}
>>>
>>> +   s5p_setup_vbus_gpio(pdev);
>>> +
>>>s5p_ehci->dev = >dev;
>>>
>>>hcd = usb_create_hcd(_ehci_hc_driver, >dev,
>>
>> Hi Alexander,
>>
>> This change, though it works for Exynos5250 based Arndale board, does
>> not actually seem correct. On Arndale board, the on-board 4-port usb
>> hub is self powered and hence the vbus 'enable' gpio line from
>> Exynos5250 SoC is instead used as a "reset" signal for the on-board
>> usb hub (and not as the vbus enable signal).
>>
>> Whereas, the driver uses the gpio used in 's5p_setup_vbus_gpio'
>> function as just a mechanism to enable vbus for downstream devices. So
>> the driver should not be modified as above to handle the board
>> specific behavior.
>>
>> Instead, what needs to be done is, remove the "samsung,vbus-gpio"
>> property from the usb2.0 node in dts files (this property is optional)
>> for Arndale board. Then, during the machine_init, perform the reset
>> sequencing as required.
>>
>> Ideally, the reset sequencing for the on-board AX88760 usb hub should
>> have been handled in the driver for this device. I have not checked if
>> there is a driver for this in the kernel.
>
> I can see your point, but as I mentioned earlier there seems to be some 
> timing issue here. By simply doing the reset a few ms earlier (in the first 
> probe, before the driver detects that it needs to defer probing), I already 
> can't find the hub on the bus later.
>
> So I'm assuming that the same thing would also happen if I put it even 
> earlier in machine init.

True, I missed that point. The usb hub connected over hsic interface,
after power-on-reset, might have initiated the 'connect' state on
seeing the idle 

Re: [PATCH v2] USB: ehci-s5p: Fix phy reset

[Thomas Abraham]

On 14 March 2013 17:31, Alexander Graf ag...@suse.de wrote:

 On 14.03.2013, at 05:19, Thomas Abraham wrote:

 On 14 March 2013 05:29, Alexander Graf ag...@suse.de wrote:
 On my Exynos 5 based Arndale system, I need to pull the reset line down
 and then let it go up again to actually perform a reset. Without that
 reset, I can't find any USB hubs on my bus, rendering the USB controller
 useless.

 We also only need to reset the line after the phy node has been found.
 This way we don't accidently reserve the vbus GPIO pin, but later on
 defer the creation of our controller, because the phy device tree node
 hasn't been probed yet.

 This patch implements the above logic, making EHCI and OHCI work on
 Arndale systems for me.

 Signed-off-by: Alexander Graf ag...@suse.de
 CC: Vivek Gautam gautam.vi...@samsung.com
 CC: Jingoo Han jg1@samsung.com
 CC: Alan Stern st...@rowland.harvard.edu
 CC: Kukjin Kim kgene@samsung.com
 CC: Felipe Balbi ba...@ti.com
 CC: Greg Kroah-Hartman gre...@linuxfoundation.org
 CC: Doug Anderson diand...@chromium.org

 ---

 v1 - v2:

  - remove gpio_free call
  - move reset logic after phy node search

 diff --git a/drivers/usb/host/ehci-s5p.c b/drivers/usb/host/ehci-s5p.c
 index 20ebf6a..b29b2b8 100644
 --- a/drivers/usb/host/ehci-s5p.c
 +++ b/drivers/usb/host/ehci-s5p.c
 @@ -103,9 +103,14 @@ static void s5p_setup_vbus_gpio(struct platform_device 
 *pdev)
if (!gpio_is_valid(gpio))
return;

 -   err = gpio_request_one(gpio, GPIOF_OUT_INIT_HIGH, ehci_vbus_gpio);
 -   if (err)
 +   /* reset pulls the line down, then up again */
 +   err = gpio_request_one(gpio, GPIOF_OUT_INIT_LOW, ehci_vbus_gpio);
 +   if (err) {
dev_err(pdev-dev, can't request ehci vbus gpio %d, gpio);
 +   return;
 +   }
 +   mdelay(1);
 +   __gpio_set_value(gpio, 1);
 }

 static u64 ehci_s5p_dma_mask = DMA_BIT_MASK(32);
 @@ -131,8 +136,6 @@ static int s5p_ehci_probe(struct platform_device *pdev)
if (!pdev-dev.coherent_dma_mask)
pdev-dev.coherent_dma_mask = DMA_BIT_MASK(32);

 -   s5p_setup_vbus_gpio(pdev);
 -
s5p_ehci = devm_kzalloc(pdev-dev, sizeof(struct s5p_ehci_hcd),
GFP_KERNEL);
if (!s5p_ehci)
 @@ -152,6 +155,8 @@ static int s5p_ehci_probe(struct platform_device *pdev)
s5p_ehci-otg = phy-otg;
}

 +   s5p_setup_vbus_gpio(pdev);
 +
s5p_ehci-dev = pdev-dev;

hcd = usb_create_hcd(s5p_ehci_hc_driver, pdev-dev,

 Hi Alexander,

 This change, though it works for Exynos5250 based Arndale board, does
 not actually seem correct. On Arndale board, the on-board 4-port usb
 hub is self powered and hence the vbus 'enable' gpio line from
 Exynos5250 SoC is instead used as a reset signal for the on-board
 usb hub (and not as the vbus enable signal).

 Whereas, the driver uses the gpio used in 's5p_setup_vbus_gpio'
 function as just a mechanism to enable vbus for downstream devices. So
 the driver should not be modified as above to handle the board
 specific behavior.

 Instead, what needs to be done is, remove the samsung,vbus-gpio
 property from the usb2.0 node in dts files (this property is optional)
 for Arndale board. Then, during the machine_init, perform the reset
 sequencing as required.

 Ideally, the reset sequencing for the on-board AX88760 usb hub should
 have been handled in the driver for this device. I have not checked if
 there is a driver for this in the kernel.

 I can see your point, but as I mentioned earlier there seems to be some 
 timing issue here. By simply doing the reset a few ms earlier (in the first 
 probe, before the driver detects that it needs to defer probing), I already 
 can't find the hub on the bus later.

 So I'm assuming that the same thing would also happen if I put it even 
 earlier in machine init.

True, I missed that point. The usb hub connected over hsic interface,
after power-on-reset, might have initiated the 'connect' state on
seeing the idle condition on the bus and since the host/phy controller
is not ready yet, the connect might have failed.

So the correct sequence would be, after the usb host controller and
the phy controllers are initialized, the 'reset' pin on the on-board
usb hub should be asserted. Upon releasing that reset, the usb hub
would initiate the 'connect' state on the HSIC bus.


 The change in this patch actually does a reset even on non-Arndale boards. By 
 taking away power and returning power to the line, the chip will most likely 
 have reset :). So even on non-Arndale boards, this should get the USB phy 
 into a clean state regardless of where the bootloader left it, right?


No, the toggling of the vbus cannot ensure hardware-reset on self
powered devices. On Arndale board, since the usb hub is self powered
and being on HSIC interface, the dedicated vbus control gpio line is
instead used to assert the 'reset' pin of the on-board usb hub.

Using

Re: [PATCH v2] USB: ehci-s5p: Fix phy reset

[Thomas Abraham]

On 14 March 2013 05:29, Alexander Graf  wrote:
> On my Exynos 5 based Arndale system, I need to pull the reset line down
> and then let it go up again to actually perform a reset. Without that
> reset, I can't find any USB hubs on my bus, rendering the USB controller
> useless.
>
> We also only need to reset the line after the phy node has been found.
> This way we don't accidently reserve the vbus GPIO pin, but later on
> defer the creation of our controller, because the phy device tree node
> hasn't been probed yet.
>
> This patch implements the above logic, making EHCI and OHCI work on
> Arndale systems for me.
>
> Signed-off-by: Alexander Graf 
> CC: Vivek Gautam 
> CC: Jingoo Han 
> CC: Alan Stern 
> CC: Kukjin Kim 
> CC: Felipe Balbi 
> CC: Greg Kroah-Hartman 
> CC: Doug Anderson 
>
> ---
>
> v1 -> v2:
>
>   - remove gpio_free call
>   - move reset logic after phy node search
>
> diff --git a/drivers/usb/host/ehci-s5p.c b/drivers/usb/host/ehci-s5p.c
> index 20ebf6a..b29b2b8 100644
> --- a/drivers/usb/host/ehci-s5p.c
> +++ b/drivers/usb/host/ehci-s5p.c
> @@ -103,9 +103,14 @@ static void s5p_setup_vbus_gpio(struct platform_device 
> *pdev)
> if (!gpio_is_valid(gpio))
> return;
>
> -   err = gpio_request_one(gpio, GPIOF_OUT_INIT_HIGH, "ehci_vbus_gpio");
> -   if (err)
> +   /* reset pulls the line down, then up again */
> +   err = gpio_request_one(gpio, GPIOF_OUT_INIT_LOW, "ehci_vbus_gpio");
> +   if (err) {
> dev_err(>dev, "can't request ehci vbus gpio %d", gpio);
> +   return;
> +   }
> +   mdelay(1);
> +   __gpio_set_value(gpio, 1);
>  }
>
>  static u64 ehci_s5p_dma_mask = DMA_BIT_MASK(32);
> @@ -131,8 +136,6 @@ static int s5p_ehci_probe(struct platform_device *pdev)
> if (!pdev->dev.coherent_dma_mask)
> pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
>
> -   s5p_setup_vbus_gpio(pdev);
> -
> s5p_ehci = devm_kzalloc(>dev, sizeof(struct s5p_ehci_hcd),
> GFP_KERNEL);
> if (!s5p_ehci)
> @@ -152,6 +155,8 @@ static int s5p_ehci_probe(struct platform_device *pdev)
> s5p_ehci->otg = phy->otg;
> }
>
> +   s5p_setup_vbus_gpio(pdev);
> +
> s5p_ehci->dev = >dev;
>
> hcd = usb_create_hcd(_ehci_hc_driver, >dev,

Hi Alexander,

This change, though it works for Exynos5250 based Arndale board, does
not actually seem correct. On Arndale board, the on-board 4-port usb
hub is self powered and hence the vbus 'enable' gpio line from
Exynos5250 SoC is instead used as a "reset" signal for the on-board
usb hub (and not as the vbus enable signal).

Whereas, the driver uses the gpio used in 's5p_setup_vbus_gpio'
function as just a mechanism to enable vbus for downstream devices. So
the driver should not be modified as above to handle the board
specific behavior.

Instead, what needs to be done is, remove the "samsung,vbus-gpio"
property from the usb2.0 node in dts files (this property is optional)
for Arndale board. Then, during the machine_init, perform the reset
sequencing as required.

Ideally, the reset sequencing for the on-board AX88760 usb hub should
have been handled in the driver for this device. I have not checked if
there is a driver for this in the kernel.

Thanks,
Thomas.

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Re: [PATCH v2] USB: ehci-s5p: Fix phy reset

[Thomas Abraham]

On 14 March 2013 05:29, Alexander Graf ag...@suse.de wrote:
 On my Exynos 5 based Arndale system, I need to pull the reset line down
 and then let it go up again to actually perform a reset. Without that
 reset, I can't find any USB hubs on my bus, rendering the USB controller
 useless.

 We also only need to reset the line after the phy node has been found.
 This way we don't accidently reserve the vbus GPIO pin, but later on
 defer the creation of our controller, because the phy device tree node
 hasn't been probed yet.

 This patch implements the above logic, making EHCI and OHCI work on
 Arndale systems for me.

 Signed-off-by: Alexander Graf ag...@suse.de
 CC: Vivek Gautam gautam.vi...@samsung.com
 CC: Jingoo Han jg1@samsung.com
 CC: Alan Stern st...@rowland.harvard.edu
 CC: Kukjin Kim kgene@samsung.com
 CC: Felipe Balbi ba...@ti.com
 CC: Greg Kroah-Hartman gre...@linuxfoundation.org
 CC: Doug Anderson diand...@chromium.org

 ---

 v1 - v2:

   - remove gpio_free call
   - move reset logic after phy node search

 diff --git a/drivers/usb/host/ehci-s5p.c b/drivers/usb/host/ehci-s5p.c
 index 20ebf6a..b29b2b8 100644
 --- a/drivers/usb/host/ehci-s5p.c
 +++ b/drivers/usb/host/ehci-s5p.c
 @@ -103,9 +103,14 @@ static void s5p_setup_vbus_gpio(struct platform_device 
 *pdev)
 if (!gpio_is_valid(gpio))
 return;

 -   err = gpio_request_one(gpio, GPIOF_OUT_INIT_HIGH, ehci_vbus_gpio);
 -   if (err)
 +   /* reset pulls the line down, then up again */
 +   err = gpio_request_one(gpio, GPIOF_OUT_INIT_LOW, ehci_vbus_gpio);
 +   if (err) {
 dev_err(pdev-dev, can't request ehci vbus gpio %d, gpio);
 +   return;
 +   }
 +   mdelay(1);
 +   __gpio_set_value(gpio, 1);
  }

  static u64 ehci_s5p_dma_mask = DMA_BIT_MASK(32);
 @@ -131,8 +136,6 @@ static int s5p_ehci_probe(struct platform_device *pdev)
 if (!pdev-dev.coherent_dma_mask)
 pdev-dev.coherent_dma_mask = DMA_BIT_MASK(32);

 -   s5p_setup_vbus_gpio(pdev);
 -
 s5p_ehci = devm_kzalloc(pdev-dev, sizeof(struct s5p_ehci_hcd),
 GFP_KERNEL);
 if (!s5p_ehci)
 @@ -152,6 +155,8 @@ static int s5p_ehci_probe(struct platform_device *pdev)
 s5p_ehci-otg = phy-otg;
 }

 +   s5p_setup_vbus_gpio(pdev);
 +
 s5p_ehci-dev = pdev-dev;

 hcd = usb_create_hcd(s5p_ehci_hc_driver, pdev-dev,

Hi Alexander,

This change, though it works for Exynos5250 based Arndale board, does
not actually seem correct. On Arndale board, the on-board 4-port usb
hub is self powered and hence the vbus 'enable' gpio line from
Exynos5250 SoC is instead used as a reset signal for the on-board
usb hub (and not as the vbus enable signal).

Whereas, the driver uses the gpio used in 's5p_setup_vbus_gpio'
function as just a mechanism to enable vbus for downstream devices. So
the driver should not be modified as above to handle the board
specific behavior.

Instead, what needs to be done is, remove the samsung,vbus-gpio
property from the usb2.0 node in dts files (this property is optional)
for Arndale board. Then, during the machine_init, perform the reset
sequencing as required.

Ideally, the reset sequencing for the on-board AX88760 usb hub should
have been handled in the driver for this device. I have not checked if
there is a driver for this in the kernel.

Thanks,
Thomas.

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Re: [PATCH v2 0/3] pinctrl: exynos: add support for Samsung's Exynos5250

[Thomas Abraham]

On 7 March 2013 05:41, Kukjin Kim  wrote:
> Thomas Abraham wrote:
>>
>> Changes since v1:
>> - Change the compatible string from "samsung,pinctrl-exynos5250" to
>>   "samsung,exynos5250-pinctrl".
>> - Rebased to v3.9-rc1
>>
>
> Thomas, this stuff is already in my tree for v3.10, and above changes
> included in there. Do you want to replace with this patches?

Dear Mr. Kim,

The v2 version includes one fix for the compatilble string. It changes
the compatible string from "samsung,pinctrl-exynos5250" to
"samsung,exynos5250-pinctrl". So could you pick this v2 series instead
of the series which you have already merged.

Thanks,
Thomas.

>
> - Kukjin
>
>> This patch series add pinctrl driver support for Samsung's Exynos5250 SoC.
>> The first patch adds the required Exynos5250 SoC specific data which is
>> used by the Samsung pinctrl driver to setup the pinctrl/pinmux/eint
>> controllers. The second and third patches skips the wakeup interrupt and
>> gpiolib registration if the pinctrl support is enabled for Exynos5250.
>>
>> Thomas Abraham (3):
>>   pinctrl: exynos: add exynos5250 SoC specific data
>>   gpio: samsung: skip gpiolib registration if pinctrl support is enabled
>> for exynos5250
>>   arm: exynos: skip wakeup interrupt registration for exynos5250 if
>> pinctrl is enabled
>>
>>  arch/arm/mach-exynos/common.c |1 +
>>  drivers/gpio/gpio-samsung.c   |1 +
>>  drivers/pinctrl/pinctrl-exynos.c  |  108
>> +
>>  drivers/pinctrl/pinctrl-samsung.c |2 +
>>  drivers/pinctrl/pinctrl-samsung.h |1 +
>>  5 files changed, 113 insertions(+), 0 deletions(-)
>
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[PATCH v2 1/3] pinctrl: exynos: add exynos5250 SoC specific data

[Thomas Abraham]

Add Samsung Exynos5250 SoC specific data to enable pinctrl support for
all platforms based on Exynos5250.

Signed-off-by: Thomas Abraham 
Reviewed-by: Tomasz Figa 
Acked-by: Linus Walleij 
---
 drivers/pinctrl/pinctrl-exynos.c  |  108 +
 drivers/pinctrl/pinctrl-samsung.c |2 +
 drivers/pinctrl/pinctrl-samsung.h |1 +
 3 files changed, 111 insertions(+), 0 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c
index 538b9dd..8738933 100644
--- a/drivers/pinctrl/pinctrl-exynos.c
+++ b/drivers/pinctrl/pinctrl-exynos.c
@@ -677,3 +677,111 @@ struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = {
.label  = "exynos4x12-gpio-ctrl3",
},
 };
+
+/* pin banks of exynos5250 pin-controller 0 */
+static struct samsung_pin_bank exynos5250_pin_banks0[] = {
+   EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
+   EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
+   EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
+   EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
+   EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
+   EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
+   EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18),
+   EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c),
+   EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc1", 0x20),
+   EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc2", 0x24),
+   EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc3", 0x28),
+   EXYNOS_PIN_BANK_EINTG(4, 0x160, "gpd0", 0x2c),
+   EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x30),
+   EXYNOS_PIN_BANK_EINTG(7, 0x2E0, "gpc4", 0x34),
+   EXYNOS_PIN_BANK_EINTN(6, 0x1A0, "gpy0"),
+   EXYNOS_PIN_BANK_EINTN(4, 0x1C0, "gpy1"),
+   EXYNOS_PIN_BANK_EINTN(6, 0x1E0, "gpy2"),
+   EXYNOS_PIN_BANK_EINTN(8, 0x200, "gpy3"),
+   EXYNOS_PIN_BANK_EINTN(8, 0x220, "gpy4"),
+   EXYNOS_PIN_BANK_EINTN(8, 0x240, "gpy5"),
+   EXYNOS_PIN_BANK_EINTN(8, 0x260, "gpy6"),
+   EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
+   EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
+   EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
+   EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
+};
+
+/* pin banks of exynos5250 pin-controller 1 */
+static struct samsung_pin_bank exynos5250_pin_banks1[] = {
+   EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00),
+   EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04),
+   EXYNOS_PIN_BANK_EINTG(4, 0x040, "gpf0", 0x08),
+   EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf1", 0x0c),
+   EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10),
+   EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14),
+   EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18),
+   EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gph0", 0x1c),
+   EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph1", 0x20),
+};
+
+/* pin banks of exynos5250 pin-controller 2 */
+static struct samsung_pin_bank exynos5250_pin_banks2[] = {
+   EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
+   EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
+   EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08),
+   EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c),
+   EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10),
+};
+
+/* pin banks of exynos5250 pin-controller 3 */
+static struct samsung_pin_bank exynos5250_pin_banks3[] = {
+   EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
+};
+
+/*
+ * Samsung pinctrl driver data for Exynos5250 SoC. Exynos5250 SoC includes
+ * four gpio/pin-mux/pinconfig controllers.
+ */
+struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
+   {
+   /* pin-controller instance 0 data */
+   .pin_banks  = exynos5250_pin_banks0,
+   .nr_banks   = ARRAY_SIZE(exynos5250_pin_banks0),
+   .geint_con  = EXYNOS_GPIO_ECON_OFFSET,
+   .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
+   .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
+   .weint_con  = EXYNOS_WKUP_ECON_OFFSET,
+   .weint_mask = EXYNOS_WKUP_EMASK_OFFSET,
+   .weint_pend = EXYNOS_WKUP_EPEND_OFFSET,
+   .svc= EXYNOS_SVC_OFFSET,
+   .eint_gpio_init = exynos_eint_gpio_init,
+   .eint_wkup_init = exynos_eint_wkup_init,
+   .label  = "exynos5250-gpio-ctrl0",
+   }, {
+   /* pin-controller instance 1 data */
+   .pin_banks  = exynos5250_pin_banks1,
+   .nr_banks   = ARRAY_SIZE(exynos5250_pin_banks1),
+   .geint_con  = EXYNOS_GPIO_ECO

[PATCH v2 3/3] arm: exynos: skip wakeup interrupt registration for exynos5250 if pinctrl is enabled

[Thomas Abraham]

Skip the wakeup interrupt registration for Exynos5250 if pinctrl support
is enabled for Exynos5250.

Signed-off-by: Thomas Abraham 
Reviewed-by: Tomasz Figa 
Acked-by: Linus Walleij 
---
 arch/arm/mach-exynos/common.c |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index d63d399..bdd9579 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -822,6 +822,7 @@ static int __init exynos_init_irq_eint(void)
static const struct of_device_id exynos_pinctrl_ids[] = {
{ .compatible = "samsung,exynos4210-pinctrl", },
{ .compatible = "samsung,exynos4x12-pinctrl", },
+   { .compatible = "samsung,exynos5250-pinctrl", },
};
struct device_node *pctrl_np, *wkup_np;
const char *wkup_compat = "samsung,exynos4210-wakeup-eint";
-- 
1.6.6.rc2

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[PATCH v2 2/3] gpio: samsung: skip gpiolib registration if pinctrl support is enabled for exynos5250

[Thomas Abraham]

Skip exynos5250 gpiolib registration if pinctrl support for exynos5250
is enabled.

Signed-off-by: Thomas Abraham 
Reviewed-by: Tomasz Figa 
Acked-by: Linus Walleij 
---
 drivers/gpio/gpio-samsung.c |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
index b3643ff..49b4292 100644
--- a/drivers/gpio/gpio-samsung.c
+++ b/drivers/gpio/gpio-samsung.c
@@ -3024,6 +3024,7 @@ static __init int samsung_gpiolib_init(void)
static const struct of_device_id exynos_pinctrl_ids[] = {
{ .compatible = "samsung,exynos4210-pinctrl", },
{ .compatible = "samsung,exynos4x12-pinctrl", },
+   { .compatible = "samsung,exynos5250-pinctrl", },
{ .compatible = "samsung,exynos5440-pinctrl", },
};
for_each_matching_node(pctrl_np, exynos_pinctrl_ids)
-- 
1.6.6.rc2

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[PATCH v2 0/3] pinctrl: exynos: add support for Samsung's Exynos5250

[Thomas Abraham]

Changes since v1:
- Change the compatible string from "samsung,pinctrl-exynos5250" to
  "samsung,exynos5250-pinctrl".
- Rebased to v3.9-rc1

This patch series add pinctrl driver support for Samsung's Exynos5250 SoC.
The first patch adds the required Exynos5250 SoC specific data which is
used by the Samsung pinctrl driver to setup the pinctrl/pinmux/eint
controllers. The second and third patches skips the wakeup interrupt and
gpiolib registration if the pinctrl support is enabled for Exynos5250.

Thomas Abraham (3):
  pinctrl: exynos: add exynos5250 SoC specific data
  gpio: samsung: skip gpiolib registration if pinctrl support is enabled for 
exynos5250
  arm: exynos: skip wakeup interrupt registration for exynos5250 if pinctrl is 
enabled

 arch/arm/mach-exynos/common.c |1 +
 drivers/gpio/gpio-samsung.c   |1 +
 drivers/pinctrl/pinctrl-exynos.c  |  108 +
 drivers/pinctrl/pinctrl-samsung.c |2 +
 drivers/pinctrl/pinctrl-samsung.h |1 +
 5 files changed, 113 insertions(+), 0 deletions(-)

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[PATCH v2 0/3] pinctrl: exynos: add support for Samsung's Exynos5250

[Thomas Abraham]

Changes since v1:
- Change the compatible string from samsung,pinctrl-exynos5250 to
  samsung,exynos5250-pinctrl.
- Rebased to v3.9-rc1

This patch series add pinctrl driver support for Samsung's Exynos5250 SoC.
The first patch adds the required Exynos5250 SoC specific data which is
used by the Samsung pinctrl driver to setup the pinctrl/pinmux/eint
controllers. The second and third patches skips the wakeup interrupt and
gpiolib registration if the pinctrl support is enabled for Exynos5250.

Thomas Abraham (3):
  pinctrl: exynos: add exynos5250 SoC specific data
  gpio: samsung: skip gpiolib registration if pinctrl support is enabled for 
exynos5250
  arm: exynos: skip wakeup interrupt registration for exynos5250 if pinctrl is 
enabled

 arch/arm/mach-exynos/common.c |1 +
 drivers/gpio/gpio-samsung.c   |1 +
 drivers/pinctrl/pinctrl-exynos.c  |  108 +
 drivers/pinctrl/pinctrl-samsung.c |2 +
 drivers/pinctrl/pinctrl-samsung.h |1 +
 5 files changed, 113 insertions(+), 0 deletions(-)

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[PATCH v2 2/3] gpio: samsung: skip gpiolib registration if pinctrl support is enabled for exynos5250

[Thomas Abraham]

Skip exynos5250 gpiolib registration if pinctrl support for exynos5250
is enabled.

Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
Reviewed-by: Tomasz Figa t.f...@samsung.com
Acked-by: Linus Walleij linus.wall...@linaro.org
---
 drivers/gpio/gpio-samsung.c |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
index b3643ff..49b4292 100644
--- a/drivers/gpio/gpio-samsung.c
+++ b/drivers/gpio/gpio-samsung.c
@@ -3024,6 +3024,7 @@ static __init int samsung_gpiolib_init(void)
static const struct of_device_id exynos_pinctrl_ids[] = {
{ .compatible = samsung,exynos4210-pinctrl, },
{ .compatible = samsung,exynos4x12-pinctrl, },
+   { .compatible = samsung,exynos5250-pinctrl, },
{ .compatible = samsung,exynos5440-pinctrl, },
};
for_each_matching_node(pctrl_np, exynos_pinctrl_ids)
-- 
1.6.6.rc2

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[PATCH v2 3/3] arm: exynos: skip wakeup interrupt registration for exynos5250 if pinctrl is enabled

[Thomas Abraham]

Skip the wakeup interrupt registration for Exynos5250 if pinctrl support
is enabled for Exynos5250.

Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
Reviewed-by: Tomasz Figa t.f...@samsung.com
Acked-by: Linus Walleij linus.wall...@linaro.org
---
 arch/arm/mach-exynos/common.c |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index d63d399..bdd9579 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -822,6 +822,7 @@ static int __init exynos_init_irq_eint(void)
static const struct of_device_id exynos_pinctrl_ids[] = {
{ .compatible = samsung,exynos4210-pinctrl, },
{ .compatible = samsung,exynos4x12-pinctrl, },
+   { .compatible = samsung,exynos5250-pinctrl, },
};
struct device_node *pctrl_np, *wkup_np;
const char *wkup_compat = samsung,exynos4210-wakeup-eint;
-- 
1.6.6.rc2

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[PATCH v2 1/3] pinctrl: exynos: add exynos5250 SoC specific data

[Thomas Abraham]

Add Samsung Exynos5250 SoC specific data to enable pinctrl support for
all platforms based on Exynos5250.

Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
Reviewed-by: Tomasz Figa t.f...@samsung.com
Acked-by: Linus Walleij linus.wall...@linaro.org
---
 drivers/pinctrl/pinctrl-exynos.c  |  108 +
 drivers/pinctrl/pinctrl-samsung.c |2 +
 drivers/pinctrl/pinctrl-samsung.h |1 +
 3 files changed, 111 insertions(+), 0 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c
index 538b9dd..8738933 100644
--- a/drivers/pinctrl/pinctrl-exynos.c
+++ b/drivers/pinctrl/pinctrl-exynos.c
@@ -677,3 +677,111 @@ struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = {
.label  = exynos4x12-gpio-ctrl3,
},
 };
+
+/* pin banks of exynos5250 pin-controller 0 */
+static struct samsung_pin_bank exynos5250_pin_banks0[] = {
+   EXYNOS_PIN_BANK_EINTG(8, 0x000, gpa0, 0x00),
+   EXYNOS_PIN_BANK_EINTG(6, 0x020, gpa1, 0x04),
+   EXYNOS_PIN_BANK_EINTG(8, 0x040, gpa2, 0x08),
+   EXYNOS_PIN_BANK_EINTG(5, 0x060, gpb0, 0x0c),
+   EXYNOS_PIN_BANK_EINTG(5, 0x080, gpb1, 0x10),
+   EXYNOS_PIN_BANK_EINTG(4, 0x0A0, gpb2, 0x14),
+   EXYNOS_PIN_BANK_EINTG(4, 0x0C0, gpb3, 0x18),
+   EXYNOS_PIN_BANK_EINTG(7, 0x0E0, gpc0, 0x1c),
+   EXYNOS_PIN_BANK_EINTG(4, 0x100, gpc1, 0x20),
+   EXYNOS_PIN_BANK_EINTG(7, 0x120, gpc2, 0x24),
+   EXYNOS_PIN_BANK_EINTG(7, 0x140, gpc3, 0x28),
+   EXYNOS_PIN_BANK_EINTG(4, 0x160, gpd0, 0x2c),
+   EXYNOS_PIN_BANK_EINTG(8, 0x180, gpd1, 0x30),
+   EXYNOS_PIN_BANK_EINTG(7, 0x2E0, gpc4, 0x34),
+   EXYNOS_PIN_BANK_EINTN(6, 0x1A0, gpy0),
+   EXYNOS_PIN_BANK_EINTN(4, 0x1C0, gpy1),
+   EXYNOS_PIN_BANK_EINTN(6, 0x1E0, gpy2),
+   EXYNOS_PIN_BANK_EINTN(8, 0x200, gpy3),
+   EXYNOS_PIN_BANK_EINTN(8, 0x220, gpy4),
+   EXYNOS_PIN_BANK_EINTN(8, 0x240, gpy5),
+   EXYNOS_PIN_BANK_EINTN(8, 0x260, gpy6),
+   EXYNOS_PIN_BANK_EINTW(8, 0xC00, gpx0, 0x00),
+   EXYNOS_PIN_BANK_EINTW(8, 0xC20, gpx1, 0x04),
+   EXYNOS_PIN_BANK_EINTW(8, 0xC40, gpx2, 0x08),
+   EXYNOS_PIN_BANK_EINTW(8, 0xC60, gpx3, 0x0c),
+};
+
+/* pin banks of exynos5250 pin-controller 1 */
+static struct samsung_pin_bank exynos5250_pin_banks1[] = {
+   EXYNOS_PIN_BANK_EINTG(8, 0x000, gpe0, 0x00),
+   EXYNOS_PIN_BANK_EINTG(2, 0x020, gpe1, 0x04),
+   EXYNOS_PIN_BANK_EINTG(4, 0x040, gpf0, 0x08),
+   EXYNOS_PIN_BANK_EINTG(4, 0x060, gpf1, 0x0c),
+   EXYNOS_PIN_BANK_EINTG(8, 0x080, gpg0, 0x10),
+   EXYNOS_PIN_BANK_EINTG(8, 0x0A0, gpg1, 0x14),
+   EXYNOS_PIN_BANK_EINTG(2, 0x0C0, gpg2, 0x18),
+   EXYNOS_PIN_BANK_EINTG(4, 0x0E0, gph0, 0x1c),
+   EXYNOS_PIN_BANK_EINTG(8, 0x100, gph1, 0x20),
+};
+
+/* pin banks of exynos5250 pin-controller 2 */
+static struct samsung_pin_bank exynos5250_pin_banks2[] = {
+   EXYNOS_PIN_BANK_EINTG(8, 0x000, gpv0, 0x00),
+   EXYNOS_PIN_BANK_EINTG(8, 0x020, gpv1, 0x04),
+   EXYNOS_PIN_BANK_EINTG(8, 0x060, gpv2, 0x08),
+   EXYNOS_PIN_BANK_EINTG(8, 0x080, gpv3, 0x0c),
+   EXYNOS_PIN_BANK_EINTG(2, 0x0C0, gpv4, 0x10),
+};
+
+/* pin banks of exynos5250 pin-controller 3 */
+static struct samsung_pin_bank exynos5250_pin_banks3[] = {
+   EXYNOS_PIN_BANK_EINTG(7, 0x000, gpz, 0x00),
+};
+
+/*
+ * Samsung pinctrl driver data for Exynos5250 SoC. Exynos5250 SoC includes
+ * four gpio/pin-mux/pinconfig controllers.
+ */
+struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
+   {
+   /* pin-controller instance 0 data */
+   .pin_banks  = exynos5250_pin_banks0,
+   .nr_banks   = ARRAY_SIZE(exynos5250_pin_banks0),
+   .geint_con  = EXYNOS_GPIO_ECON_OFFSET,
+   .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
+   .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
+   .weint_con  = EXYNOS_WKUP_ECON_OFFSET,
+   .weint_mask = EXYNOS_WKUP_EMASK_OFFSET,
+   .weint_pend = EXYNOS_WKUP_EPEND_OFFSET,
+   .svc= EXYNOS_SVC_OFFSET,
+   .eint_gpio_init = exynos_eint_gpio_init,
+   .eint_wkup_init = exynos_eint_wkup_init,
+   .label  = exynos5250-gpio-ctrl0,
+   }, {
+   /* pin-controller instance 1 data */
+   .pin_banks  = exynos5250_pin_banks1,
+   .nr_banks   = ARRAY_SIZE(exynos5250_pin_banks1),
+   .geint_con  = EXYNOS_GPIO_ECON_OFFSET,
+   .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
+   .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
+   .svc= EXYNOS_SVC_OFFSET,
+   .eint_gpio_init = exynos_eint_gpio_init,
+   .label  = exynos5250-gpio-ctrl1,
+   }, {
+   /* pin-controller instance 2 data */
+   .pin_banks  = exynos5250_pin_banks2,
+   .nr_banks

Re: [PATCH v2 0/3] pinctrl: exynos: add support for Samsung's Exynos5250

[Thomas Abraham]

On 7 March 2013 05:41, Kukjin Kim kgene@samsung.com wrote:
 Thomas Abraham wrote:

 Changes since v1:
 - Change the compatible string from samsung,pinctrl-exynos5250 to
   samsung,exynos5250-pinctrl.
 - Rebased to v3.9-rc1


 Thomas, this stuff is already in my tree for v3.10, and above changes
 included in there. Do you want to replace with this patches?

Dear Mr. Kim,

The v2 version includes one fix for the compatilble string. It changes
the compatible string from samsung,pinctrl-exynos5250 to
samsung,exynos5250-pinctrl. So could you pick this v2 series instead
of the series which you have already merged.

Thanks,
Thomas.


 - Kukjin

 This patch series add pinctrl driver support for Samsung's Exynos5250 SoC.
 The first patch adds the required Exynos5250 SoC specific data which is
 used by the Samsung pinctrl driver to setup the pinctrl/pinmux/eint
 controllers. The second and third patches skips the wakeup interrupt and
 gpiolib registration if the pinctrl support is enabled for Exynos5250.

 Thomas Abraham (3):
   pinctrl: exynos: add exynos5250 SoC specific data
   gpio: samsung: skip gpiolib registration if pinctrl support is enabled
 for exynos5250
   arm: exynos: skip wakeup interrupt registration for exynos5250 if
 pinctrl is enabled

  arch/arm/mach-exynos/common.c |1 +
  drivers/gpio/gpio-samsung.c   |1 +
  drivers/pinctrl/pinctrl-exynos.c  |  108
 +
  drivers/pinctrl/pinctrl-samsung.c |2 +
  drivers/pinctrl/pinctrl-samsung.h |1 +
  5 files changed, 113 insertions(+), 0 deletions(-)

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Re: [PATCH 1/3] pinctrl: exynos: add exynos5250 SoC specific data

[Thomas Abraham]

On 27 December 2012 22:28, Kukjin Kim  wrote:
> Thomas Abraham wrote:
>>
>> Hi Linus,
>>
>> On 14 December 2012 21:21, Linus Walleij  wrote:
>> > On Thu, Dec 13, 2012 at 12:54 PM, Thomas Abraham
>> >  wrote:
>> >
>> >> Add Samsung Exynos5250 SoC specific data to enable pinctrl support for
>> >> all platforms based on Exynos5250.
>> >>
>> >> Signed-off-by: Thomas Abraham 
>> >
>> > Acked-by: Linus Walleij 
>> >
>> > For this series, I guess you'll fix it through the Samsung tree?
>>
>> Thanks for your ack. Since there are patches to be prepared for
>> migrating the rest of Exynos5250 related code to the pinctrl
>> framework, it would be easier if this series goes through the Samsung
>> tree.
>>
> I applied this series, thanks.

This series has not made it into 3.9-rc1. So I will rebase this series
to 3.9-rc1 and post again.

Thanks,
Thomas.

>
> And I think, would be clear if the config could be changed like following.
>
> 8<--
> From: Kukjin Kim 
> Subject: [PATCH] pinctrl: exynos: change PINCTRL_EXYNOS option
>
> Since pinctrl-exynos can support exynos4 and exynos5 so changed
> the option name to PINCTRL_EXYNOS for more clarity.
>
> Cc: Thomas Abraham 
> Cc: Linus Walleij 
> Cc: Grant Likely 
> Signed-off-by: Kukjin Kim 
> ---
> diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
> index 91d5b6f..e1f63e7 100644
> --- a/arch/arm/mach-exynos/Kconfig
> +++ b/arch/arm/mach-exynos/Kconfig
> @@ -412,7 +412,7 @@ config MACH_EXYNOS4_DT
> select CPU_EXYNOS4210
> select HAVE_SAMSUNG_KEYPAD if INPUT_KEYBOARD
> select PINCTRL
> -   select PINCTRL_EXYNOS4
> +   select PINCTRL_EXYNOS
> select USE_OF
> help
>   Machine support for Samsung Exynos4 machine with device tree
> enabled.
> diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
> index c31aeb0..f59feab 100644
> --- a/drivers/pinctrl/Kconfig
> +++ b/drivers/pinctrl/Kconfig
> @@ -185,8 +185,8 @@ config PINCTRL_SAMSUNG
> select PINMUX
> select PINCONF
>
> -config PINCTRL_EXYNOS4
> -   bool "Pinctrl driver data for Exynos4 SoC"
> +config PINCTRL_EXYNOS
> +   bool "Pinctrl driver data for Samsung EXYNOS SoCs"
> depends on OF && GPIOLIB
> select PINCTRL_SAMSUNG
>
> diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
> index fc4606f..6e87e52 100644
> --- a/drivers/pinctrl/Makefile
> +++ b/drivers/pinctrl/Makefile
> @@ -36,7 +36,7 @@ obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o
>  obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o
>  obj-$(CONFIG_PINCTRL_COH901)   += pinctrl-coh901.o
>  obj-$(CONFIG_PINCTRL_SAMSUNG)  += pinctrl-samsung.o
> -obj-$(CONFIG_PINCTRL_EXYNOS4)  += pinctrl-exynos.o
> +obj-$(CONFIG_PINCTRL_EXYNOS)   += pinctrl-exynos.o
>  obj-$(CONFIG_PINCTRL_EXYNOS5440)   += pinctrl-exynos5440.o
>  obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o
>  obj-$(CONFIG_PINCTRL_LANTIQ)   += pinctrl-lantiq.o
> 8<--
>
> - Kukjin
>
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Re: [PATCH 1/3] pinctrl: exynos: add exynos5250 SoC specific data

[Thomas Abraham]

On 27 December 2012 22:28, Kukjin Kim kgene@samsung.com wrote:
 Thomas Abraham wrote:

 Hi Linus,

 On 14 December 2012 21:21, Linus Walleij linus.wall...@linaro.org wrote:
  On Thu, Dec 13, 2012 at 12:54 PM, Thomas Abraham
  thomas.abra...@linaro.org wrote:
 
  Add Samsung Exynos5250 SoC specific data to enable pinctrl support for
  all platforms based on Exynos5250.
 
  Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
 
  Acked-by: Linus Walleij linus.wall...@linaro.org
 
  For this series, I guess you'll fix it through the Samsung tree?

 Thanks for your ack. Since there are patches to be prepared for
 migrating the rest of Exynos5250 related code to the pinctrl
 framework, it would be easier if this series goes through the Samsung
 tree.

 I applied this series, thanks.

This series has not made it into 3.9-rc1. So I will rebase this series
to 3.9-rc1 and post again.

Thanks,
Thomas.


 And I think, would be clear if the config could be changed like following.

 8--
 From: Kukjin Kim kgene@samsung.com
 Subject: [PATCH] pinctrl: exynos: change PINCTRL_EXYNOS option

 Since pinctrl-exynos can support exynos4 and exynos5 so changed
 the option name to PINCTRL_EXYNOS for more clarity.

 Cc: Thomas Abraham thomas.abra...@linaro.org
 Cc: Linus Walleij linus.wall...@linaro.org
 Cc: Grant Likely grant.lik...@secretlab.ca
 Signed-off-by: Kukjin Kim kgene@samsung.com
 ---
 diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
 index 91d5b6f..e1f63e7 100644
 --- a/arch/arm/mach-exynos/Kconfig
 +++ b/arch/arm/mach-exynos/Kconfig
 @@ -412,7 +412,7 @@ config MACH_EXYNOS4_DT
 select CPU_EXYNOS4210
 select HAVE_SAMSUNG_KEYPAD if INPUT_KEYBOARD
 select PINCTRL
 -   select PINCTRL_EXYNOS4
 +   select PINCTRL_EXYNOS
 select USE_OF
 help
   Machine support for Samsung Exynos4 machine with device tree
 enabled.
 diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
 index c31aeb0..f59feab 100644
 --- a/drivers/pinctrl/Kconfig
 +++ b/drivers/pinctrl/Kconfig
 @@ -185,8 +185,8 @@ config PINCTRL_SAMSUNG
 select PINMUX
 select PINCONF

 -config PINCTRL_EXYNOS4
 -   bool Pinctrl driver data for Exynos4 SoC
 +config PINCTRL_EXYNOS
 +   bool Pinctrl driver data for Samsung EXYNOS SoCs
 depends on OF  GPIOLIB
 select PINCTRL_SAMSUNG

 diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
 index fc4606f..6e87e52 100644
 --- a/drivers/pinctrl/Makefile
 +++ b/drivers/pinctrl/Makefile
 @@ -36,7 +36,7 @@ obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o
  obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o
  obj-$(CONFIG_PINCTRL_COH901)   += pinctrl-coh901.o
  obj-$(CONFIG_PINCTRL_SAMSUNG)  += pinctrl-samsung.o
 -obj-$(CONFIG_PINCTRL_EXYNOS4)  += pinctrl-exynos.o
 +obj-$(CONFIG_PINCTRL_EXYNOS)   += pinctrl-exynos.o
  obj-$(CONFIG_PINCTRL_EXYNOS5440)   += pinctrl-exynos5440.o
  obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o
  obj-$(CONFIG_PINCTRL_LANTIQ)   += pinctrl-lantiq.o
 8--

 - Kukjin

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Re: [PATCH 4/4] regulator: add device tree support for s5m8767

[Thomas Abraham]

 +
> +   dvs_voltage_nr = 8;
> +   }
> +
> +   ret = s5m8767_pmic_dt_parse_ds_gpio(iodev, pdata, pmic_np);
> +   if (ret)
> +   return -EINVAL;
> +
> +   if (of_property_read_u32_array(pmic_np,
> +   "s5m8767,pmic-buck2-dvs-voltage",
> +   pdata->buck2_voltage, dvs_voltage_nr)) {

Same here. Maybe it is better to change pdata->buck2/3/4_voltage to
u32 data type.

> +   dev_err(iodev->dev, "buck2 voltages not specified\n");
> +   return -EINVAL;
> +   }
> +
> +   if (of_property_read_u32_array(pmic_np,
> +   "s5m8767,pmic-buck3-dvs-voltage",
> +   pdata->buck3_voltage, dvs_voltage_nr)) {

same here...

> +   dev_err(iodev->dev, "buck3 voltages not specified\n");
> +   return -EINVAL;
> +   }
> +
> +   if (of_property_read_u32_array(pmic_np,
> +   "s5m8767,pmic-buck4-dvs-voltage",
> +   pdata->buck4_voltage, dvs_voltage_nr)) {

same here...

> +   dev_err(iodev->dev, "buck4 voltages not specified\n");
> +   return -EINVAL;
> +   }
> +
> +   return 0;
> +}
> +#else
> +static int s5m8767_pmic_dt_parse_pdata(struct sec_pmic_dev *iodev,
> +   struct sec_platform_data *pdata)
> +{
> +   return 0;
> +}
> +#endif /* CONFIG_OF */
> +
>  static int s5m8767_pmic_probe(struct platform_device *pdev)
>  {
> struct sec_pmic_dev *iodev = dev_get_drvdata(pdev->dev.parent);
> -   struct sec_platform_data *pdata = dev_get_platdata(iodev->dev);
> +   struct sec_platform_data *pdata = iodev->pdata;
> struct regulator_config config = { };
> struct regulator_dev **rdev;
> struct s5m8767_info *s5m8767;
> int i, ret, size, buck_init;
>
> +   if (iodev->dev->of_node) {
> +   ret = s5m8767_pmic_dt_parse_pdata(iodev, pdata);
> +   if (ret)
> +   return ret;
> +   }
> +
> if (!pdata) {
> dev_err(pdev->dev.parent, "Platform data not supplied\n");
> return -ENODEV;
> @@ -765,6 +952,7 @@ static int s5m8767_pmic_probe(struct platform_device 
> *pdev)
> config.dev = s5m8767->dev;
> config.init_data = pdata->regulators[i].initdata;
> config.driver_data = s5m8767;
> +   config.of_node = pdata->regulators[i].reg_node;
>
> rdev[i] = regulator_register([id], );
> if (IS_ERR(rdev[i])) {
> diff --git a/include/linux/mfd/samsung/core.h 
> b/include/linux/mfd/samsung/core.h
> index b50c38f..380ed95 100644
> --- a/include/linux/mfd/samsung/core.h
> +++ b/include/linux/mfd/samsung/core.h
> @@ -26,6 +26,7 @@ enum sec_device_type {
>  /**
>   * struct sec_pmic_dev - s5m87xx master device for sub-drivers
>   * @dev: master device of the chip (can be used to access platform data)
> + * @pdata: pointer to private data used to pass platform data to child
>   * @i2c: i2c client private data for regulator
>   * @rtc: i2c client private data for rtc
>   * @iolock: mutex for serializing io access
> @@ -39,6 +40,7 @@ enum sec_device_type {
>   */
>  struct sec_pmic_dev {
> struct device *dev;
> +   struct sec_platform_data *pdata;
> struct regmap *regmap;
> struct i2c_client *i2c;
> struct i2c_client *rtc;
> @@ -127,6 +129,7 @@ struct sec_platform_data {
>  struct sec_regulator_data {
> int id;
> struct regulator_init_data  *initdata;
> +   struct device_node *reg_node;
>  };
>
>  /*
> --
> 1.7.1
>

After fixing these, you could add:
Reviewed-by: Thomas Abraham 
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Re: [PATCH 4/4] regulator: add device tree support for s5m8767

[Thomas Abraham]

;
 config.driver_data = s5m8767;
 +   config.of_node = pdata-regulators[i].reg_node;

 rdev[i] = regulator_register(regulators[id], config);
 if (IS_ERR(rdev[i])) {
 diff --git a/include/linux/mfd/samsung/core.h 
 b/include/linux/mfd/samsung/core.h
 index b50c38f..380ed95 100644
 --- a/include/linux/mfd/samsung/core.h
 +++ b/include/linux/mfd/samsung/core.h
 @@ -26,6 +26,7 @@ enum sec_device_type {
  /**
   * struct sec_pmic_dev - s5m87xx master device for sub-drivers
   * @dev: master device of the chip (can be used to access platform data)
 + * @pdata: pointer to private data used to pass platform data to child
   * @i2c: i2c client private data for regulator
   * @rtc: i2c client private data for rtc
   * @iolock: mutex for serializing io access
 @@ -39,6 +40,7 @@ enum sec_device_type {
   */
  struct sec_pmic_dev {
 struct device *dev;
 +   struct sec_platform_data *pdata;
 struct regmap *regmap;
 struct i2c_client *i2c;
 struct i2c_client *rtc;
 @@ -127,6 +129,7 @@ struct sec_platform_data {
  struct sec_regulator_data {
 int id;
 struct regulator_init_data  *initdata;
 +   struct device_node *reg_node;
  };

  /*
 --
 1.7.1


After fixing these, you could add:
Reviewed-by: Thomas Abraham thomas.abra...@linaro.org
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Re: [PATCH] ARM: DTS: exynos4210-origen: Add MAX8997 node entry

[Thomas Abraham]

On 4 January 2013 00:23, Tushar Behera  wrote:
> The node entry is added as per documentation and legacy board file.
>
> Signed-off-by: Tushar Behera 
> ---
> The patch is rebased on v3.8-rc1.
>
>  arch/arm/boot/dts/exynos4210-origen.dts |  150 
> +++
>  1 files changed, 150 insertions(+), 0 deletions(-)

This patch has already been posted. Here is the link:
https://patchwork.kernel.org/patch/1794501/

Thanks,
Thomas.
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Re: [PATCH] ARM: DTS: exynos4210-origen: Add MAX8997 node entry

[Thomas Abraham]

On 4 January 2013 00:23, Tushar Behera tushar.beh...@linaro.org wrote:
 The node entry is added as per documentation and legacy board file.

 Signed-off-by: Tushar Behera tushar.beh...@linaro.org
 ---
 The patch is rebased on v3.8-rc1.

  arch/arm/boot/dts/exynos4210-origen.dts |  150 
 +++
  1 files changed, 150 insertions(+), 0 deletions(-)

This patch has already been posted. Here is the link:
https://patchwork.kernel.org/patch/1794501/

Thanks,
Thomas.
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Re: [PATCH] mmc: host: dw_mmc-exynos: Add support for pinctrl

[Thomas Abraham]

On 21 December 2012 09:11, Dongjin Kim  wrote:
> This patch adds support for pin configuration using pinctrl subsystem to
> dw_mmc-exynos driver. The property 'wp-gpios' can be specified for write
> protect but 'samsung,cd-pinmux-gpio' and gpios used for clock, command and
> data lines will be ignored.
>
> -. 'pinctrl-0' should specify pin control groups (clock, comand and data
> lines) used for this controller.
> -. 'pinctrl-names' should contain only one value, 'default'.
>
> Signed-off-by: Dongjin Kim 
> ---
>  drivers/mmc/host/dw_mmc-exynos.c |   44 
> --
>  1 file changed, 28 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/mmc/host/dw_mmc-exynos.c 
> b/drivers/mmc/host/dw_mmc-exynos.c
> index 4d50da6..d1c9963 100644
> --- a/drivers/mmc/host/dw_mmc-exynos.c
> +++ b/drivers/mmc/host/dw_mmc-exynos.c
> @@ -16,6 +16,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>
>  #include "dw_mmc.h"
>  #include "dw_mmc-pltfm.h"
> @@ -49,6 +50,7 @@ struct dw_mci_exynos_priv_data {
> u8  ciu_div;
> u32 sdr_timing;
> u32 ddr_timing;
> +   struct pinctrl  *pctrl;
>  };
>
>  static struct dw_mci_exynos_compatible {
> @@ -84,6 +86,10 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host)
> priv->ctrl_type = exynos_compat[idx].ctrl_type;
> }
>
> +   priv->pctrl = devm_pinctrl_get_select_default(host->dev);
> +   if (IS_ERR(priv->pctrl))
> +   dev_dbg(host->dev, "no pinctrl node\n");
> +

This could have been handled in dw_mci_exynos_setup_bus function. And
we also need to check if this patch gets merged.
https://patchwork.kernel.org/patch/1870231/. If it gets merged, this
change can be avoided.

> host->priv = priv;
> return 0;
>  }
> @@ -149,32 +155,19 @@ static int dw_mci_exynos_parse_dt(struct dw_mci *host)
> return ret;
>
> priv->ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
> +
> return 0;
>  }
>
>  static int dw_mci_exynos_setup_bus(struct dw_mci *host,
> struct device_node *slot_np, u8 bus_width)
>  {
> +   struct dw_mci_exynos_priv_data *priv = host->priv;
> int idx, gpio, ret;
>
> if (!slot_np)
> return -EINVAL;
>
> -   /* cmd + clock + bus-width pins */
> -   for (idx = 0; idx < NUM_PINS(bus_width); idx++) {
> -   gpio = of_get_gpio(slot_np, idx);
> -   if (!gpio_is_valid(gpio)) {
> -   dev_err(host->dev, "invalid gpio: %d\n", gpio);
> -   return -EINVAL;
> -   }
> -
> -   ret = devm_gpio_request(host->dev, gpio, "dw-mci-bus");
> -   if (ret) {
> -   dev_err(host->dev, "gpio [%d] request failed\n", 
> gpio);
> -   return -EBUSY;
> -   }
> -   }
> -
> gpio = of_get_named_gpio(slot_np, "wp-gpios", 0);
> if (gpio_is_valid(gpio)) {
> if (devm_gpio_request(host->dev, gpio, "dw-mci-wp"))
> @@ -185,9 +178,12 @@ static int dw_mci_exynos_setup_bus(struct dw_mci *host,
> host->pdata->quirks |= DW_MCI_QUIRK_NO_WRITE_PROTECT;
> }
>
> -   if (host->pdata->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
> +   if (!IS_ERR(priv->pctrl))
> return 0;
>
> +   if (host->pdata->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
> +   goto setup_bus;
> +

Why do the entire bus setup if card detection is broken?

> gpio = of_get_named_gpio(slot_np, "samsung,cd-pinmux-gpio", 0);
> if (gpio_is_valid(gpio)) {
> if (devm_gpio_request(host->dev, gpio, "dw-mci-cd"))
> @@ -196,6 +192,22 @@ static int dw_mci_exynos_setup_bus(struct dw_mci *host,
> dev_info(host->dev, "cd gpio not available");
> }
>
> + setup_bus:
> +   /* cmd + clock + bus-width pins */
> +   for (idx = 0; idx < NUM_PINS(bus_width); idx++) {
> +   gpio = of_get_gpio(slot_np, idx);
> +   if (!gpio_is_valid(gpio)) {
> +   dev_err(host->dev, "invalid gpio: %d\n", gpio);
> +   return -EINVAL;
> +   }
> +
> +   ret = devm_gpio_request(host->dev, gpio, "dw-mci-bus");
> +   if (ret) {
> +   dev_err(host->dev, "gpio [%d] request failed\n", 
> gpio);
> +   return -EBUSY;
> +   }
> +   }

This change should not have been there. If the mmc bus setup is being
done using pinctrl framework, this change can be avoided.

Thanks,
Thomas.

> +
> return 0;
>  }
>
> --
> 1.7.9.5
>
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Re: [PATCH] mmc: host: dw_mmc-exynos: Add support for pinctrl

[Thomas Abraham]

On 21 December 2012 09:11, Dongjin Kim tobet...@gmail.com wrote:
 This patch adds support for pin configuration using pinctrl subsystem to
 dw_mmc-exynos driver. The property 'wp-gpios' can be specified for write
 protect but 'samsung,cd-pinmux-gpio' and gpios used for clock, command and
 data lines will be ignored.

 -. 'pinctrl-0' should specify pin control groups (clock, comand and data
 lines) used for this controller.
 -. 'pinctrl-names' should contain only one value, 'default'.

 Signed-off-by: Dongjin Kim tobet...@gmail.com
 ---
  drivers/mmc/host/dw_mmc-exynos.c |   44 
 --
  1 file changed, 28 insertions(+), 16 deletions(-)

 diff --git a/drivers/mmc/host/dw_mmc-exynos.c 
 b/drivers/mmc/host/dw_mmc-exynos.c
 index 4d50da6..d1c9963 100644
 --- a/drivers/mmc/host/dw_mmc-exynos.c
 +++ b/drivers/mmc/host/dw_mmc-exynos.c
 @@ -16,6 +16,7 @@
  #include linux/mmc/dw_mmc.h
  #include linux/of.h
  #include linux/of_gpio.h
 +#include linux/pinctrl/consumer.h

  #include dw_mmc.h
  #include dw_mmc-pltfm.h
 @@ -49,6 +50,7 @@ struct dw_mci_exynos_priv_data {
 u8  ciu_div;
 u32 sdr_timing;
 u32 ddr_timing;
 +   struct pinctrl  *pctrl;
  };

  static struct dw_mci_exynos_compatible {
 @@ -84,6 +86,10 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host)
 priv-ctrl_type = exynos_compat[idx].ctrl_type;
 }

 +   priv-pctrl = devm_pinctrl_get_select_default(host-dev);
 +   if (IS_ERR(priv-pctrl))
 +   dev_dbg(host-dev, no pinctrl node\n);
 +

This could have been handled in dw_mci_exynos_setup_bus function. And
we also need to check if this patch gets merged.
https://patchwork.kernel.org/patch/1870231/. If it gets merged, this
change can be avoided.

 host-priv = priv;
 return 0;
  }
 @@ -149,32 +155,19 @@ static int dw_mci_exynos_parse_dt(struct dw_mci *host)
 return ret;

 priv-ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
 +
 return 0;
  }

  static int dw_mci_exynos_setup_bus(struct dw_mci *host,
 struct device_node *slot_np, u8 bus_width)
  {
 +   struct dw_mci_exynos_priv_data *priv = host-priv;
 int idx, gpio, ret;

 if (!slot_np)
 return -EINVAL;

 -   /* cmd + clock + bus-width pins */
 -   for (idx = 0; idx  NUM_PINS(bus_width); idx++) {
 -   gpio = of_get_gpio(slot_np, idx);
 -   if (!gpio_is_valid(gpio)) {
 -   dev_err(host-dev, invalid gpio: %d\n, gpio);
 -   return -EINVAL;
 -   }
 -
 -   ret = devm_gpio_request(host-dev, gpio, dw-mci-bus);
 -   if (ret) {
 -   dev_err(host-dev, gpio [%d] request failed\n, 
 gpio);
 -   return -EBUSY;
 -   }
 -   }
 -
 gpio = of_get_named_gpio(slot_np, wp-gpios, 0);
 if (gpio_is_valid(gpio)) {
 if (devm_gpio_request(host-dev, gpio, dw-mci-wp))
 @@ -185,9 +178,12 @@ static int dw_mci_exynos_setup_bus(struct dw_mci *host,
 host-pdata-quirks |= DW_MCI_QUIRK_NO_WRITE_PROTECT;
 }

 -   if (host-pdata-quirks  DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
 +   if (!IS_ERR(priv-pctrl))
 return 0;

 +   if (host-pdata-quirks  DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
 +   goto setup_bus;
 +

Why do the entire bus setup if card detection is broken?

 gpio = of_get_named_gpio(slot_np, samsung,cd-pinmux-gpio, 0);
 if (gpio_is_valid(gpio)) {
 if (devm_gpio_request(host-dev, gpio, dw-mci-cd))
 @@ -196,6 +192,22 @@ static int dw_mci_exynos_setup_bus(struct dw_mci *host,
 dev_info(host-dev, cd gpio not available);
 }

 + setup_bus:
 +   /* cmd + clock + bus-width pins */
 +   for (idx = 0; idx  NUM_PINS(bus_width); idx++) {
 +   gpio = of_get_gpio(slot_np, idx);
 +   if (!gpio_is_valid(gpio)) {
 +   dev_err(host-dev, invalid gpio: %d\n, gpio);
 +   return -EINVAL;
 +   }
 +
 +   ret = devm_gpio_request(host-dev, gpio, dw-mci-bus);
 +   if (ret) {
 +   dev_err(host-dev, gpio [%d] request failed\n, 
 gpio);
 +   return -EBUSY;
 +   }
 +   }

This change should not have been there. If the mmc bus setup is being
done using pinctrl framework, this change can be avoided.

Thanks,
Thomas.

 +
 return 0;
  }

 --
 1.7.9.5

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Re: [PATCH 1/4] ODROID-X: dts: Add board dts file for ODROID-X

[Thomas Abraham]

Hi Dongjin,

On 17 December 2012 13:55, Dongjin Kim  wrote:
> Add initial dtb file for Hardkernel's ODROID-X board based on EXYNOS4412 SoC.
>
> Signed-off-by: Dongjin Kim 
> ---
>  arch/arm/boot/dts/Makefile   |1 +
>  arch/arm/boot/dts/exynos4412-odroidx.dts |   52 
> ++
>  2 files changed, 53 insertions(+)
>  create mode 100644 arch/arm/boot/dts/exynos4412-odroidx.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index ca6fb8e..3355af9 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -45,6 +45,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
> exynos5250-smdk5250.dtb \
> exynos5440-ssdk5440.dtb \
> exynos4412-smdk4412.dtb \
> +   exynos4412-odroidx.dtb \
> exynos5250-smdk5250.dtb \
> exynos5250-snow.dtb
>  dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \
> diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts 
> b/arch/arm/boot/dts/exynos4412-odroidx.dts
> new file mode 100644
> index 000..786ddd7
> --- /dev/null
> +++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
> @@ -0,0 +1,52 @@
> +/*
> + * Hardkernel's Exynos4412 based ODROID-X board device tree source
> + *
> + * Copyright (c) 2012-2013 Dongjin Kim 
> + *
> + * Device tree source file for Hardkernel's ODROID-X board which is based on
> + * Samsung's Exynos4412 SoC.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> +*/
> +
> +/dts-v1/;
> +/include/ "exynos4412.dtsi"
> +
> +/ {
> +   model = "Hardkernel ODROID-X board based on Exynos4412";
> +   compatible = "samsung,exynos4412";
> +
> +   memory {
> +   reg = <0x4000 0x4000>;
> +   };
> +
> +   chosen {
> +   bootargs ="root=/dev/mmcblk0p3 rw console=ttySAC1,115200 
> init=/sbin/init delay=2";
> +   };
> +
> +   serial@1380 {
> +   status = "okay";
> +   };
> +
> +   serial@1381 {
> +   status = "okay";
> +   };
> +
> +   serial@1382 {
> +   status = "okay";
> +   };
> +
> +   serial@1383 {
> +   status = "okay";
> +   };
> +
> +   sdhci@1253 {
> +   bus-width = <4>;
> +   samsung,cd-pinmux-gpio = < 2 2 3 3>;

The card detect line should also be configured using pinctrl
interface. When pinctrl is enabled on Exynos, the old-style gpio
bindings is not supported. So a pinctrl node for sd2_cmd should be
defined which then can be listed in pinctrl-0.

> +   pinctrl-0 = <_clk _cmd _bus4>;
> +   pinctrl-names = "default";
> +   status = "okay";
> +   };
> +};
> --
> 1.7.9.5
>
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Re: [PATCH 1/4] ODROID-X: dts: Add board dts file for ODROID-X

[Thomas Abraham]

Hi Dongjin,

On 17 December 2012 13:55, Dongjin Kim tobet...@gmail.com wrote:
 Add initial dtb file for Hardkernel's ODROID-X board based on EXYNOS4412 SoC.

 Signed-off-by: Dongjin Kim tobet...@gmail.com
 ---
  arch/arm/boot/dts/Makefile   |1 +
  arch/arm/boot/dts/exynos4412-odroidx.dts |   52 
 ++
  2 files changed, 53 insertions(+)
  create mode 100644 arch/arm/boot/dts/exynos4412-odroidx.dts

 diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
 index ca6fb8e..3355af9 100644
 --- a/arch/arm/boot/dts/Makefile
 +++ b/arch/arm/boot/dts/Makefile
 @@ -45,6 +45,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
 exynos5250-smdk5250.dtb \
 exynos5440-ssdk5440.dtb \
 exynos4412-smdk4412.dtb \
 +   exynos4412-odroidx.dtb \
 exynos5250-smdk5250.dtb \
 exynos5250-snow.dtb
  dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \
 diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts 
 b/arch/arm/boot/dts/exynos4412-odroidx.dts
 new file mode 100644
 index 000..786ddd7
 --- /dev/null
 +++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
 @@ -0,0 +1,52 @@
 +/*
 + * Hardkernel's Exynos4412 based ODROID-X board device tree source
 + *
 + * Copyright (c) 2012-2013 Dongjin Kim tobet...@gmail.com
 + *
 + * Device tree source file for Hardkernel's ODROID-X board which is based on
 + * Samsung's Exynos4412 SoC.
 + *
 + * This program is free software; you can redistribute it and/or modify
 + * it under the terms of the GNU General Public License version 2 as
 + * published by the Free Software Foundation.
 +*/
 +
 +/dts-v1/;
 +/include/ exynos4412.dtsi
 +
 +/ {
 +   model = Hardkernel ODROID-X board based on Exynos4412;
 +   compatible = samsung,exynos4412;
 +
 +   memory {
 +   reg = 0x4000 0x4000;
 +   };
 +
 +   chosen {
 +   bootargs =root=/dev/mmcblk0p3 rw console=ttySAC1,115200 
 init=/sbin/init delay=2;
 +   };
 +
 +   serial@1380 {
 +   status = okay;
 +   };
 +
 +   serial@1381 {
 +   status = okay;
 +   };
 +
 +   serial@1382 {
 +   status = okay;
 +   };
 +
 +   serial@1383 {
 +   status = okay;
 +   };
 +
 +   sdhci@1253 {
 +   bus-width = 4;
 +   samsung,cd-pinmux-gpio = gpk2 2 2 3 3;

The card detect line should also be configured using pinctrl
interface. When pinctrl is enabled on Exynos, the old-style gpio
bindings is not supported. So a pinctrl node for sd2_cmd should be
defined which then can be listed in pinctrl-0.

 +   pinctrl-0 = sd2_clk sd2_cmd sd2_bus4;
 +   pinctrl-names = default;
 +   status = okay;
 +   };
 +};
 --
 1.7.9.5

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Re: [PATCH] ARM: EXYNOS: Fix MSHC clocks instance names

[Thomas Abraham]

On 14 December 2012 21:43, Dongjin Kim  wrote:
> Replace clock instance name of MSHC controller for BIC and CIU of Exynos4412.
>
> Signed-off-by: Dongjin Kim 
> ---
>  arch/arm/mach-exynos/clock-exynos4.c |4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/clock-exynos4.c 
> b/arch/arm/mach-exynos/clock-exynos4.c
> index efead60..bbcb3de 100644
> --- a/arch/arm/mach-exynos/clock-exynos4.c
> +++ b/arch/arm/mach-exynos/clock-exynos4.c
> @@ -529,7 +529,7 @@ static struct clk exynos4_init_clocks_off[] = {
> .enable = exynos4_clk_ip_fsys_ctrl,
> .ctrlbit= (1 << 8),
> }, {
> -   .name   = "dwmmc",
> +   .name   = "biu",
> .parent = _clk_aclk_133.clk,
> .enable = exynos4_clk_ip_fsys_ctrl,
> .ctrlbit= (1 << 9),
> @@ -1134,7 +1134,7 @@ static struct clksrc_clk exynos4_clksrcs[] = {
> .reg_div = { .reg = EXYNOS4_CLKDIV_MFC, .shift = 0, .size = 4 
> },
> }, {
> .clk= {
> -   .name   = "sclk_dwmmc",
> +   .name   = "ciu",
> .parent = _clk_dout_mmc4.clk,
>         .enable = exynos4_clksrc_mask_fsys_ctrl,
> .ctrlbit= (1 << 16),
> --

Acked-by: Thomas Abraham 

> 1.7.9.5



>
> --
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Re: [PATCH] ARM: EXYNOS: Fix MSHC clocks instance names

[Thomas Abraham]

Hi Dongjin,

On 14 December 2012 20:29, Dongjin Kim  wrote:
> Replace clock instance name of MSHC controller for BIC and CIU of Exynos4412.
>
> Signed-off-by: Dongjin Kim 
> ---
>  arch/arm/mach-exynos/clock-exynos4.c |   25 ++---
>  1 file changed, 14 insertions(+), 11 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/clock-exynos4.c 
> b/arch/arm/mach-exynos/clock-exynos4.c
> index efead60..ae83011 100644
> --- a/arch/arm/mach-exynos/clock-exynos4.c
> +++ b/arch/arm/mach-exynos/clock-exynos4.c
> @@ -529,8 +529,8 @@ static struct clk exynos4_init_clocks_off[] = {
> .enable = exynos4_clk_ip_fsys_ctrl,
> .ctrlbit= (1 << 8),
> }, {
> -   .name   = "dwmmc",
> -   .parent = _clk_aclk_133.clk,
> +   .name   = "biu",
> +   .parent = _clk_aclk_200.clk,
> .enable = exynos4_clk_ip_fsys_ctrl,
> .ctrlbit= (1 << 9),
> }, {
> @@ -1132,15 +1132,7 @@ static struct clksrc_clk exynos4_clksrcs[] = {
> .sources = _clkset_mout_mfc,
> .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 8, .size = 1 
> },
> .reg_div = { .reg = EXYNOS4_CLKDIV_MFC, .shift = 0, .size = 4 
> },
> -   }, {
> -   .clk= {
> -   .name   = "sclk_dwmmc",
> -   .parent = _clk_dout_mmc4.clk,
> -   .enable = exynos4_clksrc_mask_fsys_ctrl,
> -   .ctrlbit= (1 << 16),
> -   },
> -   .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 8, .size = 
> 8 },
> -   }
> +   },
>  };
>
>  static struct clksrc_clk exynos4_clk_sclk_uart0 = {
> @@ -1235,6 +1227,16 @@ static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
> .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 },
>  };
>
> +static struct clksrc_clk exynos4_clk_sclk_dwmci = {
> +   .clk= {
> +   .name   = "ciu",
> +   .parent = _clk_dout_mmc4.clk,
> +   .enable = exynos4_clksrc_mask_fsys_ctrl,
> +   .ctrlbit= (1 << 16),
> +   },
> +   .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 8, .size = 8 },
> +};
> +

It is not required to move the above clock instance out of the
exynos4_clksrcs[] array. Just changing the clock name to 'ciu' is
sufficient. And this will avoid the below change as well.

>  static struct clksrc_clk exynos4_clk_mdout_spi0 = {
> .clk= {
> .name   = "mdout_spi",
> @@ -1348,6 +1350,7 @@ static struct clksrc_clk *exynos4_clksrc_cdev[] = {
> _clk_sclk_mmc1,
> _clk_sclk_mmc2,
> _clk_sclk_mmc3,
> +   _clk_sclk_dwmci,
> _clk_sclk_spi0,
> _clk_sclk_spi1,
> _clk_sclk_spi2,
> --
> 1.7.9.5

Thanks,
Thomas.
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Re: [PATCH 1/3] pinctrl: exynos: add exynos5250 SoC specific data

[Thomas Abraham]

Hi Linus,

On 14 December 2012 21:21, Linus Walleij  wrote:
> On Thu, Dec 13, 2012 at 12:54 PM, Thomas Abraham
>  wrote:
>
>> Add Samsung Exynos5250 SoC specific data to enable pinctrl support for
>> all platforms based on Exynos5250.
>>
>> Signed-off-by: Thomas Abraham 
>
> Acked-by: Linus Walleij 
>
> For this series, I guess you'll fix it through the Samsung tree?

Thanks for your ack. Since there are patches to be prepared for
migrating the rest of Exynos5250 related code to the pinctrl
framework, it would be easier if this series goes through the Samsung
tree.

Thanks,
Thomas.

>
> Yours,
> Linus Walleij
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Re: [PATCH 1/3] pinctrl: exynos: add exynos5250 SoC specific data

[Thomas Abraham]

Hi Linus,

On 14 December 2012 21:21, Linus Walleij linus.wall...@linaro.org wrote:
 On Thu, Dec 13, 2012 at 12:54 PM, Thomas Abraham
 thomas.abra...@linaro.org wrote:

 Add Samsung Exynos5250 SoC specific data to enable pinctrl support for
 all platforms based on Exynos5250.

 Signed-off-by: Thomas Abraham thomas.abra...@linaro.org

 Acked-by: Linus Walleij linus.wall...@linaro.org

 For this series, I guess you'll fix it through the Samsung tree?

Thanks for your ack. Since there are patches to be prepared for
migrating the rest of Exynos5250 related code to the pinctrl
framework, it would be easier if this series goes through the Samsung
tree.

Thanks,
Thomas.


 Yours,
 Linus Walleij
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Re: [PATCH] ARM: EXYNOS: Fix MSHC clocks instance names

[Thomas Abraham]

Hi Dongjin,

On 14 December 2012 20:29, Dongjin Kim tobet...@gmail.com wrote:
 Replace clock instance name of MSHC controller for BIC and CIU of Exynos4412.

 Signed-off-by: Dongjin Kim tobet...@gmail.com
 ---
  arch/arm/mach-exynos/clock-exynos4.c |   25 ++---
  1 file changed, 14 insertions(+), 11 deletions(-)

 diff --git a/arch/arm/mach-exynos/clock-exynos4.c 
 b/arch/arm/mach-exynos/clock-exynos4.c
 index efead60..ae83011 100644
 --- a/arch/arm/mach-exynos/clock-exynos4.c
 +++ b/arch/arm/mach-exynos/clock-exynos4.c
 @@ -529,8 +529,8 @@ static struct clk exynos4_init_clocks_off[] = {
 .enable = exynos4_clk_ip_fsys_ctrl,
 .ctrlbit= (1  8),
 }, {
 -   .name   = dwmmc,
 -   .parent = exynos4_clk_aclk_133.clk,
 +   .name   = biu,
 +   .parent = exynos4_clk_aclk_200.clk,
 .enable = exynos4_clk_ip_fsys_ctrl,
 .ctrlbit= (1  9),
 }, {
 @@ -1132,15 +1132,7 @@ static struct clksrc_clk exynos4_clksrcs[] = {
 .sources = exynos4_clkset_mout_mfc,
 .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 8, .size = 1 
 },
 .reg_div = { .reg = EXYNOS4_CLKDIV_MFC, .shift = 0, .size = 4 
 },
 -   }, {
 -   .clk= {
 -   .name   = sclk_dwmmc,
 -   .parent = exynos4_clk_dout_mmc4.clk,
 -   .enable = exynos4_clksrc_mask_fsys_ctrl,
 -   .ctrlbit= (1  16),
 -   },
 -   .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 8, .size = 
 8 },
 -   }
 +   },
  };

  static struct clksrc_clk exynos4_clk_sclk_uart0 = {
 @@ -1235,6 +1227,16 @@ static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 },
  };

 +static struct clksrc_clk exynos4_clk_sclk_dwmci = {
 +   .clk= {
 +   .name   = ciu,
 +   .parent = exynos4_clk_dout_mmc4.clk,
 +   .enable = exynos4_clksrc_mask_fsys_ctrl,
 +   .ctrlbit= (1  16),
 +   },
 +   .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 8, .size = 8 },
 +};
 +

It is not required to move the above clock instance out of the
exynos4_clksrcs[] array. Just changing the clock name to 'ciu' is
sufficient. And this will avoid the below change as well.

  static struct clksrc_clk exynos4_clk_mdout_spi0 = {
 .clk= {
 .name   = mdout_spi,
 @@ -1348,6 +1350,7 @@ static struct clksrc_clk *exynos4_clksrc_cdev[] = {
 exynos4_clk_sclk_mmc1,
 exynos4_clk_sclk_mmc2,
 exynos4_clk_sclk_mmc3,
 +   exynos4_clk_sclk_dwmci,
 exynos4_clk_sclk_spi0,
 exynos4_clk_sclk_spi1,
 exynos4_clk_sclk_spi2,
 --
 1.7.9.5

Thanks,
Thomas.
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Re: [PATCH] ARM: EXYNOS: Fix MSHC clocks instance names

[Thomas Abraham]

On 14 December 2012 21:43, Dongjin Kim tobet...@gmail.com wrote:
 Replace clock instance name of MSHC controller for BIC and CIU of Exynos4412.

 Signed-off-by: Dongjin Kim tobet...@gmail.com
 ---
  arch/arm/mach-exynos/clock-exynos4.c |4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

 diff --git a/arch/arm/mach-exynos/clock-exynos4.c 
 b/arch/arm/mach-exynos/clock-exynos4.c
 index efead60..bbcb3de 100644
 --- a/arch/arm/mach-exynos/clock-exynos4.c
 +++ b/arch/arm/mach-exynos/clock-exynos4.c
 @@ -529,7 +529,7 @@ static struct clk exynos4_init_clocks_off[] = {
 .enable = exynos4_clk_ip_fsys_ctrl,
 .ctrlbit= (1  8),
 }, {
 -   .name   = dwmmc,
 +   .name   = biu,
 .parent = exynos4_clk_aclk_133.clk,
 .enable = exynos4_clk_ip_fsys_ctrl,
 .ctrlbit= (1  9),
 @@ -1134,7 +1134,7 @@ static struct clksrc_clk exynos4_clksrcs[] = {
 .reg_div = { .reg = EXYNOS4_CLKDIV_MFC, .shift = 0, .size = 4 
 },
 }, {
 .clk= {
 -   .name   = sclk_dwmmc,
 +   .name   = ciu,
 .parent = exynos4_clk_dout_mmc4.clk,
 .enable = exynos4_clksrc_mask_fsys_ctrl,
 .ctrlbit= (1  16),
 --

Acked-by: Thomas Abraham thomas.abra...@linaro.org

 1.7.9.5




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[PATCH 3/3] arm: exynos: skip wakeup interrupt registration for exynos5250 if pinctrl is enabled

[Thomas Abraham]

Skip the wakeup interrupt registration for Exynos5250 if pinctrl support
is enabled for Exynos5250.

Signed-off-by: Thomas Abraham 
---
 arch/arm/mach-exynos/common.c |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 73b940f..7ad5011 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -1019,6 +1019,7 @@ static int __init exynos_init_irq_eint(void)
static const struct of_device_id exynos_pinctrl_ids[] = {
{ .compatible = "samsung,pinctrl-exynos4210", },
{ .compatible = "samsung,pinctrl-exynos4x12", },
+   { .compatible = "samsung,pinctrl-exynos5250", },
};
struct device_node *pctrl_np, *wkup_np;
const char *wkup_compat = "samsung,exynos4210-wakeup-eint";
-- 
1.6.6.rc2

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[PATCH 2/3] gpio: samsung: skip gpiolib registration if pinctrl support is enabled for exynos5250

[Thomas Abraham]

Skip exynos5250 gpiolib registration if pinctrl support for exynos5250
is enabled.

Signed-off-by: Thomas Abraham 
---
 drivers/gpio/gpio-samsung.c |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
index 01f7fe9..849c134 100644
--- a/drivers/gpio/gpio-samsung.c
+++ b/drivers/gpio/gpio-samsung.c
@@ -3026,6 +3026,7 @@ static __init int samsung_gpiolib_init(void)
static const struct of_device_id exynos_pinctrl_ids[] = {
{ .compatible = "samsung,pinctrl-exynos4210", },
{ .compatible = "samsung,pinctrl-exynos4x12", },
+   { .compatible = "samsung,pinctrl-exynos5250", },
};
for_each_matching_node(pctrl_np, exynos_pinctrl_ids)
if (pctrl_np && of_device_is_available(pctrl_np))
-- 
1.6.6.rc2

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[PATCH 1/3] pinctrl: exynos: add exynos5250 SoC specific data

[Thomas Abraham]

Add Samsung Exynos5250 SoC specific data to enable pinctrl support for
all platforms based on Exynos5250.

Signed-off-by: Thomas Abraham 
---
 drivers/pinctrl/pinctrl-exynos.c  |  108 +
 drivers/pinctrl/pinctrl-samsung.c |2 +
 drivers/pinctrl/pinctrl-samsung.h |1 +
 3 files changed, 111 insertions(+), 0 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c
index 538b9dd..8738933 100644
--- a/drivers/pinctrl/pinctrl-exynos.c
+++ b/drivers/pinctrl/pinctrl-exynos.c
@@ -677,3 +677,111 @@ struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = {
.label  = "exynos4x12-gpio-ctrl3",
},
 };
+
+/* pin banks of exynos5250 pin-controller 0 */
+static struct samsung_pin_bank exynos5250_pin_banks0[] = {
+   EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
+   EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
+   EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
+   EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
+   EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
+   EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
+   EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18),
+   EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c),
+   EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc1", 0x20),
+   EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc2", 0x24),
+   EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc3", 0x28),
+   EXYNOS_PIN_BANK_EINTG(4, 0x160, "gpd0", 0x2c),
+   EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x30),
+   EXYNOS_PIN_BANK_EINTG(7, 0x2E0, "gpc4", 0x34),
+   EXYNOS_PIN_BANK_EINTN(6, 0x1A0, "gpy0"),
+   EXYNOS_PIN_BANK_EINTN(4, 0x1C0, "gpy1"),
+   EXYNOS_PIN_BANK_EINTN(6, 0x1E0, "gpy2"),
+   EXYNOS_PIN_BANK_EINTN(8, 0x200, "gpy3"),
+   EXYNOS_PIN_BANK_EINTN(8, 0x220, "gpy4"),
+   EXYNOS_PIN_BANK_EINTN(8, 0x240, "gpy5"),
+   EXYNOS_PIN_BANK_EINTN(8, 0x260, "gpy6"),
+   EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
+   EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
+   EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
+   EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
+};
+
+/* pin banks of exynos5250 pin-controller 1 */
+static struct samsung_pin_bank exynos5250_pin_banks1[] = {
+   EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00),
+   EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04),
+   EXYNOS_PIN_BANK_EINTG(4, 0x040, "gpf0", 0x08),
+   EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf1", 0x0c),
+   EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10),
+   EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14),
+   EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18),
+   EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gph0", 0x1c),
+   EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph1", 0x20),
+};
+
+/* pin banks of exynos5250 pin-controller 2 */
+static struct samsung_pin_bank exynos5250_pin_banks2[] = {
+   EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
+   EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
+   EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08),
+   EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c),
+   EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10),
+};
+
+/* pin banks of exynos5250 pin-controller 3 */
+static struct samsung_pin_bank exynos5250_pin_banks3[] = {
+   EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
+};
+
+/*
+ * Samsung pinctrl driver data for Exynos5250 SoC. Exynos5250 SoC includes
+ * four gpio/pin-mux/pinconfig controllers.
+ */
+struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
+   {
+   /* pin-controller instance 0 data */
+   .pin_banks  = exynos5250_pin_banks0,
+   .nr_banks   = ARRAY_SIZE(exynos5250_pin_banks0),
+   .geint_con  = EXYNOS_GPIO_ECON_OFFSET,
+   .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
+   .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
+   .weint_con  = EXYNOS_WKUP_ECON_OFFSET,
+   .weint_mask = EXYNOS_WKUP_EMASK_OFFSET,
+   .weint_pend = EXYNOS_WKUP_EPEND_OFFSET,
+   .svc= EXYNOS_SVC_OFFSET,
+   .eint_gpio_init = exynos_eint_gpio_init,
+   .eint_wkup_init = exynos_eint_wkup_init,
+   .label  = "exynos5250-gpio-ctrl0",
+   }, {
+   /* pin-controller instance 1 data */
+   .pin_banks  = exynos5250_pin_banks1,
+   .nr_banks   = ARRAY_SIZE(exynos5250_pin_banks1),
+   .geint_con  = EXYNOS_GPIO_ECON_OFFSET,
+   .geint_mask = EXYNOS_GPIO_EMASK_OFFSET

[PATCH 0/3] pinctrl: exynos: add support for Samsung's Exynos5250

[Thomas Abraham]

This patch series adds pinctrl driver support for Samsung's Exynos5250 SoC.
The first patch adds the required Exynos5250 SoC specific data which is
used by the Samsung pinctrl driver to setup the pinctrl/pinmux/eint
controllers. The second and third patches skips the wakeup interrupt and
gpiolib registration if the pinctrl support is enabled for Exynos5250.

Thomas Abraham (3):
  pinctrl: exynos: add exynos5250 SoC specific data
  gpio: samsung: skip gpiolib registration if pinctrl support is enabled for 
exynos5250
  arm: exynos: skip wakeup interrupt registration for exynos5250 if pinctrl is 
enabled

 arch/arm/mach-exynos/common.c |1 +
 drivers/gpio/gpio-samsung.c   |1 +
 drivers/pinctrl/pinctrl-exynos.c  |  108 +
 drivers/pinctrl/pinctrl-samsung.c |2 +
 drivers/pinctrl/pinctrl-samsung.h |1 +
 5 files changed, 113 insertions(+), 0 deletions(-)

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[PATCH 0/3] pinctrl: exynos: add support for Samsung's Exynos5250

[Thomas Abraham]

This patch series adds pinctrl driver support for Samsung's Exynos5250 SoC.
The first patch adds the required Exynos5250 SoC specific data which is
used by the Samsung pinctrl driver to setup the pinctrl/pinmux/eint
controllers. The second and third patches skips the wakeup interrupt and
gpiolib registration if the pinctrl support is enabled for Exynos5250.

Thomas Abraham (3):
  pinctrl: exynos: add exynos5250 SoC specific data
  gpio: samsung: skip gpiolib registration if pinctrl support is enabled for 
exynos5250
  arm: exynos: skip wakeup interrupt registration for exynos5250 if pinctrl is 
enabled

 arch/arm/mach-exynos/common.c |1 +
 drivers/gpio/gpio-samsung.c   |1 +
 drivers/pinctrl/pinctrl-exynos.c  |  108 +
 drivers/pinctrl/pinctrl-samsung.c |2 +
 drivers/pinctrl/pinctrl-samsung.h |1 +
 5 files changed, 113 insertions(+), 0 deletions(-)

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[PATCH 1/3] pinctrl: exynos: add exynos5250 SoC specific data

[Thomas Abraham]

Add Samsung Exynos5250 SoC specific data to enable pinctrl support for
all platforms based on Exynos5250.

Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
---
 drivers/pinctrl/pinctrl-exynos.c  |  108 +
 drivers/pinctrl/pinctrl-samsung.c |2 +
 drivers/pinctrl/pinctrl-samsung.h |1 +
 3 files changed, 111 insertions(+), 0 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c
index 538b9dd..8738933 100644
--- a/drivers/pinctrl/pinctrl-exynos.c
+++ b/drivers/pinctrl/pinctrl-exynos.c
@@ -677,3 +677,111 @@ struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = {
.label  = exynos4x12-gpio-ctrl3,
},
 };
+
+/* pin banks of exynos5250 pin-controller 0 */
+static struct samsung_pin_bank exynos5250_pin_banks0[] = {
+   EXYNOS_PIN_BANK_EINTG(8, 0x000, gpa0, 0x00),
+   EXYNOS_PIN_BANK_EINTG(6, 0x020, gpa1, 0x04),
+   EXYNOS_PIN_BANK_EINTG(8, 0x040, gpa2, 0x08),
+   EXYNOS_PIN_BANK_EINTG(5, 0x060, gpb0, 0x0c),
+   EXYNOS_PIN_BANK_EINTG(5, 0x080, gpb1, 0x10),
+   EXYNOS_PIN_BANK_EINTG(4, 0x0A0, gpb2, 0x14),
+   EXYNOS_PIN_BANK_EINTG(4, 0x0C0, gpb3, 0x18),
+   EXYNOS_PIN_BANK_EINTG(7, 0x0E0, gpc0, 0x1c),
+   EXYNOS_PIN_BANK_EINTG(4, 0x100, gpc1, 0x20),
+   EXYNOS_PIN_BANK_EINTG(7, 0x120, gpc2, 0x24),
+   EXYNOS_PIN_BANK_EINTG(7, 0x140, gpc3, 0x28),
+   EXYNOS_PIN_BANK_EINTG(4, 0x160, gpd0, 0x2c),
+   EXYNOS_PIN_BANK_EINTG(8, 0x180, gpd1, 0x30),
+   EXYNOS_PIN_BANK_EINTG(7, 0x2E0, gpc4, 0x34),
+   EXYNOS_PIN_BANK_EINTN(6, 0x1A0, gpy0),
+   EXYNOS_PIN_BANK_EINTN(4, 0x1C0, gpy1),
+   EXYNOS_PIN_BANK_EINTN(6, 0x1E0, gpy2),
+   EXYNOS_PIN_BANK_EINTN(8, 0x200, gpy3),
+   EXYNOS_PIN_BANK_EINTN(8, 0x220, gpy4),
+   EXYNOS_PIN_BANK_EINTN(8, 0x240, gpy5),
+   EXYNOS_PIN_BANK_EINTN(8, 0x260, gpy6),
+   EXYNOS_PIN_BANK_EINTW(8, 0xC00, gpx0, 0x00),
+   EXYNOS_PIN_BANK_EINTW(8, 0xC20, gpx1, 0x04),
+   EXYNOS_PIN_BANK_EINTW(8, 0xC40, gpx2, 0x08),
+   EXYNOS_PIN_BANK_EINTW(8, 0xC60, gpx3, 0x0c),
+};
+
+/* pin banks of exynos5250 pin-controller 1 */
+static struct samsung_pin_bank exynos5250_pin_banks1[] = {
+   EXYNOS_PIN_BANK_EINTG(8, 0x000, gpe0, 0x00),
+   EXYNOS_PIN_BANK_EINTG(2, 0x020, gpe1, 0x04),
+   EXYNOS_PIN_BANK_EINTG(4, 0x040, gpf0, 0x08),
+   EXYNOS_PIN_BANK_EINTG(4, 0x060, gpf1, 0x0c),
+   EXYNOS_PIN_BANK_EINTG(8, 0x080, gpg0, 0x10),
+   EXYNOS_PIN_BANK_EINTG(8, 0x0A0, gpg1, 0x14),
+   EXYNOS_PIN_BANK_EINTG(2, 0x0C0, gpg2, 0x18),
+   EXYNOS_PIN_BANK_EINTG(4, 0x0E0, gph0, 0x1c),
+   EXYNOS_PIN_BANK_EINTG(8, 0x100, gph1, 0x20),
+};
+
+/* pin banks of exynos5250 pin-controller 2 */
+static struct samsung_pin_bank exynos5250_pin_banks2[] = {
+   EXYNOS_PIN_BANK_EINTG(8, 0x000, gpv0, 0x00),
+   EXYNOS_PIN_BANK_EINTG(8, 0x020, gpv1, 0x04),
+   EXYNOS_PIN_BANK_EINTG(8, 0x060, gpv2, 0x08),
+   EXYNOS_PIN_BANK_EINTG(8, 0x080, gpv3, 0x0c),
+   EXYNOS_PIN_BANK_EINTG(2, 0x0C0, gpv4, 0x10),
+};
+
+/* pin banks of exynos5250 pin-controller 3 */
+static struct samsung_pin_bank exynos5250_pin_banks3[] = {
+   EXYNOS_PIN_BANK_EINTG(7, 0x000, gpz, 0x00),
+};
+
+/*
+ * Samsung pinctrl driver data for Exynos5250 SoC. Exynos5250 SoC includes
+ * four gpio/pin-mux/pinconfig controllers.
+ */
+struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
+   {
+   /* pin-controller instance 0 data */
+   .pin_banks  = exynos5250_pin_banks0,
+   .nr_banks   = ARRAY_SIZE(exynos5250_pin_banks0),
+   .geint_con  = EXYNOS_GPIO_ECON_OFFSET,
+   .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
+   .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
+   .weint_con  = EXYNOS_WKUP_ECON_OFFSET,
+   .weint_mask = EXYNOS_WKUP_EMASK_OFFSET,
+   .weint_pend = EXYNOS_WKUP_EPEND_OFFSET,
+   .svc= EXYNOS_SVC_OFFSET,
+   .eint_gpio_init = exynos_eint_gpio_init,
+   .eint_wkup_init = exynos_eint_wkup_init,
+   .label  = exynos5250-gpio-ctrl0,
+   }, {
+   /* pin-controller instance 1 data */
+   .pin_banks  = exynos5250_pin_banks1,
+   .nr_banks   = ARRAY_SIZE(exynos5250_pin_banks1),
+   .geint_con  = EXYNOS_GPIO_ECON_OFFSET,
+   .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
+   .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
+   .svc= EXYNOS_SVC_OFFSET,
+   .eint_gpio_init = exynos_eint_gpio_init,
+   .label  = exynos5250-gpio-ctrl1,
+   }, {
+   /* pin-controller instance 2 data */
+   .pin_banks  = exynos5250_pin_banks2,
+   .nr_banks   = ARRAY_SIZE(exynos5250_pin_banks2),
+   .geint_con  = EXYNOS_GPIO_ECON_OFFSET

[PATCH 2/3] gpio: samsung: skip gpiolib registration if pinctrl support is enabled for exynos5250

[Thomas Abraham]

Skip exynos5250 gpiolib registration if pinctrl support for exynos5250
is enabled.

Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
---
 drivers/gpio/gpio-samsung.c |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
index 01f7fe9..849c134 100644
--- a/drivers/gpio/gpio-samsung.c
+++ b/drivers/gpio/gpio-samsung.c
@@ -3026,6 +3026,7 @@ static __init int samsung_gpiolib_init(void)
static const struct of_device_id exynos_pinctrl_ids[] = {
{ .compatible = samsung,pinctrl-exynos4210, },
{ .compatible = samsung,pinctrl-exynos4x12, },
+   { .compatible = samsung,pinctrl-exynos5250, },
};
for_each_matching_node(pctrl_np, exynos_pinctrl_ids)
if (pctrl_np  of_device_is_available(pctrl_np))
-- 
1.6.6.rc2

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[PATCH 3/3] arm: exynos: skip wakeup interrupt registration for exynos5250 if pinctrl is enabled

[Thomas Abraham]

Skip the wakeup interrupt registration for Exynos5250 if pinctrl support
is enabled for Exynos5250.

Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
---
 arch/arm/mach-exynos/common.c |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 73b940f..7ad5011 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -1019,6 +1019,7 @@ static int __init exynos_init_irq_eint(void)
static const struct of_device_id exynos_pinctrl_ids[] = {
{ .compatible = samsung,pinctrl-exynos4210, },
{ .compatible = samsung,pinctrl-exynos4x12, },
+   { .compatible = samsung,pinctrl-exynos5250, },
};
struct device_node *pctrl_np, *wkup_np;
const char *wkup_compat = samsung,exynos4210-wakeup-eint;
-- 
1.6.6.rc2

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Re: [PATCH] pinctrl: exynos5440/samsung: Staticize pcfgs

[Thomas Abraham]

On 27 November 2012 20:19, Axel Lin  wrote:
> I got below build error with random config if CONFIG_PINCTRL_SAMSUNG=y &&
> CONFIG_PINCTRL_EXYNOS5440=y.
>
> Fix the build error by making pcfgs static.
>
>   LD  drivers/pinctrl/built-in.o
> drivers/pinctrl/pinctrl-exynos5440.o: In function `.LANCHOR0':
> pinctrl-exynos5440.c:(.data+0x54): multiple definition of `pcfgs'
> drivers/pinctrl/pinctrl-samsung.o:pinctrl-samsung.c:(.data+0x54): first 
> defined here
> make[2]: *** [drivers/pinctrl/built-in.o] Error 1
> make[1]: *** [drivers/pinctrl] Error 2
> make: *** [drivers] Error 2
>
> Signed-off-by: Axel Lin 

Acked-by: Thomas Abraham 

Dear Mr. Kim,

Could you please consider this patch in your next pull request for fixes.

Thanks,
Thomas.

[...]
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Re: [PATCH] pinctrl: exynos5440/samsung: Staticize pcfgs

[Thomas Abraham]

On 27 November 2012 20:19, Axel Lin axel@ingics.com wrote:
 I got below build error with random config if CONFIG_PINCTRL_SAMSUNG=y 
 CONFIG_PINCTRL_EXYNOS5440=y.

 Fix the build error by making pcfgs static.

   LD  drivers/pinctrl/built-in.o
 drivers/pinctrl/pinctrl-exynos5440.o: In function `.LANCHOR0':
 pinctrl-exynos5440.c:(.data+0x54): multiple definition of `pcfgs'
 drivers/pinctrl/pinctrl-samsung.o:pinctrl-samsung.c:(.data+0x54): first 
 defined here
 make[2]: *** [drivers/pinctrl/built-in.o] Error 1
 make[1]: *** [drivers/pinctrl] Error 2
 make: *** [drivers] Error 2

 Signed-off-by: Axel Lin axel@ingics.com

Acked-by: Thomas Abraham thomas.abra...@linaro.org

Dear Mr. Kim,

Could you please consider this patch in your next pull request for fixes.

Thanks,
Thomas.

[...]
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Re: [PATCH 1/3] i2c: exynos5: add High Speed I2C controller driver

[Thomas Abraham]

On 27 November 2012 18:30, Naveen Krishna Chatradhi
 wrote:
> Adds support for High Speed I2C driver found in Exynos5 and later
> SoCs from Samsung. This driver currently supports Auto mode.
>
> Driver only supports Device Tree method.
>
> Signed-off-by: Taekgyun Ko 
> Signed-off-by: Naveen Krishna Chatradhi 
> ---
>  drivers/i2c/busses/Kconfig   |6 +
>  drivers/i2c/busses/Makefile  |1 +
>  drivers/i2c/busses/i2c-exynos5.c |  758 
> ++
>  drivers/i2c/busses/i2c-exynos5.h |   80 
>  4 files changed, 845 insertions(+)
>  create mode 100644 drivers/i2c/busses/i2c-exynos5.c
>  create mode 100644 drivers/i2c/busses/i2c-exynos5.h
>
> diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
> index 65dd599..88e8833 100644
> --- a/drivers/i2c/busses/Kconfig
> +++ b/drivers/i2c/busses/Kconfig
> @@ -609,6 +609,12 @@ config I2C_S3C2410
>   Say Y here to include support for I2C controller in the
>   Samsung SoCs.
>
> +config I2C_EXYNOS5
> +   tristate "Exynos5 HS-I2C Driver"
> +   help
> + Say Y here to include support for High Speed I2C controller in the
> + Exynos5 series SoCs from Samsung.
> +
>  config I2C_S6000
> tristate "S6000 I2C support"
> depends on XTENSA_VARIANT_S6000
> diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
> index 2d33d62..426b4fd 100644
> --- a/drivers/i2c/busses/Makefile
> +++ b/drivers/i2c/busses/Makefile
> @@ -60,6 +60,7 @@ obj-$(CONFIG_I2C_PUV3)+= i2c-puv3.o
>  obj-$(CONFIG_I2C_PXA)  += i2c-pxa.o
>  obj-$(CONFIG_I2C_PXA_PCI)  += i2c-pxa-pci.o
>  obj-$(CONFIG_I2C_S3C2410)  += i2c-s3c2410.o
> +obj-$(CONFIG_I2C_EXYNOS5)  += i2c-exynos5.o
>  obj-$(CONFIG_I2C_S6000)+= i2c-s6000.o
>  obj-$(CONFIG_I2C_SH7760)   += i2c-sh7760.o
>  obj-$(CONFIG_I2C_SH_MOBILE)+= i2c-sh_mobile.o
> diff --git a/drivers/i2c/busses/i2c-exynos5.c 
> b/drivers/i2c/busses/i2c-exynos5.c
> new file mode 100644
> index 000..5983aa9
> --- /dev/null
> +++ b/drivers/i2c/busses/i2c-exynos5.c
> @@ -0,0 +1,758 @@
> +/* linux/drivers/i2c/busses/i2c-exynos5.c
> + *
> + * Copyright (C) 2012 Samsung Electronics Co., Ltd.
> + *
> + * Exynos5 series High Speed I2C controller driver
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> +*/
> +
> +#include 
> +#include 
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include 
> +#include "i2c-exynos5.h"
> +
> +#define HSI2C_POLLING 0
> +#define HSI2C_FAST_SPD 0
> +#define HSI2C_HIGH_SPD 1
> +
> +/* Max time to wait for bus to become idle after a xfer */
> +#define EXYNOS5_I2C_TIMEOUT (msecs_to_jiffies(1000))
> +
> +struct exynos5_i2c {
> +   unsigned intsuspended:1;
> +
> +   struct i2c_msg  *msg;
> +   struct completion   msg_complete;
> +   unsigned intmsg_byte_ptr;
> +
> +   unsigned intirq;
> +
> +   void __iomem*regs;
> +   struct clk  *clk;
> +   struct device   *dev;
> +   struct resource *ioarea;
> +   struct i2c_adapter  adap;
> +   unsigned intbus_number;
> +   unsigned intspeed_mode;
> +   unsigned intfast_speed;
> +   unsigned inthigh_speed;
> +   int operation_mode;
> +   int gpios[2];
> +};
> +
> +static struct platform_device_id exynos5_driver_ids[] = {
> +   {
> +   .name   = "exynos5-hs-i2c",
> +   .driver_data= 0,
> +   }, { },
> +};
> +MODULE_DEVICE_TABLE(platform, exynos5_driver_ids);
> +
> +#ifdef CONFIG_OF
> +static const struct of_device_id exynos5_i2c_match[] = {
> +   { .compatible = "samsung,exynos5-hs-i2c", .data = (void *)0 },
> +   {},
> +};
> +MODULE_DEVICE_TABLE(of, exynos5_i2c_match);
> +#endif
> +
> +static inline void dump_i2c_register(struct exynos5_i2c *i2c)
> +{
> +   dev_dbg(i2c->dev, "Register dump(%d) :\n %x\n %x\n %x\n %x\n"
> +   " %x\n %x\n %x\n %x\n %x\n"
> +   " %x\n %x\n %x\n %x\n %x\n"
> +   " %x\n %x\n %x\n %x\n %x\n"
> +   " %x\n %x\n %x\n %x\n %x\n"
> +   , i2c->suspended
> +   , readl(i2c->regs + HSI2C_CTL)
> +   , readl(i2c->regs + HSI2C_FIFO_CTL)
> +   , readl(i2c->regs + HSI2C_TRAILIG_CTL)
> +   , readl(i2c->regs + HSI2C_CLK_CTL)
> +   , readl(i2c->regs + HSI2C_CLK_SLOT)
> +   , readl(i2c->regs + HSI2C_INT_ENABLE)
> +   , readl(i2c->regs + HSI2C_INT_STATUS)
> +   , readl(i2c->regs + HSI2C_ERR_STATUS)
> +  

[PATCH] regulator: add device tree support for max8997

[Thomas Abraham]

Add device tree based discovery support for max8997.

Cc: Karol Lewandowski 
Cc: Rajendra Nayak 
Cc: Rob Herring 
Cc: Grant Likely 
Signed-off-by: Thomas Abraham 
Acked-by: MyungJoo Ham 
Reviewed-by: Tomasz Figa 
---
This patch is based on 'topic/max8997' branch of Mark Brown's
regulator tree.

 .../bindings/regulator/max8997-regulator.txt   |  146 +++
 drivers/mfd/max8997.c  |   73 ++-
 drivers/regulator/max8997.c|  148 +++-
 include/linux/mfd/max8997-private.h|1 +
 include/linux/mfd/max8997.h|1 +
 5 files changed, 366 insertions(+), 3 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/regulator/max8997-regulator.txt

diff --git a/Documentation/devicetree/bindings/regulator/max8997-regulator.txt 
b/Documentation/devicetree/bindings/regulator/max8997-regulator.txt
new file mode 100644
index 000..9fd69a1
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/max8997-regulator.txt
@@ -0,0 +1,146 @@
+* Maxim MAX8997 Voltage and Current Regulator
+
+The Maxim MAX8997 is a multi-function device which includes volatage and
+current regulators, rtc, charger controller and other sub-blocks. It is
+interfaced to the host controller using a i2c interface. Each sub-block is
+addressed by the host system using different i2c slave address. This document
+describes the bindings for 'pmic' sub-block of max8997.
+
+Required properties:
+- compatible: Should be "maxim,max8997-pmic".
+- reg: Specifies the i2c slave address of the pmic block. It should be 0x66.
+
+- max8997,pmic-buck1-dvs-voltage: A set of 8 voltage values in micro-volt (uV)
+  units for buck1 when changing voltage using gpio dvs. Refer to [1] below
+  for additional information.
+
+- max8997,pmic-buck2-dvs-voltage: A set of 8 voltage values in micro-volt (uV)
+  units for buck2 when changing voltage using gpio dvs. Refer to [1] below
+  for additional information.
+
+- max8997,pmic-buck5-dvs-voltage: A set of 8 voltage values in micro-volt (uV)
+  units for buck5 when changing voltage using gpio dvs. Refer to [1] below
+  for additional information.
+
+[1] If none of the 'max8997,pmic-buck[1/2/5]-uses-gpio-dvs' optional
+property is specified, the 'max8997,pmic-buck[1/2/5]-dvs-voltage'
+property should specify atleast one voltage level (which would be a
+safe operating voltage).
+
+If either of the 'max8997,pmic-buck[1/2/5]-uses-gpio-dvs' optional
+property is specified, then all the eigth voltage values for the
+'max8997,pmic-buck[1/2/5]-dvs-voltage' should be specified.
+
+Optional properties:
+- interrupt-parent: Specifies the phandle of the interrupt controller to which
+  the interrupts from max8997 are delivered to.
+- interrupts: Interrupt specifiers for two interrupt sources.
+  - First interrupt specifier is for 'irq1' interrupt.
+  - Second interrupt specifier is for 'alert' interrupt.
+- max8997,pmic-buck1-uses-gpio-dvs: 'buck1' can be controlled by gpio dvs.
+- max8997,pmic-buck2-uses-gpio-dvs: 'buck2' can be controlled by gpio dvs.
+- max8997,pmic-buck5-uses-gpio-dvs: 'buck5' can be controlled by gpio dvs.
+
+Additional properties required if either of the optional properties are used:
+- max8997,pmic-ignore-gpiodvs-side-effect: When GPIO-DVS mode is used for
+  multiple bucks, changing the voltage value of one of the bucks may affect
+  that of another buck, which is the side effect of the change (set_voltage).
+  Use this property to ignore such side effects and change the voltage.
+
+- max8997,pmic-buck125-default-dvs-idx: Default voltage setting selected from
+  the possible 8 options selectable by the dvs gpios. The value of this
+  property should be between 0 and 7. If not specified or if out of range, the
+  default value of this property is set to 0.
+
+- max8997,pmic-buck125-dvs-gpios: GPIO specifiers for three host gpio's used
+  for dvs. The format of the gpio specifier depends in the gpio controller.
+
+Regulators: The regulators of max8997 that have to be instantiated should be
+included in a sub-node named 'regulators'. Regulator nodes included in this
+sub-node should be of the format as listed below.
+
+   regulator_name {
+   standard regulator bindings here
+   };
+
+The following are the names of the regulators that the max8997 pmic block
+supports. Note: The 'n' in LDOn and BUCKn represents the LDO or BUCK number
+as per the datasheet of max8997.
+
+   - LDOn
+ - valid values for n are 1 to 18 and 21
+ - Example: LDO0, LD01, LDO2, LDO21
+   - BUCKn
+ - valid values for n are 1 to 7.
+ - Example: BUCK1, BUCK2, BUCK3, BUCK7
+
+   - ENVICHG: Battery Charging Current Monitor Output. This is a fixed
+  voltage type regulator
+
+   - ESAFEOUT1: (ldo19)
+   - ESAFEOUT2: (ld020)
+
+   - CHARGER_CV: ma

[PATCH] regulator: add device tree support for max8997

[Thomas Abraham]

Add device tree based discovery support for max8997.

Cc: Karol Lewandowski k.lewando...@samsung.com
Cc: Rajendra Nayak rna...@ti.com
Cc: Rob Herring rob.herr...@calxeda.com
Cc: Grant Likely grant.lik...@secretlab.ca
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
Acked-by: MyungJoo Ham myungjoo@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
This patch is based on 'topic/max8997' branch of Mark Brown's
regulator tree.

 .../bindings/regulator/max8997-regulator.txt   |  146 +++
 drivers/mfd/max8997.c  |   73 ++-
 drivers/regulator/max8997.c|  148 +++-
 include/linux/mfd/max8997-private.h|1 +
 include/linux/mfd/max8997.h|1 +
 5 files changed, 366 insertions(+), 3 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/regulator/max8997-regulator.txt

diff --git a/Documentation/devicetree/bindings/regulator/max8997-regulator.txt 
b/Documentation/devicetree/bindings/regulator/max8997-regulator.txt
new file mode 100644
index 000..9fd69a1
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/max8997-regulator.txt
@@ -0,0 +1,146 @@
+* Maxim MAX8997 Voltage and Current Regulator
+
+The Maxim MAX8997 is a multi-function device which includes volatage and
+current regulators, rtc, charger controller and other sub-blocks. It is
+interfaced to the host controller using a i2c interface. Each sub-block is
+addressed by the host system using different i2c slave address. This document
+describes the bindings for 'pmic' sub-block of max8997.
+
+Required properties:
+- compatible: Should be maxim,max8997-pmic.
+- reg: Specifies the i2c slave address of the pmic block. It should be 0x66.
+
+- max8997,pmic-buck1-dvs-voltage: A set of 8 voltage values in micro-volt (uV)
+  units for buck1 when changing voltage using gpio dvs. Refer to [1] below
+  for additional information.
+
+- max8997,pmic-buck2-dvs-voltage: A set of 8 voltage values in micro-volt (uV)
+  units for buck2 when changing voltage using gpio dvs. Refer to [1] below
+  for additional information.
+
+- max8997,pmic-buck5-dvs-voltage: A set of 8 voltage values in micro-volt (uV)
+  units for buck5 when changing voltage using gpio dvs. Refer to [1] below
+  for additional information.
+
+[1] If none of the 'max8997,pmic-buck[1/2/5]-uses-gpio-dvs' optional
+property is specified, the 'max8997,pmic-buck[1/2/5]-dvs-voltage'
+property should specify atleast one voltage level (which would be a
+safe operating voltage).
+
+If either of the 'max8997,pmic-buck[1/2/5]-uses-gpio-dvs' optional
+property is specified, then all the eigth voltage values for the
+'max8997,pmic-buck[1/2/5]-dvs-voltage' should be specified.
+
+Optional properties:
+- interrupt-parent: Specifies the phandle of the interrupt controller to which
+  the interrupts from max8997 are delivered to.
+- interrupts: Interrupt specifiers for two interrupt sources.
+  - First interrupt specifier is for 'irq1' interrupt.
+  - Second interrupt specifier is for 'alert' interrupt.
+- max8997,pmic-buck1-uses-gpio-dvs: 'buck1' can be controlled by gpio dvs.
+- max8997,pmic-buck2-uses-gpio-dvs: 'buck2' can be controlled by gpio dvs.
+- max8997,pmic-buck5-uses-gpio-dvs: 'buck5' can be controlled by gpio dvs.
+
+Additional properties required if either of the optional properties are used:
+- max8997,pmic-ignore-gpiodvs-side-effect: When GPIO-DVS mode is used for
+  multiple bucks, changing the voltage value of one of the bucks may affect
+  that of another buck, which is the side effect of the change (set_voltage).
+  Use this property to ignore such side effects and change the voltage.
+
+- max8997,pmic-buck125-default-dvs-idx: Default voltage setting selected from
+  the possible 8 options selectable by the dvs gpios. The value of this
+  property should be between 0 and 7. If not specified or if out of range, the
+  default value of this property is set to 0.
+
+- max8997,pmic-buck125-dvs-gpios: GPIO specifiers for three host gpio's used
+  for dvs. The format of the gpio specifier depends in the gpio controller.
+
+Regulators: The regulators of max8997 that have to be instantiated should be
+included in a sub-node named 'regulators'. Regulator nodes included in this
+sub-node should be of the format as listed below.
+
+   regulator_name {
+   standard regulator bindings here
+   };
+
+The following are the names of the regulators that the max8997 pmic block
+supports. Note: The 'n' in LDOn and BUCKn represents the LDO or BUCK number
+as per the datasheet of max8997.
+
+   - LDOn
+ - valid values for n are 1 to 18 and 21
+ - Example: LDO0, LD01, LDO2, LDO21
+   - BUCKn
+ - valid values for n are 1 to 7.
+ - Example: BUCK1, BUCK2, BUCK3, BUCK7
+
+   - ENVICHG: Battery Charging Current Monitor Output

Re: [PATCH 1/3] i2c: exynos5: add High Speed I2C controller driver

[Thomas Abraham]

On 27 November 2012 18:30, Naveen Krishna Chatradhi
ch.nav...@samsung.com wrote:
 Adds support for High Speed I2C driver found in Exynos5 and later
 SoCs from Samsung. This driver currently supports Auto mode.

 Driver only supports Device Tree method.

 Signed-off-by: Taekgyun Ko taeggyun...@samsung.com
 Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
 ---
  drivers/i2c/busses/Kconfig   |6 +
  drivers/i2c/busses/Makefile  |1 +
  drivers/i2c/busses/i2c-exynos5.c |  758 
 ++
  drivers/i2c/busses/i2c-exynos5.h |   80 
  4 files changed, 845 insertions(+)
  create mode 100644 drivers/i2c/busses/i2c-exynos5.c
  create mode 100644 drivers/i2c/busses/i2c-exynos5.h

 diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
 index 65dd599..88e8833 100644
 --- a/drivers/i2c/busses/Kconfig
 +++ b/drivers/i2c/busses/Kconfig
 @@ -609,6 +609,12 @@ config I2C_S3C2410
   Say Y here to include support for I2C controller in the
   Samsung SoCs.

 +config I2C_EXYNOS5
 +   tristate Exynos5 HS-I2C Driver
 +   help
 + Say Y here to include support for High Speed I2C controller in the
 + Exynos5 series SoCs from Samsung.
 +
  config I2C_S6000
 tristate S6000 I2C support
 depends on XTENSA_VARIANT_S6000
 diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
 index 2d33d62..426b4fd 100644
 --- a/drivers/i2c/busses/Makefile
 +++ b/drivers/i2c/busses/Makefile
 @@ -60,6 +60,7 @@ obj-$(CONFIG_I2C_PUV3)+= i2c-puv3.o
  obj-$(CONFIG_I2C_PXA)  += i2c-pxa.o
  obj-$(CONFIG_I2C_PXA_PCI)  += i2c-pxa-pci.o
  obj-$(CONFIG_I2C_S3C2410)  += i2c-s3c2410.o
 +obj-$(CONFIG_I2C_EXYNOS5)  += i2c-exynos5.o
  obj-$(CONFIG_I2C_S6000)+= i2c-s6000.o
  obj-$(CONFIG_I2C_SH7760)   += i2c-sh7760.o
  obj-$(CONFIG_I2C_SH_MOBILE)+= i2c-sh_mobile.o
 diff --git a/drivers/i2c/busses/i2c-exynos5.c 
 b/drivers/i2c/busses/i2c-exynos5.c
 new file mode 100644
 index 000..5983aa9
 --- /dev/null
 +++ b/drivers/i2c/busses/i2c-exynos5.c
 @@ -0,0 +1,758 @@
 +/* linux/drivers/i2c/busses/i2c-exynos5.c
 + *
 + * Copyright (C) 2012 Samsung Electronics Co., Ltd.
 + *
 + * Exynos5 series High Speed I2C controller driver
 + *
 + * This program is free software; you can redistribute it and/or modify
 + * it under the terms of the GNU General Public License version 2 as
 + * published by the Free Software Foundation.
 +*/
 +
 +#include linux/kernel.h
 +#include linux/module.h
 +
 +#include linux/i2c.h
 +#include linux/init.h
 +#include linux/time.h
 +#include linux/interrupt.h
 +#include linux/delay.h
 +#include linux/errno.h
 +#include linux/err.h
 +#include linux/platform_device.h
 +#include linux/clk.h
 +#include linux/slab.h
 +#include linux/io.h
 +#include linux/of_i2c.h
 +#include linux/of_gpio.h
 +
 +#include asm/irq.h
 +#include i2c-exynos5.h
 +
 +#define HSI2C_POLLING 0
 +#define HSI2C_FAST_SPD 0
 +#define HSI2C_HIGH_SPD 1
 +
 +/* Max time to wait for bus to become idle after a xfer */
 +#define EXYNOS5_I2C_TIMEOUT (msecs_to_jiffies(1000))
 +
 +struct exynos5_i2c {
 +   unsigned intsuspended:1;
 +
 +   struct i2c_msg  *msg;
 +   struct completion   msg_complete;
 +   unsigned intmsg_byte_ptr;
 +
 +   unsigned intirq;
 +
 +   void __iomem*regs;
 +   struct clk  *clk;
 +   struct device   *dev;
 +   struct resource *ioarea;
 +   struct i2c_adapter  adap;
 +   unsigned intbus_number;
 +   unsigned intspeed_mode;
 +   unsigned intfast_speed;
 +   unsigned inthigh_speed;
 +   int operation_mode;
 +   int gpios[2];
 +};
 +
 +static struct platform_device_id exynos5_driver_ids[] = {
 +   {
 +   .name   = exynos5-hs-i2c,
 +   .driver_data= 0,
 +   }, { },
 +};
 +MODULE_DEVICE_TABLE(platform, exynos5_driver_ids);
 +
 +#ifdef CONFIG_OF
 +static const struct of_device_id exynos5_i2c_match[] = {
 +   { .compatible = samsung,exynos5-hs-i2c, .data = (void *)0 },
 +   {},
 +};
 +MODULE_DEVICE_TABLE(of, exynos5_i2c_match);
 +#endif
 +
 +static inline void dump_i2c_register(struct exynos5_i2c *i2c)
 +{
 +   dev_dbg(i2c-dev, Register dump(%d) :\n %x\n %x\n %x\n %x\n
 +%x\n %x\n %x\n %x\n %x\n
 +%x\n %x\n %x\n %x\n %x\n
 +%x\n %x\n %x\n %x\n %x\n
 +%x\n %x\n %x\n %x\n %x\n
 +   , i2c-suspended
 +   , readl(i2c-regs + HSI2C_CTL)
 +   , readl(i2c-regs + HSI2C_FIFO_CTL)
 +   , readl(i2c-regs + HSI2C_TRAILIG_CTL)
 +   , readl(i2c-regs + HSI2C_CLK_CTL)
 +   , readl(i2c-regs + HSI2C_CLK_SLOT)
 +   , readl(i2c-regs + HSI2C_INT_ENABLE)
 +  

Re: [PATCH 3/3] regulator: add device tree support for max8997

[Thomas Abraham]

On 26 November 2012 19:41, Mark Brown
 wrote:
> On Mon, Nov 26, 2012 at 07:16:04PM +0530, Thomas Abraham wrote:
>
>> and this patch applied cleanly. Could you please let me know if there
>> is anything I need to be doing differently for this.
>
> Hrm, try applying it on the relevant topic branch.  Your comments about
> rebasing on top of MFD changes did suggest that there's something in the
> MFD tree so I didn't check terribly closely.

I tried applying this patch on the max8997 branch in your regulator
tree. But this patch does not apply cleanly on that branch because
commits "5eb9f2b96381" (regulator: remove use of __devexit_p),
"a5023574d120" (regulator: remove use of __devinit) and "8dc995f56ef7"
(regulator: remove use of __devexit) are not available on this branch
but these commits are already in your for-next branch.

I am not sure if it is of any help in rebasing this patch to the
existing max8997 branch. If you could suggest on how I could prepare
this patch so that applies cleanly for you, I could do that.

Thanks,
Thomas.
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Re: [PATCH 3/3] regulator: add device tree support for max8997

[Thomas Abraham]

On 26 November 2012 15:21, Mark Brown
 wrote:
> On Sat, Nov 24, 2012 at 11:46:51PM +0530, Thomas Abraham wrote:
>
>> The max8997 driver is mainlined. I actually meant to say that, this v6
>> version of dt support patch for max8997, is similar in functionality
>> to the v5 version of this patch. I did prepare this patch based on
>> your latest for-next branch.
>
> I find it hard to believe that this was generated against for-next, this
> was where I tried to apply it...

I tried again to apply this patch on 'for-next' branch of your
regulator tree 
(git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator.git)

on top of commit 6aa588f43d4a (Merge remote-tracking branches
'regulator/fix/wm831x', 'regulator/topic/as3711',
'regulator/topic/da9055', 'regulator/topic/hotplug',
'regulator/topic/lp8788'.)

and this patch applied cleanly. Could you please let me know if there
is anything I need to be doing differently for this.

Thanks,
Thomas.
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Re: [PATCH 3/3] regulator: add device tree support for max8997

[Thomas Abraham]

On 26 November 2012 15:21, Mark Brown
broo...@opensource.wolfsonmicro.com wrote:
 On Sat, Nov 24, 2012 at 11:46:51PM +0530, Thomas Abraham wrote:

 The max8997 driver is mainlined. I actually meant to say that, this v6
 version of dt support patch for max8997, is similar in functionality
 to the v5 version of this patch. I did prepare this patch based on
 your latest for-next branch.

 I find it hard to believe that this was generated against for-next, this
 was where I tried to apply it...

I tried again to apply this patch on 'for-next' branch of your
regulator tree 
(git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator.git)

on top of commit 6aa588f43d4a (Merge remote-tracking branches
'regulator/fix/wm831x', 'regulator/topic/as3711',
'regulator/topic/da9055', 'regulator/topic/hotplug',
'regulator/topic/lp8788'.)

and this patch applied cleanly. Could you please let me know if there
is anything I need to be doing differently for this.

Thanks,
Thomas.
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Re: [PATCH 3/3] regulator: add device tree support for max8997

[Thomas Abraham]

On 26 November 2012 19:41, Mark Brown
broo...@opensource.wolfsonmicro.com wrote:
 On Mon, Nov 26, 2012 at 07:16:04PM +0530, Thomas Abraham wrote:

 and this patch applied cleanly. Could you please let me know if there
 is anything I need to be doing differently for this.

 Hrm, try applying it on the relevant topic branch.  Your comments about
 rebasing on top of MFD changes did suggest that there's something in the
 MFD tree so I didn't check terribly closely.

I tried applying this patch on the max8997 branch in your regulator
tree. But this patch does not apply cleanly on that branch because
commits 5eb9f2b96381 (regulator: remove use of __devexit_p),
a5023574d120 (regulator: remove use of __devinit) and 8dc995f56ef7
(regulator: remove use of __devexit) are not available on this branch
but these commits are already in your for-next branch.

I am not sure if it is of any help in rebasing this patch to the
existing max8997 branch. If you could suggest on how I could prepare
this patch so that applies cleanly for you, I could do that.

Thanks,
Thomas.
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Re: [PATCH 3/3] regulator: add device tree support for max8997

[Thomas Abraham]

On 24 November 2012 23:29, Mark Brown
 wrote:
> On Fri, Nov 23, 2012 at 01:33:15PM +0530, Thomas Abraham wrote:
>
>> This v6 patch is rebased to the latest max8997 driver code and there are no
>> functional changes from v5.
>
> That doesn't seem to be in mainline yet so the patch won't apply.

Hi Mark,

The max8997 driver is mainlined. I actually meant to say that, this v6
version of dt support patch for max8997, is similar in functionality
to the v5 version of this patch. I did prepare this patch based on
your latest for-next branch.

Thanks,
Thomas.
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Re: [PATCH 3/3] regulator: add device tree support for max8997

[Thomas Abraham]

On 24 November 2012 23:29, Mark Brown
broo...@opensource.wolfsonmicro.com wrote:
 On Fri, Nov 23, 2012 at 01:33:15PM +0530, Thomas Abraham wrote:

 This v6 patch is rebased to the latest max8997 driver code and there are no
 functional changes from v5.

 That doesn't seem to be in mainline yet so the patch won't apply.

Hi Mark,

The max8997 driver is mainlined. I actually meant to say that, this v6
version of dt support patch for max8997, is similar in functionality
to the v5 version of this patch. I did prepare this patch based on
your latest for-next branch.

Thanks,
Thomas.
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[PATCH 3/3] regulator: add device tree support for max8997

[Thomas Abraham]

Add device tree based discovery support for max8997.

Cc: Karol Lewandowski 
Cc: Rajendra Nayak 
Cc: Rob Herring 
Cc: Grant Likely 
Signed-off-by: Thomas Abraham 
Acked-by: MyungJoo Ham 
---
This is the sixth version of this patch. The link to v5 version of this patch
is http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg10368.html.
The v5 of this patch was merged by Mark Brown and later reverted from his tree
(http://lkml.indiana.edu/hypermail/linux/kernel/1204.2/00963.html) since there
was conflict in the first patch of the series which was then later corrected
by Chanwoo Choi  (https://lkml.org/lkml/2012/7/5/256).
This v6 patch is rebased to the latest max8997 driver code and there are no
functional changes from v5.

 .../bindings/regulator/max8997-regulator.txt   |  146 +++
 drivers/mfd/max8997.c  |   73 ++-
 drivers/regulator/max8997.c|  148 +++-
 include/linux/mfd/max8997-private.h|1 +
 include/linux/mfd/max8997.h|1 +
 5 files changed, 366 insertions(+), 3 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/regulator/max8997-regulator.txt

diff --git a/Documentation/devicetree/bindings/regulator/max8997-regulator.txt 
b/Documentation/devicetree/bindings/regulator/max8997-regulator.txt
new file mode 100644
index 000..d3fbc36
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/max8997-regulator.txt
@@ -0,0 +1,146 @@
+* Maxim MAX8997 Voltage and Current Regulator
+
+The Maxim MAX8997 is a multi-function device which includes volatage and
+current regulators, rtc, charger controller and other sub-blocks. It is
+interfaced to the host controller using a i2c interface. Each sub-block is
+addressed by the host system using different i2c slave address. This document
+describes the bindings for 'pmic' sub-block of max8997.
+
+Required properties:
+- compatible: Should be "maxim,max8997-pmic".
+- reg: Specifies the i2c slave address of the pmic block. It should be 0x66.
+
+- max8997,pmic-buck1-dvs-voltage: A set of 8 voltage values in micro-volt (uV)
+  units for buck1 when changing voltage using gpio dvs. Refer to [1] below
+  for additional information.
+
+- max8997,pmic-buck2-dvs-voltage: A set of 8 voltage values in micro-volt (uV)
+  units for buck2 when changing voltage using gpio dvs. Refer to [1] below
+  for additional information.
+
+- max8997,pmic-buck5-dvs-voltage: A set of 8 voltage values in micro-volt (uV)
+  units for buck5 when changing voltage using gpio dvs. Refer to [1] below
+  for additional information.
+
+[1] If none of the 'max8997,pmic-buck[1/2/5]-uses-gpio-dvs' optional
+property is specified, the 'max8997,pmic-buck[1/2/5]-dvs-voltage'
+property should specify atleast one voltage level (which would be a
+safe operating voltage).
+
+If either of the 'max8997,pmic-buck[1/2/5]-uses-gpio-dvs' optional
+property is specified, then all the eigth voltage values for the
+'max8997,pmic-buck[1/2/5]-dvs-voltage' should be specified.
+
+Optional properties:
+- interrupt-parent: Specifies the phandle of the interrupt controller to which
+  the interrupts from max8997 are delivered to.
+- interrupts: Interrupt specifiers for two interrupt sources.
+  - First interrupt specifier is for 'irq1' interrupt.
+  - Second interrupt specifier is for 'alert' interrupt.
+- max8997,pmic-buck1-uses-gpio-dvs: 'buck1' can be controlled by gpio dvs.
+- max8997,pmic-buck2-uses-gpio-dvs: 'buck2' can be controlled by gpio dvs.
+- max8997,pmic-buck5-uses-gpio-dvs: 'buck5' can be controlled by gpio dvs.
+
+Additional properties required if either of the optional properties are used:
+- max8997,pmic-ignore-gpiodvs-side-effect: When GPIO-DVS mode is used for
+  multiple bucks, changing the voltage value of one of the bucks may affect
+  that of another buck, which is the side effect of the change (set_voltage).
+  Use this property to ignore such side effects and change the voltage.
+
+- max8997,pmic-buck125-default-dvs-idx: Default voltage setting selected from
+  the possible 8 options selectable by the dvs gpios. The value of this
+  property should be between 0 and 7. If not specified or if out of range, the
+  default value of this property is set to 0.
+
+- max8997,pmic-buck125-dvs-gpios: GPIO specifiers for three host gpio's used
+  for dvs. The format of the gpio specifier depends in the gpio controller.
+
+Regulators: The regulators of max8997 that have to be instantiated should be
+included in a sub-node named 'regulators'. Regulator nodes included in this
+sub-node should be of the format as listed below.
+
+   regulator_name {
+   standard regulator bindings here
+   };
+
+The following are the names of the regulators that the max8997 pmic block
+supports. Note: The 'n' in LDOn and BUCKn represents the LDO or BUCK number
+as per the datasheet of max8997.
+
+   

[PATCH 2/3] regulator: max8997: limit the number of dvs registers programmed in non-dvs mode

[Thomas Abraham]

In case the gpio based volatage selection mode is not used for either of
buck 1/2/5, then only the BUCKxDVS1 register need to be programmed. So
determine whether dvs mode is used and limit the loop count appropriately.

Cc: MyungJoo Ham 
Signed-off-by: Thomas Abraham 
---
 drivers/regulator/max8997.c |9 ++---
 1 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/regulator/max8997.c b/drivers/regulator/max8997.c
index 8901371..231fcdb 100644
--- a/drivers/regulator/max8997.c
+++ b/drivers/regulator/max8997.c
@@ -941,7 +941,7 @@ static int max8997_pmic_probe(struct platform_device *pdev)
struct regulator_dev **rdev;
struct max8997_data *max8997;
struct i2c_client *i2c;
-   int i, ret, size;
+   int i, ret, size, nr_dvs;
u8 max_buck1 = 0, max_buck2 = 0, max_buck5 = 0;
 
if (!pdata) {
@@ -973,7 +973,10 @@ static int max8997_pmic_probe(struct platform_device *pdev)
memcpy(max8997->buck125_gpios, pdata->buck125_gpios, sizeof(int) * 3);
max8997->ignore_gpiodvs_side_effect = pdata->ignore_gpiodvs_side_effect;
 
-   for (i = 0; i < 8; i++) {
+   nr_dvs = (pdata->buck1_gpiodvs || pdata->buck2_gpiodvs ||
+   pdata->buck5_gpiodvs) ? 8 : 1;
+
+   for (i = 0; i < nr_dvs; i++) {
max8997->buck1_vol[i] = ret =
max8997_get_voltage_proper_val(
_voltage_map_desc,
@@ -1020,7 +1023,7 @@ static int max8997_pmic_probe(struct platform_device 
*pdev)
}
 
/* Initialize all the DVS related BUCK registers */
-   for (i = 0; i < 8; i++) {
+   for (i = 0; i < nr_dvs; i++) {
max8997_update_reg(i2c, MAX8997_REG_BUCK1DVS1 + i,
max8997->buck1_vol[i],
0x3f);
-- 
1.6.6.rc2

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[PATCH 1/3] regulator: max8997: reorder buck1/2/5 dvs setup code

[Thomas Abraham]

The BUCKxDVSx register programming is now moved prior to setting up of the
gpio based dvs mode. This will ensure that all the BUCKxDVSx registers
are programmed with appropriate voltage values before the gpio based dvs
mode is selected for buck1/2/5.

Cc: MyungJoo Ham 
Signed-off-by: Thomas Abraham 
---
 drivers/regulator/max8997.c |   26 +-
 1 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/drivers/regulator/max8997.c b/drivers/regulator/max8997.c
index cea9ec9..8901371 100644
--- a/drivers/regulator/max8997.c
+++ b/drivers/regulator/max8997.c
@@ -1019,6 +1019,19 @@ static int max8997_pmic_probe(struct platform_device 
*pdev)
max_buck5, 0x3f);
}
 
+   /* Initialize all the DVS related BUCK registers */
+   for (i = 0; i < 8; i++) {
+   max8997_update_reg(i2c, MAX8997_REG_BUCK1DVS1 + i,
+   max8997->buck1_vol[i],
+   0x3f);
+   max8997_update_reg(i2c, MAX8997_REG_BUCK2DVS1 + i,
+   max8997->buck2_vol[i],
+   0x3f);
+   max8997_update_reg(i2c, MAX8997_REG_BUCK5DVS1 + i,
+   max8997->buck5_vol[i],
+   0x3f);
+   }
+
/*
 * If buck 1, 2, and 5 do not care DVS GPIO settings, ignore them.
 * If at least one of them cares, set gpios.
@@ -1068,19 +1081,6 @@ static int max8997_pmic_probe(struct platform_device 
*pdev)
max8997_update_reg(i2c, MAX8997_REG_BUCK5CTRL, (pdata->buck5_gpiodvs) ?
(1 << 1) : (0 << 1), 1 << 1);
 
-   /* Initialize all the DVS related BUCK registers */
-   for (i = 0; i < 8; i++) {
-   max8997_update_reg(i2c, MAX8997_REG_BUCK1DVS1 + i,
-   max8997->buck1_vol[i],
-   0x3f);
-   max8997_update_reg(i2c, MAX8997_REG_BUCK2DVS1 + i,
-   max8997->buck2_vol[i],
-   0x3f);
-   max8997_update_reg(i2c, MAX8997_REG_BUCK5DVS1 + i,
-   max8997->buck5_vol[i],
-   0x3f);
-   }
-
/* Misc Settings */
max8997->ramp_delay = 10; /* set 10mV/us, which is the default */
max8997_write_reg(i2c, MAX8997_REG_BUCKRAMP, (0xf << 4) | 0x9);
-- 
1.6.6.rc2

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[PATCH 0/3] regulator: max8997: minor updates and device tree support

[Thomas Abraham]

This patch series includes two minor updates to the gpio dvs code in max8997
regulator driver and adds device tree support for the same driver.

Thomas Abraham (3):
  regulator: max8997: reorder buck1/2/5 dvs setup code
  regulator: max8997: limit the number of dvs registers programmed in non-dvs 
mode
  regulator: add device tree support for max8997

 .../bindings/regulator/max8997-regulator.txt   |  146 
 drivers/mfd/max8997.c  |   73 -
 drivers/regulator/max8997.c|  181 ++--
 include/linux/mfd/max8997-private.h|1 +
 include/linux/mfd/max8997.h|1 +
 5 files changed, 384 insertions(+), 18 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/regulator/max8997-regulator.txt

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Re: [PATCH] regulator: max8997: skip gpio dvs setup if not used

[Thomas Abraham]

Dear Mr. Ham,

Thanks for your comments.

On 21 November 2012 20:01, MyungJoo Ham  wrote:
> On Wed, Nov 21, 2012 at 11:23 PM, Thomas Abraham
>  wrote:
>> If gpio based voltage selection for buck 1/2/5 are not used, then the 
>> execution
>> of gpio dvs setup code during probe can be skipped completly.
>
> Even if GPIO-DVS feature is turned off, you need to setup BUCKxDVS1 anyway.
> Otherwise, you may get "unspecified" behavior from the BUCK1/2/5,
> which may incur unstable system.

I was looking into the documents but I did not find that this
condition being documented. Anyways, based on your comments, I have
tested two changes in the max8997 driver.

The first change moves the programming of the DVS related BUCK
registers above the programming of the BUCKxCTRL register. This is
required because by the time the BUCKxCTRL register is configured, the
corresponding voltage levels should already be programmed in BUCKxDVSx
registers.

diff --git a/drivers/regulator/max8997.c b/drivers/regulator/max8997.c
index cea9ec9..8901371 100644
--- a/drivers/regulator/max8997.c
+++ b/drivers/regulator/max8997.c
@@ -1019,6 +1019,19 @@ static int max8997_pmic_probe(struct
platform_device *pdev)
max_buck5, 0x3f);
}

+   /* Initialize all the DVS related BUCK registers */
+   for (i = 0; i < 8; i++) {
+   max8997_update_reg(i2c, MAX8997_REG_BUCK1DVS1 + i,
+   max8997->buck1_vol[i],
+   0x3f);
+   max8997_update_reg(i2c, MAX8997_REG_BUCK2DVS1 + i,
+   max8997->buck2_vol[i],
+   0x3f);
+   max8997_update_reg(i2c, MAX8997_REG_BUCK5DVS1 + i,
+   max8997->buck5_vol[i],
+   0x3f);
+   }
+
/*
 * If buck 1, 2, and 5 do not care DVS GPIO settings, ignore them.
 * If at least one of them cares, set gpios.
@@ -1068,19 +1081,6 @@ static int max8997_pmic_probe(struct
platform_device *pdev)
max8997_update_reg(i2c, MAX8997_REG_BUCK5CTRL, (pdata->buck5_gpiodvs) ?
(1 << 1) : (0 << 1), 1 << 1);

-   /* Initialize all the DVS related BUCK registers */
-   for (i = 0; i < 8; i++) {
-   max8997_update_reg(i2c, MAX8997_REG_BUCK1DVS1 + i,
-   max8997->buck1_vol[i],
-   0x3f);
-   max8997_update_reg(i2c, MAX8997_REG_BUCK2DVS1 + i,
-   max8997->buck2_vol[i],
-   0x3f);
-   max8997_update_reg(i2c, MAX8997_REG_BUCK5DVS1 + i,
-   max8997->buck5_vol[i],
-   0x3f);
-   }
-
/* Misc Settings */
max8997->ramp_delay = 10; /* set 10mV/us, which is the default */
max8997_write_reg(i2c, MAX8997_REG_BUCKRAMP, (0xf << 4) | 0x9);


In the second change, if the DVS feature is used, all the 8 BUCKxDVSx
registers are programmed. If DVS feature is not used, only BUCKxDVS1
register is programmed.

diff --git a/drivers/regulator/max8997.c b/drivers/regulator/max8997.c
index 8901371..231fcdb 100644
--- a/drivers/regulator/max8997.c
+++ b/drivers/regulator/max8997.c
@@ -941,7 +941,7 @@ static int max8997_pmic_probe(struct platform_device *pdev)
struct regulator_dev **rdev;
struct max8997_data *max8997;
struct i2c_client *i2c;
-   int i, ret, size;
+   int i, ret, size, nr_dvs;
u8 max_buck1 = 0, max_buck2 = 0, max_buck5 = 0;

if (!pdata) {
@@ -973,7 +973,10 @@ static int max8997_pmic_probe(struct platform_device *pdev)
memcpy(max8997->buck125_gpios, pdata->buck125_gpios, sizeof(int) * 3);
max8997->ignore_gpiodvs_side_effect = pdata->ignore_gpiodvs_side_effect;

-   for (i = 0; i < 8; i++) {
+   nr_dvs = (pdata->buck1_gpiodvs || pdata->buck2_gpiodvs ||
+   pdata->buck5_gpiodvs) ? 8 : 1;
+
+   for (i = 0; i < nr_dvs; i++) {
max8997->buck1_vol[i] = ret =
max8997_get_voltage_proper_val(
_voltage_map_desc,
@@ -1020,7 +1023,7 @@ static int max8997_pmic_probe(struct
platform_device *pdev)
}

/* Initialize all the DVS related BUCK registers */
-   for (i = 0; i < 8; i++) {
+   for (i = 0; i < nr_dvs; i++) {
max8997_update_reg(i2c, MAX8997_REG_BUCK1DVS1 + i,
max8997->buck1_vol[i],
0x3f);

If these changes are correct, could you please let me know. I will
submit patches for these changes.

Thanks for your time.

Regards,
Thomas.

> Cheers,
> MyungJoo
>
>
> --
> MyungJoo Ham, Ph.D.
> Mobile Softwa

Re: [PATCH] regulator: max8997: skip gpio dvs setup if not used

[Thomas Abraham]

Dear Mr. Ham,

Thanks for your comments.

On 21 November 2012 20:01, MyungJoo Ham myungjoo@samsung.com wrote:
 On Wed, Nov 21, 2012 at 11:23 PM, Thomas Abraham
 thomas.abra...@linaro.org wrote:
 If gpio based voltage selection for buck 1/2/5 are not used, then the 
 execution
 of gpio dvs setup code during probe can be skipped completly.

 Even if GPIO-DVS feature is turned off, you need to setup BUCKxDVS1 anyway.
 Otherwise, you may get unspecified behavior from the BUCK1/2/5,
 which may incur unstable system.

I was looking into the documents but I did not find that this
condition being documented. Anyways, based on your comments, I have
tested two changes in the max8997 driver.

The first change moves the programming of the DVS related BUCK
registers above the programming of the BUCKxCTRL register. This is
required because by the time the BUCKxCTRL register is configured, the
corresponding voltage levels should already be programmed in BUCKxDVSx
registers.

diff --git a/drivers/regulator/max8997.c b/drivers/regulator/max8997.c
index cea9ec9..8901371 100644
--- a/drivers/regulator/max8997.c
+++ b/drivers/regulator/max8997.c
@@ -1019,6 +1019,19 @@ static int max8997_pmic_probe(struct
platform_device *pdev)
max_buck5, 0x3f);
}

+   /* Initialize all the DVS related BUCK registers */
+   for (i = 0; i  8; i++) {
+   max8997_update_reg(i2c, MAX8997_REG_BUCK1DVS1 + i,
+   max8997-buck1_vol[i],
+   0x3f);
+   max8997_update_reg(i2c, MAX8997_REG_BUCK2DVS1 + i,
+   max8997-buck2_vol[i],
+   0x3f);
+   max8997_update_reg(i2c, MAX8997_REG_BUCK5DVS1 + i,
+   max8997-buck5_vol[i],
+   0x3f);
+   }
+
/*
 * If buck 1, 2, and 5 do not care DVS GPIO settings, ignore them.
 * If at least one of them cares, set gpios.
@@ -1068,19 +1081,6 @@ static int max8997_pmic_probe(struct
platform_device *pdev)
max8997_update_reg(i2c, MAX8997_REG_BUCK5CTRL, (pdata-buck5_gpiodvs) ?
(1  1) : (0  1), 1  1);

-   /* Initialize all the DVS related BUCK registers */
-   for (i = 0; i  8; i++) {
-   max8997_update_reg(i2c, MAX8997_REG_BUCK1DVS1 + i,
-   max8997-buck1_vol[i],
-   0x3f);
-   max8997_update_reg(i2c, MAX8997_REG_BUCK2DVS1 + i,
-   max8997-buck2_vol[i],
-   0x3f);
-   max8997_update_reg(i2c, MAX8997_REG_BUCK5DVS1 + i,
-   max8997-buck5_vol[i],
-   0x3f);
-   }
-
/* Misc Settings */
max8997-ramp_delay = 10; /* set 10mV/us, which is the default */
max8997_write_reg(i2c, MAX8997_REG_BUCKRAMP, (0xf  4) | 0x9);


In the second change, if the DVS feature is used, all the 8 BUCKxDVSx
registers are programmed. If DVS feature is not used, only BUCKxDVS1
register is programmed.

diff --git a/drivers/regulator/max8997.c b/drivers/regulator/max8997.c
index 8901371..231fcdb 100644
--- a/drivers/regulator/max8997.c
+++ b/drivers/regulator/max8997.c
@@ -941,7 +941,7 @@ static int max8997_pmic_probe(struct platform_device *pdev)
struct regulator_dev **rdev;
struct max8997_data *max8997;
struct i2c_client *i2c;
-   int i, ret, size;
+   int i, ret, size, nr_dvs;
u8 max_buck1 = 0, max_buck2 = 0, max_buck5 = 0;

if (!pdata) {
@@ -973,7 +973,10 @@ static int max8997_pmic_probe(struct platform_device *pdev)
memcpy(max8997-buck125_gpios, pdata-buck125_gpios, sizeof(int) * 3);
max8997-ignore_gpiodvs_side_effect = pdata-ignore_gpiodvs_side_effect;

-   for (i = 0; i  8; i++) {
+   nr_dvs = (pdata-buck1_gpiodvs || pdata-buck2_gpiodvs ||
+   pdata-buck5_gpiodvs) ? 8 : 1;
+
+   for (i = 0; i  nr_dvs; i++) {
max8997-buck1_vol[i] = ret =
max8997_get_voltage_proper_val(
buck1245_voltage_map_desc,
@@ -1020,7 +1023,7 @@ static int max8997_pmic_probe(struct
platform_device *pdev)
}

/* Initialize all the DVS related BUCK registers */
-   for (i = 0; i  8; i++) {
+   for (i = 0; i  nr_dvs; i++) {
max8997_update_reg(i2c, MAX8997_REG_BUCK1DVS1 + i,
max8997-buck1_vol[i],
0x3f);

If these changes are correct, could you please let me know. I will
submit patches for these changes.

Thanks for your time.

Regards,
Thomas.

 Cheers,
 MyungJoo


 --
 MyungJoo Ham, Ph.D.
 Mobile Software Platform Lab, DMC Business, Samsung Electronics
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[PATCH 0/3] regulator: max8997: minor updates and device tree support

[Thomas Abraham]

This patch series includes two minor updates to the gpio dvs code in max8997
regulator driver and adds device tree support for the same driver.

Thomas Abraham (3):
  regulator: max8997: reorder buck1/2/5 dvs setup code
  regulator: max8997: limit the number of dvs registers programmed in non-dvs 
mode
  regulator: add device tree support for max8997

 .../bindings/regulator/max8997-regulator.txt   |  146 
 drivers/mfd/max8997.c  |   73 -
 drivers/regulator/max8997.c|  181 ++--
 include/linux/mfd/max8997-private.h|1 +
 include/linux/mfd/max8997.h|1 +
 5 files changed, 384 insertions(+), 18 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/regulator/max8997-regulator.txt

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[PATCH 1/3] regulator: max8997: reorder buck1/2/5 dvs setup code

[Thomas Abraham]

The BUCKxDVSx register programming is now moved prior to setting up of the
gpio based dvs mode. This will ensure that all the BUCKxDVSx registers
are programmed with appropriate voltage values before the gpio based dvs
mode is selected for buck1/2/5.

Cc: MyungJoo Ham myungjoo@samsung.com
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
---
 drivers/regulator/max8997.c |   26 +-
 1 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/drivers/regulator/max8997.c b/drivers/regulator/max8997.c
index cea9ec9..8901371 100644
--- a/drivers/regulator/max8997.c
+++ b/drivers/regulator/max8997.c
@@ -1019,6 +1019,19 @@ static int max8997_pmic_probe(struct platform_device 
*pdev)
max_buck5, 0x3f);
}
 
+   /* Initialize all the DVS related BUCK registers */
+   for (i = 0; i  8; i++) {
+   max8997_update_reg(i2c, MAX8997_REG_BUCK1DVS1 + i,
+   max8997-buck1_vol[i],
+   0x3f);
+   max8997_update_reg(i2c, MAX8997_REG_BUCK2DVS1 + i,
+   max8997-buck2_vol[i],
+   0x3f);
+   max8997_update_reg(i2c, MAX8997_REG_BUCK5DVS1 + i,
+   max8997-buck5_vol[i],
+   0x3f);
+   }
+
/*
 * If buck 1, 2, and 5 do not care DVS GPIO settings, ignore them.
 * If at least one of them cares, set gpios.
@@ -1068,19 +1081,6 @@ static int max8997_pmic_probe(struct platform_device 
*pdev)
max8997_update_reg(i2c, MAX8997_REG_BUCK5CTRL, (pdata-buck5_gpiodvs) ?
(1  1) : (0  1), 1  1);
 
-   /* Initialize all the DVS related BUCK registers */
-   for (i = 0; i  8; i++) {
-   max8997_update_reg(i2c, MAX8997_REG_BUCK1DVS1 + i,
-   max8997-buck1_vol[i],
-   0x3f);
-   max8997_update_reg(i2c, MAX8997_REG_BUCK2DVS1 + i,
-   max8997-buck2_vol[i],
-   0x3f);
-   max8997_update_reg(i2c, MAX8997_REG_BUCK5DVS1 + i,
-   max8997-buck5_vol[i],
-   0x3f);
-   }
-
/* Misc Settings */
max8997-ramp_delay = 10; /* set 10mV/us, which is the default */
max8997_write_reg(i2c, MAX8997_REG_BUCKRAMP, (0xf  4) | 0x9);
-- 
1.6.6.rc2

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[PATCH 2/3] regulator: max8997: limit the number of dvs registers programmed in non-dvs mode

[Thomas Abraham]

In case the gpio based volatage selection mode is not used for either of
buck 1/2/5, then only the BUCKxDVS1 register need to be programmed. So
determine whether dvs mode is used and limit the loop count appropriately.

Cc: MyungJoo Ham myungjoo@samsung.com
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
---
 drivers/regulator/max8997.c |9 ++---
 1 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/regulator/max8997.c b/drivers/regulator/max8997.c
index 8901371..231fcdb 100644
--- a/drivers/regulator/max8997.c
+++ b/drivers/regulator/max8997.c
@@ -941,7 +941,7 @@ static int max8997_pmic_probe(struct platform_device *pdev)
struct regulator_dev **rdev;
struct max8997_data *max8997;
struct i2c_client *i2c;
-   int i, ret, size;
+   int i, ret, size, nr_dvs;
u8 max_buck1 = 0, max_buck2 = 0, max_buck5 = 0;
 
if (!pdata) {
@@ -973,7 +973,10 @@ static int max8997_pmic_probe(struct platform_device *pdev)
memcpy(max8997-buck125_gpios, pdata-buck125_gpios, sizeof(int) * 3);
max8997-ignore_gpiodvs_side_effect = pdata-ignore_gpiodvs_side_effect;
 
-   for (i = 0; i  8; i++) {
+   nr_dvs = (pdata-buck1_gpiodvs || pdata-buck2_gpiodvs ||
+   pdata-buck5_gpiodvs) ? 8 : 1;
+
+   for (i = 0; i  nr_dvs; i++) {
max8997-buck1_vol[i] = ret =
max8997_get_voltage_proper_val(
buck1245_voltage_map_desc,
@@ -1020,7 +1023,7 @@ static int max8997_pmic_probe(struct platform_device 
*pdev)
}
 
/* Initialize all the DVS related BUCK registers */
-   for (i = 0; i  8; i++) {
+   for (i = 0; i  nr_dvs; i++) {
max8997_update_reg(i2c, MAX8997_REG_BUCK1DVS1 + i,
max8997-buck1_vol[i],
0x3f);
-- 
1.6.6.rc2

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[PATCH 3/3] regulator: add device tree support for max8997

[Thomas Abraham]

Add device tree based discovery support for max8997.

Cc: Karol Lewandowski k.lewando...@samsung.com
Cc: Rajendra Nayak rna...@ti.com
Cc: Rob Herring rob.herr...@calxeda.com
Cc: Grant Likely grant.lik...@secretlab.ca
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
Acked-by: MyungJoo Ham myungjoo@samsung.com
---
This is the sixth version of this patch. The link to v5 version of this patch
is http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg10368.html.
The v5 of this patch was merged by Mark Brown and later reverted from his tree
(http://lkml.indiana.edu/hypermail/linux/kernel/1204.2/00963.html) since there
was conflict in the first patch of the series which was then later corrected
by Chanwoo Choi cw00.c...@samsung.com (https://lkml.org/lkml/2012/7/5/256).
This v6 patch is rebased to the latest max8997 driver code and there are no
functional changes from v5.

 .../bindings/regulator/max8997-regulator.txt   |  146 +++
 drivers/mfd/max8997.c  |   73 ++-
 drivers/regulator/max8997.c|  148 +++-
 include/linux/mfd/max8997-private.h|1 +
 include/linux/mfd/max8997.h|1 +
 5 files changed, 366 insertions(+), 3 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/regulator/max8997-regulator.txt

diff --git a/Documentation/devicetree/bindings/regulator/max8997-regulator.txt 
b/Documentation/devicetree/bindings/regulator/max8997-regulator.txt
new file mode 100644
index 000..d3fbc36
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/max8997-regulator.txt
@@ -0,0 +1,146 @@
+* Maxim MAX8997 Voltage and Current Regulator
+
+The Maxim MAX8997 is a multi-function device which includes volatage and
+current regulators, rtc, charger controller and other sub-blocks. It is
+interfaced to the host controller using a i2c interface. Each sub-block is
+addressed by the host system using different i2c slave address. This document
+describes the bindings for 'pmic' sub-block of max8997.
+
+Required properties:
+- compatible: Should be maxim,max8997-pmic.
+- reg: Specifies the i2c slave address of the pmic block. It should be 0x66.
+
+- max8997,pmic-buck1-dvs-voltage: A set of 8 voltage values in micro-volt (uV)
+  units for buck1 when changing voltage using gpio dvs. Refer to [1] below
+  for additional information.
+
+- max8997,pmic-buck2-dvs-voltage: A set of 8 voltage values in micro-volt (uV)
+  units for buck2 when changing voltage using gpio dvs. Refer to [1] below
+  for additional information.
+
+- max8997,pmic-buck5-dvs-voltage: A set of 8 voltage values in micro-volt (uV)
+  units for buck5 when changing voltage using gpio dvs. Refer to [1] below
+  for additional information.
+
+[1] If none of the 'max8997,pmic-buck[1/2/5]-uses-gpio-dvs' optional
+property is specified, the 'max8997,pmic-buck[1/2/5]-dvs-voltage'
+property should specify atleast one voltage level (which would be a
+safe operating voltage).
+
+If either of the 'max8997,pmic-buck[1/2/5]-uses-gpio-dvs' optional
+property is specified, then all the eigth voltage values for the
+'max8997,pmic-buck[1/2/5]-dvs-voltage' should be specified.
+
+Optional properties:
+- interrupt-parent: Specifies the phandle of the interrupt controller to which
+  the interrupts from max8997 are delivered to.
+- interrupts: Interrupt specifiers for two interrupt sources.
+  - First interrupt specifier is for 'irq1' interrupt.
+  - Second interrupt specifier is for 'alert' interrupt.
+- max8997,pmic-buck1-uses-gpio-dvs: 'buck1' can be controlled by gpio dvs.
+- max8997,pmic-buck2-uses-gpio-dvs: 'buck2' can be controlled by gpio dvs.
+- max8997,pmic-buck5-uses-gpio-dvs: 'buck5' can be controlled by gpio dvs.
+
+Additional properties required if either of the optional properties are used:
+- max8997,pmic-ignore-gpiodvs-side-effect: When GPIO-DVS mode is used for
+  multiple bucks, changing the voltage value of one of the bucks may affect
+  that of another buck, which is the side effect of the change (set_voltage).
+  Use this property to ignore such side effects and change the voltage.
+
+- max8997,pmic-buck125-default-dvs-idx: Default voltage setting selected from
+  the possible 8 options selectable by the dvs gpios. The value of this
+  property should be between 0 and 7. If not specified or if out of range, the
+  default value of this property is set to 0.
+
+- max8997,pmic-buck125-dvs-gpios: GPIO specifiers for three host gpio's used
+  for dvs. The format of the gpio specifier depends in the gpio controller.
+
+Regulators: The regulators of max8997 that have to be instantiated should be
+included in a sub-node named 'regulators'. Regulator nodes included in this
+sub-node should be of the format as listed below.
+
+   regulator_name {
+   standard regulator bindings here
+   };
+
+The following are the names of the regulators

[PATCH] regulator: max8997: skip gpio dvs setup if not used

[Thomas Abraham]

If gpio based voltage selection for buck 1/2/5 are not used, then the execution
of gpio dvs setup code during probe can be skipped completly.

Cc: MyungJoo Ham 
Cc: Mark Brown 
Signed-off-by: Thomas Abraham 
---
 drivers/regulator/max8997.c |   31 ++-
 1 files changed, 18 insertions(+), 13 deletions(-)

diff --git a/drivers/regulator/max8997.c b/drivers/regulator/max8997.c
index cea9ec9..e81a381 100644
--- a/drivers/regulator/max8997.c
+++ b/drivers/regulator/max8997.c
@@ -973,6 +973,10 @@ static int max8997_pmic_probe(struct platform_device *pdev)
memcpy(max8997->buck125_gpios, pdata->buck125_gpios, sizeof(int) * 3);
max8997->ignore_gpiodvs_side_effect = pdata->ignore_gpiodvs_side_effect;
 
+   if (!pdata->buck1_gpiodvs && !pdata->buck2_gpiodvs &&
+   !pdata->buck5_gpiodvs)
+   goto skip_gpiodvs;
+
for (i = 0; i < 8; i++) {
max8997->buck1_vol[i] = ret =
max8997_get_voltage_proper_val(
@@ -1019,6 +1023,19 @@ static int max8997_pmic_probe(struct platform_device 
*pdev)
max_buck5, 0x3f);
}
 
+   /* Initialize all the DVS related BUCK registers */
+   for (i = 0; i < 8; i++) {
+   max8997_update_reg(i2c, MAX8997_REG_BUCK1DVS1 + i,
+   max8997->buck1_vol[i],
+   0x3f);
+   max8997_update_reg(i2c, MAX8997_REG_BUCK2DVS1 + i,
+   max8997->buck2_vol[i],
+   0x3f);
+   max8997_update_reg(i2c, MAX8997_REG_BUCK5DVS1 + i,
+   max8997->buck5_vol[i],
+   0x3f);
+   }
+
/*
 * If buck 1, 2, and 5 do not care DVS GPIO settings, ignore them.
 * If at least one of them cares, set gpios.
@@ -1060,6 +1077,7 @@ static int max8997_pmic_probe(struct platform_device 
*pdev)
& 0x1); /* SET3 */
}
 
+skip_gpiodvs:
/* DVS-GPIO disabled */
max8997_update_reg(i2c, MAX8997_REG_BUCK1CTRL, (pdata->buck1_gpiodvs) ?
(1 << 1) : (0 << 1), 1 << 1);
@@ -1068,19 +1086,6 @@ static int max8997_pmic_probe(struct platform_device 
*pdev)
max8997_update_reg(i2c, MAX8997_REG_BUCK5CTRL, (pdata->buck5_gpiodvs) ?
(1 << 1) : (0 << 1), 1 << 1);
 
-   /* Initialize all the DVS related BUCK registers */
-   for (i = 0; i < 8; i++) {
-   max8997_update_reg(i2c, MAX8997_REG_BUCK1DVS1 + i,
-   max8997->buck1_vol[i],
-   0x3f);
-   max8997_update_reg(i2c, MAX8997_REG_BUCK2DVS1 + i,
-   max8997->buck2_vol[i],
-   0x3f);
-   max8997_update_reg(i2c, MAX8997_REG_BUCK5DVS1 + i,
-   max8997->buck5_vol[i],
-   0x3f);
-   }
-
/* Misc Settings */
max8997->ramp_delay = 10; /* set 10mV/us, which is the default */
max8997_write_reg(i2c, MAX8997_REG_BUCKRAMP, (0xf << 4) | 0x9);
-- 
1.6.6.rc2

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[PATCH] regulator: max8997: skip gpio dvs setup if not used

[Thomas Abraham]

If gpio based voltage selection for buck 1/2/5 are not used, then the execution
of gpio dvs setup code during probe can be skipped completly.

Cc: MyungJoo Ham myungjoo@samsung.com
Cc: Mark Brown broo...@opensource.wolfsonmicro.com
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
---
 drivers/regulator/max8997.c |   31 ++-
 1 files changed, 18 insertions(+), 13 deletions(-)

diff --git a/drivers/regulator/max8997.c b/drivers/regulator/max8997.c
index cea9ec9..e81a381 100644
--- a/drivers/regulator/max8997.c
+++ b/drivers/regulator/max8997.c
@@ -973,6 +973,10 @@ static int max8997_pmic_probe(struct platform_device *pdev)
memcpy(max8997-buck125_gpios, pdata-buck125_gpios, sizeof(int) * 3);
max8997-ignore_gpiodvs_side_effect = pdata-ignore_gpiodvs_side_effect;
 
+   if (!pdata-buck1_gpiodvs  !pdata-buck2_gpiodvs 
+   !pdata-buck5_gpiodvs)
+   goto skip_gpiodvs;
+
for (i = 0; i  8; i++) {
max8997-buck1_vol[i] = ret =
max8997_get_voltage_proper_val(
@@ -1019,6 +1023,19 @@ static int max8997_pmic_probe(struct platform_device 
*pdev)
max_buck5, 0x3f);
}
 
+   /* Initialize all the DVS related BUCK registers */
+   for (i = 0; i  8; i++) {
+   max8997_update_reg(i2c, MAX8997_REG_BUCK1DVS1 + i,
+   max8997-buck1_vol[i],
+   0x3f);
+   max8997_update_reg(i2c, MAX8997_REG_BUCK2DVS1 + i,
+   max8997-buck2_vol[i],
+   0x3f);
+   max8997_update_reg(i2c, MAX8997_REG_BUCK5DVS1 + i,
+   max8997-buck5_vol[i],
+   0x3f);
+   }
+
/*
 * If buck 1, 2, and 5 do not care DVS GPIO settings, ignore them.
 * If at least one of them cares, set gpios.
@@ -1060,6 +1077,7 @@ static int max8997_pmic_probe(struct platform_device 
*pdev)
 0x1); /* SET3 */
}
 
+skip_gpiodvs:
/* DVS-GPIO disabled */
max8997_update_reg(i2c, MAX8997_REG_BUCK1CTRL, (pdata-buck1_gpiodvs) ?
(1  1) : (0  1), 1  1);
@@ -1068,19 +1086,6 @@ static int max8997_pmic_probe(struct platform_device 
*pdev)
max8997_update_reg(i2c, MAX8997_REG_BUCK5CTRL, (pdata-buck5_gpiodvs) ?
(1  1) : (0  1), 1  1);
 
-   /* Initialize all the DVS related BUCK registers */
-   for (i = 0; i  8; i++) {
-   max8997_update_reg(i2c, MAX8997_REG_BUCK1DVS1 + i,
-   max8997-buck1_vol[i],
-   0x3f);
-   max8997_update_reg(i2c, MAX8997_REG_BUCK2DVS1 + i,
-   max8997-buck2_vol[i],
-   0x3f);
-   max8997_update_reg(i2c, MAX8997_REG_BUCK5DVS1 + i,
-   max8997-buck5_vol[i],
-   0x3f);
-   }
-
/* Misc Settings */
max8997-ramp_delay = 10; /* set 10mV/us, which is the default */
max8997_write_reg(i2c, MAX8997_REG_BUCKRAMP, (0xf  4) | 0x9);
-- 
1.6.6.rc2

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Re: [PATCH v2] pinctrl: samsung: Add ifdef CONFIG_OF_GPIO guard for gc->of_node

[Thomas Abraham]

On 5 November 2012 21:14, Axel Lin  wrote:
> This fixes below build error when !CONFIG_OF_GPIO.
>
>   CC  drivers/pinctrl/pinctrl-samsung.o
> drivers/pinctrl/pinctrl-samsung.c: In function 
> 'samsung_pinctrl_parse_dt_pins':
> drivers/pinctrl/pinctrl-samsung.c:557:19: warning: unused variable 'prop' 
> [-Wunused-variable]
> drivers/pinctrl/pinctrl-samsung.c: In function 'samsung_gpiolib_register':
> drivers/pinctrl/pinctrl-samsung.c:797:5: error: 'struct gpio_chip' has no 
> member named 'of_node'
> make[2]: *** [drivers/pinctrl/pinctrl-samsung.o] Error 1
> make[1]: *** [drivers/pinctrl] Error 2
> make: *** [drivers] Error 2
>
> Signed-off-by: Axel Lin 
> ---
> v2:
> Don't remove the prop variable.
> It is used in of_property_for_each_string() when CONFIG_OF_GPIO is enabled.
>
>  drivers/pinctrl/pinctrl-samsung.c |2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/drivers/pinctrl/pinctrl-samsung.c 
> b/drivers/pinctrl/pinctrl-samsung.c
> index fc34cac..f798b4d 100644
> --- a/drivers/pinctrl/pinctrl-samsung.c
> +++ b/drivers/pinctrl/pinctrl-samsung.c
> @@ -794,7 +794,9 @@ static int __devinit samsung_gpiolib_register(struct 
> platform_device *pdev,
> gc->base = ctrl->base + bank->pin_base;
> gc->ngpio = bank->nr_pins;
> gc->dev = >dev;
> +#if defined(CONFIG_OF_GPIO)
> gc->of_node = bank->of_node;
> +#endif
> gc->label = bank->name;
>
> ret = gpiochip_add(gc);

The samsung pinctrl driver supports only device tree enabled
platforms. So instead of adding the above #if, would it not be better
to add 'select OF_GPIO' for Samsung pinctrl driver in
drivers/pinctrl/Kconfig. ?

Thanks,
Thomas.

> --
> 1.7.9.5
>
>
>
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Re: [PATCH v2] pinctrl: samsung: Add ifdef CONFIG_OF_GPIO guard for gc-of_node

[Thomas Abraham]

On 5 November 2012 21:14, Axel Lin axel@ingics.com wrote:
 This fixes below build error when !CONFIG_OF_GPIO.

   CC  drivers/pinctrl/pinctrl-samsung.o
 drivers/pinctrl/pinctrl-samsung.c: In function 
 'samsung_pinctrl_parse_dt_pins':
 drivers/pinctrl/pinctrl-samsung.c:557:19: warning: unused variable 'prop' 
 [-Wunused-variable]
 drivers/pinctrl/pinctrl-samsung.c: In function 'samsung_gpiolib_register':
 drivers/pinctrl/pinctrl-samsung.c:797:5: error: 'struct gpio_chip' has no 
 member named 'of_node'
 make[2]: *** [drivers/pinctrl/pinctrl-samsung.o] Error 1
 make[1]: *** [drivers/pinctrl] Error 2
 make: *** [drivers] Error 2

 Signed-off-by: Axel Lin axel@ingics.com
 ---
 v2:
 Don't remove the prop variable.
 It is used in of_property_for_each_string() when CONFIG_OF_GPIO is enabled.

  drivers/pinctrl/pinctrl-samsung.c |2 ++
  1 file changed, 2 insertions(+)

 diff --git a/drivers/pinctrl/pinctrl-samsung.c 
 b/drivers/pinctrl/pinctrl-samsung.c
 index fc34cac..f798b4d 100644
 --- a/drivers/pinctrl/pinctrl-samsung.c
 +++ b/drivers/pinctrl/pinctrl-samsung.c
 @@ -794,7 +794,9 @@ static int __devinit samsung_gpiolib_register(struct 
 platform_device *pdev,
 gc-base = ctrl-base + bank-pin_base;
 gc-ngpio = bank-nr_pins;
 gc-dev = pdev-dev;
 +#if defined(CONFIG_OF_GPIO)
 gc-of_node = bank-of_node;
 +#endif
 gc-label = bank-name;

 ret = gpiochip_add(gc);

The samsung pinctrl driver supports only device tree enabled
platforms. So instead of adding the above #if, would it not be better
to add 'select OF_GPIO' for Samsung pinctrl driver in
drivers/pinctrl/Kconfig. ?

Thanks,
Thomas.

 --
 1.7.9.5



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[PATCH] ARM: Exynos: move interrupt combiner controller driver to drivers/irqchip

[Thomas Abraham]

The irqchip support for interrupt combiner controller is moved into
drivers/irqchip directory from arch/arm/mach-exynos/common.c file.

While at it, the use of soc_is_exynos4/5() macro in the combiner controller
driver (used to determine the number of combiners) is removed. Instead, a new
parameter is added to combiner_init function that allows non-dt platform code
to specify the number of combiners available.

Signed-off-by: Thomas Abraham 
---
 arch/arm/mach-exynos/common.c   |  210 +--
 drivers/irqchip/Makefile|1 +
 drivers/irqchip/irq-exynos-combiner.c   |  212 +++
 include/linux/irqchip/exynos-combiner.h |   18 +++
 4 files changed, 234 insertions(+), 207 deletions(-)
 create mode 100644 drivers/irqchip/irq-exynos-combiner.c
 create mode 100644 include/linux/irqchip/exynos-combiner.h

diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 5c75815..56844d1 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -17,11 +17,9 @@
 #include 
 #include 
 #include 
-#include 
 #include 
 #include 
-#include 
-#include 
+#include 
 
 #include 
 #include 
@@ -384,210 +382,7 @@ static void __init exynos5_init_clocks(int xtal)
exynos5_setup_clocks();
 }
 
-#define COMBINER_ENABLE_SET0x0
-#define COMBINER_ENABLE_CLEAR  0x4
-#define COMBINER_INT_STATUS0xC
-
-static DEFINE_SPINLOCK(irq_controller_lock);
-
-struct combiner_chip_data {
-   unsigned int irq_offset;
-   unsigned int irq_mask;
-   void __iomem *base;
-};
-
-static struct irq_domain *combiner_irq_domain;
-static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
-
-static inline void __iomem *combiner_base(struct irq_data *data)
-{
-   struct combiner_chip_data *combiner_data =
-   irq_data_get_irq_chip_data(data);
-
-   return combiner_data->base;
-}
-
-static void combiner_mask_irq(struct irq_data *data)
-{
-   u32 mask = 1 << (data->hwirq % 32);
-
-   __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
-}
-
-static void combiner_unmask_irq(struct irq_data *data)
-{
-   u32 mask = 1 << (data->hwirq % 32);
-
-   __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
-}
-
-static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc 
*desc)
-{
-   struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
-   struct irq_chip *chip = irq_get_chip(irq);
-   unsigned int cascade_irq, combiner_irq;
-   unsigned long status;
-
-   chained_irq_enter(chip, desc);
-
-   spin_lock(_controller_lock);
-   status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
-   spin_unlock(_controller_lock);
-   status &= chip_data->irq_mask;
-
-   if (status == 0)
-   goto out;
-
-   combiner_irq = __ffs(status);
-
-   cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
-   if (unlikely(cascade_irq >= NR_IRQS))
-   do_bad_IRQ(cascade_irq, desc);
-   else
-   generic_handle_irq(cascade_irq);
-
- out:
-   chained_irq_exit(chip, desc);
-}
-
-static struct irq_chip combiner_chip = {
-   .name   = "COMBINER",
-   .irq_mask   = combiner_mask_irq,
-   .irq_unmask = combiner_unmask_irq,
-};
-
-static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int 
irq)
-{
-   unsigned int max_nr;
-
-   if (soc_is_exynos5250())
-   max_nr = EXYNOS5_MAX_COMBINER_NR;
-   else
-   max_nr = EXYNOS4_MAX_COMBINER_NR;
-
-   if (combiner_nr >= max_nr)
-   BUG();
-   if (irq_set_handler_data(irq, _data[combiner_nr]) != 0)
-   BUG();
-   irq_set_chained_handler(irq, combiner_handle_cascade_irq);
-}
-
-static void __init combiner_init_one(unsigned int combiner_nr,
-void __iomem *base)
-{
-   combiner_data[combiner_nr].base = base;
-   combiner_data[combiner_nr].irq_offset = irq_find_mapping(
-   combiner_irq_domain, combiner_nr * MAX_IRQ_IN_COMBINER);
-   combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
-
-   /* Disable all interrupts */
-   __raw_writel(combiner_data[combiner_nr].irq_mask,
-base + COMBINER_ENABLE_CLEAR);
-}
-
 #ifdef CONFIG_OF
-static int combiner_irq_domain_xlate(struct irq_domain *d,
-struct device_node *controller,
-const u32 *intspec, unsigned int intsize,
-unsigned long *out_hwirq,
-unsigned int *out_type)
-{
-   if (d->of_node != controller)
-   return -EINVAL;
-
-   if (intsize < 2)
-   return -EINVAL;
-
-   *out_hwirq = intspec[0] * MAX_IRQ_IN_COMBINER + ints

[PATCH] ARM: Exynos: move interrupt combiner controller driver to drivers/irqchip

[Thomas Abraham]

The irqchip support for interrupt combiner controller is moved into
drivers/irqchip directory from arch/arm/mach-exynos/common.c file.

While at it, the use of soc_is_exynos4/5() macro in the combiner controller
driver (used to determine the number of combiners) is removed. Instead, a new
parameter is added to combiner_init function that allows non-dt platform code
to specify the number of combiners available.

Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
---
 arch/arm/mach-exynos/common.c   |  210 +--
 drivers/irqchip/Makefile|1 +
 drivers/irqchip/irq-exynos-combiner.c   |  212 +++
 include/linux/irqchip/exynos-combiner.h |   18 +++
 4 files changed, 234 insertions(+), 207 deletions(-)
 create mode 100644 drivers/irqchip/irq-exynos-combiner.c
 create mode 100644 include/linux/irqchip/exynos-combiner.h

diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 5c75815..56844d1 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -17,11 +17,9 @@
 #include linux/gpio.h
 #include linux/sched.h
 #include linux/serial_core.h
-#include linux/of.h
 #include linux/of_irq.h
 #include linux/export.h
-#include linux/irqdomain.h
-#include linux/of_address.h
+#include linux/irqchip/exynos-combiner.h
 
 #include asm/proc-fns.h
 #include asm/exception.h
@@ -384,210 +382,7 @@ static void __init exynos5_init_clocks(int xtal)
exynos5_setup_clocks();
 }
 
-#define COMBINER_ENABLE_SET0x0
-#define COMBINER_ENABLE_CLEAR  0x4
-#define COMBINER_INT_STATUS0xC
-
-static DEFINE_SPINLOCK(irq_controller_lock);
-
-struct combiner_chip_data {
-   unsigned int irq_offset;
-   unsigned int irq_mask;
-   void __iomem *base;
-};
-
-static struct irq_domain *combiner_irq_domain;
-static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
-
-static inline void __iomem *combiner_base(struct irq_data *data)
-{
-   struct combiner_chip_data *combiner_data =
-   irq_data_get_irq_chip_data(data);
-
-   return combiner_data-base;
-}
-
-static void combiner_mask_irq(struct irq_data *data)
-{
-   u32 mask = 1  (data-hwirq % 32);
-
-   __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
-}
-
-static void combiner_unmask_irq(struct irq_data *data)
-{
-   u32 mask = 1  (data-hwirq % 32);
-
-   __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
-}
-
-static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc 
*desc)
-{
-   struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
-   struct irq_chip *chip = irq_get_chip(irq);
-   unsigned int cascade_irq, combiner_irq;
-   unsigned long status;
-
-   chained_irq_enter(chip, desc);
-
-   spin_lock(irq_controller_lock);
-   status = __raw_readl(chip_data-base + COMBINER_INT_STATUS);
-   spin_unlock(irq_controller_lock);
-   status = chip_data-irq_mask;
-
-   if (status == 0)
-   goto out;
-
-   combiner_irq = __ffs(status);
-
-   cascade_irq = combiner_irq + (chip_data-irq_offset  ~31);
-   if (unlikely(cascade_irq = NR_IRQS))
-   do_bad_IRQ(cascade_irq, desc);
-   else
-   generic_handle_irq(cascade_irq);
-
- out:
-   chained_irq_exit(chip, desc);
-}
-
-static struct irq_chip combiner_chip = {
-   .name   = COMBINER,
-   .irq_mask   = combiner_mask_irq,
-   .irq_unmask = combiner_unmask_irq,
-};
-
-static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int 
irq)
-{
-   unsigned int max_nr;
-
-   if (soc_is_exynos5250())
-   max_nr = EXYNOS5_MAX_COMBINER_NR;
-   else
-   max_nr = EXYNOS4_MAX_COMBINER_NR;
-
-   if (combiner_nr = max_nr)
-   BUG();
-   if (irq_set_handler_data(irq, combiner_data[combiner_nr]) != 0)
-   BUG();
-   irq_set_chained_handler(irq, combiner_handle_cascade_irq);
-}
-
-static void __init combiner_init_one(unsigned int combiner_nr,
-void __iomem *base)
-{
-   combiner_data[combiner_nr].base = base;
-   combiner_data[combiner_nr].irq_offset = irq_find_mapping(
-   combiner_irq_domain, combiner_nr * MAX_IRQ_IN_COMBINER);
-   combiner_data[combiner_nr].irq_mask = 0xff  ((combiner_nr % 4)  3);
-
-   /* Disable all interrupts */
-   __raw_writel(combiner_data[combiner_nr].irq_mask,
-base + COMBINER_ENABLE_CLEAR);
-}
-
 #ifdef CONFIG_OF
-static int combiner_irq_domain_xlate(struct irq_domain *d,
-struct device_node *controller,
-const u32 *intspec, unsigned int intsize,
-unsigned long *out_hwirq,
-unsigned int *out_type)
-{
-   if (d-of_node != controller)
-   return -EINVAL

Re: [PATCH] dw_mmc: fix multiple drv_data NULL dereferences

[Thomas Abraham]

dw_mci_board *pdata;
> struct device *dev = host->dev;
> struct device_node *np = dev->of_node;
> +   struct dw_mci_drv_data *drv_data = host->drv_data;
> int idx, ret;
>
> pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
> @@ -2062,8 +2066,8 @@ static struct dw_mci_board *dw_mci_parse_dt(struct 
> dw_mci *host)
>
> of_property_read_u32(np, "card-detect-delay", 
> >detect_delay_ms);
>
> -   if (host->drv_data->parse_dt) {
> -   ret = host->drv_data->parse_dt(host);
> +   if (drv_data && drv_data->parse_dt) {
> +   ret = drv_data->parse_dt(host);
> if (ret)
> return ERR_PTR(ret);
> }
> @@ -2080,6 +2084,7 @@ static struct dw_mci_board *dw_mci_parse_dt(struct 
> dw_mci *host)
>
>  int dw_mci_probe(struct dw_mci *host)
>  {
> +   struct dw_mci_drv_data *drv_data = host->drv_data;
> int width, i, ret = 0;
> u32 fifo_size;
> int init_slots = 0;
> @@ -2127,8 +2132,8 @@ int dw_mci_probe(struct dw_mci *host)
> else
> host->bus_hz = clk_get_rate(host->ciu_clk);
>
> -   if (host->drv_data->setup_clock) {
> -   ret = host->drv_data->setup_clock(host);
> +   if (drv_data && drv_data->setup_clock) {
> +   ret = drv_data->setup_clock(host);
> if (ret) {
> dev_err(host->dev,
> "implementation specific clock setup 
> failed\n");
> --
> 1.7.7.6
>
>

Acked-by: Thomas Abraham 
--
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Re: [PATCH] dw_mmc: fix multiple drv_data NULL dereferences

[Thomas Abraham]

 @@ static struct dw_mci_board *dw_mci_parse_dt(struct 
 dw_mci *host)

  int dw_mci_probe(struct dw_mci *host)
  {
 +   struct dw_mci_drv_data *drv_data = host-drv_data;
 int width, i, ret = 0;
 u32 fifo_size;
 int init_slots = 0;
 @@ -2127,8 +2132,8 @@ int dw_mci_probe(struct dw_mci *host)
 else
 host-bus_hz = clk_get_rate(host-ciu_clk);

 -   if (host-drv_data-setup_clock) {
 -   ret = host-drv_data-setup_clock(host);
 +   if (drv_data  drv_data-setup_clock) {
 +   ret = drv_data-setup_clock(host);
 if (ret) {
 dev_err(host-dev,
 implementation specific clock setup 
 failed\n);
 --
 1.7.7.6



Acked-by: Thomas Abraham thomas.abra...@linaro.org
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Re: [PATCH 2/2] ARM: Exynos4: Register clocks via common clock framework

[Thomas Abraham]

Hi Sylwester,

Thanks for reviewing this patch series.

On 6 October 2012 00:21, Sylwester Nawrocki
 wrote:
> Hello,
>
> On 10/01/2012 02:09 PM, chander.kash...@linaro.org wrote:
>> From: Thomas Abraham
>>
>> Register clocks for Exynos4 platfotms using common clock framework.
>> Also included are set of helper functions for clock registration
>> that can be reused on other Samsung platforms as well.
>>
>> Cc: Mike Turquette
>> Cc: Kukjin Kim
>> Signed-off-by: Thomas Abraham
>> ---
>>   arch/arm/mach-exynos/Kconfig  |1 +
>>   arch/arm/mach-exynos/common.h |3 +
>>   arch/arm/mach-exynos/mct.c|   11 +-
>>   arch/arm/plat-samsung/Kconfig |4 +-
>>   drivers/clk/Makefile  |1 +
>>   drivers/clk/clk.c |   12 +-
>>   drivers/clk/samsung/Makefile  |6 +
>>   drivers/clk/samsung/clk-exynos4.c |  585 
>> +
>>   drivers/clk/samsung/clk.c |  231 +++
>>   drivers/clk/samsung/clk.h |  190 
>>   10 files changed, 1037 insertions(+), 7 deletions(-)
>>   create mode 100644 drivers/clk/samsung/Makefile
>>   create mode 100644 drivers/clk/samsung/clk-exynos4.c
>>   create mode 100644 drivers/clk/samsung/clk.c
>>   create mode 100644 drivers/clk/samsung/clk.h
> ...
>> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
>> index 56e4495..456c50b 100644
>> --- a/drivers/clk/clk.c
>> +++ b/drivers/clk/clk.c
>> @@ -1196,6 +1196,7 @@ EXPORT_SYMBOL_GPL(clk_set_parent);
>>   int __clk_init(struct device *dev, struct clk *clk)
>>   {
>>   int i, ret = 0;
>> + u8 index;
>>   struct clk *orphan;
>>   struct hlist_node *tmp, *tmp2;
>>
>> @@ -1259,6 +1260,7 @@ int __clk_init(struct device *dev, struct clk *clk)
>>   __clk_lookup(clk->parent_names[i]);
>>   }
>>
>> +
>>   clk->parent = __clk_init_parent(clk);
>>
>>   /*
>> @@ -1298,11 +1300,13 @@ int __clk_init(struct device *dev, struct clk *clk)
>>* this clock
>>*/
>>   hlist_for_each_entry_safe(orphan, tmp, tmp2,_orphan_list, 
>> child_node)
>> - for (i = 0; i<  orphan->num_parents; i++)
>> - if (!strcmp(clk->name, orphan->parent_names[i])) {
>> + if (orphan->num_parents>  1) {
>> + index = orphan->ops->get_parent(orphan->hw);
>> + if (!strcmp(clk->name, orphan->parent_names[index]))
>>   __clk_reparent(orphan, clk);
>> - break;
>> - }
>> + } else if (!strcmp(clk->name, orphan->parent_names[0])) {
>> + __clk_reparent(orphan, clk);
>> + }
>
> As this touches generic code it should rather be put into a separate patch,
> along with an explanation why such a change is needed.

There is fix for this in mainline now.

>
>>
>>   /*
>>* optional platform-specific magic
>> diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
>> new file mode 100644
>> index 000..69487f7
>> --- /dev/null
>> +++ b/drivers/clk/samsung/Makefile
>> @@ -0,0 +1,6 @@
>> +#
>> +# Samsung Clock specific Makefile
>> +#
>> +
>> +obj-$(CONFIG_PLAT_SAMSUNG)   += clk.o
>> +obj-$(CONFIG_ARCH_EXYNOS4)   += clk-exynos4.o
>> diff --git a/drivers/clk/samsung/clk-exynos4.c 
>> b/drivers/clk/samsung/clk-exynos4.c
>> new file mode 100644
>> index 000..74a6f03
>> --- /dev/null
>> +++ b/drivers/clk/samsung/clk-exynos4.c
>> @@ -0,0 +1,585 @@
>> +/*
>> + * Copyright (c) 2012 Samsung Electronics Co., Ltd.
>> + * Copyright (c) 2012 Linaro Ltd.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + * Common Clock Framework support for all Exynos4 platforms
>> +*/
>> +
>> +#include
>> +#include
>> +#include
>> +#include
>> +
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +
>> +#include "clk.h"
>> +
>> +#define EXYNOS4_OP_MODE  (S5P_VA_CHIPID + 8)
>> +
>> +static const char *pll_parent_names[] __initdata = { "fin_pll" };
>> +static con

Re: [PATCH 2/2] ARM: Exynos4: Register clocks via common clock framework

[Thomas Abraham]

Hi Tomasz,

On 3 October 2012 17:25, Tomasz Figa  wrote:
> Hi Chander, Thomas,
>
> I think this patch could be split into several smaller, while retaining 
> logical integrity of particular patches, e.g.:
>  - the change introduced to __clk_init (with proper description and rationale 
> why the generic code is being touched)
>  - generic exynos4 code
>  - exynos4210-specific code
>  - exynos4x12-specific code
>  - patch enabling common clock framework on exynos4.
>
> Also, see some nitpicks inline.
>
> On Monday 01 of October 2012 17:39:21 chander.kash...@linaro.org wrote:
>> From: Thomas Abraham 
>>
>> Register clocks for Exynos4 platfotms using common clock framework.
>> Also included are set of helper functions for clock registration
>> that can be reused on other Samsung platforms as well.
>>
>> Cc: Mike Turquette 
>> Cc: Kukjin Kim 
>> Signed-off-by: Thomas Abraham 
>> ---
>>  arch/arm/mach-exynos/Kconfig  |1 +
>>  arch/arm/mach-exynos/common.h |3 +
>>  arch/arm/mach-exynos/mct.c|   11 +-
>>  arch/arm/plat-samsung/Kconfig |4 +-
>>  drivers/clk/Makefile  |1 +
>>  drivers/clk/clk.c |   12 +-
>>  drivers/clk/samsung/Makefile  |6 +
>>  drivers/clk/samsung/clk-exynos4.c |  585
>> + drivers/clk/samsung/clk.c
>> |  231 +++
>>  drivers/clk/samsung/clk.h |  190 
>>  10 files changed, 1037 insertions(+), 7 deletions(-)
>>  create mode 100644 drivers/clk/samsung/Makefile
>>  create mode 100644 drivers/clk/samsung/clk-exynos4.c
>>  create mode 100644 drivers/clk/samsung/clk.c
>>  create mode 100644 drivers/clk/samsung/clk.h
>>
>> diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
>> index b5b4c8c..4866ec7 100644
>> --- a/arch/arm/mach-exynos/Kconfig
>> +++ b/arch/arm/mach-exynos/Kconfig
>> @@ -15,6 +15,7 @@ config ARCH_EXYNOS4
>>   bool "SAMSUNG EXYNOS4"
>>   default y
>>   select HAVE_SMP
>> + select COMMON_CLK
>>   select MIGHT_HAVE_CACHE_L2X0
>>   help
>> Samsung EXYNOS4 SoCs based systems
>> diff --git a/arch/arm/mach-exynos/common.h
>> b/arch/arm/mach-exynos/common.h index aed2eeb..2274431 100644
>> --- a/arch/arm/mach-exynos/common.h
>> +++ b/arch/arm/mach-exynos/common.h
>> @@ -21,6 +21,9 @@ void exynos4_restart(char mode, const char *cmd);
>>  void exynos5_restart(char mode, const char *cmd);
>>  void exynos_init_late(void);
>>
>> +void exynos4210_clk_init(void);
>> +void exynos4212_clk_init(void);
>
> exynos4x12_clk_init?
>
>> +
>>  #ifdef CONFIG_PM_GENERIC_DOMAINS
>>  int exynos_pm_late_initcall(void);
>>  #else
>> diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c
>> index b601fb8..a7cace0 100644
>> --- a/arch/arm/mach-exynos/mct.c
>> +++ b/arch/arm/mach-exynos/mct.c
>> @@ -30,6 +30,8 @@
>>  #include 
>>  #include 
>>
>> +#include "common.h"
>> +
>>  #define TICK_BASE_CNT1
>>
>>  enum {
>> @@ -457,7 +459,7 @@ static struct local_timer_ops exynos4_mct_tick_ops
>> __cpuinitdata = { static void __init exynos4_timer_resources(void)
>>  {
>>   struct clk *mct_clk;
>> - mct_clk = clk_get(NULL, "xtal");
>> + mct_clk = clk_get(NULL, "fin_pll");
>>
>>   clk_rate = clk_get_rate(mct_clk);
>>
>> @@ -478,6 +480,13 @@ static void __init exynos4_timer_resources(void)
>>
>>  static void __init exynos4_timer_init(void)
>>  {
>> +#ifdef CONFIG_COMMON_CLK
>> + if (soc_is_exynos4210())
>> + exynos4210_clk_init();
>> + else if (soc_is_exynos4212() || soc_is_exynos4412())
>> + exynos4212_clk_init();
>
> exynos4x12_clk_init?

Ok.

>
>> +#endif
>> +
>>   if ((soc_is_exynos4210()) || (soc_is_exynos5250()))
>>   mct_int_type = MCT_INT_SPI;
>>   else
>> diff --git a/arch/arm/plat-samsung/Kconfig
>> b/arch/arm/plat-samsung/Kconfig index 9c3b90c..35b4cb8 100644
>> --- a/arch/arm/plat-samsung/Kconfig
>> +++ b/arch/arm/plat-samsung/Kconfig
>> @@ -26,7 +26,7 @@ config PLAT_S5P
>>   select S5P_GPIO_DRVSTR
>>   select SAMSUNG_GPIOLIB_4BIT
>>   select PLAT_SAMSUNG
>> - select SAMSUNG_CLKSRC
>> + select SAMSUNG_CLKSRC if !COMMON_CLK
>>   select SAMSUNG_IRQ_VIC_TIMER
>>   help
>> Base platform code for Samsung's S5P serie

Re: [PATCH 2/2] ARM: Exynos4: Register clocks via common clock framework

[Thomas Abraham]

Hi Tomasz,

On 3 October 2012 19:40, Tomasz Figa  wrote:
> Hi Chander, Thomas,
>
> I can see one more problem here.
>
> Based on the fact that sdhci-s3c driver receives only the endpoint gate
> clock (hsmmc), doesn't the following setup make the driver unable to change
> the frequency of this clock?

The driver never changes the clock frequency of the core system clocks
nor of the endpoint. There are internal dividers inside the sdhci
controller which are divide to acheive required clock speed.

Thanks,
Thomas.

>
> On Monday 01 of October 2012 17:39:21 chander.kash...@linaro.org wrote:
>> +static struct samsung_mux_clock exynos4_mux_clks[] = {
> [snip]
>> + MUXCLK("exynos4-sdhci.0", "mout_mmc0", group1_parents, 0,
>> + EXYNOS4_CLKSRC_FSYS, 0, 4, 0),
>> + MUXCLK("exynos4-sdhci.1", "mout_mmc1", group1_parents, 0,
>> + EXYNOS4_CLKSRC_FSYS, 4, 4, 0),
>> + MUXCLK("exynos4-sdhci.1", "mout_mmc2", group1_parents, 0,
>> + EXYNOS4_CLKSRC_FSYS, 8, 4, 0),
>> + MUXCLK("exynos4-sdhci.1", "mout_mmc3", group1_parents, 0,
>> + EXYNOS4_CLKSRC_FSYS, 12, 4, 0),
> [snip]
>> +};
>> +
>> +static struct samsung_div_clock exynos4_div_clks[] = {
> [snip]
>> + DIVCLK("exynos4-sdhci.0", "div_mmc0", "mout_mmc0", 0,
>> + EXYNOS4_CLKDIV_FSYS1, 0, 4, 0),
>> + DIVCLK("exynos4-sdhci.0", "div_mmc0_pre", "div_mmc0", 0,
>> + EXYNOS4_CLKDIV_FSYS1, 8, 8, 0),
>> + DIVCLK("exynos4-sdhci.1", "div_mmc1", "mout_mmc1", 0,
>> + EXYNOS4_CLKDIV_FSYS1, 16, 4, 0),
>> + DIVCLK("exynos4-sdhci.1", "div_mmc1_pre", "div_mmc1", 0,
>> + EXYNOS4_CLKDIV_FSYS1, 24, 8, 0),
>> + DIVCLK("exynos4-sdhci.2", "div_mmc2", "mout_mmc2", 0,
>> + EXYNOS4_CLKDIV_FSYS2, 0, 4, 0),
>> + DIVCLK("exynos4-sdhci.2", "div_mmc2_pre", "div_mmc2", 0,
>> + EXYNOS4_CLKDIV_FSYS2, 8, 8, 0),
>> + DIVCLK("exynos4-sdhci.3", "div_mmc3", "mout_mmc3", 0,
>> + EXYNOS4_CLKDIV_FSYS2, 16, 4, 0),
>> + DIVCLK("exynos4-sdhci.3", "div_mmc3_pre", "div_mmc3", 0,
>> + EXYNOS4_CLKDIV_FSYS2, 24, 8, 0),
> [snip]
>> +};
>> +
>> +struct samsung_gate_clock exynos4_gate_clks[] = {
> [snip]
>> + GATECLK("exynos4-sdhci.0", "hsmmc0", "aclk_133", 0,
>> + EXYNOS4_CLKGATE_IP_FSYS, 5, "hsmmc"),
>> + GATECLK("exynos4-sdhci.1", "hsmmc1", "aclk_133", 0,
>> + EXYNOS4_CLKGATE_IP_FSYS, 6, "hsmmc"),
>> + GATECLK("exynos4-sdhci.2", "hsmmc2", "aclk_133", 0,
>> + EXYNOS4_CLKGATE_IP_FSYS, 7, "hsmmc"),
>> + GATECLK("exynos4-sdhci.3", "hsmmc3", "aclk_133", 0,
>> + EXYNOS4_CLKGATE_IP_FSYS, 8, "hsmmc"),
> [snip]
>> +};
>
> Best regards,
> --
> Tomasz Figa
> Samsung Poland R Center
>
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Re: [PATCH 0/2] ARM: Exynos4: Migrate to common clock framework.

[Thomas Abraham]

Hi Tomasz,

Thanks for reviewing this patch series.

On 3 October 2012 16:26, Tomasz Figa  wrote:
> Hi Chander, Thomas,
>
> On Monday 01 of October 2012 17:39:19 chander.kash...@linaro.org wrote:
>> From: Thomas Abraham 
>>
>> This patch series migrates Exynos4 clock support to common clock
>> framework. The first patch in this series removes the existing Exynos4
>> clock support that uses the Samsung specific clock framework. The second
>> patch in this series add Exynos4 clock support using common clock
>> framework.
>>
>> Thomas Abraham (2):
>>   ARM: Exynos4: Remove Samsung clock type support
>>   ARM: Exynos4: Register clocks via common clock framework
>
> I think the order of changes is a little bit off here:
>  - patch 1 will break all exynos4-based boards (what about bisects?)
>  - patch 2 will be still broken until all related drivers get converted to
> use clk_prepare(_enable) and clk_(disable_)unprepare.

Ok. I got the sequence wrong and I have fixed this in the next version.

>
> Shouldn't the order be exactly opposite, i.e.:
>  - all the patches for prepare/unprepare first
>  - then the patch adding common clock frameworks support for exynos4
> (disabling the old clock code)
>  - and finally the patch removing remaining (disabled by previous patch)
> code.

Right.

>
> Also, I assume that these patches doesn't consider native device tree
> support (without auxdata, using OF-based clock lookup), correct me if I'm
> wrong. If I'm right, since Exynos SoCs are going to be DT-only, is there
> really a point for adding common clock framework support for non-DT
> platforms (which are going to be eventually dropped anyway)?

The non-dt Exynos4 platforms require some effort to get basic device
tree support into them. Until then, the common clock support for them
are required. I have added device tree support as well in the second
version of this patch series.

Thanks,
Thomas.

>
> Best regards,
> --
> Tomasz Figa
> Samsung Poland R Center
>
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Re: [PATCH 0/2] ARM: Exynos4: Migrate to common clock framework.

[Thomas Abraham]

Hi Tomasz,

Thanks for reviewing this patch series.

On 3 October 2012 16:26, Tomasz Figa t.f...@samsung.com wrote:
 Hi Chander, Thomas,

 On Monday 01 of October 2012 17:39:19 chander.kash...@linaro.org wrote:
 From: Thomas Abraham thomas.abra...@linaro.org

 This patch series migrates Exynos4 clock support to common clock
 framework. The first patch in this series removes the existing Exynos4
 clock support that uses the Samsung specific clock framework. The second
 patch in this series add Exynos4 clock support using common clock
 framework.

 Thomas Abraham (2):
   ARM: Exynos4: Remove Samsung clock type support
   ARM: Exynos4: Register clocks via common clock framework

 I think the order of changes is a little bit off here:
  - patch 1 will break all exynos4-based boards (what about bisects?)
  - patch 2 will be still broken until all related drivers get converted to
 use clk_prepare(_enable) and clk_(disable_)unprepare.

Ok. I got the sequence wrong and I have fixed this in the next version.


 Shouldn't the order be exactly opposite, i.e.:
  - all the patches for prepare/unprepare first
  - then the patch adding common clock frameworks support for exynos4
 (disabling the old clock code)
  - and finally the patch removing remaining (disabled by previous patch)
 code.

Right.


 Also, I assume that these patches doesn't consider native device tree
 support (without auxdata, using OF-based clock lookup), correct me if I'm
 wrong. If I'm right, since Exynos SoCs are going to be DT-only, is there
 really a point for adding common clock framework support for non-DT
 platforms (which are going to be eventually dropped anyway)?

The non-dt Exynos4 platforms require some effort to get basic device
tree support into them. Until then, the common clock support for them
are required. I have added device tree support as well in the second
version of this patch series.

Thanks,
Thomas.


 Best regards,
 --
 Tomasz Figa
 Samsung Poland RD Center

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Re: [PATCH 2/2] ARM: Exynos4: Register clocks via common clock framework

[Thomas Abraham]

Hi Tomasz,

On 3 October 2012 17:25, Tomasz Figa t.f...@samsung.com wrote:
 Hi Chander, Thomas,

 I think this patch could be split into several smaller, while retaining 
 logical integrity of particular patches, e.g.:
  - the change introduced to __clk_init (with proper description and rationale 
 why the generic code is being touched)
  - generic exynos4 code
  - exynos4210-specific code
  - exynos4x12-specific code
  - patch enabling common clock framework on exynos4.

 Also, see some nitpicks inline.

 On Monday 01 of October 2012 17:39:21 chander.kash...@linaro.org wrote:
 From: Thomas Abraham thomas.abra...@linaro.org

 Register clocks for Exynos4 platfotms using common clock framework.
 Also included are set of helper functions for clock registration
 that can be reused on other Samsung platforms as well.

 Cc: Mike Turquette mturque...@linaro.org
 Cc: Kukjin Kim kgene@samsung.com
 Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
 ---
  arch/arm/mach-exynos/Kconfig  |1 +
  arch/arm/mach-exynos/common.h |3 +
  arch/arm/mach-exynos/mct.c|   11 +-
  arch/arm/plat-samsung/Kconfig |4 +-
  drivers/clk/Makefile  |1 +
  drivers/clk/clk.c |   12 +-
  drivers/clk/samsung/Makefile  |6 +
  drivers/clk/samsung/clk-exynos4.c |  585
 + drivers/clk/samsung/clk.c
 |  231 +++
  drivers/clk/samsung/clk.h |  190 
  10 files changed, 1037 insertions(+), 7 deletions(-)
  create mode 100644 drivers/clk/samsung/Makefile
  create mode 100644 drivers/clk/samsung/clk-exynos4.c
  create mode 100644 drivers/clk/samsung/clk.c
  create mode 100644 drivers/clk/samsung/clk.h

 diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
 index b5b4c8c..4866ec7 100644
 --- a/arch/arm/mach-exynos/Kconfig
 +++ b/arch/arm/mach-exynos/Kconfig
 @@ -15,6 +15,7 @@ config ARCH_EXYNOS4
   bool SAMSUNG EXYNOS4
   default y
   select HAVE_SMP
 + select COMMON_CLK
   select MIGHT_HAVE_CACHE_L2X0
   help
 Samsung EXYNOS4 SoCs based systems
 diff --git a/arch/arm/mach-exynos/common.h
 b/arch/arm/mach-exynos/common.h index aed2eeb..2274431 100644
 --- a/arch/arm/mach-exynos/common.h
 +++ b/arch/arm/mach-exynos/common.h
 @@ -21,6 +21,9 @@ void exynos4_restart(char mode, const char *cmd);
  void exynos5_restart(char mode, const char *cmd);
  void exynos_init_late(void);

 +void exynos4210_clk_init(void);
 +void exynos4212_clk_init(void);

 exynos4x12_clk_init?

 +
  #ifdef CONFIG_PM_GENERIC_DOMAINS
  int exynos_pm_late_initcall(void);
  #else
 diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c
 index b601fb8..a7cace0 100644
 --- a/arch/arm/mach-exynos/mct.c
 +++ b/arch/arm/mach-exynos/mct.c
 @@ -30,6 +30,8 @@
  #include mach/regs-mct.h
  #include asm/mach/time.h

 +#include common.h
 +
  #define TICK_BASE_CNT1

  enum {
 @@ -457,7 +459,7 @@ static struct local_timer_ops exynos4_mct_tick_ops
 __cpuinitdata = { static void __init exynos4_timer_resources(void)
  {
   struct clk *mct_clk;
 - mct_clk = clk_get(NULL, xtal);
 + mct_clk = clk_get(NULL, fin_pll);

   clk_rate = clk_get_rate(mct_clk);

 @@ -478,6 +480,13 @@ static void __init exynos4_timer_resources(void)

  static void __init exynos4_timer_init(void)
  {
 +#ifdef CONFIG_COMMON_CLK
 + if (soc_is_exynos4210())
 + exynos4210_clk_init();
 + else if (soc_is_exynos4212() || soc_is_exynos4412())
 + exynos4212_clk_init();

 exynos4x12_clk_init?

Ok.


 +#endif
 +
   if ((soc_is_exynos4210()) || (soc_is_exynos5250()))
   mct_int_type = MCT_INT_SPI;
   else
 diff --git a/arch/arm/plat-samsung/Kconfig
 b/arch/arm/plat-samsung/Kconfig index 9c3b90c..35b4cb8 100644
 --- a/arch/arm/plat-samsung/Kconfig
 +++ b/arch/arm/plat-samsung/Kconfig
 @@ -26,7 +26,7 @@ config PLAT_S5P
   select S5P_GPIO_DRVSTR
   select SAMSUNG_GPIOLIB_4BIT
   select PLAT_SAMSUNG
 - select SAMSUNG_CLKSRC
 + select SAMSUNG_CLKSRC if !COMMON_CLK
   select SAMSUNG_IRQ_VIC_TIMER
   help
 Base platform code for Samsung's S5P series SoC.
 @@ -89,7 +89,7 @@ config SAMSUNG_CLKSRC
 used by newer systems such as the S3C64XX.

  config S5P_CLOCK
 - def_bool (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS)
 + def_bool ((ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS)
  !COMMON_CLK) help
 Support common clock part for ARCH_S5P and ARCH_EXYNOS SoCs

 diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
 index 6327536..5f5b060 100644
 --- a/drivers/clk/Makefile
 +++ b/drivers/clk/Makefile
 @@ -16,6 +16,7 @@ obj-$(CONFIG_ARCH_MMP)  += mmp/
  endif
  obj-$(CONFIG_MACH_LOONGSON1) += clk-ls1x.o
  obj-$(CONFIG_ARCH_U8500) += ux500/
 +obj-$(CONFIG_PLAT_SAMSUNG)   += samsung/

  # Chip specific
  obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
 diff --git a/drivers

Re: [PATCH 2/2] ARM: Exynos4: Register clocks via common clock framework

[Thomas Abraham]

Hi Tomasz,

On 3 October 2012 19:40, Tomasz Figa t.f...@samsung.com wrote:
 Hi Chander, Thomas,

 I can see one more problem here.

 Based on the fact that sdhci-s3c driver receives only the endpoint gate
 clock (hsmmc), doesn't the following setup make the driver unable to change
 the frequency of this clock?

The driver never changes the clock frequency of the core system clocks
nor of the endpoint. There are internal dividers inside the sdhci
controller which are divide to acheive required clock speed.

Thanks,
Thomas.


 On Monday 01 of October 2012 17:39:21 chander.kash...@linaro.org wrote:
 +static struct samsung_mux_clock exynos4_mux_clks[] = {
 [snip]
 + MUXCLK(exynos4-sdhci.0, mout_mmc0, group1_parents, 0,
 + EXYNOS4_CLKSRC_FSYS, 0, 4, 0),
 + MUXCLK(exynos4-sdhci.1, mout_mmc1, group1_parents, 0,
 + EXYNOS4_CLKSRC_FSYS, 4, 4, 0),
 + MUXCLK(exynos4-sdhci.1, mout_mmc2, group1_parents, 0,
 + EXYNOS4_CLKSRC_FSYS, 8, 4, 0),
 + MUXCLK(exynos4-sdhci.1, mout_mmc3, group1_parents, 0,
 + EXYNOS4_CLKSRC_FSYS, 12, 4, 0),
 [snip]
 +};
 +
 +static struct samsung_div_clock exynos4_div_clks[] = {
 [snip]
 + DIVCLK(exynos4-sdhci.0, div_mmc0, mout_mmc0, 0,
 + EXYNOS4_CLKDIV_FSYS1, 0, 4, 0),
 + DIVCLK(exynos4-sdhci.0, div_mmc0_pre, div_mmc0, 0,
 + EXYNOS4_CLKDIV_FSYS1, 8, 8, 0),
 + DIVCLK(exynos4-sdhci.1, div_mmc1, mout_mmc1, 0,
 + EXYNOS4_CLKDIV_FSYS1, 16, 4, 0),
 + DIVCLK(exynos4-sdhci.1, div_mmc1_pre, div_mmc1, 0,
 + EXYNOS4_CLKDIV_FSYS1, 24, 8, 0),
 + DIVCLK(exynos4-sdhci.2, div_mmc2, mout_mmc2, 0,
 + EXYNOS4_CLKDIV_FSYS2, 0, 4, 0),
 + DIVCLK(exynos4-sdhci.2, div_mmc2_pre, div_mmc2, 0,
 + EXYNOS4_CLKDIV_FSYS2, 8, 8, 0),
 + DIVCLK(exynos4-sdhci.3, div_mmc3, mout_mmc3, 0,
 + EXYNOS4_CLKDIV_FSYS2, 16, 4, 0),
 + DIVCLK(exynos4-sdhci.3, div_mmc3_pre, div_mmc3, 0,
 + EXYNOS4_CLKDIV_FSYS2, 24, 8, 0),
 [snip]
 +};
 +
 +struct samsung_gate_clock exynos4_gate_clks[] = {
 [snip]
 + GATECLK(exynos4-sdhci.0, hsmmc0, aclk_133, 0,
 + EXYNOS4_CLKGATE_IP_FSYS, 5, hsmmc),
 + GATECLK(exynos4-sdhci.1, hsmmc1, aclk_133, 0,
 + EXYNOS4_CLKGATE_IP_FSYS, 6, hsmmc),
 + GATECLK(exynos4-sdhci.2, hsmmc2, aclk_133, 0,
 + EXYNOS4_CLKGATE_IP_FSYS, 7, hsmmc),
 + GATECLK(exynos4-sdhci.3, hsmmc3, aclk_133, 0,
 + EXYNOS4_CLKGATE_IP_FSYS, 8, hsmmc),
 [snip]
 +};

 Best regards,
 --
 Tomasz Figa
 Samsung Poland RD Center

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Re: [PATCH 2/2] ARM: Exynos4: Register clocks via common clock framework

[Thomas Abraham]

Hi Sylwester,

Thanks for reviewing this patch series.

On 6 October 2012 00:21, Sylwester Nawrocki
sylvester.nawro...@gmail.com wrote:
 Hello,

 On 10/01/2012 02:09 PM, chander.kash...@linaro.org wrote:
 From: Thomas Abrahamthomas.abra...@linaro.org

 Register clocks for Exynos4 platfotms using common clock framework.
 Also included are set of helper functions for clock registration
 that can be reused on other Samsung platforms as well.

 Cc: Mike Turquettemturque...@linaro.org
 Cc: Kukjin Kimkgene@samsung.com
 Signed-off-by: Thomas Abrahamthomas.abra...@linaro.org
 ---
   arch/arm/mach-exynos/Kconfig  |1 +
   arch/arm/mach-exynos/common.h |3 +
   arch/arm/mach-exynos/mct.c|   11 +-
   arch/arm/plat-samsung/Kconfig |4 +-
   drivers/clk/Makefile  |1 +
   drivers/clk/clk.c |   12 +-
   drivers/clk/samsung/Makefile  |6 +
   drivers/clk/samsung/clk-exynos4.c |  585 
 +
   drivers/clk/samsung/clk.c |  231 +++
   drivers/clk/samsung/clk.h |  190 
   10 files changed, 1037 insertions(+), 7 deletions(-)
   create mode 100644 drivers/clk/samsung/Makefile
   create mode 100644 drivers/clk/samsung/clk-exynos4.c
   create mode 100644 drivers/clk/samsung/clk.c
   create mode 100644 drivers/clk/samsung/clk.h
 ...
 diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
 index 56e4495..456c50b 100644
 --- a/drivers/clk/clk.c
 +++ b/drivers/clk/clk.c
 @@ -1196,6 +1196,7 @@ EXPORT_SYMBOL_GPL(clk_set_parent);
   int __clk_init(struct device *dev, struct clk *clk)
   {
   int i, ret = 0;
 + u8 index;
   struct clk *orphan;
   struct hlist_node *tmp, *tmp2;

 @@ -1259,6 +1260,7 @@ int __clk_init(struct device *dev, struct clk *clk)
   __clk_lookup(clk-parent_names[i]);
   }

 +
   clk-parent = __clk_init_parent(clk);

   /*
 @@ -1298,11 +1300,13 @@ int __clk_init(struct device *dev, struct clk *clk)
* this clock
*/
   hlist_for_each_entry_safe(orphan, tmp, tmp2,clk_orphan_list, 
 child_node)
 - for (i = 0; i  orphan-num_parents; i++)
 - if (!strcmp(clk-name, orphan-parent_names[i])) {
 + if (orphan-num_parents  1) {
 + index = orphan-ops-get_parent(orphan-hw);
 + if (!strcmp(clk-name, orphan-parent_names[index]))
   __clk_reparent(orphan, clk);
 - break;
 - }
 + } else if (!strcmp(clk-name, orphan-parent_names[0])) {
 + __clk_reparent(orphan, clk);
 + }

 As this touches generic code it should rather be put into a separate patch,
 along with an explanation why such a change is needed.

There is fix for this in mainline now.



   /*
* optional platform-specific magic
 diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
 new file mode 100644
 index 000..69487f7
 --- /dev/null
 +++ b/drivers/clk/samsung/Makefile
 @@ -0,0 +1,6 @@
 +#
 +# Samsung Clock specific Makefile
 +#
 +
 +obj-$(CONFIG_PLAT_SAMSUNG)   += clk.o
 +obj-$(CONFIG_ARCH_EXYNOS4)   += clk-exynos4.o
 diff --git a/drivers/clk/samsung/clk-exynos4.c 
 b/drivers/clk/samsung/clk-exynos4.c
 new file mode 100644
 index 000..74a6f03
 --- /dev/null
 +++ b/drivers/clk/samsung/clk-exynos4.c
 @@ -0,0 +1,585 @@
 +/*
 + * Copyright (c) 2012 Samsung Electronics Co., Ltd.
 + * Copyright (c) 2012 Linaro Ltd.
 + *
 + * This program is free software; you can redistribute it and/or modify
 + * it under the terms of the GNU General Public License version 2 as
 + * published by the Free Software Foundation.
 + *
 + * Common Clock Framework support for all Exynos4 platforms
 +*/
 +
 +#includelinux/clk.h
 +#includelinux/clkdev.h
 +#includelinux/io.h
 +#includelinux/clk-provider.h
 +
 +#includeplat/pll.h
 +#includeplat/cpu.h
 +#includemach/regs-clock.h
 +#includemach/sysmmu.h
 +#includeplat/map-s5p.h
 +
 +#include clk.h
 +
 +#define EXYNOS4_OP_MODE  (S5P_VA_CHIPID + 8)
 +
 +static const char *pll_parent_names[] __initdata = { fin_pll };
 +static const char *fin_pll_parents[] __initdata = { xxti, xusbxti };
 +static const char *mout_apll_parents[] __initdata = { fin_pll, 
 fout_apll, };
 +static const char *mout_mpll_parents[] __initdata = { fin_pll, 
 fout_mpll, };
 +static const char *mout_epll_parents[] __initdata = { fin_pll, 
 fout_epll, };
 +
 +static const char *sclk_ampll_parents[] __initdata = {
 + mout_mpll, sclk_apll, };
 +
 +static const char *sclk_evpll_parents[] __initdata = {
 + mout_epll, mout_vpll, };
 +
 +static const char *mout_core_parents[] __initdata = {
 + mout_apll, mout_mpll, };
 +
 +static const char *mout_mfc_parents[] __initdata = {
 + mout_mfc0, mout_mfc1, };
 +
 +static const char *mout_dac_parents[] __initdata = {
 +