RE: [PATCH v2 7/9] riscv: dts: add initial support for the SiFive FU740-C000 SoC
> -Original Message-
> From: Bin Meng
> Sent: 16 December 2020 11:36
> To: Yash Shah
> Cc: linux-...@vger.kernel.org; linux-ser...@vger.kernel.org; linux-
> p...@vger.kernel.org; linux-...@vger.kernel.org; linux-kernel ker...@vger.kernel.org>; linux-riscv ;
> devicetree ; open list:GPIO SUBSYSTEM g...@vger.kernel.org>; broo...@kernel.org; Greg Kroah-Hartman
> ; Albert Ou ;
> lee.jo...@linaro.org; u.kleine-koe...@pengutronix.de; Thierry Reding
> ; and...@lunn.ch; Peter Korsgaard
> ; Paul Walmsley ( Sifive)
> ; Palmer Dabbelt ; Rob
> Herring ; Bartosz Golaszewski
> ; Linus Walleij
> Subject: Re: [PATCH v2 7/9] riscv: dts: add initial support for the SiFive
> FU740-
> C000 SoC
>
> [External Email] Do not click links or attachments unless you recognize the
> sender and know the content is safe
>
> Hi Yash,
>
> On Wed, Dec 16, 2020 at 1:24 PM Yash Shah
> wrote:
> >
> > > -----Original Message-
> > > From: Bin Meng
> > > Sent: 10 December 2020 19:05
> > > To: Yash Shah
> > > Cc: linux-...@vger.kernel.org; linux-ser...@vger.kernel.org; linux-
> > > p...@vger.kernel.org; linux-...@vger.kernel.org; linux-kernel > > ker...@vger.kernel.org>; linux-riscv
> > > ;
> > > devicetree ; open list:GPIO SUBSYSTEM
> > > ; broo...@kernel.org; Greg
> > > Kroah-Hartman ; Albert Ou
> > > ; lee.jo...@linaro.org;
> > > u.kleine-koe...@pengutronix.de; Thierry Reding
> > > ; and...@lunn.ch; Peter Korsgaard
> > > ; Paul Walmsley ( Sifive)
> > > ; Palmer Dabbelt ;
> Rob
> > > Herring ; Bartosz Golaszewski
> > > ; Linus Walleij
> > >
> > > Subject: Re: [PATCH v2 7/9] riscv: dts: add initial support for the
> > > SiFive FU740-
> > > C000 SoC
> > >
> > > [External Email] Do not click links or attachments unless you
> > > recognize the sender and know the content is safe
> > >
> > > On Tue, Dec 8, 2020 at 3:06 PM Yash Shah
> wrote:
> > > >
> > > > Add initial support for the SiFive FU540-C000 SoC. FU740-C000 is
> > > > built
> > >
> > > FU740-C000 Soc
> > >
> > > > around the SiFIve U7 Core Complex and a TileLink interconnect.
> > > >
> > > > This file is expected to grow as more device drivers are added to
> > > > the kernel.
> > > >
> > > > Signed-off-by: Yash Shah
> > > > ---
> > > > arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 293
> > > > +
> > > > 1 file changed, 293 insertions(+) create mode 100644
> > > > arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > > >
> > > > diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > > > b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > > > new file mode 100644
> > > > index 000..eeb4f8c3
> > > > --- /dev/null
> > > > +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > > > @@ -0,0 +1,293 @@
> >
> > ...
> >
> > > > + plic0: interrupt-controller@c00 {
> > > > + #interrupt-cells = <1>;
> > > > + #address-cells = <0>;
> > > > + compatible = "sifive,fu540-c000-plic",
> > > > + "sifive,plic-1.0.0";
> > >
> > > I don't see bindings updated for FU740 PLIC, like
> > > "sifive,fu740-c000-plic"?
> >
> > That's because it is not required. There won't be any difference in driver
> code for FU740 plic.
>
> Are there any driver changes for the drivers that have an updated
> fu640-c000-* bindings? I don't see them in the linux-riscv list.
Yes, they will be posted soon.
- Yash
>
> >
> > ...
> >
> > > > + eth0: ethernet@1009 {
> > > > + compatible = "sifive,fu540-c000-gem";
> > >
> > > "sifive,fu740-c000-gem"?
> > >
> >
> > Same reason as above.
> >
> > Thanks for your review.
>
> Regards,
> Bin
RE: [PATCH v2 7/9] riscv: dts: add initial support for the SiFive FU740-C000 SoC
> -Original Message-
> From: Bin Meng
> Sent: 10 December 2020 19:05
> To: Yash Shah
> Cc: linux-...@vger.kernel.org; linux-ser...@vger.kernel.org; linux-
> p...@vger.kernel.org; linux-...@vger.kernel.org; linux-kernel ker...@vger.kernel.org>; linux-riscv ;
> devicetree ; open list:GPIO SUBSYSTEM g...@vger.kernel.org>; broo...@kernel.org; Greg Kroah-Hartman
> ; Albert Ou ;
> lee.jo...@linaro.org; u.kleine-koe...@pengutronix.de; Thierry Reding
> ; and...@lunn.ch; Peter Korsgaard
> ; Paul Walmsley ( Sifive)
> ; Palmer Dabbelt ; Rob
> Herring ; Bartosz Golaszewski
> ; Linus Walleij
> Subject: Re: [PATCH v2 7/9] riscv: dts: add initial support for the SiFive
> FU740-
> C000 SoC
>
> [External Email] Do not click links or attachments unless you recognize the
> sender and know the content is safe
>
> On Tue, Dec 8, 2020 at 3:06 PM Yash Shah wrote:
> >
> > Add initial support for the SiFive FU540-C000 SoC. FU740-C000 is built
>
> FU740-C000 Soc
>
> > around the SiFIve U7 Core Complex and a TileLink interconnect.
> >
> > This file is expected to grow as more device drivers are added to the
> > kernel.
> >
> > Signed-off-by: Yash Shah
> > ---
> > arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 293
> > +
> > 1 file changed, 293 insertions(+)
> > create mode 100644 arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> >
> > diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > new file mode 100644
> > index 000..eeb4f8c3
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > @@ -0,0 +1,293 @@
...
> > + plic0: interrupt-controller@c00 {
> > + #interrupt-cells = <1>;
> > + #address-cells = <0>;
> > + compatible = "sifive,fu540-c000-plic",
> > + "sifive,plic-1.0.0";
>
> I don't see bindings updated for FU740 PLIC, like "sifive,fu740-c000-plic"?
That's because it is not required. There won't be any difference in driver code
for FU740 plic.
...
> > + eth0: ethernet@1009 {
> > + compatible = "sifive,fu540-c000-gem";
>
> "sifive,fu740-c000-gem"?
>
Same reason as above.
Thanks for your review.
- Yash
> > + interrupt-parent = <>;
> > + interrupts = <55>;
> > + reg = <0x0 0x1009 0x0 0x2000>,
> > + <0x0 0x100a 0x0 0x1000>;
> > + local-mac-address = [00 00 00 00 00 00];
> > + clock-names = "pclk", "hclk";
> > + clocks = < PRCI_CLK_GEMGXLPLL>,
> > +< PRCI_CLK_GEMGXLPLL>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + status = "disabled";
> > + };
> > + pwm0: pwm@1002 {
> > + compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
> > + reg = <0x0 0x1002 0x0 0x1000>;
> > + interrupt-parent = <>;
> > + interrupts = <44>, <45>, <46>, <47>;
> > + clocks = < PRCI_CLK_PCLK>;
> > + #pwm-cells = <3>;
> > + status = "disabled";
> > + };
> > + pwm1: pwm@10021000 {
> > + compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
> > + reg = <0x0 0x10021000 0x0 0x1000>;
> > + interrupt-parent = <>;
> > + interrupts = <48>, <49>, <50>, <51>;
> > + clocks = < PRCI_CLK_PCLK>;
> > + #pwm-cells = <3>;
> > + status = "disabled";
> > + };
> > + ccache: cache-controller@201 {
> > + compatible = "sifive,fu740-c000-ccache", "cache";
> > + cache-block-size = <64>;
> > + cache-level = <2>;
> > + cache-sets = <2048>;
> > + cache-s
[PATCH v3 2/2] RISC-V: sifive_l2_cache: Update L2 cache driver to support SiFive FU740
SiFive FU740 has 4 ECC interrupt sources as compared to 3 in FU540.
Update the L2 cache controller driver to support this additional
interrupt in case of FU740-C000 chip.
Signed-off-by: Yash Shah
---
drivers/soc/sifive/sifive_l2_cache.c | 27 ---
1 file changed, 24 insertions(+), 3 deletions(-)
diff --git a/drivers/soc/sifive/sifive_l2_cache.c
b/drivers/soc/sifive/sifive_l2_cache.c
index 44d7e19..59640a1 100644
--- a/drivers/soc/sifive/sifive_l2_cache.c
+++ b/drivers/soc/sifive/sifive_l2_cache.c
@@ -17,6 +17,10 @@
#define SIFIVE_L2_DIRECCFIX_HIGH 0x104
#define SIFIVE_L2_DIRECCFIX_COUNT 0x108
+#define SIFIVE_L2_DIRECCFAIL_LOW 0x120
+#define SIFIVE_L2_DIRECCFAIL_HIGH 0x124
+#define SIFIVE_L2_DIRECCFAIL_COUNT 0x128
+
#define SIFIVE_L2_DATECCFIX_LOW 0x140
#define SIFIVE_L2_DATECCFIX_HIGH 0x144
#define SIFIVE_L2_DATECCFIX_COUNT 0x148
@@ -29,7 +33,7 @@
#define SIFIVE_L2_WAYENABLE 0x08
#define SIFIVE_L2_ECCINJECTERR 0x40
-#define SIFIVE_L2_MAX_ECCINTR 3
+#define SIFIVE_L2_MAX_ECCINTR 4
static void __iomem *l2_base;
static int g_irq[SIFIVE_L2_MAX_ECCINTR];
@@ -39,6 +43,7 @@ enum {
DIR_CORR = 0,
DATA_CORR,
DATA_UNCORR,
+ DIR_UNCORR,
};
#ifdef CONFIG_DEBUG_FS
@@ -93,6 +98,7 @@ static void l2_config_read(void)
static const struct of_device_id sifive_l2_ids[] = {
{ .compatible = "sifive,fu540-c000-ccache" },
+ { .compatible = "sifive,fu740-c000-ccache" },
{ /* end of table */ },
};
@@ -155,6 +161,15 @@ static irqreturn_t l2_int_handler(int irq, void *device)
atomic_notifier_call_chain(_err_chain, SIFIVE_L2_ERR_TYPE_CE,
"DirECCFix");
}
+ if (irq == g_irq[DIR_UNCORR]) {
+ add_h = readl(l2_base + SIFIVE_L2_DIRECCFAIL_HIGH);
+ add_l = readl(l2_base + SIFIVE_L2_DIRECCFAIL_LOW);
+ /* Reading this register clears the DirFail interrupt sig */
+ readl(l2_base + SIFIVE_L2_DIRECCFAIL_COUNT);
+ atomic_notifier_call_chain(_err_chain, SIFIVE_L2_ERR_TYPE_UE,
+ "DirECCFail");
+ panic("L2CACHE: DirFail @ 0x%08X.%08X\n", add_h, add_l);
+ }
if (irq == g_irq[DATA_CORR]) {
add_h = readl(l2_base + SIFIVE_L2_DATECCFIX_HIGH);
add_l = readl(l2_base + SIFIVE_L2_DATECCFIX_LOW);
@@ -181,7 +196,7 @@ static int __init sifive_l2_init(void)
{
struct device_node *np;
struct resource res;
- int i, rc;
+ int i, rc, intr_num;
np = of_find_matching_node(NULL, sifive_l2_ids);
if (!np)
@@ -194,7 +209,13 @@ static int __init sifive_l2_init(void)
if (!l2_base)
return -ENOMEM;
- for (i = 0; i < SIFIVE_L2_MAX_ECCINTR; i++) {
+ intr_num = of_property_count_u32_elems(np, "interrupts");
+ if (!intr_num) {
+ pr_err("L2CACHE: no interrupts property\n");
+ return -ENODEV;
+ }
+
+ for (i = 0; i < intr_num; i++) {
g_irq[i] = irq_of_parse_and_map(np, i);
rc = request_irq(g_irq[i], l2_int_handler, 0, "l2_ecc", NULL);
if (rc) {
--
2.7.4
[PATCH v3 1/2] dt-bindings: riscv: Update l2 cache DT documentation to add support for SiFive FU740
The L2 cache controller in SiFive FU740 has 4 ECC interrupt sources as compared to 3 in FU540. Update the DT documentation accordingly with "compatible" and "interrupt" property changes. Signed-off-by: Yash Shah --- .../devicetree/bindings/riscv/sifive-l2-cache.yaml | 34 +++--- 1 file changed, 30 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml index efc0198..6a576dc 100644 --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml +++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml @@ -27,6 +27,7 @@ select: items: - enum: - sifive,fu540-c000-ccache +- sifive,fu740-c000-ccache required: - compatible @@ -34,7 +35,9 @@ select: properties: compatible: items: - - const: sifive,fu540-c000-ccache + - enum: + - sifive,fu540-c000-ccache + - sifive,fu740-c000-ccache - const: cache cache-block-size: @@ -52,10 +55,13 @@ properties: cache-unified: true interrupts: -description: | - Must contain entries for DirError, DataError and DataFail signals. minItems: 3 -maxItems: 3 +maxItems: 4 +items: + - description: DirError interrupt + - description: DataError interrupt + - description: DataFail interrupt + - description: DirFail interrupt reg: maxItems: 1 @@ -67,6 +73,26 @@ properties: The reference to the reserved-memory for the L2 Loosely Integrated Memory region. The reserved memory node should be defined as per the bindings in reserved-memory.txt. +if: + properties: +compatible: + contains: +const: sifive,fu540-c000-ccache + +then: + properties: +interrupts: + description: | +Must contain entries for DirError, DataError and DataFail signals. + maxItems: 3 + +else: + properties: +interrupts: + description: | +Must contain entries for DirError, DataError, DataFail, DirFail signals. + minItems: 4 + additionalProperties: false required: -- 2.7.4
[PATCH v3 0/2] riscv: sifive_l2_cache: Add support for SiFive FU740 SoC
Add support for additional interrupt present in SiFive FU740 chip. Changes: v3: - Rename the subject line of dt-binding patch - Add the additional interrupt "DirFail" as the last entry so as to keep the order of all previous index same. v2: - Changes as per Rob Herring's request on v1 Yash Shah (2): dt-bindings: riscv: Update l2 cache DT documentation to add support for SiFive FU740 RISC-V: sifive_l2_cache: Update L2 cache driver to support SiFive FU740 .../devicetree/bindings/riscv/sifive-l2-cache.yaml | 34 +++--- drivers/soc/sifive/sifive_l2_cache.c | 27 +++-- 2 files changed, 54 insertions(+), 7 deletions(-) -- 2.7.4
RE: [PATCH 2/3] soc: sifive: beu: Add support for SiFive Bus Error Unit
Any updates on this patch?
- Yash
> -Original Message-
> From: Yash Shah
> Sent: 12 November 2020 17:31
> To: robh...@kernel.org; Paul Walmsley ( Sifive)
> ; pal...@dabbelt.com; b...@alien8.de;
> mche...@kernel.org; tony.l...@intel.com; james.mo...@arm.com;
> r...@kernel.org
> Cc: a...@eecs.berkeley.edu; devicet...@vger.kernel.org; linux-
> ri...@lists.infradead.org; linux-kernel@vger.kernel.org; linux-
> e...@vger.kernel.org; Sachin Ghadi ; Yash
> Shah
> Subject: [PATCH 2/3] soc: sifive: beu: Add support for SiFive Bus Error Unit
>
> Add driver support for Bus Error Unit present in SiFive's FU740 chip.
> Currently the driver reports erroneous events only using Platform-level
> interrupts. The support for reporting events using hart-local interrupts can
> be added in future.
>
> Signed-off-by: Yash Shah
> ---
> drivers/soc/sifive/Kconfig | 5 +
> drivers/soc/sifive/Makefile | 1 +
> drivers/soc/sifive/sifive_beu.c | 197
>
> include/soc/sifive/sifive_beu.h | 16
> 4 files changed, 219 insertions(+)
> create mode 100644 drivers/soc/sifive/sifive_beu.c create mode 100644
> include/soc/sifive/sifive_beu.h
>
> diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig index
> 58cf8c4..d575fc1 100644
> --- a/drivers/soc/sifive/Kconfig
> +++ b/drivers/soc/sifive/Kconfig
> @@ -7,4 +7,9 @@ config SIFIVE_L2
> help
> Support for the L2 cache controller on SiFive platforms.
>
> +config SIFIVE_BEU
> + bool "Sifive Bus Error Unit"
> + help
> + Support for the Bus Error Unit on SiFive platforms.
> +
> endif
> diff --git a/drivers/soc/sifive/Makefile b/drivers/soc/sifive/Makefile index
> b5caff7..1b43ecd 100644
> --- a/drivers/soc/sifive/Makefile
> +++ b/drivers/soc/sifive/Makefile
> @@ -1,3 +1,4 @@
> # SPDX-License-Identifier: GPL-2.0
>
> obj-$(CONFIG_SIFIVE_L2) += sifive_l2_cache.o
> +obj-$(CONFIG_SIFIVE_BEU) += sifive_beu.o
> diff --git a/drivers/soc/sifive/sifive_beu.c b/drivers/soc/sifive/sifive_beu.c
> new file mode 100644 index 000..87b69ba
> --- /dev/null
> +++ b/drivers/soc/sifive/sifive_beu.c
> @@ -0,0 +1,197 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * SiFive Bus Error Unit driver
> + * Copyright (C) 2020 SiFive
> + * Author: Yash Shah
> + *
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#define SIFIVE_BEU_CAUSE 0x00
> +#define SIFIVE_BEU_VALUE 0x08
> +#define SIFIVE_BEU_ENABLE0x10
> +#define SIFIVE_BEU_PLIC_INTR 0x18
> +#define SIFIVE_BEU_ACCRUED 0x20
> +#define SIFIVE_BEU_LOCAL_INTR0x28
> +
> +#define LOCAL_INTERRUPT 0
> +#define PLIC_INTERRUPT 1
> +#define MAX_ERR_EVENTS 5
> +
> +enum beu_err_events {
> + RESERVED = -1,
> + NO_ERR,
> + ITIM_CORR_ECC = 2,
> + ITIM_UNCORR_ECC,
> + TILINKBUS_ERR = 5,
> + DCACHE_CORR_ECC,
> + DCACHE_UNCORR_ECC
> +};
> +
> +static
> +int err_events[MAX_ERR_EVENTS] = {ITIM_CORR_ECC, ITIM_UNCORR_ECC,
> TILINKBUS_ERR,
> + DCACHE_CORR_ECC,
> DCACHE_UNCORR_ECC};
> +
> +struct beu_sifive_ddata {
> + void __iomem *regs;
> + int irq;
> +};
> +
> +static int beu_enable_event(struct beu_sifive_ddata *ddata,
> + int event, int intr_type)
> +{
> + unsigned char event_mask = BIT(event), val;
> +
> + val = readb(ddata->regs + SIFIVE_BEU_ENABLE);
> + val |= event_mask;
> + writeb(val, ddata->regs + SIFIVE_BEU_ENABLE);
> +
> + if (intr_type == PLIC_INTERRUPT) {
> + val = readb(ddata->regs + SIFIVE_BEU_PLIC_INTR);
> + val |= event_mask;
> + writeb(val, ddata->regs + SIFIVE_BEU_PLIC_INTR);
> + } else if (intr_type == LOCAL_INTERRUPT) {
> + val = readb(ddata->regs + SIFIVE_BEU_LOCAL_INTR);
> + val |= event_mask;
> + writeb(event_mask, ddata->regs + SIFIVE_BEU_LOCAL_INTR);
> + }
> +
> + return 0;
> +}
> +
> +static ATOMIC_NOTIFIER_HEAD(beu_chain);
> +
> +int register_sifive_beu_error_notifier(struct notifier_block *nb) {
> + return atomic_notifier_chain_register(_chain, nb); }
> +
> +int unregister_sifive_beu_error_notifier(struct notifier_block *nb) {
> + return atomic_notifier_chain_unregister(_chain, nb); }
> +
> +static irqreturn_t beu_sifive_irq(int irq, void *data) {
> + struct beu_sifive_ddata *ddata = data;
> + unsigned char cause, addr;
> +
> + addr = readb(ddata->regs + SIFIVE_BEU_VALUE);
>
RE: [PATCH v2 1/2] RISC-V: Update l2 cache DT documentation to add support for SiFive FU740
> -Original Message- > From: Rob Herring > Sent: 09 December 2020 04:52 > To: Yash Shah > Cc: linux-kernel@vger.kernel.org; linux-ri...@lists.infradead.org; > devicet...@vger.kernel.org; b...@suse.de; a...@brainfault.org; > jonathan.came...@huawei.com; w...@kernel.org; s...@ravnborg.org; > a...@eecs.berkeley.edu; pal...@dabbelt.com; Paul Walmsley ( Sifive) > ; Sagar Kadam ; > Sachin Ghadi > Subject: Re: [PATCH v2 1/2] RISC-V: Update l2 cache DT documentation to > add support for SiFive FU740 > > [External Email] Do not click links or attachments unless you recognize the > sender and know the content is safe > > On Mon, Nov 30, 2020 at 11:13:03AM +0530, Yash Shah wrote: > > The L2 cache controller in SiFive FU740 has 4 ECC interrupt sources as > > compared to 3 in FU540. Update the DT documentation accordingly with > > "compatible" and "interrupt" property changes. > > 'dt-bindings: riscv: ...' for the subject. > > > > > Signed-off-by: Yash Shah > > --- > > Changes in v2: > > - Changes as per Rob Herring's request on v1 > > --- > > .../devicetree/bindings/riscv/sifive-l2-cache.yaml | 35 > > -- > > 1 file changed, 32 insertions(+), 3 deletions(-) > > > > diff --git > > a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml > > b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml > > index efc0198..749265c 100644 > > --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml > > +++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml > > @@ -27,6 +27,7 @@ select: > >items: > > - enum: > > - sifive,fu540-c000-ccache > > +- sifive,fu740-c000-ccache > > > >required: > > - compatible > > @@ -34,7 +35,9 @@ select: > > properties: > >compatible: > > items: > > - - const: sifive,fu540-c000-ccache > > + - enum: > > + - sifive,fu540-c000-ccache > > + - sifive,fu740-c000-ccache > >- const: cache > > > >cache-block-size: > > @@ -53,9 +56,15 @@ properties: > > > >interrupts: > > description: | > > - Must contain entries for DirError, DataError and DataFail signals. > > + Must contain 3 entries for FU540 (DirError, DataError and DataFail) > > or > 4 > > + entries for other chips (DirError, DirFail, DataError, DataFail > > + signals) > > While below is wrong, don't give descriptions that just repeat what the > schema says. Ok will remove the above description. > > > minItems: 3 > > -maxItems: 3 > > +maxItems: 4 > > +items: > > + - description: DirError interrupt > > + - description: DirFail interrupt > > + - description: DataError interrupt > > + - description: DataFail interrupt > > This says DataFail is optional. I will move back to your initial suggestion to add the new entry "DirFail" as the last index to keep the order same. Will make the corresponding changes in the driver and send a v3 patch. Thanks for your review. - Yash
[PATCH v2 9/9] riscv: dts: add initial board data for the SiFive HiFive Unmatched
Add initial board data for the SiFive HiFive Unmatched A00.
This patch is dependent on Zong's Patchset[0].
[0]:
https://lore.kernel.org/linux-riscv/20201130082330.77268-4-zong...@sifive.com/T/#u
Signed-off-by: Yash Shah
---
arch/riscv/boot/dts/sifive/Makefile| 3 +-
.../riscv/boot/dts/sifive/hifive-unmatched-a00.dts | 253 +
2 files changed, 255 insertions(+), 1 deletion(-)
create mode 100644 arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
diff --git a/arch/riscv/boot/dts/sifive/Makefile
b/arch/riscv/boot/dts/sifive/Makefile
index 6d6189e..74c47fe 100644
--- a/arch/riscv/boot/dts/sifive/Makefile
+++ b/arch/riscv/boot/dts/sifive/Makefile
@@ -1,2 +1,3 @@
# SPDX-License-Identifier: GPL-2.0
-dtb-$(CONFIG_SOC_SIFIVE) += hifive-unleashed-a00.dtb
+dtb-$(CONFIG_SOC_SIFIVE) += hifive-unleashed-a00.dtb \
+ hifive-unmatched-a00.dtb
diff --git a/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
b/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
new file mode 100644
index 000..b1c3c59
--- /dev/null
+++ b/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
@@ -0,0 +1,253 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020 SiFive, Inc */
+
+#include "fu740-c000.dtsi"
+#include
+
+/* Clock frequency (in Hz) of the PCB crystal for rtcclk */
+#define RTCCLK_FREQ100
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "SiFive HiFive Unmatched A00";
+ compatible = "sifive,hifive-unmatched-a00", "sifive,fu740-c000",
+"sifive,fu740";
+
+ chosen {
+ stdout-path = "serial0";
+ };
+
+ cpus {
+ timebase-frequency = ;
+ };
+
+ memory@8000 {
+ device_type = "memory";
+ reg = <0x0 0x8000 0x2 0x>;
+ };
+
+ soc {
+ };
+
+ hfclk: hfclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <2600>;
+ clock-output-names = "hfclk";
+ };
+
+ rtcclk: rtcclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = ;
+ clock-output-names = "rtcclk";
+ };
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+
+ temperature-sensor@4c {
+ compatible = "ti,tmp451";
+ reg = <0x4c>;
+ interrupt-parent = <>;
+ interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ pmic@58 {
+ compatible = "dlg,da9063";
+ reg = <0x58>;
+ interrupt-parent = <>;
+ interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+
+ regulators {
+ vdd_bcore1: bcore1 {
+ regulator-min-microvolt = <90>;
+ regulator-max-microvolt = <90>;
+ regulator-min-microamp = <500>;
+ regulator-max-microamp = <500>;
+ regulator-always-on;
+ };
+
+ vdd_bcore2: bcore2 {
+ regulator-min-microvolt = <90>;
+ regulator-max-microvolt = <90>;
+ regulator-min-microamp = <500>;
+ regulator-max-microamp = <500>;
+ regulator-always-on;
+ };
+
+ vdd_bpro: bpro {
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ regulator-min-microamp = <250>;
+ regulator-max-microamp = <250>;
+ regulator-always-on;
+ };
+
+ vdd_bperi: bperi {
+ regulator-min-microvolt = <105>;
+ regulator-max-microvolt = <105>;
+ regulator-min-microamp = <150>;
+ regulator-max-microamp = <150>;
+ regulator-always-on;
+ };
+
+ vdd_bmem: bmem {
+ regulator-min-microvolt = <120>;
+ regulator-max-microvolt =
[PATCH v2 7/9] riscv: dts: add initial support for the SiFive FU740-C000 SoC
Add initial support for the SiFive FU540-C000 SoC. FU740-C000 is built
around the SiFIve U7 Core Complex and a TileLink interconnect.
This file is expected to grow as more device drivers are added to the
kernel.
Signed-off-by: Yash Shah
---
arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 293 +
1 file changed, 293 insertions(+)
create mode 100644 arch/riscv/boot/dts/sifive/fu740-c000.dtsi
diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
new file mode 100644
index 000..eeb4f8c3
--- /dev/null
+++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
@@ -0,0 +1,293 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020 SiFive, Inc */
+
+/dts-v1/;
+
+#include
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "sifive,fu740-c000", "sifive,fu740";
+
+ aliases {
+ serial0 =
+ serial1 =
+ ethernet0 =
+ };
+
+ chosen {
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu0: cpu@0 {
+ compatible = "sifive,bullet0", "riscv";
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <16384>;
+ next-level-cache = <>;
+ reg = <0x0>;
+ riscv,isa = "rv64imac";
+ status = "disabled";
+ cpu0_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu1: cpu@1 {
+ compatible = "sifive,bullet0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <>;
+ reg = <0x1>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+ cpu1_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu2: cpu@2 {
+ compatible = "sifive,bullet0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <>;
+ reg = <0x2>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+ cpu2_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu3: cpu@3 {
+ compatible = "sifive,bullet0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-
[PATCH v2 8/9] dt-bindings: riscv: Update YAML doc to support SiFive HiFive Unmatched board
Add new compatible strings to the YAML DT binding document to support SiFive's HiFive Unmatched board Signed-off-by: Yash Shah --- Documentation/devicetree/bindings/riscv/sifive.yaml | 17 - 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/riscv/sifive.yaml b/Documentation/devicetree/bindings/riscv/sifive.yaml index 3a8647d..ee0a239 100644 --- a/Documentation/devicetree/bindings/riscv/sifive.yaml +++ b/Documentation/devicetree/bindings/riscv/sifive.yaml @@ -17,11 +17,18 @@ properties: $nodename: const: '/' compatible: -items: - - enum: - - sifive,hifive-unleashed-a00 - - const: sifive,fu540-c000 - - const: sifive,fu540 +oneOf: + - items: + - enum: + - sifive,hifive-unleashed-a00 + - const: sifive,fu540-c000 + - const: sifive,fu540 + + - items: + - enum: + - sifive,hifive-unmatched-a00 + - const: sifive,fu740-c000 + - const: sifive,fu740 additionalProperties: true -- 2.7.4
[PATCH v2 3/9] dt-bindings: pwm: Update DT binding docs to support SiFive FU740 SoC
Add new compatible strings to the DT binding documents to support SiFive FU740-C000. Signed-off-by: Yash Shah --- Documentation/devicetree/bindings/pwm/pwm-sifive.yaml | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml b/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml index 5ac2527..84e6691 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml +++ b/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml @@ -25,12 +25,15 @@ description: properties: compatible: items: - - const: sifive,fu540-c000-pwm + - enum: + - sifive,fu540-c000-pwm + - sifive,fu740-c000-pwm - const: sifive,pwm0 description: Should be "sifive,-pwm" and "sifive,pwm". Supported - compatible strings are "sifive,fu540-c000-pwm" for the SiFive PWM v0 - as integrated onto the SiFive FU540 chip, and "sifive,pwm0" for the + compatible strings are "sifive,fu540-c000-pwm" and + "sifive,fu740-c000-pwm" for the SiFive PWM v0 as integrated onto the + SiFive FU540 and FU740 chip respectively, and "sifive,pwm0" for the SiFive PWM v0 IP block with no chip integration tweaks. Please refer to sifive-blocks-ip-versioning.txt for details. -- 2.7.4
[PATCH v2 6/9] dt-bindings: i2c: Update DT binding docs to support SiFive FU740 SoC
Add new compatible strings to the DT binding documents to support SiFive FU740-C000. Signed-off-by: Yash Shah --- Documentation/devicetree/bindings/i2c/i2c-ocores.txt | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/i2c/i2c-ocores.txt b/Documentation/devicetree/bindings/i2c/i2c-ocores.txt index 6b25a80..a37c945 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-ocores.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-ocores.txt @@ -5,8 +5,12 @@ Required properties: "aeroflexgaisler,i2cmst" "sifive,fu540-c000-i2c", "sifive,i2c0" For Opencore based I2C IP block reimplemented in -FU540-C000 SoC. Please refer to sifive-blocks-ip-versioning.txt -for additional details. +FU540-C000 SoC. +"sifive,fu740-c000-i2c", "sifive,i2c0" +For Opencore based I2C IP block reimplemented in +FU740-C000 SoC. +Please refer to sifive-blocks-ip-versioning.txt for +additional details. - reg : bus address start and address range size of device - clocks : handle to the controller clock; see the note below. Mutually exclusive with opencores,ip-clock-frequency -- 2.7.4
[PATCH v2 5/9] dt-bindings: gpio: Update DT binding docs to support SiFive FU740 SoC
Add new compatible strings to the DT binding documents to support SiFive FU740-C000. Signed-off-by: Yash Shah --- Documentation/devicetree/bindings/gpio/sifive,gpio.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml b/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml index a0efd8d..ab22056 100644 --- a/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml @@ -13,7 +13,9 @@ maintainers: properties: compatible: items: - - const: sifive,fu540-c000-gpio + - enum: + - sifive,fu540-c000-gpio + - sifive,fu740-c000-gpio - const: sifive,gpio0 reg: -- 2.7.4
[PATCH v2 4/9] dt-bindings: serial: Update DT binding docs to support SiFive FU740 SoC
Add new compatible strings to the DT binding documents to support SiFive FU740-C000. Signed-off-by: Yash Shah --- Documentation/devicetree/bindings/serial/sifive-serial.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/serial/sifive-serial.yaml b/Documentation/devicetree/bindings/serial/sifive-serial.yaml index 92283f6..3ac5c7f 100644 --- a/Documentation/devicetree/bindings/serial/sifive-serial.yaml +++ b/Documentation/devicetree/bindings/serial/sifive-serial.yaml @@ -17,7 +17,9 @@ allOf: properties: compatible: items: - - const: sifive,fu540-c000-uart + - enum: + - sifive,fu540-c000-uart + - sifive,fu740-c000-uart - const: sifive,uart0 description: -- 2.7.4
[PATCH v2 1/9] dt-bindings: riscv: Update DT binding docs to support SiFive FU740 SoC
Add new compatible strings in cpus.yaml to support the E71 and U74 CPU
cores ("harts") that are present on FU740-C000 SoC.
Signed-off-by: Yash Shah
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml
b/Documentation/devicetree/bindings/riscv/cpus.yaml
index c6925e0..eb6843f 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -28,11 +28,17 @@ properties:
- items:
- enum:
- sifive,rocket0
+ - sifive,bullet0
- sifive,e5
+ - sifive,e7
- sifive,e51
+ - sifive,e71
- sifive,u54-mc
+ - sifive,u74-mc
- sifive,u54
+ - sifive,u74
- sifive,u5
+ - sifive,u7
- const: riscv
- const: riscv# Simulator only
description:
--
2.7.4
[PATCH v2 2/9] dt-bindings: spi: Update DT binding docs to support SiFive FU740 SoC
Add new compatible strings to the DT binding documents to support SiFive FU740-C000. Signed-off-by: Yash Shah --- Documentation/devicetree/bindings/spi/spi-sifive.yaml | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/spi-sifive.yaml b/Documentation/devicetree/bindings/spi/spi-sifive.yaml index 56dcf1d..6e7e394 100644 --- a/Documentation/devicetree/bindings/spi/spi-sifive.yaml +++ b/Documentation/devicetree/bindings/spi/spi-sifive.yaml @@ -17,15 +17,17 @@ allOf: properties: compatible: items: - - const: sifive,fu540-c000-spi + - enum: + - sifive,fu540-c000-spi + - sifive,fu740-c000-spi - const: sifive,spi0 description: Should be "sifive,-spi" and "sifive,spi". Supported compatible strings are - - "sifive,fu540-c000-spi" for the SiFive SPI v0 as integrated - onto the SiFive FU540 chip, and "sifive,spi0" for the SiFive - SPI v0 IP block with no chip integration tweaks. + "sifive,fu540-c000-spi" and "sifive,fu740-c000-spi" for the SiFive SPI v0 + as integrated onto the SiFive FU540 and FU740 chip resp, and "sifive,spi0" + for the SiFive SPI v0 IP block with no chip integration tweaks. Please refer to sifive-blocks-ip-versioning.txt for details SPI RTL that corresponds to the IP block version numbers can be found here - -- 2.7.4
[PATCH v2 0/9] arch: riscv: add board and SoC DT file support
Start board support by adding initial support for the SiFive FU740 SoC and the first development board that uses it, the SiFive HiFive Unmatched A00. Boot-tested on Linux 5.10-rc4 on a HiFive Unmatched A00 board using the U-boot and OpenSBI. This patch series is dependent on Zong's Patchset[0]. The patchset also adds two new nodes in dtsi file. The binding documentation patch for these nodes are already posted on the mailing list[1][2]. [0]: https://lore.kernel.org/linux-riscv/20201130082330.77268-4-zong...@sifive.com/T/#u [1]: https://lore.kernel.org/linux-riscv/1606714984-16593-1-git-send-email-yash.s...@sifive.com/T/#t [2]: https://lore.kernel.org/linux-riscv/20201126030043.67390-1-zong...@sifive.com/T/#u Changes in v2: - The dt bindings patch is split into several individual patches. - Expand the full list for compatible strings in i2c-ocores.txt Yash Shah (9): dt-bindings: riscv: Update DT binding docs to support SiFive FU740 SoC dt-bindings: spi: Update DT binding docs to support SiFive FU740 SoC dt-bindings: pwm: Update DT binding docs to support SiFive FU740 SoC dt-bindings: serial: Update DT binding docs to support SiFive FU740 SoC dt-bindings: gpio: Update DT binding docs to support SiFive FU740 SoC dt-bindings: i2c: Update DT binding docs to support SiFive FU740 SoC riscv: dts: add initial support for the SiFive FU740-C000 SoC dt-bindings: riscv: Update YAML doc to support SiFive HiFive Unmatched board riscv: dts: add initial board data for the SiFive HiFive Unmatched .../devicetree/bindings/gpio/sifive,gpio.yaml | 4 +- .../devicetree/bindings/i2c/i2c-ocores.txt | 8 +- .../devicetree/bindings/pwm/pwm-sifive.yaml| 9 +- Documentation/devicetree/bindings/riscv/cpus.yaml | 6 + .../devicetree/bindings/riscv/sifive.yaml | 17 +- .../devicetree/bindings/serial/sifive-serial.yaml | 4 +- .../devicetree/bindings/spi/spi-sifive.yaml| 10 +- arch/riscv/boot/dts/sifive/Makefile| 3 +- arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 293 + .../riscv/boot/dts/sifive/hifive-unmatched-a00.dts | 253 ++ 10 files changed, 590 insertions(+), 17 deletions(-) create mode 100644 arch/riscv/boot/dts/sifive/fu740-c000.dtsi create mode 100644 arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts -- 2.7.4
RE: [PATCH 1/4] dt-bindings: riscv: Update DT binding docs to support SiFive FU740 SoC
> -Original Message- > From: Andrew Lunn > Sent: 02 December 2020 20:28 > To: Yash Shah > Cc: linux-...@vger.kernel.org; linux-ser...@vger.kernel.org; linux- > p...@vger.kernel.org; linux-...@vger.kernel.org; linux- > ker...@vger.kernel.org; linux-ri...@lists.infradead.org; > devicet...@vger.kernel.org; linux-g...@vger.kernel.org; > broo...@kernel.org; gre...@linuxfoundation.org; a...@eecs.berkeley.edu; > lee.jo...@linaro.org; u.kleine-koe...@pengutronix.de; > thierry.red...@gmail.com; pe...@korsgaard.com; Paul Walmsley ( Sifive) > ; pal...@dabbelt.com; robh...@kernel.org; > bgolaszew...@baylibre.com; linus.wall...@linaro.org; Sachin Ghadi > > Subject: Re: [PATCH 1/4] dt-bindings: riscv: Update DT binding docs to > support SiFive FU740 SoC > > [External Email] Do not click links or attachments unless you recognize the > sender and know the content is safe > > > diff --git a/Documentation/devicetree/bindings/i2c/i2c-ocores.txt > > b/Documentation/devicetree/bindings/i2c/i2c-ocores.txt > > index 6b25a80..1966b2c 100644 > > --- a/Documentation/devicetree/bindings/i2c/i2c-ocores.txt > > +++ b/Documentation/devicetree/bindings/i2c/i2c-ocores.txt > > @@ -3,9 +3,11 @@ Device tree configuration for i2c-ocores Required > > properties: > > - compatible : "opencores,i2c-ocores" > > "aeroflexgaisler,i2cmst" > > -"sifive,fu540-c000-i2c", "sifive,i2c0" > > +"sifive,-i2c", "sifive,i2c0" > > Please make this a full list. At some point, this file will get turned into > yaml, at > which point substitution like this will need expanding. It is better to do > that > now. Ok sure, will do that in patch v2. - Yash > > Andrew
[PATCH 4/4] riscv: dts: add initial board data for the SiFive HiFive Unmatched
Add initial board data for the SiFive HiFive Unmatched A00
Signed-off-by: Yash Shah
---
arch/riscv/boot/dts/sifive/Makefile| 3 +-
.../riscv/boot/dts/sifive/hifive-unmatched-a00.dts | 253 +
2 files changed, 255 insertions(+), 1 deletion(-)
create mode 100644 arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
diff --git a/arch/riscv/boot/dts/sifive/Makefile
b/arch/riscv/boot/dts/sifive/Makefile
index 6d6189e..74c47fe 100644
--- a/arch/riscv/boot/dts/sifive/Makefile
+++ b/arch/riscv/boot/dts/sifive/Makefile
@@ -1,2 +1,3 @@
# SPDX-License-Identifier: GPL-2.0
-dtb-$(CONFIG_SOC_SIFIVE) += hifive-unleashed-a00.dtb
+dtb-$(CONFIG_SOC_SIFIVE) += hifive-unleashed-a00.dtb \
+ hifive-unmatched-a00.dtb
diff --git a/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
b/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
new file mode 100644
index 000..b1c3c59
--- /dev/null
+++ b/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
@@ -0,0 +1,253 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020 SiFive, Inc */
+
+#include "fu740-c000.dtsi"
+#include
+
+/* Clock frequency (in Hz) of the PCB crystal for rtcclk */
+#define RTCCLK_FREQ100
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "SiFive HiFive Unmatched A00";
+ compatible = "sifive,hifive-unmatched-a00", "sifive,fu740-c000",
+"sifive,fu740";
+
+ chosen {
+ stdout-path = "serial0";
+ };
+
+ cpus {
+ timebase-frequency = ;
+ };
+
+ memory@8000 {
+ device_type = "memory";
+ reg = <0x0 0x8000 0x2 0x>;
+ };
+
+ soc {
+ };
+
+ hfclk: hfclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <2600>;
+ clock-output-names = "hfclk";
+ };
+
+ rtcclk: rtcclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = ;
+ clock-output-names = "rtcclk";
+ };
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+
+ temperature-sensor@4c {
+ compatible = "ti,tmp451";
+ reg = <0x4c>;
+ interrupt-parent = <>;
+ interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ pmic@58 {
+ compatible = "dlg,da9063";
+ reg = <0x58>;
+ interrupt-parent = <>;
+ interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+
+ regulators {
+ vdd_bcore1: bcore1 {
+ regulator-min-microvolt = <90>;
+ regulator-max-microvolt = <90>;
+ regulator-min-microamp = <500>;
+ regulator-max-microamp = <500>;
+ regulator-always-on;
+ };
+
+ vdd_bcore2: bcore2 {
+ regulator-min-microvolt = <90>;
+ regulator-max-microvolt = <90>;
+ regulator-min-microamp = <500>;
+ regulator-max-microamp = <500>;
+ regulator-always-on;
+ };
+
+ vdd_bpro: bpro {
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ regulator-min-microamp = <250>;
+ regulator-max-microamp = <250>;
+ regulator-always-on;
+ };
+
+ vdd_bperi: bperi {
+ regulator-min-microvolt = <105>;
+ regulator-max-microvolt = <105>;
+ regulator-min-microamp = <150>;
+ regulator-max-microamp = <150>;
+ regulator-always-on;
+ };
+
+ vdd_bmem: bmem {
+ regulator-min-microvolt = <120>;
+ regulator-max-microvolt = <120>;
+ regulator-min-microamp = <300>;
+ regulator-max-
[PATCH 1/4] dt-bindings: riscv: Update DT binding docs to support SiFive FU740 SoC
Add new compatible strings to the DT binding documents to support SiFive
FU740-C000. Also, add new compatible strings in cpus.yaml to support the
E71 and U74 CPU cores ("harts") that are present on FU740-C000 SoC.
Signed-off-by: Yash Shah
---
Documentation/devicetree/bindings/gpio/sifive,gpio.yaml | 4 +++-
Documentation/devicetree/bindings/i2c/i2c-ocores.txt| 6 --
Documentation/devicetree/bindings/pwm/pwm-sifive.yaml | 9 ++---
Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++
Documentation/devicetree/bindings/serial/sifive-serial.yaml | 4 +++-
Documentation/devicetree/bindings/spi/spi-sifive.yaml | 10 ++
6 files changed, 28 insertions(+), 11 deletions(-)
diff --git a/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml
b/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml
index a0efd8d..ab22056 100644
--- a/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml
+++ b/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml
@@ -13,7 +13,9 @@ maintainers:
properties:
compatible:
items:
- - const: sifive,fu540-c000-gpio
+ - enum:
+ - sifive,fu540-c000-gpio
+ - sifive,fu740-c000-gpio
- const: sifive,gpio0
reg:
diff --git a/Documentation/devicetree/bindings/i2c/i2c-ocores.txt
b/Documentation/devicetree/bindings/i2c/i2c-ocores.txt
index 6b25a80..1966b2c 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-ocores.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-ocores.txt
@@ -3,9 +3,11 @@ Device tree configuration for i2c-ocores
Required properties:
- compatible : "opencores,i2c-ocores"
"aeroflexgaisler,i2cmst"
-"sifive,fu540-c000-i2c", "sifive,i2c0"
+"sifive,-i2c", "sifive,i2c0"
For Opencore based I2C IP block reimplemented in
-FU540-C000 SoC. Please refer to
sifive-blocks-ip-versioning.txt
+SiFive SoC. Supported compatible strings are:
+"sifive,fu540-c000-i2c" and "sifive,fu740-c000-i2c"
+Please refer to sifive-blocks-ip-versioning.txt
for additional details.
- reg : bus address start and address range size of device
- clocks : handle to the controller clock; see the note below.
diff --git a/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml
b/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml
index 5ac2527..84e6691 100644
--- a/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml
+++ b/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml
@@ -25,12 +25,15 @@ description:
properties:
compatible:
items:
- - const: sifive,fu540-c000-pwm
+ - enum:
+ - sifive,fu540-c000-pwm
+ - sifive,fu740-c000-pwm
- const: sifive,pwm0
description:
Should be "sifive,-pwm" and "sifive,pwm". Supported
- compatible strings are "sifive,fu540-c000-pwm" for the SiFive PWM v0
- as integrated onto the SiFive FU540 chip, and "sifive,pwm0" for the
+ compatible strings are "sifive,fu540-c000-pwm" and
+ "sifive,fu740-c000-pwm" for the SiFive PWM v0 as integrated onto the
+ SiFive FU540 and FU740 chip respectively, and "sifive,pwm0" for the
SiFive PWM v0 IP block with no chip integration tweaks.
Please refer to sifive-blocks-ip-versioning.txt for details.
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml
b/Documentation/devicetree/bindings/riscv/cpus.yaml
index c6925e0..eb6843f 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -28,11 +28,17 @@ properties:
- items:
- enum:
- sifive,rocket0
+ - sifive,bullet0
- sifive,e5
+ - sifive,e7
- sifive,e51
+ - sifive,e71
- sifive,u54-mc
+ - sifive,u74-mc
- sifive,u54
+ - sifive,u74
- sifive,u5
+ - sifive,u7
- const: riscv
- const: riscv# Simulator only
description:
diff --git a/Documentation/devicetree/bindings/serial/sifive-serial.yaml
b/Documentation/devicetree/bindings/serial/sifive-serial.yaml
index 92283f6..3ac5c7f 100644
--- a/Documentation/devicetree/bindings/serial/sifive-serial.yaml
+++ b/Documentation/devicetree/bindings/serial/sifive-serial.yaml
@@ -17,7 +17,9 @@ allOf:
properties:
compatible:
items:
- - const: sifive,fu540-c000-uart
+ - enum:
+ - sifive,fu540-c000-uart
+ - sifive,fu740-c000-uart
- const: sifive,uart0
description:
diff --git a/Documentation/devicetree/bindings/spi/spi-sifive.yaml
b/Documentation/devicetree/bindings/spi/spi-s
[PATCH 3/4] dt-bindings: riscv: Update YAML doc to support SiFive HiFive Unmatched board
Add new compatible strings to the YAML DT binding document to support SiFive's HiFive Unmatched board Signed-off-by: Yash Shah --- Documentation/devicetree/bindings/riscv/sifive.yaml | 17 - 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/riscv/sifive.yaml b/Documentation/devicetree/bindings/riscv/sifive.yaml index 3a8647d..ee0a239 100644 --- a/Documentation/devicetree/bindings/riscv/sifive.yaml +++ b/Documentation/devicetree/bindings/riscv/sifive.yaml @@ -17,11 +17,18 @@ properties: $nodename: const: '/' compatible: -items: - - enum: - - sifive,hifive-unleashed-a00 - - const: sifive,fu540-c000 - - const: sifive,fu540 +oneOf: + - items: + - enum: + - sifive,hifive-unleashed-a00 + - const: sifive,fu540-c000 + - const: sifive,fu540 + + - items: + - enum: + - sifive,hifive-unmatched-a00 + - const: sifive,fu740-c000 + - const: sifive,fu740 additionalProperties: true -- 2.7.4
[PATCH 2/4] riscv: dts: add initial support for the SiFive FU740-C000 SoC
Add initial support for the SiFive FU540-C000 SoC. FU740-C000 is built
around the SiFIve U7 Core Complex and a TileLink interconnect.
This file is expected to grow as more device drivers are added to the
kernel.
Signed-off-by: Yash Shah
---
arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 293 +
1 file changed, 293 insertions(+)
create mode 100644 arch/riscv/boot/dts/sifive/fu740-c000.dtsi
diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
new file mode 100644
index 000..eeb4f8c3
--- /dev/null
+++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
@@ -0,0 +1,293 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020 SiFive, Inc */
+
+/dts-v1/;
+
+#include
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "sifive,fu740-c000", "sifive,fu740";
+
+ aliases {
+ serial0 =
+ serial1 =
+ ethernet0 =
+ };
+
+ chosen {
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu0: cpu@0 {
+ compatible = "sifive,bullet0", "riscv";
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <16384>;
+ next-level-cache = <>;
+ reg = <0x0>;
+ riscv,isa = "rv64imac";
+ status = "disabled";
+ cpu0_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu1: cpu@1 {
+ compatible = "sifive,bullet0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <>;
+ reg = <0x1>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+ cpu1_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu2: cpu@2 {
+ compatible = "sifive,bullet0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <>;
+ reg = <0x2>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+ cpu2_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu3: cpu@3 {
+ compatible = "sifive,bullet0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-
[PATCH 0/4] arch: riscv: add board and SoC DT file support
Start board support by adding initial support for the SiFive FU740 SoC and the first development board that uses it, the SiFive HiFive Unmatched A00. Boot-tested on Linux 5.10-rc4 on a HiFive Unmatched A00 board using the U-boot and OpenSBI. This patch series is dependent on Zong's Patchset[0]. The patchset also adds two new nodes in dtsi file. The binding documentation patch for these nodes are already posted on the mailing list[1][2]. [0]: https://lore.kernel.org/linux-riscv/20201130082330.77268-4-zong...@sifive.com/T/#u [1]: https://lore.kernel.org/linux-riscv/1606714984-16593-1-git-send-email-yash.s...@sifive.com/T/#t [2]: https://lore.kernel.org/linux-riscv/20201126030043.67390-1-zong...@sifive.com/T/#u Yash Shah (4): dt-bindings: riscv: Update DT binding docs to support SiFive FU740 SoC riscv: dts: add initial support for the SiFive FU740-C000 SoC dt-bindings: riscv: Update YAML doc to support SiFive HiFive Unmatched board riscv: dts: add initial board data for the SiFive HiFive Unmatched .../devicetree/bindings/gpio/sifive,gpio.yaml | 4 +- .../devicetree/bindings/i2c/i2c-ocores.txt | 6 +- .../devicetree/bindings/pwm/pwm-sifive.yaml| 9 +- Documentation/devicetree/bindings/riscv/cpus.yaml | 6 + .../devicetree/bindings/riscv/sifive.yaml | 17 +- .../devicetree/bindings/serial/sifive-serial.yaml | 4 +- .../devicetree/bindings/spi/spi-sifive.yaml| 10 +- arch/riscv/boot/dts/sifive/Makefile| 3 +- arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 293 + .../riscv/boot/dts/sifive/hifive-unmatched-a00.dts | 253 ++ 10 files changed, 588 insertions(+), 17 deletions(-) create mode 100644 arch/riscv/boot/dts/sifive/fu740-c000.dtsi create mode 100644 arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts -- 2.7.4
[PATCH v2 2/2] RISC-V: sifive_l2_cache: Update L2 cache driver to support SiFive FU740
SiFive FU740 has 4 ECC interrupt sources as compared to 3 in FU540.
Update the L2 cache controller driver to support this additional
interrupt in case of FU740-C000 chip.
Signed-off-by: Yash Shah
---
drivers/soc/sifive/sifive_l2_cache.c | 49 +++-
1 file changed, 43 insertions(+), 6 deletions(-)
diff --git a/drivers/soc/sifive/sifive_l2_cache.c
b/drivers/soc/sifive/sifive_l2_cache.c
index 44d7e19..4e5e841 100644
--- a/drivers/soc/sifive/sifive_l2_cache.c
+++ b/drivers/soc/sifive/sifive_l2_cache.c
@@ -17,6 +17,10 @@
#define SIFIVE_L2_DIRECCFIX_HIGH 0x104
#define SIFIVE_L2_DIRECCFIX_COUNT 0x108
+#define SIFIVE_L2_DIRECCFAIL_LOW 0x120
+#define SIFIVE_L2_DIRECCFAIL_HIGH 0x124
+#define SIFIVE_L2_DIRECCFAIL_COUNT 0x128
+
#define SIFIVE_L2_DATECCFIX_LOW 0x140
#define SIFIVE_L2_DATECCFIX_HIGH 0x144
#define SIFIVE_L2_DATECCFIX_COUNT 0x148
@@ -29,7 +33,7 @@
#define SIFIVE_L2_WAYENABLE 0x08
#define SIFIVE_L2_ECCINJECTERR 0x40
-#define SIFIVE_L2_MAX_ECCINTR 3
+#define SIFIVE_L2_MAX_ECCINTR 4
static void __iomem *l2_base;
static int g_irq[SIFIVE_L2_MAX_ECCINTR];
@@ -37,6 +41,7 @@ static struct riscv_cacheinfo_ops l2_cache_ops;
enum {
DIR_CORR = 0,
+ DIR_UNCORR,
DATA_CORR,
DATA_UNCORR,
};
@@ -93,6 +98,7 @@ static void l2_config_read(void)
static const struct of_device_id sifive_l2_ids[] = {
{ .compatible = "sifive,fu540-c000-ccache" },
+ { .compatible = "sifive,fu740-c000-ccache" },
{ /* end of table */ },
};
@@ -155,6 +161,15 @@ static irqreturn_t l2_int_handler(int irq, void *device)
atomic_notifier_call_chain(_err_chain, SIFIVE_L2_ERR_TYPE_CE,
"DirECCFix");
}
+ if (irq == g_irq[DIR_UNCORR]) {
+ add_h = readl(l2_base + SIFIVE_L2_DIRECCFAIL_HIGH);
+ add_l = readl(l2_base + SIFIVE_L2_DIRECCFAIL_LOW);
+ /* Reading this register clears the DirFail interrupt sig */
+ readl(l2_base + SIFIVE_L2_DIRECCFAIL_COUNT);
+ atomic_notifier_call_chain(_err_chain, SIFIVE_L2_ERR_TYPE_UE,
+ "DirECCFail");
+ panic("L2CACHE: DirFail @ 0x%08X.%08X\n", add_h, add_l);
+ }
if (irq == g_irq[DATA_CORR]) {
add_h = readl(l2_base + SIFIVE_L2_DATECCFIX_HIGH);
add_l = readl(l2_base + SIFIVE_L2_DATECCFIX_LOW);
@@ -179,9 +194,9 @@ static irqreturn_t l2_int_handler(int irq, void *device)
static int __init sifive_l2_init(void)
{
+ int i, k, rc, intr_num, offset = 0;
struct device_node *np;
struct resource res;
- int i, rc;
np = of_find_matching_node(NULL, sifive_l2_ids);
if (!np)
@@ -194,11 +209,33 @@ static int __init sifive_l2_init(void)
if (!l2_base)
return -ENOMEM;
- for (i = 0; i < SIFIVE_L2_MAX_ECCINTR; i++) {
- g_irq[i] = irq_of_parse_and_map(np, i);
- rc = request_irq(g_irq[i], l2_int_handler, 0, "l2_ecc", NULL);
+ intr_num = of_property_count_u32_elems(np, "interrupts");
+ if (!intr_num) {
+ pr_err("L2CACHE: no interrupts property\n");
+ return -ENODEV;
+ }
+
+ /*
+* Only FU540 have 3 interrupts. Rest all other variants have
+* 4 interrupts (+dirfail). Therefore offset is required to skip
+* 'dirfail' interrupt entry in case of FU540
+*/
+ if (of_device_is_compatible(np, "sifive,fu540-c000-ccache"))
+ offset = 1;
+
+ g_irq[0] = irq_of_parse_and_map(np, 0);
+ rc = request_irq(g_irq[0], l2_int_handler, 0, "l2_ecc", NULL);
+ if (rc) {
+ pr_err("L2CACHE: Could not request IRQ %d\n", g_irq[0]);
+ return rc;
+ }
+
+ for (i = 1; i < intr_num; i++) {
+ k = i + offset;
+ g_irq[k] = irq_of_parse_and_map(np, i);
+ rc = request_irq(g_irq[k], l2_int_handler, 0, "l2_ecc", NULL);
if (rc) {
- pr_err("L2CACHE: Could not request IRQ %d\n", g_irq[i]);
+ pr_err("L2CACHE: Could not request IRQ %d\n", g_irq[k]);
return rc;
}
}
--
2.7.4
[PATCH v2 1/2] RISC-V: Update l2 cache DT documentation to add support for SiFive FU740
The L2 cache controller in SiFive FU740 has 4 ECC interrupt sources as compared to 3 in FU540. Update the DT documentation accordingly with "compatible" and "interrupt" property changes. Signed-off-by: Yash Shah --- Changes in v2: - Changes as per Rob Herring's request on v1 --- .../devicetree/bindings/riscv/sifive-l2-cache.yaml | 35 -- 1 file changed, 32 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml index efc0198..749265c 100644 --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml +++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml @@ -27,6 +27,7 @@ select: items: - enum: - sifive,fu540-c000-ccache +- sifive,fu740-c000-ccache required: - compatible @@ -34,7 +35,9 @@ select: properties: compatible: items: - - const: sifive,fu540-c000-ccache + - enum: + - sifive,fu540-c000-ccache + - sifive,fu740-c000-ccache - const: cache cache-block-size: @@ -53,9 +56,15 @@ properties: interrupts: description: | - Must contain entries for DirError, DataError and DataFail signals. + Must contain 3 entries for FU540 (DirError, DataError and DataFail) or 4 + entries for other chips (DirError, DirFail, DataError, DataFail signals) minItems: 3 -maxItems: 3 +maxItems: 4 +items: + - description: DirError interrupt + - description: DirFail interrupt + - description: DataError interrupt + - description: DataFail interrupt reg: maxItems: 1 @@ -67,6 +76,26 @@ properties: The reference to the reserved-memory for the L2 Loosely Integrated Memory region. The reserved memory node should be defined as per the bindings in reserved-memory.txt. +if: + properties: +compatible: + contains: +const: sifive,fu540-c000-ccache + +then: + properties: +interrupts: + description: | +Must contain entries for DirError, DataError and DataFail signals. + maxItems: 3 + +else: + properties: +interrupts: + description: | +Must contain entries for DirError, DirFail, DataError, DataFail signals. + minItems: 4 + additionalProperties: false required: -- 2.7.4
RE: [PATCH 1/2] RISC-V: Update l2 cache DT documentation to add support for SiFive FU740
> -Original Message- > From: Rob Herring > Sent: 21 November 2020 18:25 > To: Yash Shah > Cc: Paul Walmsley ( Sifive) ; > pal...@dabbelt.com; a...@eecs.berkeley.edu; > jonathan.came...@huawei.com; w...@kernel.org; s...@ravnborg.org; > Sagar Kadam ; a...@brainfault.org; > b...@suse.de; devicet...@vger.kernel.org; linux-ri...@lists.infradead.org; > linux-kernel@vger.kernel.org; Sachin Ghadi > Subject: Re: [PATCH 1/2] RISC-V: Update l2 cache DT documentation to add > support for SiFive FU740 > > [External Email] Do not click links or attachments unless you recognize the > sender and know the content is safe > > On Thu, Nov 12, 2020 at 02:41:13PM +0530, Yash Shah wrote: > > The L2 cache controller in SiFive FU740 has 4 ECC interrupt sources as > > compared to 3 in FU540. Update the DT documentation accordingly with > > "compatible" and "interrupt" property changes. > > > > Signed-off-by: Yash Shah > > --- > > .../devicetree/bindings/riscv/sifive-l2-cache.yaml | 33 > > +- > > 1 file changed, 26 insertions(+), 7 deletions(-) > > > > diff --git > > a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml > > b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml > > index efc0198..4873d5c 100644 > > --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml > > +++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml <...> > > @@ -51,12 +54,6 @@ properties: > > > >cache-unified: true > > > > - interrupts: > > -description: | > > - Must contain entries for DirError, DataError and DataFail signals. > > -minItems: 3 > > -maxItems: 3 > > Keep this here and just change maxItems to 4. Really, what each interrupt is > should be listed out as an 'items' entry. > Sure will send a v2 with the above modifications. <...> > > > + > > +else: > > + properties: > > +interrupts: > > + description: | > > +Must contain entries for DirError, DirFail, DataError, DataFail > > signals. > > DirFail should be last so you keep the same indices. Actually, the interrupts have been numbered like that in FU740 SoCs and the driver expects the interrupts to be in this order. I will keep the same order for v2 as well. Let me know if you still disagree. Thanks for your review. - Yash
[PATCH 1/3] dt-bindings: riscv: Add DT documentation for SiFive Bus Error Unit
Add DT json-schema for SiFive Bus Error unit present in FU740-C000 chip
Signed-off-by: Yash Shah
---
.../devicetree/bindings/riscv/sifive-beu.yaml | 47 ++
1 file changed, 47 insertions(+)
create mode 100644 Documentation/devicetree/bindings/riscv/sifive-beu.yaml
diff --git a/Documentation/devicetree/bindings/riscv/sifive-beu.yaml
b/Documentation/devicetree/bindings/riscv/sifive-beu.yaml
new file mode 100644
index 000..4697787
--- /dev/null
+++ b/Documentation/devicetree/bindings/riscv/sifive-beu.yaml
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright (C) 2020 SiFive, Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/riscv/sifive-beu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SiFive BUS Error Unit
+
+maintainers:
+ - Yash Shah
+ - Paul Walmsley
+
+description:
+ The Bus-Error Unit (BEU) is a per-processor device that records erroneous
+ events and reports them using platform-level and hart-local interrupts. The
+ BEU can be configured to generate interrupts on correctable memory errors,
+ uncorrectable memory errors, and/or TileLink bus errors.
+ All the properties in ePAPR/DeviceTree specification applies for this
platform.
+
+properties:
+ compatible:
+items:
+ - const: sifive,fu740-c000-beu
+ - const: sifive,beu0
+
+ interrupts:
+maxItems: 1
+
+ reg:
+maxItems: 1
+
+additionalProperties: false
+
+required:
+ - compatible
+ - interrupts
+ - reg
+
+examples:
+ - |
+bus-error-unit@170 {
+compatible = "sifive,fu740-c000-beu", "sifive,beu0";
+reg = <0x170 0x1000>;
+interrupt-parent = <>;
+interrupts = <65>;
+};
--
2.7.4
[PATCH 2/3] soc: sifive: beu: Add support for SiFive Bus Error Unit
Add driver support for Bus Error Unit present in SiFive's FU740 chip.
Currently the driver reports erroneous events only using Platform-level
interrupts. The support for reporting events using hart-local interrupts
can be added in future.
Signed-off-by: Yash Shah
---
drivers/soc/sifive/Kconfig | 5 +
drivers/soc/sifive/Makefile | 1 +
drivers/soc/sifive/sifive_beu.c | 197
include/soc/sifive/sifive_beu.h | 16
4 files changed, 219 insertions(+)
create mode 100644 drivers/soc/sifive/sifive_beu.c
create mode 100644 include/soc/sifive/sifive_beu.h
diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig
index 58cf8c4..d575fc1 100644
--- a/drivers/soc/sifive/Kconfig
+++ b/drivers/soc/sifive/Kconfig
@@ -7,4 +7,9 @@ config SIFIVE_L2
help
Support for the L2 cache controller on SiFive platforms.
+config SIFIVE_BEU
+ bool "Sifive Bus Error Unit"
+ help
+ Support for the Bus Error Unit on SiFive platforms.
+
endif
diff --git a/drivers/soc/sifive/Makefile b/drivers/soc/sifive/Makefile
index b5caff7..1b43ecd 100644
--- a/drivers/soc/sifive/Makefile
+++ b/drivers/soc/sifive/Makefile
@@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_SIFIVE_L2)+= sifive_l2_cache.o
+obj-$(CONFIG_SIFIVE_BEU) += sifive_beu.o
diff --git a/drivers/soc/sifive/sifive_beu.c b/drivers/soc/sifive/sifive_beu.c
new file mode 100644
index 000..87b69ba
--- /dev/null
+++ b/drivers/soc/sifive/sifive_beu.c
@@ -0,0 +1,197 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * SiFive Bus Error Unit driver
+ * Copyright (C) 2020 SiFive
+ * Author: Yash Shah
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define SIFIVE_BEU_CAUSE 0x00
+#define SIFIVE_BEU_VALUE 0x08
+#define SIFIVE_BEU_ENABLE 0x10
+#define SIFIVE_BEU_PLIC_INTR 0x18
+#define SIFIVE_BEU_ACCRUED 0x20
+#define SIFIVE_BEU_LOCAL_INTR 0x28
+
+#define LOCAL_INTERRUPT0
+#define PLIC_INTERRUPT 1
+#define MAX_ERR_EVENTS 5
+
+enum beu_err_events {
+ RESERVED = -1,
+ NO_ERR,
+ ITIM_CORR_ECC = 2,
+ ITIM_UNCORR_ECC,
+ TILINKBUS_ERR = 5,
+ DCACHE_CORR_ECC,
+ DCACHE_UNCORR_ECC
+};
+
+static
+int err_events[MAX_ERR_EVENTS] = {ITIM_CORR_ECC, ITIM_UNCORR_ECC,
TILINKBUS_ERR,
+ DCACHE_CORR_ECC, DCACHE_UNCORR_ECC};
+
+struct beu_sifive_ddata {
+ void __iomem *regs;
+ int irq;
+};
+
+static int beu_enable_event(struct beu_sifive_ddata *ddata,
+ int event, int intr_type)
+{
+ unsigned char event_mask = BIT(event), val;
+
+ val = readb(ddata->regs + SIFIVE_BEU_ENABLE);
+ val |= event_mask;
+ writeb(val, ddata->regs + SIFIVE_BEU_ENABLE);
+
+ if (intr_type == PLIC_INTERRUPT) {
+ val = readb(ddata->regs + SIFIVE_BEU_PLIC_INTR);
+ val |= event_mask;
+ writeb(val, ddata->regs + SIFIVE_BEU_PLIC_INTR);
+ } else if (intr_type == LOCAL_INTERRUPT) {
+ val = readb(ddata->regs + SIFIVE_BEU_LOCAL_INTR);
+ val |= event_mask;
+ writeb(event_mask, ddata->regs + SIFIVE_BEU_LOCAL_INTR);
+ }
+
+ return 0;
+}
+
+static ATOMIC_NOTIFIER_HEAD(beu_chain);
+
+int register_sifive_beu_error_notifier(struct notifier_block *nb)
+{
+ return atomic_notifier_chain_register(_chain, nb);
+}
+
+int unregister_sifive_beu_error_notifier(struct notifier_block *nb)
+{
+ return atomic_notifier_chain_unregister(_chain, nb);
+}
+
+static irqreturn_t beu_sifive_irq(int irq, void *data)
+{
+ struct beu_sifive_ddata *ddata = data;
+ unsigned char cause, addr;
+
+ addr = readb(ddata->regs + SIFIVE_BEU_VALUE);
+ cause = readb(ddata->regs + SIFIVE_BEU_CAUSE);
+ switch (cause) {
+ case NO_ERR:
+ break;
+ case ITIM_CORR_ECC:
+ pr_err("BEU: ITIM ECCFIX @ %d\n", addr);
+ atomic_notifier_call_chain(_chain, SIFIVE_BEU_ERR_TYPE_CE,
+ "ITIM ECCFIX");
+ break;
+ case ITIM_UNCORR_ECC:
+ pr_err("BEU: ITIM ECCFAIL @ %d\n", addr);
+ atomic_notifier_call_chain(_chain, SIFIVE_BEU_ERR_TYPE_UE,
+ "ITIM ECCFAIL");
+ break;
+ case TILINKBUS_ERR:
+ pr_err("BEU: Load or Store TILINK BUS ERR occurred\n");
+ break;
+ case DCACHE_CORR_ECC:
+ pr_err("BEU: DATACACHE ECCFIX @ %d\n", addr);
+ atomic_notifier_call_chain(_chain, SIFIVE_BEU_ERR_TYPE_CE,
+ "DCACHE ECCFIX");
+ break;
+ case DCACHE_UNCORR_ECC:
+ pr_err("BEU
[PATCH 3/3] EDAC/sifive: Add support for SiFive BEU in SiFive platform EDAC
Register for ECC error events from SiFive BEU in SiFive platform EDAC
driver.
Signed-off-by: Yash Shah
---
drivers/edac/Kconfig | 2 +-
drivers/edac/sifive_edac.c | 13 +++--
2 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 7a47680..8f662ff 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -469,7 +469,7 @@ config EDAC_ALTERA_SDMMC
config EDAC_SIFIVE
bool "Sifive platform EDAC driver"
- depends on EDAC=y && SIFIVE_L2
+ depends on EDAC=y && (SIFIVE_L2 || SIFIVE_BEU)
help
Support for error detection and correction on the SiFive SoCs.
diff --git a/drivers/edac/sifive_edac.c b/drivers/edac/sifive_edac.c
index 3a3dcb1..0f6d457 100644
--- a/drivers/edac/sifive_edac.c
+++ b/drivers/edac/sifive_edac.c
@@ -11,6 +11,7 @@
#include
#include "edac_module.h"
#include
+#include
#define DRVNAME "sifive_edac"
@@ -67,7 +68,11 @@ static int ecc_register(struct platform_device *pdev)
goto err;
}
- register_sifive_l2_error_notifier(>notifier);
+ if (IS_ENABLED(CONFIG_SIFIVE_L2))
+ register_sifive_l2_error_notifier(>notifier);
+
+ if (IS_ENABLED(CONFIG_SIFIVE_BEU))
+ register_sifive_beu_error_notifier(>notifier);
return 0;
@@ -81,7 +86,11 @@ static int ecc_unregister(struct platform_device *pdev)
{
struct sifive_edac_priv *p = platform_get_drvdata(pdev);
- unregister_sifive_l2_error_notifier(>notifier);
+ if (IS_ENABLED(CONFIG_SIFIVE_L2))
+ unregister_sifive_l2_error_notifier(>notifier);
+ if (IS_ENABLED(CONFIG_SIFIVE_BEU))
+ unregister_sifive_beu_error_notifier(>notifier);
+
edac_device_del_device(>dev);
edac_device_free_ctl_info(p->dci);
--
2.7.4
[PATCH 1/2] RISC-V: Update l2 cache DT documentation to add support for SiFive FU740
The L2 cache controller in SiFive FU740 has 4 ECC interrupt sources as compared to 3 in FU540. Update the DT documentation accordingly with "compatible" and "interrupt" property changes. Signed-off-by: Yash Shah --- .../devicetree/bindings/riscv/sifive-l2-cache.yaml | 33 +- 1 file changed, 26 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml index efc0198..4873d5c 100644 --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml +++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml @@ -27,6 +27,7 @@ select: items: - enum: - sifive,fu540-c000-ccache +- sifive,fu740-c000-ccache required: - compatible @@ -34,7 +35,9 @@ select: properties: compatible: items: - - const: sifive,fu540-c000-ccache + - enum: + - sifive,fu540-c000-ccache + - sifive,fu740-c000-ccache - const: cache cache-block-size: @@ -51,12 +54,6 @@ properties: cache-unified: true - interrupts: -description: | - Must contain entries for DirError, DataError and DataFail signals. -minItems: 3 -maxItems: 3 - reg: maxItems: 1 @@ -67,6 +64,28 @@ properties: The reference to the reserved-memory for the L2 Loosely Integrated Memory region. The reserved memory node should be defined as per the bindings in reserved-memory.txt. +if: + properties: +compatible: + contains: +const: sifive,fu540-c000-ccache + +then: + properties: +interrupts: + description: | +Must contain entries for DirError, DataError and DataFail signals. + minItems: 3 + maxItems: 3 + +else: + properties: +interrupts: + description: | +Must contain entries for DirError, DirFail, DataError, DataFail signals. + minItems: 4 + maxItems: 4 + additionalProperties: false required: -- 2.7.4
[PATCH 2/2] RISC-V: sifive_l2_cache: Update L2 cache driver to support SiFive FU740
SiFive FU740 has 4 ECC interrupt sources as compared to 3 in FU540.
Update the L2 cache controller driver to support this additional
interrupt in case of FU740-C000 chip.
Signed-off-by: Yash Shah
---
drivers/soc/sifive/sifive_l2_cache.c | 49 +++-
1 file changed, 43 insertions(+), 6 deletions(-)
diff --git a/drivers/soc/sifive/sifive_l2_cache.c
b/drivers/soc/sifive/sifive_l2_cache.c
index 44d7e19..4e5e841 100644
--- a/drivers/soc/sifive/sifive_l2_cache.c
+++ b/drivers/soc/sifive/sifive_l2_cache.c
@@ -17,6 +17,10 @@
#define SIFIVE_L2_DIRECCFIX_HIGH 0x104
#define SIFIVE_L2_DIRECCFIX_COUNT 0x108
+#define SIFIVE_L2_DIRECCFAIL_LOW 0x120
+#define SIFIVE_L2_DIRECCFAIL_HIGH 0x124
+#define SIFIVE_L2_DIRECCFAIL_COUNT 0x128
+
#define SIFIVE_L2_DATECCFIX_LOW 0x140
#define SIFIVE_L2_DATECCFIX_HIGH 0x144
#define SIFIVE_L2_DATECCFIX_COUNT 0x148
@@ -29,7 +33,7 @@
#define SIFIVE_L2_WAYENABLE 0x08
#define SIFIVE_L2_ECCINJECTERR 0x40
-#define SIFIVE_L2_MAX_ECCINTR 3
+#define SIFIVE_L2_MAX_ECCINTR 4
static void __iomem *l2_base;
static int g_irq[SIFIVE_L2_MAX_ECCINTR];
@@ -37,6 +41,7 @@ static struct riscv_cacheinfo_ops l2_cache_ops;
enum {
DIR_CORR = 0,
+ DIR_UNCORR,
DATA_CORR,
DATA_UNCORR,
};
@@ -93,6 +98,7 @@ static void l2_config_read(void)
static const struct of_device_id sifive_l2_ids[] = {
{ .compatible = "sifive,fu540-c000-ccache" },
+ { .compatible = "sifive,fu740-c000-ccache" },
{ /* end of table */ },
};
@@ -155,6 +161,15 @@ static irqreturn_t l2_int_handler(int irq, void *device)
atomic_notifier_call_chain(_err_chain, SIFIVE_L2_ERR_TYPE_CE,
"DirECCFix");
}
+ if (irq == g_irq[DIR_UNCORR]) {
+ add_h = readl(l2_base + SIFIVE_L2_DIRECCFAIL_HIGH);
+ add_l = readl(l2_base + SIFIVE_L2_DIRECCFAIL_LOW);
+ /* Reading this register clears the DirFail interrupt sig */
+ readl(l2_base + SIFIVE_L2_DIRECCFAIL_COUNT);
+ atomic_notifier_call_chain(_err_chain, SIFIVE_L2_ERR_TYPE_UE,
+ "DirECCFail");
+ panic("L2CACHE: DirFail @ 0x%08X.%08X\n", add_h, add_l);
+ }
if (irq == g_irq[DATA_CORR]) {
add_h = readl(l2_base + SIFIVE_L2_DATECCFIX_HIGH);
add_l = readl(l2_base + SIFIVE_L2_DATECCFIX_LOW);
@@ -179,9 +194,9 @@ static irqreturn_t l2_int_handler(int irq, void *device)
static int __init sifive_l2_init(void)
{
+ int i, k, rc, intr_num, offset = 0;
struct device_node *np;
struct resource res;
- int i, rc;
np = of_find_matching_node(NULL, sifive_l2_ids);
if (!np)
@@ -194,11 +209,33 @@ static int __init sifive_l2_init(void)
if (!l2_base)
return -ENOMEM;
- for (i = 0; i < SIFIVE_L2_MAX_ECCINTR; i++) {
- g_irq[i] = irq_of_parse_and_map(np, i);
- rc = request_irq(g_irq[i], l2_int_handler, 0, "l2_ecc", NULL);
+ intr_num = of_property_count_u32_elems(np, "interrupts");
+ if (!intr_num) {
+ pr_err("L2CACHE: no interrupts property\n");
+ return -ENODEV;
+ }
+
+ /*
+* Only FU540 have 3 interrupts. Rest all other variants have
+* 4 interrupts (+dirfail). Therefore offset is required to skip
+* 'dirfail' interrupt entry in case of FU540
+*/
+ if (of_device_is_compatible(np, "sifive,fu540-c000-ccache"))
+ offset = 1;
+
+ g_irq[0] = irq_of_parse_and_map(np, 0);
+ rc = request_irq(g_irq[0], l2_int_handler, 0, "l2_ecc", NULL);
+ if (rc) {
+ pr_err("L2CACHE: Could not request IRQ %d\n", g_irq[0]);
+ return rc;
+ }
+
+ for (i = 1; i < intr_num; i++) {
+ k = i + offset;
+ g_irq[k] = irq_of_parse_and_map(np, i);
+ rc = request_irq(g_irq[k], l2_int_handler, 0, "l2_ecc", NULL);
if (rc) {
- pr_err("L2CACHE: Could not request IRQ %d\n", g_irq[i]);
+ pr_err("L2CACHE: Could not request IRQ %d\n", g_irq[k]);
return rc;
}
}
--
2.7.4
RE: [PATCH v2 2/3] soc: sifive: Add SiFive specific Cadence DDR controller driver
> -Original Message- > From: Palmer Dabbelt > Sent: 09 September 2020 08:42 > To: Christoph Hellwig ; dkang...@cadence.com > Cc: Yash Shah ; robh...@kernel.org; Paul > Walmsley ( Sifive) ; b...@alien8.de; > mche...@kernel.org; tony.l...@intel.com; devicet...@vger.kernel.org; > a...@eecs.berkeley.edu; linux-kernel@vger.kernel.org; Sachin Ghadi > ; rrich...@marvell.com; > james.mo...@arm.com; linux-ri...@lists.infradead.org; linux- > e...@vger.kernel.org > Subject: Re: [PATCH v2 2/3] soc: sifive: Add SiFive specific Cadence DDR > controller driver > > [External Email] Do not click links or attachments unless you recognize the > sender and know the content is safe > > On Sun, 06 Sep 2020 23:11:26 PDT (-0700), Christoph Hellwig wrote: > > On Mon, Sep 07, 2020 at 11:17:58AM +0530, Yash Shah wrote: > >> Add a driver to manage the Cadence DDR controller present on SiFive > >> SoCs At present the driver manages the EDAC feature of the DDR > controller. > >> Additional features may be added to the driver in future to control > >> other aspects of the DDR controller. > > > > So if this is a generic(ish) Cadence IP block shouldn't it be named > > Cadence and made generic? Or is the frontend somehow SiFive specific? > > For some reason I thought we had a SiFive-specific interface to this, but I > may > have gotten that confused with something else as it's been a while. Someone > from SiFive would probably have a better idea, but it looks like the person > I'd > ask isn't thereany more so I'm all out of options ;) > > It looks like there was a very similar driver posted by Dhananjay Kangude > from Cadence in April: https://lkml.org/lkml/2020/4/6/358 . Some of the > register definitions seem to be different, but the code I looked at is very > similar so there's at least some bits that could be shared. I found a v4 of > that > patch set, but that was back in May: https://lkml.org/lkml/2020/5/11/912 . It > alludes to a v5, but I can't find one. I've added Dhananjay, maybe he knows > what's up? > I consulted with Dhananjay before posting this patch. From what I understood, Cadence provide highly configurable and customised DDR IP blocks based on the SoC vendor's need. This impacts the register configuration and probably the offsets too. I had also refer the v4 patch posted by Dhananjay mentioned above and found that the registers offsets are not matching with that of Cadence DDR IP in SiFive SoC. Therefore it seems this DDR IP block has SiFive specific configurations and hence this Sifive specific driver. > I don't know enough about the block to know if the subtle difference in > register names/offsets means. They look properly jumbled up (ie, not just an > offset), so maybe there's just different versions or that's the > SiFive-specific > part I had bouncing around my head? Either way, it seems like one driver > with some simple configuration could handle both of these -- either sticking > the offsets in the DT (if they're going to be different everywhere) or by > coming up with some version sort of thing (if there's a handful of these). > > I'm now also a bit worried about the provenace of this code. The two drivers > are errily similar -- for example, the variable definitions in handle_ce() > >u64 err_c_addr = 0x0; >u64 err_c_data = 0x0; >u32 err_c_synd, err_c_id; >u32 sig_val_l, sig_val_h; > > are exactly the same. I apologized, I forgot to mention it in cover-letter. I have based my work on Dhananjay's v4 patch[0]. - Yash [0]: https://lkml.org/lkml/2020/4/24/183
[PATCH v2 1/3] dt-bindings: riscv: Add DT documentation for DDR Controller in SiFive SoCs
Add device tree bindings for SiFive FU540 DDR controller driver
Signed-off-by: Yash Shah
Reviewed-by: Palmer Dabbelt
Acked-by: Palmer Dabbelt
---
.../devicetree/bindings/riscv/sifive-ddr.yaml | 41 ++
1 file changed, 41 insertions(+)
create mode 100644 Documentation/devicetree/bindings/riscv/sifive-ddr.yaml
diff --git a/Documentation/devicetree/bindings/riscv/sifive-ddr.yaml
b/Documentation/devicetree/bindings/riscv/sifive-ddr.yaml
new file mode 100644
index 000..0288119
--- /dev/null
+++ b/Documentation/devicetree/bindings/riscv/sifive-ddr.yaml
@@ -0,0 +1,41 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/riscv/sifive-ddr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SiFive DDR memory controller binding
+
+description: |
+ The Sifive DDR controller driver is used to manage the Cadence DDR
+ controller present in SiFive FU540-C000 SoC. Currently the driver is
+ used to manage EDAC feature of the DDR controller.
+
+maintainers:
+ - Yash Shah
+
+properties:
+ compatible:
+enum:
+ - sifive,fu540-c000-ddr
+
+ reg:
+maxItems: 1
+
+ interrupts:
+maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+memory-controller@100b {
+compatible = "sifive,fu540-c000-ddr";
+reg = <0x100b 0x4000>;
+interrupts = <31>;
+};
--
2.7.4
[PATCH v2 0/3] SiFive DDR controller and EDAC support
The series add supports for SiFive DDR controller driver. This driver is use to manage the Cadence DDR controller present in SiFive SoCs. Currently it manages only the EDAC feature of the DDR controller. The series also adds Memory controller EDAC support for SiFive platform. It register for notifier event from SiFive DDR controller driver. The series is tested and based on Linux v5.8. For testing on Hifive Unleashed: 1. Enable the ECC bit of DDR controller during DDR initialization 2. Erase the entire DRAM in bootloader stage 3. Using FWC feature of DDR controller force ecc error to test Changes in v2: Incorporate below changes in EDAC patch as suggested by Borislav Petkov - Replace all ifdeffery with if(IS_ENABLED(CONFIG_...)) - A few textual changes in patch description and code Yash Shah (3): dt-bindings: riscv: Add DT documentation for DDR Controller in SiFive SoCs soc: sifive: Add SiFive specific Cadence DDR controller driver EDAC/sifive: Add EDAC support for Memory Controller in SiFive SoCs .../devicetree/bindings/riscv/sifive-ddr.yaml | 41 drivers/edac/Kconfig | 2 +- drivers/edac/sifive_edac.c | 119 +++- drivers/soc/sifive/Kconfig | 6 + drivers/soc/sifive/Makefile| 3 +- drivers/soc/sifive/sifive_ddr.c| 207 + include/soc/sifive/sifive_ddr.h| 73 7 files changed, 447 insertions(+), 4 deletions(-) create mode 100644 Documentation/devicetree/bindings/riscv/sifive-ddr.yaml create mode 100644 drivers/soc/sifive/sifive_ddr.c create mode 100644 include/soc/sifive/sifive_ddr.h -- 2.7.4
[PATCH v2 3/3] EDAC/sifive: Add EDAC support for Memory Controller in SiFive SoCs
Add Memory controller EDAC support to the SiFive platform EDAC driver.
It registers for ECC notifier events from the memory controller.
Signed-off-by: Yash Shah
Reviewed-by: Palmer Dabbelt
Acked-by: Palmer Dabbelt
---
drivers/edac/Kconfig | 2 +-
drivers/edac/sifive_edac.c | 119 -
2 files changed, 118 insertions(+), 3 deletions(-)
diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 7b6ec30..f8b3b53 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -462,7 +462,7 @@ config EDAC_ALTERA_SDMMC
config EDAC_SIFIVE
bool "Sifive platform EDAC driver"
- depends on EDAC=y && SIFIVE_L2
+ depends on EDAC=y && (SIFIVE_L2 || SIFIVE_DDR)
help
Support for error detection and correction on the SiFive SoCs.
diff --git a/drivers/edac/sifive_edac.c b/drivers/edac/sifive_edac.c
index 3a3dcb1..17dd556 100644
--- a/drivers/edac/sifive_edac.c
+++ b/drivers/edac/sifive_edac.c
@@ -11,14 +11,119 @@
#include
#include "edac_module.h"
#include
+#include
#define DRVNAME "sifive_edac"
+#define EDAC_MOD_NAME "Sifive ECC Manager"
struct sifive_edac_priv {
struct notifier_block notifier;
struct edac_device_ctl_info *dci;
};
+struct sifive_edac_mc_priv {
+ struct notifier_block notifier;
+ struct mem_ctl_info *mci;
+};
+
+/**
+ * EDAC MC error callback
+ *
+ * @event: non-zero if unrecoverable.
+ */
+static
+int ecc_mc_err_event(struct notifier_block *this, unsigned long event, void
*ptr)
+{
+ struct sifive_ddr_priv *priv = ptr;
+ struct sifive_edac_mc_priv *p;
+
+ p = container_of(this, struct sifive_edac_mc_priv, notifier);
+ if (event == SIFIVE_DDR_ERR_TYPE_UE) {
+ edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, p->mci,
+priv->error_count, priv->page_frame_number,
+priv->offset_in_page, priv->syndrome,
+priv->top_layer, priv->mid_layer,
+priv->low_layer, p->mci->ctl_name, "");
+ } else if (event == SIFIVE_DDR_ERR_TYPE_CE) {
+ edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, p->mci,
+priv->error_count, priv->page_frame_number,
+priv->offset_in_page, priv->syndrome,
+priv->top_layer, priv->mid_layer,
+priv->low_layer, p->mci->ctl_name, "");
+ }
+
+ return NOTIFY_OK;
+}
+
+static int ecc_mc_register(struct platform_device *pdev)
+{
+ struct sifive_edac_mc_priv *p;
+ struct edac_mc_layer layers[1];
+ int ret;
+
+ p = devm_kzalloc(>dev, sizeof(*p), GFP_KERNEL);
+ if (!p)
+ return -ENOMEM;
+
+ p->notifier.notifier_call = ecc_mc_err_event;
+ platform_set_drvdata(pdev, p);
+
+ layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
+ layers[0].size = 1;
+ layers[0].is_virt_csrow = true;
+
+ p->mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
+ if (!p->mci) {
+ dev_err(>dev, "Failed mem allocation for mc instance\n");
+ return -ENOMEM;
+ }
+
+ p->mci->pdev = >dev;
+ /* Initialize controller capabilities */
+ p->mci->mtype_cap = MEM_FLAG_DDR4;
+ p->mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
+ p->mci->edac_cap = EDAC_FLAG_SECDED;
+ p->mci->scrub_cap = SCRUB_UNKNOWN;
+ p->mci->scrub_mode = SCRUB_HW_PROG;
+ p->mci->ctl_name = dev_name(>dev);
+ p->mci->dev_name = dev_name(>dev);
+ p->mci->mod_name = EDAC_MOD_NAME;
+ p->mci->ctl_page_to_phys = NULL;
+
+ /* Interrupt feature is supported by cadence mc */
+ edac_op_state = EDAC_OPSTATE_INT;
+
+ ret = edac_mc_add_mc(p->mci);
+ if (ret) {
+ edac_printk(KERN_ERR, EDAC_MOD_NAME,
+ "Failed to register with EDAC core\n");
+ goto err;
+ }
+
+ if (IS_ENABLED(CONFIG_SIFIVE_DDR))
+ register_sifive_ddr_error_notifier(>notifier);
+
+ return 0;
+
+err:
+ edac_mc_free(p->mci);
+
+ return -ENXIO;
+}
+
+static int ecc_mc_unregister(struct platform_device *pdev)
+{
+ struct sifive_edac_mc_priv *p = platform_get_drvdata(pdev);
+
+ if (IS_ENABLED(CONFIG_SIFIVE_DDR))
+ unregister_sifive_ddr_error_notifier(>notifier);
+
+ edac_mc_del_mc(>dev);
+ edac_mc_free(p->mci);
+
+ return 0;
+}
+
/**
* EDAC error callback
*
@@ -67,7 +172,8 @@ static int ecc_register(struct platform_device *pdev)
[PATCH v2 2/3] soc: sifive: Add SiFive specific Cadence DDR controller driver
Add a driver to manage the Cadence DDR controller present on SiFive SoCs
At present the driver manages the EDAC feature of the DDR controller.
Additional features may be added to the driver in future to control
other aspects of the DDR controller.
Signed-off-by: Yash Shah
Reviewed-by: Palmer Dabbelt
Acked-by: Palmer Dabbelt
---
drivers/soc/sifive/Kconfig | 6 ++
drivers/soc/sifive/Makefile | 3 +-
drivers/soc/sifive/sifive_ddr.c | 207
include/soc/sifive/sifive_ddr.h | 73 ++
4 files changed, 288 insertions(+), 1 deletion(-)
create mode 100644 drivers/soc/sifive/sifive_ddr.c
create mode 100644 include/soc/sifive/sifive_ddr.h
diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig
index 58cf8c4..f41d8fe 100644
--- a/drivers/soc/sifive/Kconfig
+++ b/drivers/soc/sifive/Kconfig
@@ -7,4 +7,10 @@ config SIFIVE_L2
help
Support for the L2 cache controller on SiFive platforms.
+config SIFIVE_DDR
+ bool "Sifive DDR controller driver"
+ help
+ Support for the management of cadence DDR controller on SiFive
+ platforms.
+
endif
diff --git a/drivers/soc/sifive/Makefile b/drivers/soc/sifive/Makefile
index b5caff7..b4acb5c 100644
--- a/drivers/soc/sifive/Makefile
+++ b/drivers/soc/sifive/Makefile
@@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0
-obj-$(CONFIG_SIFIVE_L2)+= sifive_l2_cache.o
+obj-$(CONFIG_SIFIVE_L2)+= sifive_l2_cache.o
+obj-$(CONFIG_SIFIVE_DDR) += sifive_ddr.o
diff --git a/drivers/soc/sifive/sifive_ddr.c b/drivers/soc/sifive/sifive_ddr.c
new file mode 100644
index 000..b1b421c
--- /dev/null
+++ b/drivers/soc/sifive/sifive_ddr.c
@@ -0,0 +1,207 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * SiFive specific cadence DDR controller Driver
+ *
+ * Copyright (C) 2019-2020 SiFive, Inc.
+ *
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+static ATOMIC_NOTIFIER_HEAD(ddr_err_chain);
+
+int register_sifive_ddr_error_notifier(struct notifier_block *nb)
+{
+ return atomic_notifier_chain_register(_err_chain, nb);
+}
+EXPORT_SYMBOL_GPL(register_sifive_ddr_error_notifier);
+
+int unregister_sifive_ddr_error_notifier(struct notifier_block *nb)
+{
+ return atomic_notifier_chain_unregister(_err_chain, nb);
+}
+EXPORT_SYMBOL_GPL(unregister_sifive_ddr_error_notifier);
+
+static void handle_ce(struct sifive_ddr_priv *pv)
+{
+ u64 err_c_addr = 0x0;
+ u64 err_c_data = 0x0;
+ u32 err_c_synd, err_c_id;
+ u32 sig_val_l, sig_val_h;
+
+ sig_val_l = readl(pv->reg + ECC_C_ADDR_L_REG);
+ sig_val_h = (readl(pv->reg + ECC_C_ADDR_H_REG) &
+ECC_ADDR_H_MASK);
+ err_c_addr = (((ulong)sig_val_h << CTL_REG_WIDTH_SHIFT) | sig_val_l);
+
+ sig_val_l = readl(pv->reg + ECC_C_DATA_L_REG);
+ sig_val_h = readl(pv->reg + ECC_C_DATA_H_REG);
+ err_c_data = (((ulong)sig_val_h << CTL_REG_WIDTH_SHIFT) | sig_val_l);
+
+ err_c_id = ((readl(pv->reg + ECC_U_C_ID_REG) &
+ECC_C_ID_MASK) >> ECC_C_ID_SHIFT);
+
+ err_c_synd = ((readl(pv->reg + ECC_C_SYND_REG) &
+ ECC_SYND_MASK) >> ECC_SYND_SHIFT);
+
+ pv->error_count = 1;
+ pv->page_frame_number = err_c_addr >> PAGE_SHIFT;
+ pv->offset_in_page = err_c_addr & ~PAGE_MASK;
+ pv->syndrome = err_c_synd;
+ pv->top_layer = 0;
+ pv->mid_layer = 0;
+ pv->low_layer = -1;
+
+ atomic_notifier_call_chain(_err_chain, SIFIVE_DDR_ERR_TYPE_CE, pv);
+}
+
+static void handle_ue(struct sifive_ddr_priv *pv)
+{
+ u64 err_u_addr = 0x0;
+ u64 err_u_data = 0x0;
+ u32 err_u_synd, err_u_id;
+ u32 sig_val_l, sig_val_h;
+
+ sig_val_l = readl(pv->reg + ECC_U_ADDR_L_REG);
+ sig_val_h = (readl(pv->reg + ECC_U_ADDR_H_REG) &
+ECC_ADDR_H_MASK);
+ err_u_addr = (((ulong)sig_val_h << CTL_REG_WIDTH_SHIFT) | sig_val_l);
+
+ sig_val_l = readl(pv->reg + ECC_U_DATA_L_REG);
+ sig_val_h = readl(pv->reg + ECC_U_DATA_H_REG);
+ err_u_data = (((ulong)sig_val_h << CTL_REG_WIDTH_SHIFT) | sig_val_l);
+
+ err_u_id = ((readl(pv->reg + ECC_U_C_ID_REG) &
+ ECC_U_ID_MASK) >> ECC_U_ID_SHIFT);
+
+ err_u_synd = ((readl(pv->reg + ECC_U_SYND_REG) &
+ ECC_SYND_MASK) >> ECC_SYND_SHIFT);
+
+ pv->error_count = 1;
+ pv->page_frame_number = err_u_addr >> PAGE_SHIFT;
+ pv->offset_in_page = err_u_addr & ~PAGE_MASK;
+ pv->syndrome = err_u_synd;
+ pv->top_layer = 0;
+ pv->mid_layer = 0;
+ pv->low_layer = -1;
+
+ atomic_notifier_call_chain(_err_chain, SIFIVE_DDR_ERR_TYPE_UE, pv);
+}
+
+static irqretur
RE: [PATCH 3/3] edac: sifive: Add EDAC support for Memory Controller in SiFive SoCs
> -Original Message-
> From: Borislav Petkov
> Sent: 31 August 2020 14:22
> To: Yash Shah
> Cc: robh...@kernel.org; pal...@dabbelt.com; Paul Walmsley ( Sifive)
> ; mche...@kernel.org; tony.l...@intel.com;
> a...@eecs.berkeley.edu; james.mo...@arm.com; rrich...@marvell.com;
> devicet...@vger.kernel.org; linux-ri...@lists.infradead.org; linux-
> ker...@vger.kernel.org; linux-e...@vger.kernel.org; Sachin Ghadi
>
> Subject: Re: [PATCH 3/3] edac: sifive: Add EDAC support for Memory
> Controller in SiFive SoCs
>
> [External Email] Do not click links or attachments unless you recognize the
> sender and know the content is safe
>
> > Subject: Re: [PATCH 3/3] edac: sifive: Add EDAC support for Memory
> > Controller in SiFive SoCs
>
> Fix subject prefix: "EDAC/sifive: ..."
>
> On Tue, Aug 25, 2020 at 05:36:22PM +0530, Yash Shah wrote:
> > Add Memory controller EDAC support in exisiting SiFive platform EDAC
>
> s/in exisiting/to the/
>
> > driver. It registers for notifier events from the SiFive DDR
> > controller driver for DDR ECC events.
>
> Simplify:
>
> "It registers for ECC notifier events from the memory controller."
>
> > Signed-off-by: Yash Shah
> > ---
> > drivers/edac/Kconfig | 2 +-
> > drivers/edac/sifive_edac.c | 117
> > +
> > 2 files changed, 118 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig index
> > 7b6ec30..f8b3b53 100644
> > --- a/drivers/edac/Kconfig
> > +++ b/drivers/edac/Kconfig
> > @@ -462,7 +462,7 @@ config EDAC_ALTERA_SDMMC
> >
> > config EDAC_SIFIVE
> > bool "Sifive platform EDAC driver"
> > - depends on EDAC=y && SIFIVE_L2
> > + depends on EDAC=y && (SIFIVE_L2 || SIFIVE_DDR)
> > help
> > Support for error detection and correction on the SiFive SoCs.
> >
> > diff --git a/drivers/edac/sifive_edac.c b/drivers/edac/sifive_edac.c
> > index 3a3dcb1..cf032685 100644
> > --- a/drivers/edac/sifive_edac.c
> > +++ b/drivers/edac/sifive_edac.c
> > @@ -11,14 +11,120 @@
> > #include
> > #include "edac_module.h"
> > #include
> > +#include
> >
> > #define DRVNAME "sifive_edac"
> > +#define SIFIVE_EDAC_MOD_NAME "Sifive ECC Manager"
>
> s/SIFIVE_EDAC_MOD_NAME/EDAC_MOD_NAME/g
>
> like the other EDAC drivers.
>
Sure, will make all the above suggested textual changes in v2.
> ...
>
> > +static int ecc_mc_register(struct platform_device *pdev) {
> > + struct sifive_edac_mc_priv *p;
> > + struct edac_mc_layer layers[1];
> > + int ret;
> > +
> > + p = devm_kzalloc(>dev, sizeof(*p), GFP_KERNEL);
> > + if (!p)
> > + return -ENOMEM;
> > +
> > + p->notifier.notifier_call = ecc_mc_err_event;
> > + platform_set_drvdata(pdev, p);
> > +
> > + layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
> > + layers[0].size = 1;
> > + layers[0].is_virt_csrow = true;
> > +
> > + p->mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
> > + if (!p->mci) {
> > + dev_err(>dev, "Failed mem allocation for mc
> > instance\n");
> > + return -ENOMEM;
> > + }
> > +
> > + p->mci->pdev = >dev;
> > + /* Initialize controller capabilities */
> > + p->mci->mtype_cap = MEM_FLAG_DDR4;
> > + p->mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
> > + p->mci->edac_cap = EDAC_FLAG_SECDED;
> > + p->mci->scrub_cap = SCRUB_UNKNOWN;
> > + p->mci->scrub_mode = SCRUB_HW_PROG;
> > + p->mci->ctl_name = dev_name(>dev);
> > + p->mci->dev_name = dev_name(>dev);
> > + p->mci->mod_name = SIFIVE_EDAC_MOD_NAME;
> > + p->mci->ctl_page_to_phys = NULL;
> > +
> > + /* Interrupt feature is supported by cadence mc */
> > + edac_op_state = EDAC_OPSTATE_INT;
> > +
> > + ret = edac_mc_add_mc(p->mci);
> > + if (ret) {
> > + edac_printk(KERN_ERR, SIFIVE_EDAC_MOD_NAME,
> > + "Failed to register with EDAC core\n");
> > + goto err;
> > + }
> > +
> > +#ifdef CONFIG_SIFIVE_DDR
>
> It seems all that ifdeffery can be replaced with
>
> if (IS_ENABLED(CONFIG_...))
Yes, will replace all the ifdeffery in v2
Thanks for the review.
- Yash
>
> Thx.
>
> --
> Regards/Gruss,
> Boris.
>
> https://people.kernel.org/tglx/notes-about-netiquette
[PATCH 3/3] edac: sifive: Add EDAC support for Memory Controller in SiFive SoCs
Add Memory controller EDAC support in exisiting SiFive platform EDAC
driver. It registers for notifier events from the SiFive DDR controller
driver for DDR ECC events.
Signed-off-by: Yash Shah
---
drivers/edac/Kconfig | 2 +-
drivers/edac/sifive_edac.c | 117 +
2 files changed, 118 insertions(+), 1 deletion(-)
diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 7b6ec30..f8b3b53 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -462,7 +462,7 @@ config EDAC_ALTERA_SDMMC
config EDAC_SIFIVE
bool "Sifive platform EDAC driver"
- depends on EDAC=y && SIFIVE_L2
+ depends on EDAC=y && (SIFIVE_L2 || SIFIVE_DDR)
help
Support for error detection and correction on the SiFive SoCs.
diff --git a/drivers/edac/sifive_edac.c b/drivers/edac/sifive_edac.c
index 3a3dcb1..cf032685 100644
--- a/drivers/edac/sifive_edac.c
+++ b/drivers/edac/sifive_edac.c
@@ -11,14 +11,120 @@
#include
#include "edac_module.h"
#include
+#include
#define DRVNAME "sifive_edac"
+#define SIFIVE_EDAC_MOD_NAME "Sifive ECC Manager"
struct sifive_edac_priv {
struct notifier_block notifier;
struct edac_device_ctl_info *dci;
};
+struct sifive_edac_mc_priv {
+ struct notifier_block notifier;
+ struct mem_ctl_info *mci;
+};
+
+/**
+ * EDAC MC error callback
+ *
+ * @event: non-zero if unrecoverable.
+ */
+static
+int ecc_mc_err_event(struct notifier_block *this, unsigned long event, void
*ptr)
+{
+ struct sifive_ddr_priv *priv = ptr;
+ struct sifive_edac_mc_priv *p;
+
+ p = container_of(this, struct sifive_edac_mc_priv, notifier);
+ if (event == SIFIVE_DDR_ERR_TYPE_UE) {
+ edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, p->mci,
+priv->error_count, priv->page_frame_number,
+priv->offset_in_page, priv->syndrome,
+priv->top_layer, priv->mid_layer,
+priv->low_layer, p->mci->ctl_name, "");
+ } else if (event == SIFIVE_DDR_ERR_TYPE_CE) {
+ edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, p->mci,
+priv->error_count, priv->page_frame_number,
+priv->offset_in_page, priv->syndrome,
+priv->top_layer, priv->mid_layer,
+priv->low_layer, p->mci->ctl_name, "");
+ }
+
+ return NOTIFY_OK;
+}
+
+static int ecc_mc_register(struct platform_device *pdev)
+{
+ struct sifive_edac_mc_priv *p;
+ struct edac_mc_layer layers[1];
+ int ret;
+
+ p = devm_kzalloc(>dev, sizeof(*p), GFP_KERNEL);
+ if (!p)
+ return -ENOMEM;
+
+ p->notifier.notifier_call = ecc_mc_err_event;
+ platform_set_drvdata(pdev, p);
+
+ layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
+ layers[0].size = 1;
+ layers[0].is_virt_csrow = true;
+
+ p->mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
+ if (!p->mci) {
+ dev_err(>dev, "Failed mem allocation for mc instance\n");
+ return -ENOMEM;
+ }
+
+ p->mci->pdev = >dev;
+ /* Initialize controller capabilities */
+ p->mci->mtype_cap = MEM_FLAG_DDR4;
+ p->mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
+ p->mci->edac_cap = EDAC_FLAG_SECDED;
+ p->mci->scrub_cap = SCRUB_UNKNOWN;
+ p->mci->scrub_mode = SCRUB_HW_PROG;
+ p->mci->ctl_name = dev_name(>dev);
+ p->mci->dev_name = dev_name(>dev);
+ p->mci->mod_name = SIFIVE_EDAC_MOD_NAME;
+ p->mci->ctl_page_to_phys = NULL;
+
+ /* Interrupt feature is supported by cadence mc */
+ edac_op_state = EDAC_OPSTATE_INT;
+
+ ret = edac_mc_add_mc(p->mci);
+ if (ret) {
+ edac_printk(KERN_ERR, SIFIVE_EDAC_MOD_NAME,
+ "Failed to register with EDAC core\n");
+ goto err;
+ }
+
+#ifdef CONFIG_SIFIVE_DDR
+ register_sifive_ddr_error_notifier(>notifier);
+#endif
+
+ return 0;
+
+err:
+ edac_mc_free(p->mci);
+
+ return -ENXIO;
+}
+
+static int ecc_mc_unregister(struct platform_device *pdev)
+{
+ struct sifive_edac_mc_priv *p = platform_get_drvdata(pdev);
+
+#ifdef CONFIG_SIFIVE_DDR
+ unregister_sifive_ddr_error_notifier(>notifier);
+#endif
+ edac_mc_del_mc(>dev);
+ edac_mc_free(p->mci);
+
+ return 0;
+}
+
/**
* EDAC error callback
*
@@ -67,7 +173,9 @@ static int ecc_register(struct platform_device *pdev)
goto err;
}
+#i
[PATCH 1/3] dt-bindings: riscv: Add DT documentation for DDR Controller in SiFive SoCs
Add device tree bindings for SiFive FU540 DDR controller driver
Signed-off-by: Yash Shah
---
.../devicetree/bindings/riscv/sifive-ddr.yaml | 41 ++
1 file changed, 41 insertions(+)
create mode 100644 Documentation/devicetree/bindings/riscv/sifive-ddr.yaml
diff --git a/Documentation/devicetree/bindings/riscv/sifive-ddr.yaml
b/Documentation/devicetree/bindings/riscv/sifive-ddr.yaml
new file mode 100644
index 000..0288119
--- /dev/null
+++ b/Documentation/devicetree/bindings/riscv/sifive-ddr.yaml
@@ -0,0 +1,41 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/riscv/sifive-ddr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SiFive DDR memory controller binding
+
+description: |
+ The Sifive DDR controller driver is used to manage the Cadence DDR
+ controller present in SiFive FU540-C000 SoC. Currently the driver is
+ used to manage EDAC feature of the DDR controller.
+
+maintainers:
+ - Yash Shah
+
+properties:
+ compatible:
+enum:
+ - sifive,fu540-c000-ddr
+
+ reg:
+maxItems: 1
+
+ interrupts:
+maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+memory-controller@100b {
+compatible = "sifive,fu540-c000-ddr";
+reg = <0x100b 0x4000>;
+interrupts = <31>;
+};
--
2.7.4
[PATCH 2/3] soc: sifive: Add SiFive specific Cadence DDR controller driver
Add a driver to manage the Cadence DDR controller present on SiFive SoCs
At present the driver manages the EDAC feature of the DDR controller.
Additional features may be added to the driver in future to control
other aspects of the DDR controller.
Signed-off-by: Yash Shah
---
drivers/soc/sifive/Kconfig | 6 ++
drivers/soc/sifive/Makefile | 3 +-
drivers/soc/sifive/sifive_ddr.c | 207
include/soc/sifive/sifive_ddr.h | 73 ++
4 files changed, 288 insertions(+), 1 deletion(-)
create mode 100644 drivers/soc/sifive/sifive_ddr.c
create mode 100644 include/soc/sifive/sifive_ddr.h
diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig
index 58cf8c4..f41d8fe 100644
--- a/drivers/soc/sifive/Kconfig
+++ b/drivers/soc/sifive/Kconfig
@@ -7,4 +7,10 @@ config SIFIVE_L2
help
Support for the L2 cache controller on SiFive platforms.
+config SIFIVE_DDR
+ bool "Sifive DDR controller driver"
+ help
+ Support for the management of cadence DDR controller on SiFive
+ platforms.
+
endif
diff --git a/drivers/soc/sifive/Makefile b/drivers/soc/sifive/Makefile
index b5caff7..b4acb5c 100644
--- a/drivers/soc/sifive/Makefile
+++ b/drivers/soc/sifive/Makefile
@@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0
-obj-$(CONFIG_SIFIVE_L2)+= sifive_l2_cache.o
+obj-$(CONFIG_SIFIVE_L2)+= sifive_l2_cache.o
+obj-$(CONFIG_SIFIVE_DDR) += sifive_ddr.o
diff --git a/drivers/soc/sifive/sifive_ddr.c b/drivers/soc/sifive/sifive_ddr.c
new file mode 100644
index 000..b1b421c
--- /dev/null
+++ b/drivers/soc/sifive/sifive_ddr.c
@@ -0,0 +1,207 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * SiFive specific cadence DDR controller Driver
+ *
+ * Copyright (C) 2019-2020 SiFive, Inc.
+ *
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+static ATOMIC_NOTIFIER_HEAD(ddr_err_chain);
+
+int register_sifive_ddr_error_notifier(struct notifier_block *nb)
+{
+ return atomic_notifier_chain_register(_err_chain, nb);
+}
+EXPORT_SYMBOL_GPL(register_sifive_ddr_error_notifier);
+
+int unregister_sifive_ddr_error_notifier(struct notifier_block *nb)
+{
+ return atomic_notifier_chain_unregister(_err_chain, nb);
+}
+EXPORT_SYMBOL_GPL(unregister_sifive_ddr_error_notifier);
+
+static void handle_ce(struct sifive_ddr_priv *pv)
+{
+ u64 err_c_addr = 0x0;
+ u64 err_c_data = 0x0;
+ u32 err_c_synd, err_c_id;
+ u32 sig_val_l, sig_val_h;
+
+ sig_val_l = readl(pv->reg + ECC_C_ADDR_L_REG);
+ sig_val_h = (readl(pv->reg + ECC_C_ADDR_H_REG) &
+ECC_ADDR_H_MASK);
+ err_c_addr = (((ulong)sig_val_h << CTL_REG_WIDTH_SHIFT) | sig_val_l);
+
+ sig_val_l = readl(pv->reg + ECC_C_DATA_L_REG);
+ sig_val_h = readl(pv->reg + ECC_C_DATA_H_REG);
+ err_c_data = (((ulong)sig_val_h << CTL_REG_WIDTH_SHIFT) | sig_val_l);
+
+ err_c_id = ((readl(pv->reg + ECC_U_C_ID_REG) &
+ECC_C_ID_MASK) >> ECC_C_ID_SHIFT);
+
+ err_c_synd = ((readl(pv->reg + ECC_C_SYND_REG) &
+ ECC_SYND_MASK) >> ECC_SYND_SHIFT);
+
+ pv->error_count = 1;
+ pv->page_frame_number = err_c_addr >> PAGE_SHIFT;
+ pv->offset_in_page = err_c_addr & ~PAGE_MASK;
+ pv->syndrome = err_c_synd;
+ pv->top_layer = 0;
+ pv->mid_layer = 0;
+ pv->low_layer = -1;
+
+ atomic_notifier_call_chain(_err_chain, SIFIVE_DDR_ERR_TYPE_CE, pv);
+}
+
+static void handle_ue(struct sifive_ddr_priv *pv)
+{
+ u64 err_u_addr = 0x0;
+ u64 err_u_data = 0x0;
+ u32 err_u_synd, err_u_id;
+ u32 sig_val_l, sig_val_h;
+
+ sig_val_l = readl(pv->reg + ECC_U_ADDR_L_REG);
+ sig_val_h = (readl(pv->reg + ECC_U_ADDR_H_REG) &
+ECC_ADDR_H_MASK);
+ err_u_addr = (((ulong)sig_val_h << CTL_REG_WIDTH_SHIFT) | sig_val_l);
+
+ sig_val_l = readl(pv->reg + ECC_U_DATA_L_REG);
+ sig_val_h = readl(pv->reg + ECC_U_DATA_H_REG);
+ err_u_data = (((ulong)sig_val_h << CTL_REG_WIDTH_SHIFT) | sig_val_l);
+
+ err_u_id = ((readl(pv->reg + ECC_U_C_ID_REG) &
+ ECC_U_ID_MASK) >> ECC_U_ID_SHIFT);
+
+ err_u_synd = ((readl(pv->reg + ECC_U_SYND_REG) &
+ ECC_SYND_MASK) >> ECC_SYND_SHIFT);
+
+ pv->error_count = 1;
+ pv->page_frame_number = err_u_addr >> PAGE_SHIFT;
+ pv->offset_in_page = err_u_addr & ~PAGE_MASK;
+ pv->syndrome = err_u_synd;
+ pv->top_layer = 0;
+ pv->mid_layer = 0;
+ pv->low_layer = -1;
+
+ atomic_notifier_call_chain(_err_chain, SIFIVE_DDR_ERR_TYPE_UE, pv);
+}
+
+static irqreturn_t ecc_isr(int irq, void *ptr)
+{
+ struct sifive_ddr_pri
[PATCH 0/3] SiFive DDR controller and EDAC support
The series add supports for SiFive DDR controller driver. This driver is use to manage the Cadence DDR controller present in SiFive SoCs. Currently it manages only the EDAC feature of the DDR controller. The series also adds Memory controller EDAC support for SiFive platform. It register for notifier event from SiFive DDR controller driver. The series is tested and based on Linux v5.8. For testing on Hifive Unleashed: 1. Enable the ECC bit of DDR controller during DDR initialization 2. Erase the entire DRAM in bootloader stage 3. Using FWC feature of DDR controller force ecc error to test Yash Shah (3): dt-bindings: riscv: Add DT documentation for DDR Controller in SiFive SoCs soc: sifive: Add SiFive specific Cadence DDR controller driver edac: sifive: Add EDAC support for Memory Controller in SiFive SoCs .../devicetree/bindings/riscv/sifive-ddr.yaml | 41 drivers/edac/Kconfig | 2 +- drivers/edac/sifive_edac.c | 117 drivers/soc/sifive/Kconfig | 6 + drivers/soc/sifive/Makefile| 3 +- drivers/soc/sifive/sifive_ddr.c| 207 + include/soc/sifive/sifive_ddr.h| 73 7 files changed, 447 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/riscv/sifive-ddr.yaml create mode 100644 drivers/soc/sifive/sifive_ddr.c create mode 100644 include/soc/sifive/sifive_ddr.h -- 2.7.4
RE: [PATCH 0/3] Dynamic CPU frequency switching for the HiFive
Hi Andreas, > -Original Message- > From: Andreas Schwab > Sent: 01 July 2020 16:11 > To: Yash Shah > Cc: Paul Walmsley ( Sifive) ; > pal...@dabbelt.com; robh...@kernel.org; linux-ri...@lists.infradead.org; > linux-kernel@vger.kernel.org; devicet...@vger.kernel.org; Sachin Ghadi > ; a...@eecs.berkeley.edu; a...@brainfault.org; > lolliv...@baylibre.com; Green Wan ; > atish.pa...@wdc.com; alistair.fran...@wdc.com; deepa.ker...@gmail.com; > bmeng...@gmail.com > Subject: Re: [PATCH 0/3] Dynamic CPU frequency switching for the HiFive > > [External Email] Do not click links or attachments unless you recognize the > sender and know the content is safe > > On Jun 16 2020, Yash Shah wrote: > > > The patch series adds the support for dynamic CPU frequency switching > > for FU540-C000 SoC on the HiFive Unleashed board. All the patches are > > based on Paul Walmsley's work. > > > > This series is based on Linux v5.7 and tested on HiFive unleashed board. > > I'm using that patch with 5.7.5. > > It appears to interfer with serial output when using the ondemand governor. > > I also see soft lockups when using the performance governor: > > [ 101.587527] rcu: INFO: rcu_sched self-detected stall on CPU > [ 101.592322] rcu: 0-...!: (932 ticks this GP) > idle=11a/1/0x4004 softirq=4301/4301 fqs=4 > [ 101.601432] (t=6001 jiffies g=4017 q=859) [ 101.605514] rcu: rcu_sched > kthread starved for 5984 jiffies! g4017 f0x0 RCU_GP_WAIT_FQS(5) - > >state=0x0 ->cpu=2 [ 101.615494] rcu: RCU grace-period kthread stack > dump: > [ 101.620530] rcu_sched R running task010 2 > 0x > [ 101.627560] Call Trace: > [ 101.630004] [] __schedule+0x25c/0x616 [ 101.635205] > [] schedule+0x42/0xb2 [ 101.640070] > [] schedule_timeout+0x56/0xb8 [ 101.645626] > [] rcu_gp_fqs_loop+0x208/0x248 [ 101.651266] > [] rcu_gp_kthread+0xc2/0xcc [ 101.656651] > [] kthread+0xda/0xec [ 101.661426] [] > ret_from_exception+0x0/0xc [ 101.666977] Task dump for CPU 0: > [ 101.670187] loop0 R running task0 655 2 > 0x0008 > [ 101.677218] Call Trace: > [ 101.679657] [] walk_stackframe+0x0/0xaa [ > 101.685036] [] show_stack+0x2a/0x34 [ 101.690074] > [] sched_show_task.part.0+0xc2/0xd2 [ 101.696154] > [] sched_show_task+0x64/0x66 [ 101.701618] > [] dump_cpu_task+0x3e/0x48 [ 101.706916] > [] rcu_dump_cpu_stacks+0x94/0xce [ 101.712731] > [] print_cpu_stall+0x116/0x18a [ 101.718375] > [] check_cpu_stall+0xcc/0x1a2 [ 101.723929] > [] rcu_pending.constprop.0+0x36/0xaa [ 101.730094] > [] rcu_sched_clock_irq+0xa6/0xea [ 101.735913] > [] update_process_times+0x1e/0x42 [ 101.741821] > [] tick_sched_handle+0x26/0x52 [ 101.747456] > [] tick_sched_timer+0x6a/0xd0 [ 101.753015] > [] __run_hrtimer.constprop.0+0x50/0xe8 > [ 101.759353] [] __hrtimer_run_queues+0x48/0x6c [ > 101.765254] [] hrtimer_interrupt+0xca/0x1d4 [ > 101.770985] [] riscv_timer_interrupt+0x32/0x3a [ > 101.776976] [] do_IRQ+0xa4/0xb8 [ 101.781663] > [] ret_from_exception+0x0/0xc > > Andreas. > > -- > Andreas Schwab, SUSE Labs, sch...@suse.de GPG Key fingerprint = 0196 > BAD8 1CE9 1970 F4BE 1748 E4D4 88E3 0EEA B9D7 "And now for something > completely different." I am looking into the issues you reported. I will update soon. Thanks for testing. - Yash
RE: [PATCH 0/3] Dynamic CPU frequency switching for the HiFive
> -Original Message- > From: David Abdurachmanov > Sent: 01 July 2020 17:34 > To: Andreas Schwab > Cc: Yash Shah ; devicet...@vger.kernel.org; Albert > Ou ; Atish Patra ; Anup > Patel ; lolliv...@baylibre.com; linux- > ker...@vger.kernel.org List ; Green Wan > ; Sachin Ghadi ; > robh...@kernel.org; Palmer Dabbelt ; > deepa.ker...@gmail.com; Paul Walmsley ( Sifive) > ; Alistair Francis ; > linux-riscv ; Bin Meng > > Subject: Re: [PATCH 0/3] Dynamic CPU frequency switching for the HiFive > > [External Email] Do not click links or attachments unless you recognize the > sender and know the content is safe > > On Wed, Jul 1, 2020 at 1:41 PM Andreas Schwab wrote: > > > > On Jun 16 2020, Yash Shah wrote: > > > > > The patch series adds the support for dynamic CPU frequency > > > switching for FU540-C000 SoC on the HiFive Unleashed board. All the > > > patches are based on Paul Walmsley's work. > > > > > > This series is based on Linux v5.7 and tested on HiFive unleashed board. > > > > I'm using that patch with 5.7.5. > > > > It appears to interfer with serial output when using the ondemand > > governor. > > I do recall that userspace governor is the only one supported but this might > have changed before this patch was posted. > > Yash, do you have more details? Yes, you are right. The userspace governor is the only one supported. - Yash > > > > > I also see soft lockups when using the performance governor: > > > > [ 101.587527] rcu: INFO: rcu_sched self-detected stall on CPU > > [ 101.592322] rcu: 0-...!: (932 ticks this GP) > idle=11a/1/0x4004 softirq=4301/4301 fqs=4 > > [ 101.601432] (t=6001 jiffies g=4017 q=859) [ 101.605514] rcu: > > rcu_sched kthread starved for 5984 jiffies! g4017 f0x0 > > RCU_GP_WAIT_FQS(5) ->state=0x0 ->cpu=2 [ 101.615494] rcu: RCU grace- > period kthread stack dump: > > [ 101.620530] rcu_sched R running task010 2 > > 0x > > [ 101.627560] Call Trace: > > [ 101.630004] [] __schedule+0x25c/0x616 [ > > 101.635205] [] schedule+0x42/0xb2 [ 101.640070] > > [] schedule_timeout+0x56/0xb8 [ 101.645626] > > [] rcu_gp_fqs_loop+0x208/0x248 [ 101.651266] > > [] rcu_gp_kthread+0xc2/0xcc [ 101.656651] > > [] kthread+0xda/0xec [ 101.661426] > > [] ret_from_exception+0x0/0xc [ 101.666977] Task > > dump for CPU 0: > > [ 101.670187] loop0 R running task0 655 2 > > 0x0008 > > [ 101.677218] Call Trace: > > [ 101.679657] [] walk_stackframe+0x0/0xaa [ > > 101.685036] [] show_stack+0x2a/0x34 [ 101.690074] > > [] sched_show_task.part.0+0xc2/0xd2 [ 101.696154] > > [] sched_show_task+0x64/0x66 [ 101.701618] > > [] dump_cpu_task+0x3e/0x48 [ 101.706916] > > [] rcu_dump_cpu_stacks+0x94/0xce [ 101.712731] > > [] print_cpu_stall+0x116/0x18a [ 101.718375] > > [] check_cpu_stall+0xcc/0x1a2 [ 101.723929] > > [] rcu_pending.constprop.0+0x36/0xaa [ 101.730094] > > [] rcu_sched_clock_irq+0xa6/0xea [ 101.735913] > > [] update_process_times+0x1e/0x42 [ 101.741821] > > [] tick_sched_handle+0x26/0x52 [ 101.747456] > > [] tick_sched_timer+0x6a/0xd0 [ 101.753015] > > [] __run_hrtimer.constprop.0+0x50/0xe8 > > [ 101.759353] [] __hrtimer_run_queues+0x48/0x6c [ > > 101.765254] [] hrtimer_interrupt+0xca/0x1d4 [ > > 101.770985] [] riscv_timer_interrupt+0x32/0x3a [ > > 101.776976] [] do_IRQ+0xa4/0xb8 [ 101.781663] > > [] ret_from_exception+0x0/0xc > > > > Andreas. > > > > -- > > Andreas Schwab, SUSE Labs, sch...@suse.de GPG Key fingerprint = 0196 > > BAD8 1CE9 1970 F4BE 1748 E4D4 88E3 0EEA B9D7 "And now for something > > completely different." > > > > ___ > > linux-riscv mailing list > > linux-ri...@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-riscv
[PATCH] RISC-V: Don't allow write+exec only page mapping request in mmap
As per the table 4.2 of the RISC-V instruction set manual[0], the PTE
permission bit combination of "write+exec only" is invalid and reserved
for future use. Hence, don't allow such mapping request in mmap call.
An issue is been reported by David Abdurachmanov, that while running
stress-ng with "sysbadaddr" argument, RCU stalls are observed on RISC-V
specific kernel.
This issue arises when the stress-sysbadaddr request for pages with
"write+exec only" permission bits and then passes the address obtain
from this mmap call to various system call. For the riscv kernel, the
mmap call should fail for this particular combination of permission bits
since it's not valid.
[0]: https://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-161.pdf
Signed-off-by: Yash Shah
Reported-by: David Abdurachmanov
---
arch/riscv/kernel/sys_riscv.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c
index f3619f5..12f8a7f 100644
--- a/arch/riscv/kernel/sys_riscv.c
+++ b/arch/riscv/kernel/sys_riscv.c
@@ -8,6 +8,7 @@
#include
#include
#include
+#include
static long riscv_sys_mmap(unsigned long addr, unsigned long len,
unsigned long prot, unsigned long flags,
@@ -16,6 +17,11 @@ static long riscv_sys_mmap(unsigned long addr, unsigned long
len,
{
if (unlikely(offset & (~PAGE_MASK >> page_shift_offset)))
return -EINVAL;
+
+ if ((prot & PROT_WRITE) && (prot & PROT_EXEC))
+ if (unlikely(!(prot & PROT_READ)))
+ return -EINVAL;
+
return ksys_mmap_pgoff(addr, len, prot, flags, fd,
offset >> (PAGE_SHIFT - page_shift_offset));
}
--
2.7.4
[PATCH 1/3] riscv: defconfig, Kconfig: enable CPU power management
Enable CPUFreq and CPUIdle for RISC-V systems to be configured with Kconfig, and compile the kernel code to support it by default. This will be used to support dynamic CPU frequency switching for the HiFive Unleashed board, along with any future RISC-V boards that support CPU power management. Signed-off-by: Yash Shah --- arch/riscv/Kconfig | 8 arch/riscv/configs/defconfig | 5 + 2 files changed, 13 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index a31e1a4..1c8443e 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -381,6 +381,14 @@ endchoice endmenu +menu "CPU Power Management" + +source "drivers/cpuidle/Kconfig" + +source "drivers/cpufreq/Kconfig" + +endmenu + menu "Power management options" source "kernel/power/Kconfig" diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index 4da4886..58f4bce 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -17,6 +17,11 @@ CONFIG_BPF_SYSCALL=y CONFIG_SOC_SIFIVE=y CONFIG_SOC_VIRT=y CONFIG_SMP=y +CONFIG_CPU_IDLE=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y +CONFIG_CPUFREQ_DT=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_NET=y -- 2.7.4
[PATCH 2/3] riscv: dts: fu540-c000: define hart clocks
Declare that each hart defined in the FU540 DT data is clocked by the
COREPLL. This is in preparation for enabling CPUFreq for the
FU540-C000 SoC on the HiFive Unleashed board.
Signed-off-by: Yash Shah
---
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
index 7db8610..735e102 100644
--- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
+++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
@@ -30,6 +30,7 @@
i-cache-size = <16384>;
reg = <0>;
riscv,isa = "rv64imac";
+ clocks = < PRCI_CLK_COREPLL>;
status = "disabled";
cpu0_intc: interrupt-controller {
#interrupt-cells = <1>;
@@ -55,6 +56,7 @@
riscv,isa = "rv64imafdc";
tlb-split;
next-level-cache = <>;
+ clocks = < PRCI_CLK_COREPLL>;
cpu1_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
@@ -79,6 +81,7 @@
riscv,isa = "rv64imafdc";
tlb-split;
next-level-cache = <>;
+ clocks = < PRCI_CLK_COREPLL>;
cpu2_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
@@ -103,6 +106,7 @@
riscv,isa = "rv64imafdc";
tlb-split;
next-level-cache = <>;
+ clocks = < PRCI_CLK_COREPLL>;
cpu3_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
@@ -127,6 +131,7 @@
riscv,isa = "rv64imafdc";
tlb-split;
next-level-cache = <>;
+ clocks = < PRCI_CLK_COREPLL>;
cpu4_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
--
2.7.4
[PATCH 0/3] Dynamic CPU frequency switching for the HiFive
The patch series adds the support for dynamic CPU frequency switching for FU540-C000 SoC on the HiFive Unleashed board. All the patches are based on Paul Walmsley's work. This series is based on Linux v5.7 and tested on HiFive unleashed board. Yash Shah (3): riscv: defconfig, Kconfig: enable CPU power management riscv: dts: fu540-c000: define hart clocks riscv: dts: HiFive Unleashed: define a default set of CPU OPPs arch/riscv/Kconfig | 8 + arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 5 +++ .../riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 38 ++ arch/riscv/configs/defconfig | 5 +++ 4 files changed, 56 insertions(+) -- 2.7.4
[PATCH 3/3] riscv: dts: HiFive Unleashed: define a default set of CPU OPPs
Define a default set of CPU OPPs for the HiFive Unleashed with the
FU540-C000 SoC. This allows CPUFreq to be enabled for this board.
The FU540-C000 SoC PVT corners haven't been characterized separately
from the HiFive Unleashed board. Thus the OPPs are added to the board
DT file, rather than the SoC itself.
The specific selection of OPPs are designed to enable fast switching
by simply changing the CORE PLL output divider. The exception is the
1GHz OPP. Since the OPP code apparently requires that, upon kernel
start, the CPU clock frequency must have been set to an existing OPP
frequency, the 1GHz rate is present solely because the default HiFive
Unleashed bootloaders set the CPU to run at 1GHz before starting the
kernel.
Signed-off-by: Yash Shah
---
.../riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 38 ++
1 file changed, 38 insertions(+)
diff --git a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
index 4a2729f..59db9c0 100644
--- a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
+++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
@@ -46,6 +46,44 @@
compatible = "gpio-restart";
gpios = < 10 GPIO_ACTIVE_LOW>;
};
+
+ fu540_c000_opp_table: opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-35000 {
+ opp-hz = /bits/ 64 <35000>;
+ };
+ opp-7 {
+ opp-hz = /bits/ 64 <7>;
+ };
+ opp-9 {
+ opp-hz = /bits/ 64 <9>;
+ };
+ opp-14 {
+ opp-hz = /bits/ 64 <14>;
+ };
+ };
+};
+
+ {
+ operating-points-v2 = <_c000_opp_table>;
+};
+
+ {
+ operating-points-v2 = <_c000_opp_table>;
+};
+
+ {
+ operating-points-v2 = <_c000_opp_table>;
+};
+
+ {
+ operating-points-v2 = <_c000_opp_table>;
+};
+
+ {
+ operating-points-v2 = <_c000_opp_table>;
};
{
--
2.7.4
Re: [PATCH] riscv: dts: Add DT support for SiFive FU540 PWM driver
On Sat, Sep 14, 2019 at 2:50 AM Palmer Dabbelt wrote:
>
> On Tue, 10 Sep 2019 02:52:07 PDT (-0700), yash.s...@sifive.com wrote:
> > Hi,
> >
> > Any comments on this patch?
>
> I don't see "sifive,pwm0" in the DT bindings documentation, and it doesn't
> match our standard way of doing these things (which would have at least
> "sifive,fu540-c000-pwm").
"sifive,pwm0" is present in the DT bindings documentation at
Documentation/devicetree/bindings/pwm/pwm-sifive.txt
Yes, I agree that this patch is missing "sifive,fu540-c000-pwm". I
will add it along with "sifive,pwm0" and repost as version 2.
Thanks for your comment.
- Yash
>
> >
> > - Yash
> >
> > On Wed, Aug 21, 2019 at 2:53 PM Yash Shah wrote:
> >>
> >> Add the PWM DT node in SiFive FU540 soc-specific DT file.
> >> Enable the PWM nodes in HiFive Unleashed board-specific DT file.
> >>
> >> Signed-off-by: Yash Shah
> >> ---
> >> arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 19
> >> +++
> >> arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 8
> >> 2 files changed, 27 insertions(+)
> >>
> >> diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
> >> b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
> >> index 42b5ec2..bb422db 100644
> >> --- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
> >> +++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
> >> @@ -230,6 +230,25 @@
> >> #size-cells = <0>;
> >> status = "disabled";
> >> };
> >> + pwm0: pwm@1002 {
> >> + compatible = "sifive,pwm0";
> >> + reg = <0x0 0x1002 0x0 0x1000>;
> >> + interrupt-parent = <>;
> >> + interrupts = <42 43 44 45>;
> >> + clocks = < PRCI_CLK_TLCLK>;
> >> + #pwm-cells = <3>;
> >> + status = "disabled";
> >> + };
> >> + pwm1: pwm@10021000 {
> >> + compatible = "sifive,pwm0";
> >> + reg = <0x0 0x10021000 0x0 0x1000>;
> >> + interrupt-parent = <>;
> >> + interrupts = <46 47 48 49>;
> >> + reg-names = "control";
> >> + clocks = < PRCI_CLK_TLCLK>;
> >> + #pwm-cells = <3>;
> >> + status = "disabled";
> >> + };
> >>
> >> };
> >> };
> >> diff --git a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
> >> b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
> >> index 93d68cb..104d334 100644
> >> --- a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
> >> +++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
> >> @@ -85,3 +85,11 @@
> >> reg = <0>;
> >> };
> >> };
> >> +
> >> + {
> >> + status = "okay";
> >> +};
> >> +
> >> + {
> >> + status = "okay";
> >> +};
> >> --
> >> 1.9.1
> >>
Re: [PATCH] riscv: dts: Add DT support for SiFive FU540 PWM driver
Hi,
Any comments on this patch?
- Yash
On Wed, Aug 21, 2019 at 2:53 PM Yash Shah wrote:
>
> Add the PWM DT node in SiFive FU540 soc-specific DT file.
> Enable the PWM nodes in HiFive Unleashed board-specific DT file.
>
> Signed-off-by: Yash Shah
> ---
> arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 19 +++
> arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 8
> 2 files changed, 27 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
> b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
> index 42b5ec2..bb422db 100644
> --- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
> +++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
> @@ -230,6 +230,25 @@
> #size-cells = <0>;
> status = "disabled";
> };
> + pwm0: pwm@1002 {
> + compatible = "sifive,pwm0";
> + reg = <0x0 0x1002 0x0 0x1000>;
> + interrupt-parent = <>;
> + interrupts = <42 43 44 45>;
> + clocks = < PRCI_CLK_TLCLK>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> + pwm1: pwm@10021000 {
> + compatible = "sifive,pwm0";
> + reg = <0x0 0x10021000 0x0 0x1000>;
> + interrupt-parent = <>;
> + interrupts = <46 47 48 49>;
> + reg-names = "control";
> + clocks = < PRCI_CLK_TLCLK>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
>
> };
> };
> diff --git a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
> b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
> index 93d68cb..104d334 100644
> --- a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
> +++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
> @@ -85,3 +85,11 @@
> reg = <0>;
> };
> };
> +
> + {
> + status = "okay";
> +};
> +
> + {
> + status = "okay";
> +};
> --
> 1.9.1
>
Re: [PATCH v2 0/2] Update ethernet compatible string for SiFive FU540
On Thu, Aug 29, 2019 at 2:36 AM David Miller wrote: > > From: Yash Shah > Date: Tue, 27 Aug 2019 10:36:02 +0530 > > > This patch series renames the compatible property to a more appropriate > > string. The patchset is based on Linux-5.3-rc6 and tested on SiFive > > Unleashed board > > You should always base changes off of "net" or "net-next" and be explicitly > in your Subject lines which of those two trees your changes are for f.e.: > > Subject: [PATCH v2 net-next N/M] ... I will keep this in mind for future patches. > > > > > Change history: > > Since v1: > > - Dropped PATCH3 because it's already merged > > - Change the reference url in the patch descriptions to point to a > > 'lore.kernel.org' link instead of 'lkml.org' > > Series applied to 'net'. Thanks! - Yash
[PATCH v2 2/2] macb: Update compatibility string for SiFive FU540-C000
Update the compatibility string for SiFive FU540-C000 as per the new
string updated in the binding doc.
Reference:
https://lore.kernel.org/netdev/caj2_jofevzqat0yprg4hem4jrrqkb72fkseqj4p8p5ka-+r...@mail.gmail.com/
Signed-off-by: Yash Shah
Acked-by: Nicolas Ferre
Reviewed-by: Paul Walmsley
Tested-by: Paul Walmsley
---
drivers/net/ethernet/cadence/macb_main.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/cadence/macb_main.c
b/drivers/net/ethernet/cadence/macb_main.c
index 5ca17e6..35b59b5 100644
--- a/drivers/net/ethernet/cadence/macb_main.c
+++ b/drivers/net/ethernet/cadence/macb_main.c
@@ -4154,7 +4154,7 @@ static int fu540_c000_init(struct platform_device *pdev)
{ .compatible = "cdns,emac", .data = _config },
{ .compatible = "cdns,zynqmp-gem", .data = _config},
{ .compatible = "cdns,zynq-gem", .data = _config },
- { .compatible = "sifive,fu540-macb", .data = _c000_config },
+ { .compatible = "sifive,fu540-c000-gem", .data = _c000_config },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, macb_dt_ids);
--
1.9.1
[PATCH v2 1/2] macb: bindings doc: update sifive fu540-c000 binding
As per the discussion with Nicolas Ferre[0], rename the compatible property to a more appropriate and specific string. [0] https://lore.kernel.org/netdev/caj2_jofevzqat0yprg4hem4jrrqkb72fkseqj4p8p5ka-+r...@mail.gmail.com/ Signed-off-by: Yash Shah Acked-by: Nicolas Ferre Reviewed-by: Paul Walmsley Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/net/macb.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/net/macb.txt b/Documentation/devicetree/bindings/net/macb.txt index 63c73fa..0b61a90 100644 --- a/Documentation/devicetree/bindings/net/macb.txt +++ b/Documentation/devicetree/bindings/net/macb.txt @@ -15,10 +15,10 @@ Required properties: Use "atmel,sama5d4-gem" for the GEM IP (10/100) available on Atmel sama5d4 SoCs. Use "cdns,zynq-gem" Xilinx Zynq-7xxx SoC. Use "cdns,zynqmp-gem" for Zynq Ultrascale+ MPSoC. - Use "sifive,fu540-macb" for SiFive FU540-C000 SoC. + Use "sifive,fu540-c000-gem" for SiFive FU540-C000 SoC. Or the generic form: "cdns,emac". - reg: Address and length of the register set for the device - For "sifive,fu540-macb", second range is required to specify the + For "sifive,fu540-c000-gem", second range is required to specify the address and length of the registers for GEMGXL Management block. - interrupts: Should contain macb interrupt - phy-mode: See ethernet.txt file in the same directory. -- 1.9.1
[PATCH v2 0/2] Update ethernet compatible string for SiFive FU540
This patch series renames the compatible property to a more appropriate string. The patchset is based on Linux-5.3-rc6 and tested on SiFive Unleashed board Change history: Since v1: - Dropped PATCH3 because it's already merged - Change the reference url in the patch descriptions to point to a 'lore.kernel.org' link instead of 'lkml.org' Yash Shah (2): macb: bindings doc: update sifive fu540-c000 binding macb: Update compatibility string for SiFive FU540-C000 Documentation/devicetree/bindings/net/macb.txt | 4 ++-- drivers/net/ethernet/cadence/macb_main.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) -- 1.9.1
[PATCH] riscv: dts: Add DT support for SiFive FU540 PWM driver
Add the PWM DT node in SiFive FU540 soc-specific DT file.
Enable the PWM nodes in HiFive Unleashed board-specific DT file.
Signed-off-by: Yash Shah
---
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 19 +++
arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 8
2 files changed, 27 insertions(+)
diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
index 42b5ec2..bb422db 100644
--- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
+++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
@@ -230,6 +230,25 @@
#size-cells = <0>;
status = "disabled";
};
+ pwm0: pwm@1002 {
+ compatible = "sifive,pwm0";
+ reg = <0x0 0x1002 0x0 0x1000>;
+ interrupt-parent = <>;
+ interrupts = <42 43 44 45>;
+ clocks = < PRCI_CLK_TLCLK>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+ pwm1: pwm@10021000 {
+ compatible = "sifive,pwm0";
+ reg = <0x0 0x10021000 0x0 0x1000>;
+ interrupt-parent = <>;
+ interrupts = <46 47 48 49>;
+ reg-names = "control";
+ clocks = < PRCI_CLK_TLCLK>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
};
};
diff --git a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
index 93d68cb..104d334 100644
--- a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
+++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
@@ -85,3 +85,11 @@
reg = <0>;
};
};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
--
1.9.1
Re: [PATCH] riscv: move sifive_l2_cache.c to drivers/soc
On Mon, Aug 19, 2019 at 11:56 AM Christoph Hellwig wrote: > > On Mon, Aug 19, 2019 at 08:09:04AM +0200, Borislav Petkov wrote: > > On Sun, Aug 18, 2019 at 10:29:35AM +0200, Christoph Hellwig wrote: > > > The sifive_l2_cache.c is in no way related to RISC-V architecture > > > memory management. It is a little stub driver working around the fact > > > that the EDAC maintainers prefer their drivers to be structured in a > > > certain way > > > > That changed recently so I guess we can do the per-IP block driver after > > all, if people would still prefer it. > > That would seem like the best idea. But I don't really know this code > well enough myself, and I really need to get this code out of the > forced on RISC-V codebase as some SOCs I'm working with simply don't > have the memory for it.. > > So unless someone signs up to do a per-IP block edac drivers instead > very quickly I'd still like to see something like this go into 5.4 > for now. As of now, we can pull this patch into 5.4. Later, I will review if per-IP block edac driver is needed and if so, will take care of implementing it. - Yash
Re: [PATCH 2/3] macb: Update compatibility string for SiFive FU540-C000
On Fri, Jul 19, 2019 at 5:36 PM wrote: > > On 19/07/2019 at 13:10, Yash Shah wrote: > > Update the compatibility string for SiFive FU540-C000 as per the new > > string updated in the binding doc. > > Reference: https://lkml.org/lkml/2019/7/17/200 > > Maybe referring to lore.kernel.org is better: > https://lore.kernel.org/netdev/caj2_jofevzqat0yprg4hem4jrrqkb72fkseqj4p8p5ka-+r...@mail.gmail.com/ Sure. Will keep that in mind for future reference. > > > Signed-off-by: Yash Shah > > Acked-by: Nicolas Ferre Thanks. - Yash
[PATCH 2/3] macb: Update compatibility string for SiFive FU540-C000
Update the compatibility string for SiFive FU540-C000 as per the new
string updated in the binding doc.
Reference: https://lkml.org/lkml/2019/7/17/200
Signed-off-by: Yash Shah
---
drivers/net/ethernet/cadence/macb_main.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/cadence/macb_main.c
b/drivers/net/ethernet/cadence/macb_main.c
index 15d0737..305371c 100644
--- a/drivers/net/ethernet/cadence/macb_main.c
+++ b/drivers/net/ethernet/cadence/macb_main.c
@@ -4112,7 +4112,7 @@ static int fu540_c000_init(struct platform_device *pdev)
{ .compatible = "cdns,emac", .data = _config },
{ .compatible = "cdns,zynqmp-gem", .data = _config},
{ .compatible = "cdns,zynq-gem", .data = _config },
- { .compatible = "sifive,fu540-macb", .data = _c000_config },
+ { .compatible = "sifive,fu540-c000-gem", .data = _c000_config },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, macb_dt_ids);
--
1.9.1
[PATCH 3/3] riscv: dts: Add DT node for SiFive FU540 Ethernet controller driver
DT node for SiFive FU540-C000 GEMGXL Ethernet controller driver added
Signed-off-by: Yash Shah
---
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 15 +++
arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 9 +
2 files changed, 24 insertions(+)
diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
index cc73522..588669f0 100644
--- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
+++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
@@ -231,5 +231,20 @@
#size-cells = <0>;
status = "disabled";
};
+ eth0: ethernet@1009 {
+ compatible = "sifive,fu540-c000-gem";
+ interrupt-parent = <>;
+ interrupts = <53>;
+ reg = <0x0 0x1009 0x0 0x2000
+ 0x0 0x100a 0x0 0x1000>;
+ local-mac-address = [00 00 00 00 00 00];
+ clock-names = "pclk", "hclk";
+ clocks = < PRCI_CLK_GEMGXLPLL>,
+< PRCI_CLK_GEMGXLPLL>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
};
};
diff --git a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
index 0b55c53..85c17a7 100644
--- a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
+++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
@@ -76,3 +76,12 @@
disable-wp;
};
};
+
+ {
+ status = "okay";
+ phy-mode = "gmii";
+ phy-handle = <>;
+ phy1: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
--
1.9.1
[PATCH 1/3] macb: bindings doc: update sifive fu540-c000 binding
As per the discussion with Nicolas Ferre, rename the compatible property to a more appropriate and specific string. LINK: https://lkml.org/lkml/2019/7/17/200 Signed-off-by: Yash Shah --- Documentation/devicetree/bindings/net/macb.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/net/macb.txt b/Documentation/devicetree/bindings/net/macb.txt index 63c73fa..0b61a90 100644 --- a/Documentation/devicetree/bindings/net/macb.txt +++ b/Documentation/devicetree/bindings/net/macb.txt @@ -15,10 +15,10 @@ Required properties: Use "atmel,sama5d4-gem" for the GEM IP (10/100) available on Atmel sama5d4 SoCs. Use "cdns,zynq-gem" Xilinx Zynq-7xxx SoC. Use "cdns,zynqmp-gem" for Zynq Ultrascale+ MPSoC. - Use "sifive,fu540-macb" for SiFive FU540-C000 SoC. + Use "sifive,fu540-c000-gem" for SiFive FU540-C000 SoC. Or the generic form: "cdns,emac". - reg: Address and length of the register set for the device - For "sifive,fu540-macb", second range is required to specify the + For "sifive,fu540-c000-gem", second range is required to specify the address and length of the registers for GEMGXL Management block. - interrupts: Should contain macb interrupt - phy-mode: See ethernet.txt file in the same directory. -- 1.9.1
Re: [PATCH 1/2] net/macb: bindings doc: add sifive fu540-c000 binding
On Mon, Jun 24, 2019 at 9:08 PM wrote:
>
> On 23/05/2019 at 22:50, Rob Herring wrote:
> > On Thu, May 23, 2019 at 6:46 AM Yash Shah wrote:
> >>
> >> Add the compatibility string documentation for SiFive FU540-C
> >> interface.
> >> On the FU540, this driver also needs to read and write registers in a
> >> management IP block that monitors or drives boundary signals for the
> >> GEMGXL IP block that are not directly mapped to GEMGXL registers.
> >> Therefore, add additional range to "reg" property for SiFive GEMGXL
> >> management IP registers.
> >>
> >> Signed-off-by: Yash Shah
> >> ---
> >> Documentation/devicetree/bindings/net/macb.txt | 3 +++
> >> 1 file changed, 3 insertions(+)
> >>
> >> diff --git a/Documentation/devicetree/bindings/net/macb.txt
> >> b/Documentation/devicetree/bindings/net/macb.txt
> >> index 9c5e944..91a2a66 100644
> >> --- a/Documentation/devicetree/bindings/net/macb.txt
> >> +++ b/Documentation/devicetree/bindings/net/macb.txt
> >> @@ -4,6 +4,7 @@ Required properties:
> >> - compatible: Should be "cdns,[-]{macb|gem}"
> >> Use "cdns,at91rm9200-emac" Atmel at91rm9200 SoC.
> >> Use "cdns,at91sam9260-macb" for Atmel at91sam9 SoCs.
> >> + Use "cdns,fu540-macb" for SiFive FU540-C000 SoC.
> >
> > This pattern that Atmel started isn't really correct. The vendor
> > prefix here should be sifive. 'cdns' would be appropriate for a
> > fallback.
>
> Ok, we missed this for the sam9x60 SoC that we added recently then.
>
> Anyway a little too late, coming back to this machine, and talking to
> Yash, isn't "sifive,fu540-c000-macb" more specific and a better match
> for being future proof? I would advice for the most specific possible
> with other compatible strings on the same line in the DT, like:
>
> "sifive,fu540-c000-macb", "sifive,fu540-macb"
>
Yes, I agree that "sifive,fu540-c000-macb" is a better match.
> Moreover, is it really a "macb" or a "gem" type of interface from
> Cadence? Not a big deal, but just to discuss the topic to the bone...
I believe it should be "gem". I will plan to submit the patch for
these changes. Thanks for pointing it out.
- Yash
>
> Note that I'm fine if you consider that what you have in net-next new is
> correct.
>
> Regards,
>Nicolas
>
> >> Use "cdns,sam9x60-macb" for Microchip sam9x60 SoC.
> >> Use "cdns,np4-macb" for NP4 SoC devices.
> >> Use "cdns,at32ap7000-macb" for other 10/100 usage or use the generic
> >> form: "cdns,macb".
> >> @@ -17,6 +18,8 @@ Required properties:
> >> Use "cdns,zynqmp-gem" for Zynq Ultrascale+ MPSoC.
> >> Or the generic form: "cdns,emac".
> >> - reg: Address and length of the register set for the device
> >> + For "cdns,fu540-macb", second range is required to specify the
> >> + address and length of the registers for GEMGXL Management block.
> >> - interrupts: Should contain macb interrupt
> >> - phy-mode: See ethernet.txt file in the same directory.
> >> - clock-names: Tuple listing input clock names.
> >> --
> >> 1.9.1
> >>
> >
>
>
> --
> Nicolas Ferre
[PATCH v2] riscv: ccache: Remove unused variable
Reading the count register clears the interrupt signal. Currently, the
count registers are read into 'regval' variable but the variable is
never used. Therefore remove it. V2 of this patch add comments to
justify the readl calls without checking the return value.
Signed-off-by: Yash Shah
---
arch/riscv/mm/sifive_l2_cache.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/arch/riscv/mm/sifive_l2_cache.c b/arch/riscv/mm/sifive_l2_cache.c
index 4eb6461..2e637ad 100644
--- a/arch/riscv/mm/sifive_l2_cache.c
+++ b/arch/riscv/mm/sifive_l2_cache.c
@@ -109,13 +109,14 @@ int unregister_sifive_l2_error_notifier(struct
notifier_block *nb)
static irqreturn_t l2_int_handler(int irq, void *device)
{
- unsigned int regval, add_h, add_l;
+ unsigned int add_h, add_l;
if (irq == g_irq[DIR_CORR]) {
add_h = readl(l2_base + SIFIVE_L2_DIRECCFIX_HIGH);
add_l = readl(l2_base + SIFIVE_L2_DIRECCFIX_LOW);
pr_err("L2CACHE: DirError @ 0x%08X.%08X\n", add_h, add_l);
- regval = readl(l2_base + SIFIVE_L2_DIRECCFIX_COUNT);
+ /* Reading this register clears the DirError interrupt sig */
+ readl(l2_base + SIFIVE_L2_DIRECCFIX_COUNT);
atomic_notifier_call_chain(_err_chain, SIFIVE_L2_ERR_TYPE_CE,
"DirECCFix");
}
@@ -123,7 +124,8 @@ static irqreturn_t l2_int_handler(int irq, void *device)
add_h = readl(l2_base + SIFIVE_L2_DATECCFIX_HIGH);
add_l = readl(l2_base + SIFIVE_L2_DATECCFIX_LOW);
pr_err("L2CACHE: DataError @ 0x%08X.%08X\n", add_h, add_l);
- regval = readl(l2_base + SIFIVE_L2_DATECCFIX_COUNT);
+ /* Reading this register clears the DataError interrupt sig */
+ readl(l2_base + SIFIVE_L2_DATECCFIX_COUNT);
atomic_notifier_call_chain(_err_chain, SIFIVE_L2_ERR_TYPE_CE,
"DatECCFix");
}
@@ -131,7 +133,8 @@ static irqreturn_t l2_int_handler(int irq, void *device)
add_h = readl(l2_base + SIFIVE_L2_DATECCFAIL_HIGH);
add_l = readl(l2_base + SIFIVE_L2_DATECCFAIL_LOW);
pr_err("L2CACHE: DataFail @ 0x%08X.%08X\n", add_h, add_l);
- regval = readl(l2_base + SIFIVE_L2_DATECCFAIL_COUNT);
+ /* Reading this register clears the DataFail interrupt sig */
+ readl(l2_base + SIFIVE_L2_DATECCFAIL_COUNT);
atomic_notifier_call_chain(_err_chain, SIFIVE_L2_ERR_TYPE_UE,
"DatECCFail");
}
--
1.9.1
Re: [PATCH] riscv: ccache: Remove unused variable
On Thu, Jun 27, 2019 at 9:43 PM Paul Walmsley wrote: > > On Thu, 27 Jun 2019, Yash Shah wrote: > > > Reading the count register clears the interrupt signal. Currently, the > > count registers are read into 'regval' variable but the variable is > > never used. Therefore remove it. > > > > Signed-off-by: Yash Shah > > This is a good start. Could you also add comments in the code that > describe what those reads are doing, as you did in the patch description? > Otherwise they look pretty mysterious. > Sure, will add comments and send v2 > > - Paul
[PATCH] riscv: ccache: Remove unused variable
Reading the count register clears the interrupt signal. Currently, the
count registers are read into 'regval' variable but the variable is
never used. Therefore remove it.
Signed-off-by: Yash Shah
---
arch/riscv/mm/sifive_l2_cache.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/riscv/mm/sifive_l2_cache.c b/arch/riscv/mm/sifive_l2_cache.c
index 4eb6461..3052a42 100644
--- a/arch/riscv/mm/sifive_l2_cache.c
+++ b/arch/riscv/mm/sifive_l2_cache.c
@@ -109,13 +109,13 @@ int unregister_sifive_l2_error_notifier(struct
notifier_block *nb)
static irqreturn_t l2_int_handler(int irq, void *device)
{
- unsigned int regval, add_h, add_l;
+ unsigned int add_h, add_l;
if (irq == g_irq[DIR_CORR]) {
add_h = readl(l2_base + SIFIVE_L2_DIRECCFIX_HIGH);
add_l = readl(l2_base + SIFIVE_L2_DIRECCFIX_LOW);
pr_err("L2CACHE: DirError @ 0x%08X.%08X\n", add_h, add_l);
- regval = readl(l2_base + SIFIVE_L2_DIRECCFIX_COUNT);
+ readl(l2_base + SIFIVE_L2_DIRECCFIX_COUNT);
atomic_notifier_call_chain(_err_chain, SIFIVE_L2_ERR_TYPE_CE,
"DirECCFix");
}
@@ -123,7 +123,7 @@ static irqreturn_t l2_int_handler(int irq, void *device)
add_h = readl(l2_base + SIFIVE_L2_DATECCFIX_HIGH);
add_l = readl(l2_base + SIFIVE_L2_DATECCFIX_LOW);
pr_err("L2CACHE: DataError @ 0x%08X.%08X\n", add_h, add_l);
- regval = readl(l2_base + SIFIVE_L2_DATECCFIX_COUNT);
+ readl(l2_base + SIFIVE_L2_DATECCFIX_COUNT);
atomic_notifier_call_chain(_err_chain, SIFIVE_L2_ERR_TYPE_CE,
"DatECCFix");
}
@@ -131,7 +131,7 @@ static irqreturn_t l2_int_handler(int irq, void *device)
add_h = readl(l2_base + SIFIVE_L2_DATECCFAIL_HIGH);
add_l = readl(l2_base + SIFIVE_L2_DATECCFAIL_LOW);
pr_err("L2CACHE: DataFail @ 0x%08X.%08X\n", add_h, add_l);
- regval = readl(l2_base + SIFIVE_L2_DATECCFAIL_COUNT);
+ readl(l2_base + SIFIVE_L2_DATECCFAIL_COUNT);
atomic_notifier_call_chain(_err_chain, SIFIVE_L2_ERR_TYPE_UE,
"DatECCFail");
}
--
1.9.1
[PATCH] riscv: dts: Re-organize the DT nodes
As per the convention for any SOC device with external connection,
define only device DT node in SOC DTSi file with status = "disabled"
and enable device in Board DTS file with status = "okay"
Reported-by: Anup Patel
Signed-off-by: Yash Shah
---
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 6 ++
arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 13 +
2 files changed, 19 insertions(+)
diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
index 4e8fbde..cc73522 100644
--- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
+++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
@@ -177,6 +177,7 @@
interrupt-parent = <>;
interrupts = <4>;
clocks = < PRCI_CLK_TLCLK>;
+ status = "disabled";
};
uart1: serial@10011000 {
compatible = "sifive,fu540-c000-uart", "sifive,uart0";
@@ -184,6 +185,7 @@
interrupt-parent = <>;
interrupts = <5>;
clocks = < PRCI_CLK_TLCLK>;
+ status = "disabled";
};
i2c0: i2c@1003 {
compatible = "sifive,fu540-c000-i2c", "sifive,i2c0";
@@ -195,6 +197,7 @@
reg-io-width = <1>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
};
qspi0: spi@1004 {
compatible = "sifive,fu540-c000-spi", "sifive,spi0";
@@ -205,6 +208,7 @@
clocks = < PRCI_CLK_TLCLK>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
};
qspi1: spi@10041000 {
compatible = "sifive,fu540-c000-spi", "sifive,spi0";
@@ -215,6 +219,7 @@
clocks = < PRCI_CLK_TLCLK>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
};
qspi2: spi@1005 {
compatible = "sifive,fu540-c000-spi", "sifive,spi0";
@@ -224,6 +229,7 @@
clocks = < PRCI_CLK_TLCLK>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
};
};
};
diff --git a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
index 4da8870..0b55c53 100644
--- a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
+++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
@@ -42,7 +42,20 @@
};
};
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
{
+ status = "okay";
flash@0 {
compatible = "issi,is25wp256", "jedec,spi-nor";
reg = <0>;
--
1.9.1
Re: [PATCH] riscv: dts: Re-organize SPI DT nodes
On Tue, Jun 25, 2019 at 2:53 AM Paul Walmsley wrote: > > On Mon, 24 Jun 2019, Yash Shah wrote: > > > As per the General convention, define only device DT node in SOC DTSi > > file with status = "disabled" and enable device in Board DTS file with > > status = "okay" > > > > Reported-by: Anup Patel > > Signed-off-by: Yash Shah > > This is a good start, but should also cover the other I/O devices in the > chip DT file. The mandatory internal devices, like the PRCI and PLIC, can > stay the way they are. Ok, I will send another patch which will cover the other I/O devices as well. Please ignore this patch. - Yash > > > - Paul
[PATCH] riscv: dts: Re-organize SPI DT nodes
As per the General convention, define only device DT node in SOC DTSi
file with status = "disabled" and enable device in Board DTS file with
status = "okay"
Reported-by: Anup Patel
Signed-off-by: Yash Shah
---
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 3 +++
arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 1 +
2 files changed, 4 insertions(+)
diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
index 4e8fbde..270f6e8 100644
--- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
+++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
@@ -203,6 +203,7 @@
interrupt-parent = <>;
interrupts = <51>;
clocks = < PRCI_CLK_TLCLK>;
+ status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
@@ -213,6 +214,7 @@
interrupt-parent = <>;
interrupts = <52>;
clocks = < PRCI_CLK_TLCLK>;
+ status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
@@ -222,6 +224,7 @@
interrupt-parent = <>;
interrupts = <6>;
clocks = < PRCI_CLK_TLCLK>;
+ status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
diff --git a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
index 4da8870..73e2af6 100644
--- a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
+++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
@@ -43,6 +43,7 @@
};
{
+ status = "okay";
flash@0 {
compatible = "issi,is25wp256", "jedec,spi-nor";
reg = <0>;
--
1.9.1
[PATCH v2] riscv: dts: Add DT node for SiFive FU540 Ethernet controller driver
DT node for SiFive FU540-C000 GEMGXL Ethernet controller driver added
Signed-off-by: Yash Shah
---
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 16
arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 9 +
2 files changed, 25 insertions(+)
diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
index 4e8fbde..c53b4ea 100644
--- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
+++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
@@ -225,5 +225,21 @@
#address-cells = <1>;
#size-cells = <0>;
};
+ eth0: ethernet@1009 {
+ compatible = "sifive,fu540-macb";
+ interrupt-parent = <>;
+ interrupts = <53>;
+ reg = <0x0 0x1009 0x0 0x2000
+ 0x0 0x100a 0x0 0x1000>;
+ reg-names = "control";
+ status = "disabled";
+ local-mac-address = [00 00 00 00 00 00];
+ clock-names = "pclk", "hclk";
+ clocks = < PRCI_CLK_GEMGXLPLL>,
+< PRCI_CLK_GEMGXLPLL>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
};
};
diff --git a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
index 4da8870..d783bf2 100644
--- a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
+++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
@@ -63,3 +63,12 @@
disable-wp;
};
};
+
+ {
+ status = "okay";
+ phy-mode = "gmii";
+ phy-handle = <>;
+ phy1: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
--
1.9.1
[PATCH v2] DT node for SiFive FU540 Ethernet Controller driver
This patch-set is based on 'riscv-for-v5.2/fixes-rc6' tag of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git Tested on HiFive Unleashed board with additional patches required for testing can be found at dev/yashs/ethernet_dt_v2 branch of: https://github.com/yashshah7/riscv-linux.git Change history: v2: - Set "status = disabled" in DTSI file and enable it in Board DTS file - Move PHY related nodes into board DTS file Yash Shah (1): riscv: dts: Add DT node for SiFive FU540 Ethernet controller driver arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 16 arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 9 + 2 files changed, 25 insertions(+) -- 1.9.1
Re: [PATCH] riscv: dts: Add DT node for SiFive FU540 Ethernet controller driver
On Fri, Jun 21, 2019 at 2:31 PM Anup Patel wrote:
>
> On Fri, Jun 21, 2019 at 11:40 AM Yash Shah wrote:
> >
> > DT node for SiFive FU540-C000 GEMGXL Ethernet controller driver added
> >
> > Signed-off-by: Yash Shah
> > ---
> > arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 20
> > 1 file changed, 20 insertions(+)
> >
> > diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
> > b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
> > index 4e8fbde..584e737 100644
> > --- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
> > +++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
> > @@ -225,5 +225,25 @@
> > #address-cells = <1>;
> > #size-cells = <0>;
> > };
> > + eth0: ethernet@1009 {
> > + compatible = "sifive,fu540-macb";
> > + interrupt-parent = <>;
> > + interrupts = <53>;
> > + reg = <0x0 0x1009 0x0 0x2000
> > + 0x0 0x100a 0x0 0x1000>;
> > + reg-names = "control";
> > + local-mac-address = [00 00 00 00 00 00];
> > + phy-mode = "gmii";
> > + phy-handle = <>;
> > + clock-names = "pclk", "hclk";
> > + clocks = < PRCI_CLK_GEMGXLPLL>,
> > +< PRCI_CLK_GEMGXLPLL>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
>
> Have status = "disabled"; here and have
> status = "okay" in board DTS file.
>
> General convention for any SOC device with external
> connection (e.g. ethernet, SPI, SDHC, SATA, PCI, etc)
> is:
>
> 1. Define only device DT node in SOC DTSi file with
> status = "disabled"
> 2. Enable device in Board DTS file with
> status = "okay"
> 3. Define PHY or external PIN connection details
> in Board DTS file
>
> > + phy1: ethernet-phy@0 {
> > + reg = <0>;
> > + };
>
> The PHY DT node should be in Board DTS file.
Will move all PHY related nodes in board DTS file.
>
> Of course, same comments apply to SPI DT nodes as well
> but I missed reviewing those DT nodes. You can send separate
> DT patch to re-organize SPI DT nodes.
Sure, will send a separate patch for SPI DT nodes as well.
Thanks for your comments.
- Yash
>
> Regards,
> Anup
[PATCH] DT node for SiFive FU540 Ethernet Controller driver
This patch-set is based on 'riscv-for-v5.2/fixes-rc6' tag of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git Tested on HiFive Unleashed board with additional patches required for testing can be found at dev/yashs/ethernet_dt branch of: https://github.com/yashshah7/riscv-linux.git Yash Shah (1): riscv: dts: Add DT node for SiFive FU540 Ethernet controller driver arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 20 1 file changed, 20 insertions(+) -- 1.9.1
[PATCH] riscv: dts: Add DT node for SiFive FU540 Ethernet controller driver
DT node for SiFive FU540-C000 GEMGXL Ethernet controller driver added
Signed-off-by: Yash Shah
---
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 20
1 file changed, 20 insertions(+)
diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
index 4e8fbde..584e737 100644
--- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
+++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
@@ -225,5 +225,25 @@
#address-cells = <1>;
#size-cells = <0>;
};
+ eth0: ethernet@1009 {
+ compatible = "sifive,fu540-macb";
+ interrupt-parent = <>;
+ interrupts = <53>;
+ reg = <0x0 0x1009 0x0 0x2000
+ 0x0 0x100a 0x0 0x1000>;
+ reg-names = "control";
+ local-mac-address = [00 00 00 00 00 00];
+ phy-mode = "gmii";
+ phy-handle = <>;
+ clock-names = "pclk", "hclk";
+ clocks = < PRCI_CLK_GEMGXLPLL>,
+< PRCI_CLK_GEMGXLPLL>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy1: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
+
};
};
--
1.9.1
[PATCH v3 2/2] macb: Add support for SiFive FU540-C000
The management IP block is tightly coupled with the Cadence MACB IP
block on the FU540, and manages many of the boundary signals from the
MACB IP. This patch only controls the tx_clk input signal to the MACB
IP. Future patches may add support for monitoring or controlling other
IP boundary signals.
Signed-off-by: Yash Shah
---
drivers/net/ethernet/cadence/macb_main.c | 123 +++
1 file changed, 123 insertions(+)
diff --git a/drivers/net/ethernet/cadence/macb_main.c
b/drivers/net/ethernet/cadence/macb_main.c
index c049410..15d0737 100644
--- a/drivers/net/ethernet/cadence/macb_main.c
+++ b/drivers/net/ethernet/cadence/macb_main.c
@@ -10,6 +10,7 @@
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include
+#include
#include
#include
#include
@@ -40,6 +41,15 @@
#include
#include "macb.h"
+/* This structure is only used for MACB on SiFive FU540 devices */
+struct sifive_fu540_macb_mgmt {
+ void __iomem *reg;
+ unsigned long rate;
+ struct clk_hw hw;
+};
+
+static struct sifive_fu540_macb_mgmt *mgmt;
+
#define MACB_RX_BUFFER_SIZE128
#define RX_BUFFER_MULTIPLE 64 /* bytes */
@@ -3903,6 +3913,116 @@ static int at91ether_init(struct platform_device *pdev)
return 0;
}
+static unsigned long fu540_macb_tx_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ return mgmt->rate;
+}
+
+static long fu540_macb_tx_round_rate(struct clk_hw *hw, unsigned long rate,
+unsigned long *parent_rate)
+{
+ if (WARN_ON(rate < 250))
+ return 250;
+ else if (rate == 250)
+ return 250;
+ else if (WARN_ON(rate < 1375))
+ return 250;
+ else if (WARN_ON(rate < 2500))
+ return 2500;
+ else if (rate == 2500)
+ return 2500;
+ else if (WARN_ON(rate < 7500))
+ return 2500;
+ else if (WARN_ON(rate < 12500))
+ return 12500;
+ else if (rate == 12500)
+ return 12500;
+
+ WARN_ON(rate > 12500);
+
+ return 12500;
+}
+
+static int fu540_macb_tx_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ rate = fu540_macb_tx_round_rate(hw, rate, _rate);
+ if (rate != 12500)
+ iowrite32(1, mgmt->reg);
+ else
+ iowrite32(0, mgmt->reg);
+ mgmt->rate = rate;
+
+ return 0;
+}
+
+static const struct clk_ops fu540_c000_ops = {
+ .recalc_rate = fu540_macb_tx_recalc_rate,
+ .round_rate = fu540_macb_tx_round_rate,
+ .set_rate = fu540_macb_tx_set_rate,
+};
+
+static int fu540_c000_clk_init(struct platform_device *pdev, struct clk **pclk,
+ struct clk **hclk, struct clk **tx_clk,
+ struct clk **rx_clk, struct clk **tsu_clk)
+{
+ struct clk_init_data init;
+ int err = 0;
+
+ err = macb_clk_init(pdev, pclk, hclk, tx_clk, rx_clk, tsu_clk);
+ if (err)
+ return err;
+
+ mgmt = devm_kzalloc(>dev, sizeof(*mgmt), GFP_KERNEL);
+ if (!mgmt)
+ return -ENOMEM;
+
+ init.name = "sifive-gemgxl-mgmt";
+ init.ops = _c000_ops;
+ init.flags = 0;
+ init.num_parents = 0;
+
+ mgmt->rate = 0;
+ mgmt->hw.init =
+
+ *tx_clk = clk_register(NULL, >hw);
+ if (IS_ERR(*tx_clk))
+ return PTR_ERR(*tx_clk);
+
+ err = clk_prepare_enable(*tx_clk);
+ if (err)
+ dev_err(>dev, "failed to enable tx_clk (%u)\n", err);
+ else
+ dev_info(>dev, "Registered clk switch '%s'\n", init.name);
+
+ return 0;
+}
+
+static int fu540_c000_init(struct platform_device *pdev)
+{
+ struct resource *res;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ if (!res)
+ return -ENODEV;
+
+ mgmt->reg = ioremap(res->start, resource_size(res));
+ if (!mgmt->reg)
+ return -ENOMEM;
+
+ return macb_init(pdev);
+}
+
+static const struct macb_config fu540_c000_config = {
+ .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO |
+ MACB_CAPS_GEM_HAS_PTP,
+ .dma_burst_length = 16,
+ .clk_init = fu540_c000_clk_init,
+ .init = fu540_c000_init,
+ .jumbo_max_len = 10240,
+};
+
static const struct macb_config at91sam9260_config = {
.caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
.clk_init = macb_clk_init,
@@ -3992,6 +4112,7 @@ static int at91ether_init(struct platform_device *pdev)
{ .compatible = "cdns,emac", .data = _config },
{ .compatible = "cdns,zynqmp
[PATCH v3 0/2] Add macb support for SiFive FU540-C000
On FU540, the management IP block is tightly coupled with the Cadence MACB IP block. It manages many of the boundary signals from the MACB IP This patchset controls the tx_clk input signal to the MACB IP. It switches between the local TX clock (125MHz) and PHY TX clocks. This is necessary to toggle between 1Gb and 100/10Mb speeds. Future patches may add support for monitoring or controlling other IP boundary signals. This patchset is mostly based on work done by Wesley Terpstra This patchset is based on Linux v5.2-rc1 and tested on HiFive Unleashed board with additional board related patches needed for testing can be found at dev/yashs/ethernet_v3 branch of: https://github.com/yashshah7/riscv-linux.git Change History: V3: - Revert "MACB_SIFIVE_FU540" config changes in Kconfig and driver code. The driver does not depend on SiFive GPIO driver. V2: - Change compatible string from "cdns,fu540-macb" to "sifive,fu540-macb" - Add "MACB_SIFIVE_FU540" in Kconfig to support SiFive FU540 in macb driver. This is needed because on FU540, the macb driver depends on SiFive GPIO driver. - Avoid writing the result of a comparison to a register. - Fix the issue of probe fail on reloading the module reported by: Andreas Schwab Yash Shah (2): macb: bindings doc: add sifive fu540-c000 binding macb: Add support for SiFive FU540-C000 Documentation/devicetree/bindings/net/macb.txt | 3 + drivers/net/ethernet/cadence/macb_main.c | 123 + 2 files changed, 126 insertions(+) -- 1.9.1
[PATCH v3 1/2] macb: bindings doc: add sifive fu540-c000 binding
Add the compatibility string documentation for SiFive FU540-C interface. On the FU540, this driver also needs to read and write registers in a management IP block that monitors or drives boundary signals for the GEMGXL IP block that are not directly mapped to GEMGXL registers. Therefore, add additional range to "reg" property for SiFive GEMGXL management IP registers. Signed-off-by: Yash Shah Reviewed-by: Paul Walmsley --- Documentation/devicetree/bindings/net/macb.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/net/macb.txt b/Documentation/devicetree/bindings/net/macb.txt index 9c5e944..63c73fa 100644 --- a/Documentation/devicetree/bindings/net/macb.txt +++ b/Documentation/devicetree/bindings/net/macb.txt @@ -15,8 +15,11 @@ Required properties: Use "atmel,sama5d4-gem" for the GEM IP (10/100) available on Atmel sama5d4 SoCs. Use "cdns,zynq-gem" Xilinx Zynq-7xxx SoC. Use "cdns,zynqmp-gem" for Zynq Ultrascale+ MPSoC. + Use "sifive,fu540-macb" for SiFive FU540-C000 SoC. Or the generic form: "cdns,emac". - reg: Address and length of the register set for the device + For "sifive,fu540-macb", second range is required to specify the + address and length of the registers for GEMGXL Management block. - interrupts: Should contain macb interrupt - phy-mode: See ethernet.txt file in the same directory. - clock-names: Tuple listing input clock names. -- 1.9.1
Re: [PATCH v2 2/2] macb: Add support for SiFive FU540-C000
On Mon, Jun 17, 2019 at 9:28 PM Andrew Lunn wrote:
>
> On Mon, Jun 17, 2019 at 09:49:27AM +0530, Yash Shah wrote:
...
> > static const struct macb_config at91sam9260_config = {
> > .caps = MACB_CAPS_USRIO_HAS_CLKEN |
> > MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
> > .clk_init = macb_clk_init,
> > @@ -3992,6 +4112,9 @@ static int at91ether_init(struct platform_device
> > *pdev)
> > { .compatible = "cdns,emac", .data = _config },
> > { .compatible = "cdns,zynqmp-gem", .data = _config},
> > { .compatible = "cdns,zynq-gem", .data = _config },
> > +#ifdef CONFIG_MACB_SIFIVE_FU540
> > + { .compatible = "sifive,fu540-macb", .data = _c000_config },
> > +#endif
>
> This #ifdef should not be needed.
>
> > { /* sentinel */ }
> > };
> > MODULE_DEVICE_TABLE(of, macb_dt_ids);
> > @@ -4199,6 +4322,9 @@ static int macb_probe(struct platform_device *pdev)
> >
> > err_disable_clocks:
> > clk_disable_unprepare(tx_clk);
> > +#ifdef CONFIG_MACB_SIFIVE_FU540
> > + clk_unregister(tx_clk);
> > +#endif
>
> So long as tx_clk is NULL, you can call clk_unregister(). So please
> remove the #ifdef.
>
>
> > clk_disable_unprepare(hclk);
> > clk_disable_unprepare(pclk);
> > clk_disable_unprepare(rx_clk);
> > @@ -4233,6 +4359,9 @@ static int macb_remove(struct platform_device *pdev)
> > pm_runtime_dont_use_autosuspend(>dev);
> > if (!pm_runtime_suspended(>dev)) {
> > clk_disable_unprepare(bp->tx_clk);
> > +#ifdef CONFIG_MACB_SIFIVE_FU540
> > + clk_unregister(bp->tx_clk);
> > +#endif
>
> Same here.
>
> In general try to avoid #ifdef in C code.
Will remove all the #ifdef in v3.
Thanks for your comments.
- Yash
Re: [PATCH v2 0/2] Add macb support for SiFive FU540-C000
On Mon, Jun 17, 2019 at 3:58 PM Paul Walmsley wrote: > > On Mon, 17 Jun 2019, Yash Shah wrote: > > > On Mon, Jun 17, 2019 at 3:28 PM Paul Walmsley > > wrote: > > > > > On Mon, 17 Jun 2019, Andreas Schwab wrote: > > > > > > > On Jun 17 2019, Yash Shah wrote: > > > > > > > > > - Add "MACB_SIFIVE_FU540" in Kconfig to support SiFive FU540 in macb > > > > > driver. This is needed because on FU540, the macb driver depends on > > > > > SiFive GPIO driver. > > > > > > > > This of course requires that the GPIO driver is upstreamed first. > > > > > > What's the impact of enabling CONFIG_MACB_SIFIVE_FU540 when the GPIO > > > driver isn't present? (After modifying the Kconfig "depends" line > > > appropriately.) > > > > > > Looks to me that it shouldn't have an impact unless the DT string is > > > present, and even then, the impact might simply be that the MACB driver > > > may not work? > > > > Yes, there won't be an impact other than MACB driver not working. > > OK. In that case, there doesn't seem much point to adding the Kconfig > option. Could you please post a new version without it? Sure, will do that. > > > In any case, without GPIO driver, PHY won't get reset and the network > > interface won't come up. > > Naturally, in the medium term, we want Linux to handle the reset. But if > there's no GPIO driver present, and the bootloader handles the PHY reset > before the kernel starts, would the network driver work in that case? Yes, if bootloader handles the PHY reset then the network driver will work in that case. I will post a new version without the GPIO driver dependency. > > > - Paul
Re: [PATCH v2 0/2] Add macb support for SiFive FU540-C000
On Mon, Jun 17, 2019 at 3:28 PM Paul Walmsley wrote: > > Hi Yash, > > On Mon, 17 Jun 2019, Andreas Schwab wrote: > > > On Jun 17 2019, Yash Shah wrote: > > > > > - Add "MACB_SIFIVE_FU540" in Kconfig to support SiFive FU540 in macb > > > driver. This is needed because on FU540, the macb driver depends on > > > SiFive GPIO driver. > > > > This of course requires that the GPIO driver is upstreamed first. > > What's the impact of enabling CONFIG_MACB_SIFIVE_FU540 when the GPIO > driver isn't present? (After modifying the Kconfig "depends" line > appropriately.) > > Looks to me that it shouldn't have an impact unless the DT string is > present, and even then, the impact might simply be that the MACB driver > may not work? Yes, there won't be an impact other than MACB driver not working. In any case, without GPIO driver, PHY won't get reset and the network interface won't come up. > > > - Paul
Re: [PATCH v2 0/2] Add macb support for SiFive FU540-C000
On Mon, Jun 17, 2019 at 9:49 AM Yash Shah wrote: > > On FU540, the management IP block is tightly coupled with the Cadence > MACB IP block. It manages many of the boundary signals from the MACB IP > This patchset controls the tx_clk input signal to the MACB IP. It > switches between the local TX clock (125MHz) and PHY TX clocks. This > is necessary to toggle between 1Gb and 100/10Mb speeds. > > Future patches may add support for monitoring or controlling other IP > boundary signals. > > This patchset is mostly based on work done by > Wesley Terpstra > > This patchset is based on Linux v5.2-rc1 and tested on HiFive Unleashed > board with additional board related patches needed for testing can be > found at dev/yashs/ethernet branch of: Correction in branch name: dev/yashs/ethernet_v2 > https://github.com/yashshah7/riscv-linux.git > > Change History: > V2: > - Change compatible string from "cdns,fu540-macb" to "sifive,fu540-macb" > - Add "MACB_SIFIVE_FU540" in Kconfig to support SiFive FU540 in macb > driver. This is needed because on FU540, the macb driver depends on > SiFive GPIO driver. > - Avoid writing the result of a comparison to a register. > - Fix the issue of probe fail on reloading the module reported by: > Andreas Schwab > > Yash Shah (2): > macb: bindings doc: add sifive fu540-c000 binding > macb: Add support for SiFive FU540-C000 > > Documentation/devicetree/bindings/net/macb.txt | 3 + > drivers/net/ethernet/cadence/Kconfig | 6 ++ > drivers/net/ethernet/cadence/macb_main.c | 129 > + > 3 files changed, 138 insertions(+) > > -- > 1.9.1 >
[PATCH v2 2/2] macb: Add support for SiFive FU540-C000
The management IP block is tightly coupled with the Cadence MACB IP
block on the FU540, and manages many of the boundary signals from the
MACB IP. This patch only controls the tx_clk input signal to the MACB
IP. Future patches may add support for monitoring or controlling other
IP boundary signals.
Signed-off-by: Yash Shah
---
drivers/net/ethernet/cadence/Kconfig | 6 ++
drivers/net/ethernet/cadence/macb_main.c | 129 +++
2 files changed, 135 insertions(+)
diff --git a/drivers/net/ethernet/cadence/Kconfig
b/drivers/net/ethernet/cadence/Kconfig
index b998401..d478fae 100644
--- a/drivers/net/ethernet/cadence/Kconfig
+++ b/drivers/net/ethernet/cadence/Kconfig
@@ -48,4 +48,10 @@ config MACB_PCI
To compile this driver as a module, choose M here: the module
will be called macb_pci.
+config MACB_SIFIVE_FU540
+ bool "Cadence MACB/GEM support for SiFive FU540 SoC"
+ depends on MACB && GPIO_SIFIVE
+ help
+ Enable the Cadence MACB/GEM support for SiFive FU540 SoC.
+
endif # NET_VENDOR_CADENCE
diff --git a/drivers/net/ethernet/cadence/macb_main.c
b/drivers/net/ethernet/cadence/macb_main.c
index c049410..275b5e8 100644
--- a/drivers/net/ethernet/cadence/macb_main.c
+++ b/drivers/net/ethernet/cadence/macb_main.c
@@ -10,6 +10,7 @@
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include
+#include
#include
#include
#include
@@ -40,6 +41,15 @@
#include
#include "macb.h"
+/* This structure is only used for MACB on SiFive FU540 devices */
+struct sifive_fu540_macb_mgmt {
+ void __iomem *reg;
+ unsigned long rate;
+ struct clk_hw hw;
+};
+
+static struct sifive_fu540_macb_mgmt *mgmt;
+
#define MACB_RX_BUFFER_SIZE128
#define RX_BUFFER_MULTIPLE 64 /* bytes */
@@ -3903,6 +3913,116 @@ static int at91ether_init(struct platform_device *pdev)
return 0;
}
+static unsigned long fu540_macb_tx_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ return mgmt->rate;
+}
+
+static long fu540_macb_tx_round_rate(struct clk_hw *hw, unsigned long rate,
+unsigned long *parent_rate)
+{
+ if (WARN_ON(rate < 250))
+ return 250;
+ else if (rate == 250)
+ return 250;
+ else if (WARN_ON(rate < 1375))
+ return 250;
+ else if (WARN_ON(rate < 2500))
+ return 2500;
+ else if (rate == 2500)
+ return 2500;
+ else if (WARN_ON(rate < 7500))
+ return 2500;
+ else if (WARN_ON(rate < 12500))
+ return 12500;
+ else if (rate == 12500)
+ return 12500;
+
+ WARN_ON(rate > 12500);
+
+ return 12500;
+}
+
+static int fu540_macb_tx_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ rate = fu540_macb_tx_round_rate(hw, rate, _rate);
+ if (rate != 12500)
+ iowrite32(1, mgmt->reg);
+ else
+ iowrite32(0, mgmt->reg);
+ mgmt->rate = rate;
+
+ return 0;
+}
+
+static const struct clk_ops fu540_c000_ops = {
+ .recalc_rate = fu540_macb_tx_recalc_rate,
+ .round_rate = fu540_macb_tx_round_rate,
+ .set_rate = fu540_macb_tx_set_rate,
+};
+
+static int fu540_c000_clk_init(struct platform_device *pdev, struct clk **pclk,
+ struct clk **hclk, struct clk **tx_clk,
+ struct clk **rx_clk, struct clk **tsu_clk)
+{
+ struct clk_init_data init;
+ int err = 0;
+
+ err = macb_clk_init(pdev, pclk, hclk, tx_clk, rx_clk, tsu_clk);
+ if (err)
+ return err;
+
+ mgmt = devm_kzalloc(>dev, sizeof(*mgmt), GFP_KERNEL);
+ if (!mgmt)
+ return -ENOMEM;
+
+ init.name = "sifive-gemgxl-mgmt";
+ init.ops = _c000_ops;
+ init.flags = 0;
+ init.num_parents = 0;
+
+ mgmt->rate = 0;
+ mgmt->hw.init =
+
+ *tx_clk = clk_register(NULL, >hw);
+ if (IS_ERR(*tx_clk))
+ return PTR_ERR(*tx_clk);
+
+ err = clk_prepare_enable(*tx_clk);
+ if (err)
+ dev_err(>dev, "failed to enable tx_clk (%u)\n", err);
+ else
+ dev_info(>dev, "Registered clk switch '%s'\n", init.name);
+
+ return 0;
+}
+
+static int fu540_c000_init(struct platform_device *pdev)
+{
+ struct resource *res;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ if (!res)
+ return -ENODEV;
+
+ mgmt->reg = ioremap(res->start, resource_size(res));
+ if (!mgmt->reg)
+ return -ENOMEM;
+
+ return macb_init(pdev);
+
[PATCH v2 1/2] macb: bindings doc: add sifive fu540-c000 binding
Add the compatibility string documentation for SiFive FU540-C interface. On the FU540, this driver also needs to read and write registers in a management IP block that monitors or drives boundary signals for the GEMGXL IP block that are not directly mapped to GEMGXL registers. Therefore, add additional range to "reg" property for SiFive GEMGXL management IP registers. Signed-off-by: Yash Shah --- Documentation/devicetree/bindings/net/macb.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/net/macb.txt b/Documentation/devicetree/bindings/net/macb.txt index 9c5e944..63c73fa 100644 --- a/Documentation/devicetree/bindings/net/macb.txt +++ b/Documentation/devicetree/bindings/net/macb.txt @@ -15,8 +15,11 @@ Required properties: Use "atmel,sama5d4-gem" for the GEM IP (10/100) available on Atmel sama5d4 SoCs. Use "cdns,zynq-gem" Xilinx Zynq-7xxx SoC. Use "cdns,zynqmp-gem" for Zynq Ultrascale+ MPSoC. + Use "sifive,fu540-macb" for SiFive FU540-C000 SoC. Or the generic form: "cdns,emac". - reg: Address and length of the register set for the device + For "sifive,fu540-macb", second range is required to specify the + address and length of the registers for GEMGXL Management block. - interrupts: Should contain macb interrupt - phy-mode: See ethernet.txt file in the same directory. - clock-names: Tuple listing input clock names. -- 1.9.1
[PATCH v2 0/2] Add macb support for SiFive FU540-C000
On FU540, the management IP block is tightly coupled with the Cadence MACB IP block. It manages many of the boundary signals from the MACB IP This patchset controls the tx_clk input signal to the MACB IP. It switches between the local TX clock (125MHz) and PHY TX clocks. This is necessary to toggle between 1Gb and 100/10Mb speeds. Future patches may add support for monitoring or controlling other IP boundary signals. This patchset is mostly based on work done by Wesley Terpstra This patchset is based on Linux v5.2-rc1 and tested on HiFive Unleashed board with additional board related patches needed for testing can be found at dev/yashs/ethernet branch of: https://github.com/yashshah7/riscv-linux.git Change History: V2: - Change compatible string from "cdns,fu540-macb" to "sifive,fu540-macb" - Add "MACB_SIFIVE_FU540" in Kconfig to support SiFive FU540 in macb driver. This is needed because on FU540, the macb driver depends on SiFive GPIO driver. - Avoid writing the result of a comparison to a register. - Fix the issue of probe fail on reloading the module reported by: Andreas Schwab Yash Shah (2): macb: bindings doc: add sifive fu540-c000 binding macb: Add support for SiFive FU540-C000 Documentation/devicetree/bindings/net/macb.txt | 3 + drivers/net/ethernet/cadence/Kconfig | 6 ++ drivers/net/ethernet/cadence/macb_main.c | 129 + 3 files changed, 138 insertions(+) -- 1.9.1
[PATCH v13 2/2] pwm: sifive: Add a driver for SiFive SoC PWM
Adds a PWM driver for PWM chip present in SiFive's HiFive Unleashed SoC.
Signed-off-by: Wesley W. Terpstra
[Atish: Various fixes and code cleanup]
Signed-off-by: Atish Patra
Signed-off-by: Yash Shah
---
drivers/pwm/Kconfig | 11 ++
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-sifive.c | 339 +++
3 files changed, 351 insertions(+)
create mode 100644 drivers/pwm/pwm-sifive.c
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index 1311b540..f7eacac 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -400,6 +400,17 @@ config PWM_SAMSUNG
To compile this driver as a module, choose M here: the module
will be called pwm-samsung.
+config PWM_SIFIVE
+ tristate "SiFive PWM support"
+ depends on OF
+ depends on COMMON_CLK
+ depends on RISCV || COMPILE_TEST
+ help
+ Generic PWM framework driver for SiFive SoCs.
+
+ To compile this driver as a module, choose M here: the module
+ will be called pwm-sifive.
+
config PWM_SPEAR
tristate "STMicroelectronics SPEAr PWM support"
depends on PLAT_SPEAR
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index c368599..76b555b 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -39,6 +39,7 @@ obj-$(CONFIG_PWM_RCAR)+= pwm-rcar.o
obj-$(CONFIG_PWM_RENESAS_TPU) += pwm-renesas-tpu.o
obj-$(CONFIG_PWM_ROCKCHIP) += pwm-rockchip.o
obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o
+obj-$(CONFIG_PWM_SIFIVE) += pwm-sifive.o
obj-$(CONFIG_PWM_SPEAR)+= pwm-spear.o
obj-$(CONFIG_PWM_STI) += pwm-sti.o
obj-$(CONFIG_PWM_STM32)+= pwm-stm32.o
diff --git a/drivers/pwm/pwm-sifive.c b/drivers/pwm/pwm-sifive.c
new file mode 100644
index 000..a7c107f
--- /dev/null
+++ b/drivers/pwm/pwm-sifive.c
@@ -0,0 +1,339 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017-2018 SiFive
+ * For SiFive's PWM IP block documentation please refer Chapter 14 of
+ * Reference Manual : https://static.dev.sifive.com/FU540-C000-v1.0.pdf
+ *
+ * Limitations:
+ * - When changing both duty cycle and period, we cannot prevent in
+ * software that the output might produce a period with mixed
+ * settings (new period length and old duty cycle).
+ * - The hardware cannot generate a 100% duty cycle.
+ * - The hardware generates only inverted output.
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* Register offsets */
+#define PWM_SIFIVE_PWMCFG 0x0
+#define PWM_SIFIVE_PWMCOUNT0x8
+#define PWM_SIFIVE_PWMS0x10
+#define PWM_SIFIVE_PWMCMP0 0x20
+
+/* PWMCFG fields */
+#define PWM_SIFIVE_PWMCFG_SCALEGENMASK(3, 0)
+#define PWM_SIFIVE_PWMCFG_STICKY BIT(8)
+#define PWM_SIFIVE_PWMCFG_ZERO_CMP BIT(9)
+#define PWM_SIFIVE_PWMCFG_DEGLITCH BIT(10)
+#define PWM_SIFIVE_PWMCFG_EN_ALWAYSBIT(12)
+#define PWM_SIFIVE_PWMCFG_EN_ONCE BIT(13)
+#define PWM_SIFIVE_PWMCFG_CENTER BIT(16)
+#define PWM_SIFIVE_PWMCFG_GANG BIT(24)
+#define PWM_SIFIVE_PWMCFG_IP BIT(28)
+
+/* PWM_SIFIVE_SIZE_PWMCMP is used to calculate offset for pwmcmpX registers */
+#define PWM_SIFIVE_SIZE_PWMCMP 4
+#define PWM_SIFIVE_CMPWIDTH16
+#define PWM_SIFIVE_DEFAULT_PERIOD 1000
+
+struct pwm_sifive_ddata {
+ struct pwm_chip chip;
+ struct mutex lock; /* lock to protect user_count */
+ struct notifier_block notifier;
+ struct clk *clk;
+ void __iomem *regs;
+ unsigned int real_period;
+ unsigned int approx_period;
+ int user_count;
+};
+
+static inline
+struct pwm_sifive_ddata *pwm_sifive_chip_to_ddata(struct pwm_chip *c)
+{
+ return container_of(c, struct pwm_sifive_ddata, chip);
+}
+
+static int pwm_sifive_request(struct pwm_chip *chip, struct pwm_device *pwm)
+{
+ struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
+
+ mutex_lock(>lock);
+ ddata->user_count++;
+ mutex_unlock(>lock);
+
+ return 0;
+}
+
+static void pwm_sifive_free(struct pwm_chip *chip, struct pwm_device *pwm)
+{
+ struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
+
+ mutex_lock(>lock);
+ ddata->user_count--;
+ mutex_unlock(>lock);
+}
+
+static void pwm_sifive_update_clock(struct pwm_sifive_ddata *ddata,
+ unsigned long rate)
+{
+ unsigned long long num;
+ unsigned long scale_pow;
+ int scale;
+ u32 val;
+ /*
+* The PWM unit is used with pwmzerocmp=0, so the only way to modify the
+* period length is using pwmscale which provides the number of bits the
+* counter is shifted before being feed to the comparators. A period
+* lasts (1 << (PWM_SIFIVE_CMPWIDTH + pwmscale)) clock ticks.
+*
[PATCH v13 1/2] pwm: sifive: Add DT documentation for SiFive PWM Controller
DT documentation for PWM controller added.
Signed-off-by: Wesley W. Terpstra
[Atish: Compatible string update]
Signed-off-by: Atish Patra
Signed-off-by: Yash Shah
Reviewed-by: Rob Herring
---
.../devicetree/bindings/pwm/pwm-sifive.txt | 33 ++
1 file changed, 33 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pwm/pwm-sifive.txt
diff --git a/Documentation/devicetree/bindings/pwm/pwm-sifive.txt
b/Documentation/devicetree/bindings/pwm/pwm-sifive.txt
new file mode 100644
index 000..36447e3
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/pwm-sifive.txt
@@ -0,0 +1,33 @@
+SiFive PWM controller
+
+Unlike most other PWM controllers, the SiFive PWM controller currently only
+supports one period for all channels in the PWM. All PWMs need to run at
+the same period. The period also has significant restrictions on the values
+it can achieve, which the driver rounds to the nearest achievable period.
+PWM RTL that corresponds to the IP block version numbers can be found
+here:
+
+https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm
+
+Required properties:
+- compatible: Should be "sifive,-pwm" and "sifive,pwm".
+ Supported compatible strings are: "sifive,fu540-c000-pwm" for the SiFive
+ PWM v0 as integrated onto the SiFive FU540 chip, and "sifive,pwm0" for the
+ SiFive PWM v0 IP block with no chip integration tweaks.
+ Please refer to sifive-blocks-ip-versioning.txt for details.
+- reg: physical base address and length of the controller's registers
+- clocks: Should contain a clock identifier for the PWM's parent clock.
+- #pwm-cells: Should be 3. See pwm.txt in this directory
+ for a description of the cell format.
+- interrupts: one interrupt per PWM channel
+
+Examples:
+
+pwm: pwm@1002 {
+ compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
+ reg = <0x0 0x1002 0x0 0x1000>;
+ clocks = <>;
+ interrupt-parent = <>;
+ interrupts = <42 43 44 45>;
+ #pwm-cells = <3>;
+};
--
1.9.1
[PATCH v13 0/2] PWM support for HiFive Unleashed
This patch series adds a PWM driver and DT documentation for HiFive Unleashed board. The patches are mostly based on Wesley's patch. This patchset is based on Linux v5.2-rc1 and tested on HiFive Unleashed board with additional board related patches needed for testing can be found at dev/yashs/pwm_v13 branch of: https://github.com/yashshah7/riscv-linux.git v13 - Rebased onto Mainline v5.2-rc1 - Correct the order of pwmchip_remove() after clk_disable() in .remove() v12 - Rebased onto Mainline v5.1 v11 - Change naming convention for pwm_device and pwm_sifive_ddata pointers - Assign of_pwm_xlate_with_flag() to of_xlate func ptr since this driver use three pwm-cells (Issue reported by Andreas Schwab - Other minor fixes v10 - Use DIV_ROUND_CLOSEST_ULL instead of div_u64_round - Change 'num' defination to u64 bit (in pwm_sifive_apply). - Remove the usage of pwm_get_state() v9 - Use appropriate bitfield macros - Add approx_period in pwm_sifive_ddata struct and related changes - Correct the eqn for calculation of frac (in pwm_sifive_apply) - Other minor fixes v8 - Typo corrections - Remove active_user and related code - Do not clear PWM_SIFIVE_PWMCFG_EN_ALWAYS - Other minor fixes v7 - Modify description of compatible property in DT documentation - Use mutex locks at appropriate places - Fix all bad line breaks - Allow enabling/disabling PWM only when the user is the only active user - Remove Deglitch logic - Other minor fixes v6 - Remove the global property 'sifive,period-ns' - Implement free and request callbacks to maintain user counts. - Add user_count member to struct pwm_sifive_ddata - Allow period change only if user_count is one - Add pwm_sifive_enable function to enable/disable PWM - Change calculation logic of frac (in pwm_sifive_apply) - Remove state correction - Remove pwm_sifive_xlate function - Clock to be enabled only when PWM is enabled - Other minor fixes v5 - Correct the order of compatible string properties - PWM state correction to be done always - Other minor fixes based upon feedback on v4 v4 - Rename macros with appropriate names - Remove unused macros - Rename struct sifive_pwm_device to struct pwm_sifive_ddata - Rename function prefix as per driver name - Other minor fixes based upon feedback on v3 v3 - Add a link to the reference manaul - Use appropriate apis for division operation - Add check for polarity - Enable clk before calling clk_get_rate - Other minor fixes based upon feedback on v2 V2 changed from V1: - Remove inclusion of dt-bindings/pwm/pwm.h - Remove artificial alignments - Replace ioread32/iowrite32 with readl/writel - Remove camelcase - Change dev_info to dev_dbg for unnecessary log - Correct typo in driver name - Remove use of of_match_ptr macro - Update the DT compatible strings and Add reference to a common versioning document Yash Shah (2): pwm: sifive: Add DT documentation for SiFive PWM Controller pwm: sifive: Add a driver for SiFive SoC PWM .../devicetree/bindings/pwm/pwm-sifive.txt | 33 ++ drivers/pwm/Kconfig| 11 + drivers/pwm/Makefile | 1 + drivers/pwm/pwm-sifive.c | 339 + 4 files changed, 384 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/pwm-sifive.txt create mode 100644 drivers/pwm/pwm-sifive.c -- 1.9.1
Re: [PATCH 0/2] net: macb: Add support for SiFive FU540-C000
On Mon, May 27, 2019 at 1:34 PM Andreas Schwab wrote: > > On Mai 24 2019, Yash Shah wrote: > > > Hi Andreas, > > > > On Thu, May 23, 2019 at 6:19 PM Andreas Schwab wrote: > >> > >> On Mai 23 2019, Yash Shah wrote: > >> > >> > On FU540, the management IP block is tightly coupled with the Cadence > >> > MACB IP block. It manages many of the boundary signals from the MACB IP > >> > This patchset controls the tx_clk input signal to the MACB IP. It > >> > switches between the local TX clock (125MHz) and PHY TX clocks. This > >> > is necessary to toggle between 1Gb and 100/10Mb speeds. > >> > >> Doesn't work for me: > >> > >> [ 365.842801] macb: probe of 1009.ethernet failed with error -17 > >> > > > > Make sure you have applied all the patches needed for testing found at > > dev/yashs/ethernet branch of: > > Nope, try reloading the module. Yes, I could see the error on reloading the module. Thanks for the catch. I will fix this in the next version of this patch. - Yash
Re: [PATCH 1/2] net/macb: bindings doc: add sifive fu540-c000 binding
On Fri, May 24, 2019 at 2:20 AM Rob Herring wrote:
>
> On Thu, May 23, 2019 at 6:46 AM Yash Shah wrote:
> >
> > Add the compatibility string documentation for SiFive FU540-C
> > interface.
> > On the FU540, this driver also needs to read and write registers in a
> > management IP block that monitors or drives boundary signals for the
> > GEMGXL IP block that are not directly mapped to GEMGXL registers.
> > Therefore, add additional range to "reg" property for SiFive GEMGXL
> > management IP registers.
> >
> > Signed-off-by: Yash Shah
> > ---
> > Documentation/devicetree/bindings/net/macb.txt | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/net/macb.txt
> > b/Documentation/devicetree/bindings/net/macb.txt
> > index 9c5e944..91a2a66 100644
> > --- a/Documentation/devicetree/bindings/net/macb.txt
> > +++ b/Documentation/devicetree/bindings/net/macb.txt
> > @@ -4,6 +4,7 @@ Required properties:
> > - compatible: Should be "cdns,[-]{macb|gem}"
> >Use "cdns,at91rm9200-emac" Atmel at91rm9200 SoC.
> >Use "cdns,at91sam9260-macb" for Atmel at91sam9 SoCs.
> > + Use "cdns,fu540-macb" for SiFive FU540-C000 SoC.
>
> This pattern that Atmel started isn't really correct. The vendor
> prefix here should be sifive. 'cdns' would be appropriate for a
> fallback.
Ok sure. WIll change it to "sifive,fu540-macb"
Thanks for your comment.
- Yash
Re: [PATCH 0/2] net: macb: Add support for SiFive FU540-C000
On Thu, May 23, 2019 at 9:58 PM David Miller wrote: > > > Please be consistent in your subsystem prefixes used in your Subject lines. > You use "net: macb:" then "net/macb:" Really, plain "macb: " is sufficient. Sure, Will take care of this in the next revision of this patch. Thanks for your comment. - Yash
Re: [PATCH 2/2] net: macb: Add support for SiFive FU540-C000
On Thu, May 23, 2019 at 8:24 PM Andrew Lunn wrote:
>
> > +static int fu540_macb_tx_set_rate(struct clk_hw *hw, unsigned long rate,
> > + unsigned long parent_rate)
> > +{
> > + rate = fu540_macb_tx_round_rate(hw, rate, _rate);
> > + iowrite32(rate != 12500, mgmt->reg);
>
> That looks odd. Writing the result of a comparison to a register?
The idea was to write "1" to the register if the value of rate is
anything else than 12500.
To make it easier to read, I will change this to below:
- iowrite32(rate != 12500, mgmt->reg);
+ if (rate != 12500)
+ iowrite32(1, mgmt->reg);
+ else
+ iowrite32(0, mgmt->reg);
Hope that's fine. Thanks for your comment
- Yash
>
> Andrew
>
> ___
> linux-riscv mailing list
> linux-ri...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
Re: [PATCH 0/2] net: macb: Add support for SiFive FU540-C000
Hi Andreas, On Thu, May 23, 2019 at 6:19 PM Andreas Schwab wrote: > > On Mai 23 2019, Yash Shah wrote: > > > On FU540, the management IP block is tightly coupled with the Cadence > > MACB IP block. It manages many of the boundary signals from the MACB IP > > This patchset controls the tx_clk input signal to the MACB IP. It > > switches between the local TX clock (125MHz) and PHY TX clocks. This > > is necessary to toggle between 1Gb and 100/10Mb speeds. > > Doesn't work for me: > > [ 365.842801] macb: probe of 1009.ethernet failed with error -17 > Make sure you have applied all the patches needed for testing found at dev/yashs/ethernet branch of: https://github.com/yashshah7/riscv-linux.git In addition to that, make sure in your kernel config GPIO_SIFIVE=y In v2 of this patch, I will add this select GPIO_SIFIVE config in the Cadence Kconfig file. - Yash
[PATCH 2/2] net: macb: Add support for SiFive FU540-C000
The management IP block is tightly coupled with the Cadence MACB IP
block on the FU540, and manages many of the boundary signals from the
MACB IP. This patch only controls the tx_clk input signal to the MACB
IP. Future patches may add support for monitoring or controlling other
IP boundary signals.
Signed-off-by: Yash Shah
---
drivers/net/ethernet/cadence/macb_main.c | 118 +++
1 file changed, 118 insertions(+)
diff --git a/drivers/net/ethernet/cadence/macb_main.c
b/drivers/net/ethernet/cadence/macb_main.c
index c049410..a9e5227 100644
--- a/drivers/net/ethernet/cadence/macb_main.c
+++ b/drivers/net/ethernet/cadence/macb_main.c
@@ -10,6 +10,7 @@
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include
+#include
#include
#include
#include
@@ -40,6 +41,15 @@
#include
#include "macb.h"
+/* This structure is only used for MACB on SiFive FU540 devices */
+struct sifive_fu540_macb_mgmt {
+ void __iomem *reg;
+ unsigned long rate;
+ struct clk_hw hw;
+};
+
+static struct sifive_fu540_macb_mgmt *mgmt;
+
#define MACB_RX_BUFFER_SIZE128
#define RX_BUFFER_MULTIPLE 64 /* bytes */
@@ -3903,6 +3913,113 @@ static int at91ether_init(struct platform_device *pdev)
return 0;
}
+static unsigned long fu540_macb_tx_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ return mgmt->rate;
+}
+
+static long fu540_macb_tx_round_rate(struct clk_hw *hw, unsigned long rate,
+unsigned long *parent_rate)
+{
+ if (WARN_ON(rate < 250))
+ return 250;
+ else if (rate == 250)
+ return 250;
+ else if (WARN_ON(rate < 1375))
+ return 250;
+ else if (WARN_ON(rate < 2500))
+ return 2500;
+ else if (rate == 2500)
+ return 2500;
+ else if (WARN_ON(rate < 7500))
+ return 2500;
+ else if (WARN_ON(rate < 12500))
+ return 12500;
+ else if (rate == 12500)
+ return 12500;
+
+ WARN_ON(rate > 12500);
+
+ return 12500;
+}
+
+static int fu540_macb_tx_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ rate = fu540_macb_tx_round_rate(hw, rate, _rate);
+ iowrite32(rate != 12500, mgmt->reg);
+ mgmt->rate = rate;
+
+ return 0;
+}
+
+static const struct clk_ops fu540_c000_ops = {
+ .recalc_rate = fu540_macb_tx_recalc_rate,
+ .round_rate = fu540_macb_tx_round_rate,
+ .set_rate = fu540_macb_tx_set_rate,
+};
+
+static int fu540_c000_clk_init(struct platform_device *pdev, struct clk **pclk,
+ struct clk **hclk, struct clk **tx_clk,
+ struct clk **rx_clk, struct clk **tsu_clk)
+{
+ struct clk_init_data init;
+ int err = 0;
+
+ err = macb_clk_init(pdev, pclk, hclk, tx_clk, rx_clk, tsu_clk);
+ if (err)
+ return err;
+
+ mgmt = devm_kzalloc(>dev, sizeof(*mgmt), GFP_KERNEL);
+ if (!mgmt)
+ return -ENOMEM;
+
+ init.name = "sifive-gemgxl-mgmt";
+ init.ops = _c000_ops;
+ init.flags = 0;
+ init.num_parents = 0;
+
+ mgmt->rate = 0;
+ mgmt->hw.init =
+
+ *tx_clk = clk_register(NULL, >hw);
+ if (IS_ERR(*tx_clk))
+ return PTR_ERR(*tx_clk);
+
+ err = clk_prepare_enable(*tx_clk);
+ if (err)
+ dev_err(>dev, "failed to enable tx_clk (%u)\n", err);
+ else
+ dev_info(>dev, "Registered clk switch '%s'\n", init.name);
+
+ return 0;
+}
+
+static int fu540_c000_init(struct platform_device *pdev)
+{
+ struct resource *res;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ if (!res)
+ return -ENODEV;
+
+ mgmt->reg = ioremap(res->start, resource_size(res));
+ if (!mgmt->reg)
+ return -ENOMEM;
+
+ return macb_init(pdev);
+}
+
+static const struct macb_config fu540_c000_config = {
+ .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO |
+ MACB_CAPS_GEM_HAS_PTP,
+ .dma_burst_length = 16,
+ .clk_init = fu540_c000_clk_init,
+ .init = fu540_c000_init,
+ .jumbo_max_len = 10240,
+};
+
static const struct macb_config at91sam9260_config = {
.caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
.clk_init = macb_clk_init,
@@ -3980,6 +4097,7 @@ static int at91ether_init(struct platform_device *pdev)
{ .compatible = "cdns,at32ap7000-macb" },
{ .compatible = "cdns,at91sam9260-macb", .data = _config },
{ .compatible = "cdns,mac
[PATCH 1/2] net/macb: bindings doc: add sifive fu540-c000 binding
Add the compatibility string documentation for SiFive FU540-C
interface.
On the FU540, this driver also needs to read and write registers in a
management IP block that monitors or drives boundary signals for the
GEMGXL IP block that are not directly mapped to GEMGXL registers.
Therefore, add additional range to "reg" property for SiFive GEMGXL
management IP registers.
Signed-off-by: Yash Shah
---
Documentation/devicetree/bindings/net/macb.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/macb.txt
b/Documentation/devicetree/bindings/net/macb.txt
index 9c5e944..91a2a66 100644
--- a/Documentation/devicetree/bindings/net/macb.txt
+++ b/Documentation/devicetree/bindings/net/macb.txt
@@ -4,6 +4,7 @@ Required properties:
- compatible: Should be "cdns,[-]{macb|gem}"
Use "cdns,at91rm9200-emac" Atmel at91rm9200 SoC.
Use "cdns,at91sam9260-macb" for Atmel at91sam9 SoCs.
+ Use "cdns,fu540-macb" for SiFive FU540-C000 SoC.
Use "cdns,sam9x60-macb" for Microchip sam9x60 SoC.
Use "cdns,np4-macb" for NP4 SoC devices.
Use "cdns,at32ap7000-macb" for other 10/100 usage or use the generic form:
"cdns,macb".
@@ -17,6 +18,8 @@ Required properties:
Use "cdns,zynqmp-gem" for Zynq Ultrascale+ MPSoC.
Or the generic form: "cdns,emac".
- reg: Address and length of the register set for the device
+ For "cdns,fu540-macb", second range is required to specify the
+ address and length of the registers for GEMGXL Management block.
- interrupts: Should contain macb interrupt
- phy-mode: See ethernet.txt file in the same directory.
- clock-names: Tuple listing input clock names.
--
1.9.1
[PATCH 0/2] net: macb: Add support for SiFive FU540-C000
On FU540, the management IP block is tightly coupled with the Cadence MACB IP block. It manages many of the boundary signals from the MACB IP This patchset controls the tx_clk input signal to the MACB IP. It switches between the local TX clock (125MHz) and PHY TX clocks. This is necessary to toggle between 1Gb and 100/10Mb speeds. Future patches may add support for monitoring or controlling other IP boundary signals. This patchset is mostly based on work done by Wesley Terpstra This patchset is based on Linux v5.2-rc1 and tested on HiFive Unleashed board with additional board related patches needed for testing can be found at dev/yashs/ethernet branch of: https://github.com/yashshah7/riscv-linux.git Yash Shah (2): net/macb: bindings doc: add sifive fu540-c000 binding net: macb: Add support for SiFive FU540-C000 Documentation/devicetree/bindings/net/macb.txt | 3 + drivers/net/ethernet/cadence/macb_main.c | 118 + 2 files changed, 121 insertions(+) -- 1.9.1
Re: [PATCH v2] edac: sifive: Add EDAC platform driver for SiFive SoCs
On Mon, May 6, 2019 at 4:57 PM Yash Shah wrote: > > The initial ver of EDAC driver supports: > - ECC event monitoring and reporting through the EDAC framework for SiFive > L2 cache controller. > > The EDAC driver registers for notifier events from the L2 cache controller > driver (arch/riscv/mm/sifive_l2_cache.c) for L2 ECC events > > Signed-off-by: Yash Shah > Reviewed-by: James Morse > --- > This patch depends on patch > 'RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs' > https://lkml.org/lkml/2019/5/6/255 The prerequisite patch (sifive_l2_cache driver) has been merged into mainline v5.2-rc1 It should be OK to merge this edac driver now. - Yash
[PATCH v12 2/2] pwm: sifive: Add a driver for SiFive SoC PWM
Adds a PWM driver for PWM chip present in SiFive's HiFive Unleashed SoC.
Signed-off-by: Wesley W. Terpstra
[Atish: Various fixes and code cleanup]
Signed-off-by: Atish Patra
Signed-off-by: Yash Shah
---
drivers/pwm/Kconfig | 11 ++
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-sifive.c | 338 +++
3 files changed, 350 insertions(+)
create mode 100644 drivers/pwm/pwm-sifive.c
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index 54f8238..95c1181 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -389,6 +389,17 @@ config PWM_SAMSUNG
To compile this driver as a module, choose M here: the module
will be called pwm-samsung.
+config PWM_SIFIVE
+ tristate "SiFive PWM support"
+ depends on OF
+ depends on COMMON_CLK
+ depends on RISCV || COMPILE_TEST
+ help
+ Generic PWM framework driver for SiFive SoCs.
+
+ To compile this driver as a module, choose M here: the module
+ will be called pwm-sifive.
+
config PWM_SPEAR
tristate "STMicroelectronics SPEAr PWM support"
depends on PLAT_SPEAR
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index 448825e..0da3e99 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -38,6 +38,7 @@ obj-$(CONFIG_PWM_RCAR)+= pwm-rcar.o
obj-$(CONFIG_PWM_RENESAS_TPU) += pwm-renesas-tpu.o
obj-$(CONFIG_PWM_ROCKCHIP) += pwm-rockchip.o
obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o
+obj-$(CONFIG_PWM_SIFIVE) += pwm-sifive.o
obj-$(CONFIG_PWM_SPEAR)+= pwm-spear.o
obj-$(CONFIG_PWM_STI) += pwm-sti.o
obj-$(CONFIG_PWM_STM32)+= pwm-stm32.o
diff --git a/drivers/pwm/pwm-sifive.c b/drivers/pwm/pwm-sifive.c
new file mode 100644
index 000..1921e6ea
--- /dev/null
+++ b/drivers/pwm/pwm-sifive.c
@@ -0,0 +1,338 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017-2018 SiFive
+ * For SiFive's PWM IP block documentation please refer Chapter 14 of
+ * Reference Manual : https://static.dev.sifive.com/FU540-C000-v1.0.pdf
+ *
+ * Limitations:
+ * - When changing both duty cycle and period, we cannot prevent in
+ * software that the output might produce a period with mixed
+ * settings (new period length and old duty cycle).
+ * - The hardware cannot generate a 100% duty cycle.
+ * - The hardware generates only inverted output.
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* Register offsets */
+#define PWM_SIFIVE_PWMCFG 0x0
+#define PWM_SIFIVE_PWMCOUNT0x8
+#define PWM_SIFIVE_PWMS0x10
+#define PWM_SIFIVE_PWMCMP0 0x20
+
+/* PWMCFG fields */
+#define PWM_SIFIVE_PWMCFG_SCALEGENMASK(3, 0)
+#define PWM_SIFIVE_PWMCFG_STICKY BIT(8)
+#define PWM_SIFIVE_PWMCFG_ZERO_CMP BIT(9)
+#define PWM_SIFIVE_PWMCFG_DEGLITCH BIT(10)
+#define PWM_SIFIVE_PWMCFG_EN_ALWAYSBIT(12)
+#define PWM_SIFIVE_PWMCFG_EN_ONCE BIT(13)
+#define PWM_SIFIVE_PWMCFG_CENTER BIT(16)
+#define PWM_SIFIVE_PWMCFG_GANG BIT(24)
+#define PWM_SIFIVE_PWMCFG_IP BIT(28)
+
+/* PWM_SIFIVE_SIZE_PWMCMP is used to calculate offset for pwmcmpX registers */
+#define PWM_SIFIVE_SIZE_PWMCMP 4
+#define PWM_SIFIVE_CMPWIDTH16
+#define PWM_SIFIVE_DEFAULT_PERIOD 1000
+
+struct pwm_sifive_ddata {
+ struct pwm_chip chip;
+ struct mutex lock; /* lock to protect user_count */
+ struct notifier_block notifier;
+ struct clk *clk;
+ void __iomem *regs;
+ unsigned int real_period;
+ unsigned int approx_period;
+ int user_count;
+};
+
+static inline
+struct pwm_sifive_ddata *pwm_sifive_chip_to_ddata(struct pwm_chip *c)
+{
+ return container_of(c, struct pwm_sifive_ddata, chip);
+}
+
+static int pwm_sifive_request(struct pwm_chip *chip, struct pwm_device *pwm)
+{
+ struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
+
+ mutex_lock(>lock);
+ ddata->user_count++;
+ mutex_unlock(>lock);
+
+ return 0;
+}
+
+static void pwm_sifive_free(struct pwm_chip *chip, struct pwm_device *pwm)
+{
+ struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
+
+ mutex_lock(>lock);
+ ddata->user_count--;
+ mutex_unlock(>lock);
+}
+
+static void pwm_sifive_update_clock(struct pwm_sifive_ddata *ddata,
+ unsigned long rate)
+{
+ unsigned long long num;
+ unsigned long scale_pow;
+ int scale;
+ u32 val;
+ /*
+* The PWM unit is used with pwmzerocmp=0, so the only way to modify the
+* period length is using pwmscale which provides the number of bits the
+* counter is shifted before being feed to the comparators. A period
+* lasts (1 << (PWM_SIFIVE_CMPWIDTH + pwmscale)) clock ticks.
+*
[PATCH v12 1/2] pwm: sifive: Add DT documentation for SiFive PWM Controller
DT documentation for PWM controller added.
Signed-off-by: Wesley W. Terpstra
[Atish: Compatible string update]
Signed-off-by: Atish Patra
Signed-off-by: Yash Shah
Reviewed-by: Rob Herring
---
.../devicetree/bindings/pwm/pwm-sifive.txt | 33 ++
1 file changed, 33 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pwm/pwm-sifive.txt
diff --git a/Documentation/devicetree/bindings/pwm/pwm-sifive.txt
b/Documentation/devicetree/bindings/pwm/pwm-sifive.txt
new file mode 100644
index 000..36447e3
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/pwm-sifive.txt
@@ -0,0 +1,33 @@
+SiFive PWM controller
+
+Unlike most other PWM controllers, the SiFive PWM controller currently only
+supports one period for all channels in the PWM. All PWMs need to run at
+the same period. The period also has significant restrictions on the values
+it can achieve, which the driver rounds to the nearest achievable period.
+PWM RTL that corresponds to the IP block version numbers can be found
+here:
+
+https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm
+
+Required properties:
+- compatible: Should be "sifive,-pwm" and "sifive,pwm".
+ Supported compatible strings are: "sifive,fu540-c000-pwm" for the SiFive
+ PWM v0 as integrated onto the SiFive FU540 chip, and "sifive,pwm0" for the
+ SiFive PWM v0 IP block with no chip integration tweaks.
+ Please refer to sifive-blocks-ip-versioning.txt for details.
+- reg: physical base address and length of the controller's registers
+- clocks: Should contain a clock identifier for the PWM's parent clock.
+- #pwm-cells: Should be 3. See pwm.txt in this directory
+ for a description of the cell format.
+- interrupts: one interrupt per PWM channel
+
+Examples:
+
+pwm: pwm@1002 {
+ compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
+ reg = <0x0 0x1002 0x0 0x1000>;
+ clocks = <>;
+ interrupt-parent = <>;
+ interrupts = <42 43 44 45>;
+ #pwm-cells = <3>;
+};
--
1.9.1
[PATCH v12 0/2] PWM support for HiFive Unleashed
This patch series adds a PWM driver and DT documentation for HiFive Unleashed board. The patches are mostly based on Wesley's patch. This patchset is based on Linux v5.1 and tested on HiFive Unleashed board with additional board related patches needed for testing can be found at dev/yashs/pwm branch of: https://github.com/yashshah7/riscv-linux.git v12 - Rebased onto Mainline v5.1 v11 - Change naming convention for pwm_device and pwm_sifive_ddata pointers - Assign of_pwm_xlate_with_flag() to of_xlate func ptr since this driver use three pwm-cells (Issue reported by Andreas Schwab - Other minor fixes v10 - Use DIV_ROUND_CLOSEST_ULL instead of div_u64_round - Change 'num' defination to u64 bit (in pwm_sifive_apply). - Remove the usage of pwm_get_state() v9 - Use appropriate bitfield macros - Add approx_period in pwm_sifive_ddata struct and related changes - Correct the eqn for calculation of frac (in pwm_sifive_apply) - Other minor fixes v8 - Typo corrections - Remove active_user and related code - Do not clear PWM_SIFIVE_PWMCFG_EN_ALWAYS - Other minor fixes v7 - Modify description of compatible property in DT documentation - Use mutex locks at appropriate places - Fix all bad line breaks - Allow enabling/disabling PWM only when the user is the only active user - Remove Deglitch logic - Other minor fixes v6 - Remove the global property 'sifive,period-ns' - Implement free and request callbacks to maintain user counts. - Add user_count member to struct pwm_sifive_ddata - Allow period change only if user_count is one - Add pwm_sifive_enable function to enable/disable PWM - Change calculation logic of frac (in pwm_sifive_apply) - Remove state correction - Remove pwm_sifive_xlate function - Clock to be enabled only when PWM is enabled - Other minor fixes v5 - Correct the order of compatible string properties - PWM state correction to be done always - Other minor fixes based upon feedback on v4 v4 - Rename macros with appropriate names - Remove unused macros - Rename struct sifive_pwm_device to struct pwm_sifive_ddata - Rename function prefix as per driver name - Other minor fixes based upon feedback on v3 v3 - Add a link to the reference manaul - Use appropriate apis for division operation - Add check for polarity - Enable clk before calling clk_get_rate - Other minor fixes based upon feedback on v2 V2 changed from V1: - Remove inclusion of dt-bindings/pwm/pwm.h - Remove artificial alignments - Replace ioread32/iowrite32 with readl/writel - Remove camelcase - Change dev_info to dev_dbg for unnecessary log - Correct typo in driver name - Remove use of of_match_ptr macro - Update the DT compatible strings and Add reference to a common versioning document Yash Shah (2): pwm: sifive: Add DT documentation for SiFive PWM Controller pwm: sifive: Add a driver for SiFive SoC PWM .../devicetree/bindings/pwm/pwm-sifive.txt | 33 ++ drivers/pwm/Kconfig| 11 + drivers/pwm/Makefile | 1 + drivers/pwm/pwm-sifive.c | 338 + 4 files changed, 383 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/pwm-sifive.txt create mode 100644 drivers/pwm/pwm-sifive.c -- 1.9.1
Re: [PATCH v3 2/2] RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs
On Tue, May 7, 2019 at 7:15 PM Andrew F. Davis wrote:
>
> On 5/7/19 2:48 AM, Yash Shah wrote:
> > On Mon, May 6, 2019 at 5:48 PM Andrew F. Davis wrote:
> >>
> >> On 5/6/19 6:48 AM, Yash Shah wrote:
> >>> The driver currently supports only SiFive FU540-C000 platform.
> >>>
> >>> The initial version of L2 cache controller driver includes:
> >>> - Initial configuration reporting at boot up.
> >>> - Support for ECC related functionality.
> >>>
> >>> Signed-off-by: Yash Shah
> >>> ---
> >>> arch/riscv/include/asm/sifive_l2_cache.h | 16 +++
> >>> arch/riscv/mm/Makefile | 1 +
> >>> arch/riscv/mm/sifive_l2_cache.c | 175
> >>> +++
> >>> 3 files changed, 192 insertions(+)
> >>> create mode 100644 arch/riscv/include/asm/sifive_l2_cache.h
> >>> create mode 100644 arch/riscv/mm/sifive_l2_cache.c
> >>>
> >>> diff --git a/arch/riscv/include/asm/sifive_l2_cache.h
> >>> b/arch/riscv/include/asm/sifive_l2_cache.h
> >>> new file mode 100644
> >>> index 000..04f6748
> >>> --- /dev/null
> >>> +++ b/arch/riscv/include/asm/sifive_l2_cache.h
> >>> @@ -0,0 +1,16 @@
> >>> +/* SPDX-License-Identifier: GPL-2.0 */
> >>> +/*
> >>> + * SiFive L2 Cache Controller header file
> >>> + *
> >>> + */
> >>> +
> >>> +#ifndef _ASM_RISCV_SIFIVE_L2_CACHE_H
> >>> +#define _ASM_RISCV_SIFIVE_L2_CACHE_H
> >>> +
> >>> +extern int register_sifive_l2_error_notifier(struct notifier_block *nb);
> >>> +extern int unregister_sifive_l2_error_notifier(struct notifier_block
> >>> *nb);
> >>> +
> >>> +#define SIFIVE_L2_ERR_TYPE_CE 0
> >>> +#define SIFIVE_L2_ERR_TYPE_UE 1
> >>> +
> >>> +#endif /* _ASM_RISCV_SIFIVE_L2_CACHE_H */
> >>> diff --git a/arch/riscv/mm/Makefile b/arch/riscv/mm/Makefile
> >>> index eb22ab4..1523ee5 100644
> >>> --- a/arch/riscv/mm/Makefile
> >>> +++ b/arch/riscv/mm/Makefile
> >>> @@ -3,3 +3,4 @@ obj-y += fault.o
> >>> obj-y += extable.o
> >>> obj-y += ioremap.o
> >>> obj-y += cacheflush.o
> >>> +obj-y += sifive_l2_cache.o
> >>> diff --git a/arch/riscv/mm/sifive_l2_cache.c
> >>> b/arch/riscv/mm/sifive_l2_cache.c
> >>> new file mode 100644
> >>> index 000..4eb6461
> >>> --- /dev/null
> >>> +++ b/arch/riscv/mm/sifive_l2_cache.c
> >>> @@ -0,0 +1,175 @@
> >>> +// SPDX-License-Identifier: GPL-2.0
> >>> +/*
> >>> + * SiFive L2 cache controller Driver
> >>> + *
> >>> + * Copyright (C) 2018-2019 SiFive, Inc.
> >>> + *
> >>> + */
> > [...]
> >>> +
> >>> +#ifdef CONFIG_DEBUG_FS
> >>> +static struct dentry *sifive_test;
> >>> +
> >>> +static ssize_t l2_write(struct file *file, const char __user *data,
> >>> + size_t count, loff_t *ppos)
> >>> +{
> >>> + unsigned int val;
> >>> +
> >>> + if (kstrtouint_from_user(data, count, 0, ))
> >>> + return -EINVAL;
> >>> + if ((val >= 0 && val < 0xFF) || (val >= 0x1 && val < 0x100FF))
> >>
> >> I'm guessing bit 16 is the enable and the lower 8 are some kind of
> >> region to enable the error? This is probably a bad interface, it looks
> >> useful for testing but doesn't provide any debugging info useful for
> >> running systems. Do you really want userspace to be able to do this?
> >
> > Bit 16 selects the type of ECC error (0=data or 1=directory error).
> > The lower 8 bits toggles (corrupt) that bit index.
> > Are you suggesting to remove this debug interface altogether or you
> > want me to improve the current interface?
> > Something like providing 2 separate debugfs files for data and
> > directory errors. And create a separate 8-bit debugfs variable to
> > select the bit index to toggle.
> >
>
> I was suggesting to remove the whole thing. I don't see it being all
> that useful, but it is up to you.
Thanks for the suggestion, but I will keep it as we do need it for our testing.
- Yash
Re: [PATCH v11 0/2] PWM support for HiFive Unleashed
Hi Andreas, On Tue, May 7, 2019 at 3:09 PM Andreas Schwab wrote: > > On Mai 02 2019, Yash Shah wrote: > > > The PWM default output state is high (When duty cycle is 0), So I > > guess leds will remain on by default. > > So that's the bug that needs to be fixed. Sorry I didn't probably get you before. I now understood the scenario. Leds on HiFive Unleashed are wired to supply instead of ground. And as per ./Documentation/devicetree/bindings/leds/leds-pwm.txt, you need to provide additional property "active-low" in such case. - active-low : (optional) For PWMs where the LED is wired to supply rather than ground. The leds will remain off by default when you add the "active-low" property under the pwm-leds subnode in your DT file. So, this isn't a bug in the driver code. For DT file change, you may refer https://github.com/yashshah7/riscv-linux/commit/dd55057a26150e50525643a423b20e07b72617b5 Can you test this at your end and confirm? - Yash > > Andreas. > > -- > Andreas Schwab, SUSE Labs, sch...@suse.de > GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE 1748 E4D4 88E3 0EEA B9D7 > "And now for something completely different." -- The information transmitted is intended only for the person or entity to which it is addressed and may contain confidential and/or privileged material. If you are not the intended recipient of this message please do not read, copy, use or disclose this communication and notify the sender immediately. It should be noted that any review, retransmission, dissemination or other use of, or taking action or reliance upon, this information by persons or entities other than the intended recipient is prohibited.
Re: [PATCH v3 2/2] RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs
On Mon, May 6, 2019 at 5:48 PM Andrew F. Davis wrote:
>
> On 5/6/19 6:48 AM, Yash Shah wrote:
> > The driver currently supports only SiFive FU540-C000 platform.
> >
> > The initial version of L2 cache controller driver includes:
> > - Initial configuration reporting at boot up.
> > - Support for ECC related functionality.
> >
> > Signed-off-by: Yash Shah
> > ---
> > arch/riscv/include/asm/sifive_l2_cache.h | 16 +++
> > arch/riscv/mm/Makefile | 1 +
> > arch/riscv/mm/sifive_l2_cache.c | 175
> > +++
> > 3 files changed, 192 insertions(+)
> > create mode 100644 arch/riscv/include/asm/sifive_l2_cache.h
> > create mode 100644 arch/riscv/mm/sifive_l2_cache.c
> >
> > diff --git a/arch/riscv/include/asm/sifive_l2_cache.h
> > b/arch/riscv/include/asm/sifive_l2_cache.h
> > new file mode 100644
> > index 000..04f6748
> > --- /dev/null
> > +++ b/arch/riscv/include/asm/sifive_l2_cache.h
> > @@ -0,0 +1,16 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * SiFive L2 Cache Controller header file
> > + *
> > + */
> > +
> > +#ifndef _ASM_RISCV_SIFIVE_L2_CACHE_H
> > +#define _ASM_RISCV_SIFIVE_L2_CACHE_H
> > +
> > +extern int register_sifive_l2_error_notifier(struct notifier_block *nb);
> > +extern int unregister_sifive_l2_error_notifier(struct notifier_block *nb);
> > +
> > +#define SIFIVE_L2_ERR_TYPE_CE 0
> > +#define SIFIVE_L2_ERR_TYPE_UE 1
> > +
> > +#endif /* _ASM_RISCV_SIFIVE_L2_CACHE_H */
> > diff --git a/arch/riscv/mm/Makefile b/arch/riscv/mm/Makefile
> > index eb22ab4..1523ee5 100644
> > --- a/arch/riscv/mm/Makefile
> > +++ b/arch/riscv/mm/Makefile
> > @@ -3,3 +3,4 @@ obj-y += fault.o
> > obj-y += extable.o
> > obj-y += ioremap.o
> > obj-y += cacheflush.o
> > +obj-y += sifive_l2_cache.o
> > diff --git a/arch/riscv/mm/sifive_l2_cache.c
> > b/arch/riscv/mm/sifive_l2_cache.c
> > new file mode 100644
> > index 000..4eb6461
> > --- /dev/null
> > +++ b/arch/riscv/mm/sifive_l2_cache.c
> > @@ -0,0 +1,175 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * SiFive L2 cache controller Driver
> > + *
> > + * Copyright (C) 2018-2019 SiFive, Inc.
> > + *
> > + */
[...]
> > +
> > +#ifdef CONFIG_DEBUG_FS
> > +static struct dentry *sifive_test;
> > +
> > +static ssize_t l2_write(struct file *file, const char __user *data,
> > + size_t count, loff_t *ppos)
> > +{
> > + unsigned int val;
> > +
> > + if (kstrtouint_from_user(data, count, 0, ))
> > + return -EINVAL;
> > + if ((val >= 0 && val < 0xFF) || (val >= 0x1 && val < 0x100FF))
>
> I'm guessing bit 16 is the enable and the lower 8 are some kind of
> region to enable the error? This is probably a bad interface, it looks
> useful for testing but doesn't provide any debugging info useful for
> running systems. Do you really want userspace to be able to do this?
Bit 16 selects the type of ECC error (0=data or 1=directory error).
The lower 8 bits toggles (corrupt) that bit index.
Are you suggesting to remove this debug interface altogether or you
want me to improve the current interface?
Something like providing 2 separate debugfs files for data and
directory errors. And create a separate 8-bit debugfs variable to
select the bit index to toggle.
- Yash
>
> Andrew
>
--
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which it is addressed and may contain confidential and/or privileged
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