[PATCH v3 10/11] dt-bindings: clock: stm32mp1 new compatible for secure rcc

[gabriel.fernandez]

From: Gabriel Fernandez 

Introduce new compatible string "st,stm32mp1-rcc-secure" for
stm32mp1 clock driver when the device is configured with RCC
security support hardened.

Signed-off-by: Etienne Carriere 
Signed-off-by: Gabriel Fernandez 
---
 .../devicetree/bindings/clock/st,stm32mp1-rcc.yaml  | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml 
b/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml
index 4e385508f516..8b1ecb2ecdd5 100644
--- a/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml
+++ b/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml
@@ -54,7 +54,9 @@ properties:
 
   compatible:
 items:
-  - const: st,stm32mp1-rcc
+  - enum:
+  - st,stm32mp1-rcc-secure
+  - st,stm32mp1-rcc
   - const: syscon
 
   reg:
@@ -71,7 +73,7 @@ additionalProperties: false
 examples:
   - |
 rcc: rcc@5000 {
-compatible = "st,stm32mp1-rcc", "syscon";
+compatible = "st,stm32mp1-rcc-secure", "syscon";
 reg = <0x5000 0x1000>;
 #clock-cells = <1>;
 #reset-cells = <1>;
-- 
2.17.1

[PATCH v3 11/11] clk: stm32mp1: new compatible for secure RCC support

[gabriel.fernandez]

From: Gabriel Fernandez 

Platform STM32MP1 can be used in configuration where some clock
resources cannot be accessed by Linux kernel when executing in non-secure
state of the CPU(s).
In such configuration, the RCC clock driver must not register clocks
it cannot access.
They are expected to be registered from another clock driver such
as the SCMI clock driver.
This change uses specific compatible string "st,stm32mp1-rcc-secure"
to specify RCC clock driver configuration where RCC is secure.

Signed-off-by: Etienne Carriere 
Signed-off-by: Gabriel Fernandez 
---
 drivers/clk/Kconfig|  10 
 drivers/clk/clk-stm32mp1.c | 101 -
 2 files changed, 110 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index a588d56502d4..44cc662f11f2 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -335,6 +335,16 @@ config COMMON_CLK_STM32MP157
help
  Support for stm32mp157 SoC family clocks
 
+config COMMON_CLK_STM32MP157_SCMI
+   bool "stm32mp157 Clock driver with Trusted Firmware"
+   depends on COMMON_CLK_STM32MP157
+   select COMMON_CLK_SCMI
+   select ARM_SCMI_PROTOCOL
+   default y
+   help
+ Support for stm32mp157 SoC family clocks with Trusted Firmware using
+ SCMI protocol.
+
 config COMMON_CLK_STM32F
def_bool COMMON_CLK && (MACH_STM32F429 || MACH_STM32F469 || 
MACH_STM32F746)
help
diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index 6d3a36f81b2d..6adc625e79cb 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -2056,11 +2056,61 @@ static const struct clock_config stm32mp1_clock_cfg[] = 
{
  _DIV(RCC_DBGCFGR, 0, 3, 0, ck_trace_div_table)),
 };
 
+static const u32 stm32mp1_clock_secured[] = {
+   CK_HSE,
+   CK_HSI,
+   CK_CSI,
+   CK_LSI,
+   CK_LSE,
+   PLL1,
+   PLL2,
+   PLL1_P,
+   PLL2_P,
+   PLL2_Q,
+   PLL2_R,
+   CK_MPU,
+   CK_AXI,
+   SPI6,
+   I2C4,
+   I2C6,
+   USART1,
+   RTCAPB,
+   TZC1,
+   TZC2,
+   TZPC,
+   IWDG1,
+   BSEC,
+   STGEN,
+   GPIOZ,
+   CRYP1,
+   HASH1,
+   RNG1,
+   BKPSRAM,
+   RNG1_K,
+   STGEN_K,
+   SPI6_K,
+   I2C4_K,
+   I2C6_K,
+   USART1_K,
+   RTC,
+};
+
+static bool stm32_check_security(const struct clock_config *cfg)
+{
+   int i;
+
+   for (i = 0; i < ARRAY_SIZE(stm32mp1_clock_secured); i++)
+   if (cfg->id == stm32mp1_clock_secured[i])
+   return true;
+   return false;
+}
+
 struct stm32_rcc_match_data {
const struct clock_config *cfg;
unsigned int num;
unsigned int maxbinding;
u32 clear_offset;
+   bool (*check_security)(const struct clock_config *cfg);
 };
 
 static struct stm32_rcc_match_data stm32mp1_data = {
@@ -2070,11 +2120,23 @@ static struct stm32_rcc_match_data stm32mp1_data = {
.clear_offset   = RCC_CLR,
 };
 
+static struct stm32_rcc_match_data stm32mp1_data_secure = {
+   .cfg= stm32mp1_clock_cfg,
+   .num= ARRAY_SIZE(stm32mp1_clock_cfg),
+   .maxbinding = STM32MP1_LAST_CLK,
+   .clear_offset   = RCC_CLR,
+   .check_security = _check_security
+};
+
 static const struct of_device_id stm32mp1_match_data[] = {
{
.compatible = "st,stm32mp1-rcc",
.data = _data,
},
+   {
+   .compatible = "st,stm32mp1-rcc-secure",
+   .data = _data_secure,
+   },
{ }
 };
 MODULE_DEVICE_TABLE(of, stm32mp1_match_data);
@@ -2234,6 +2296,9 @@ static int stm32_rcc_clock_init(struct device *dev, void 
__iomem *base,
hws[n] = ERR_PTR(-ENOENT);
 
for (n = 0; n < data->num; n++) {
+   if (data->check_security && data->check_security(>cfg[n]))
+   continue;
+
err = stm32_register_hw_clk(dev, clk_data, base, ,
>cfg[n]);
if (err) {
@@ -2301,11 +2366,45 @@ static int stm32mp1_rcc_init(struct device *dev)
return ret;
 }
 
+static int get_clock_deps(struct device *dev)
+{
+   static const char * const clock_deps_name[] = {
+   "hsi", "hse", "csi", "lsi", "lse",
+   };
+   size_t deps_size = sizeof(struct clk *) * ARRAY_SIZE(clock_deps_name);
+   struct clk **clk_deps;
+   int i;
+
+   clk_deps = devm_kzalloc(dev, deps_size, GFP_KERNEL);
+   if (!clk_deps)
+   return -ENOMEM;
+
+   for (i = 0; i < ARRAY_SIZE(clock_deps_name); i++) {
+   struct clk *clk = of_clk_get_by_name(dev_of_node(dev),
+clock_deps_name[i]);
+
+   if (IS_ERR(clk)) {
+   if (PTR_ERR(clk) != -EINVAL && PTR_ERR(clk) != -ENOENT)
+ 

[PATCH v3 02/11] clk: stm32mp1: merge 'ck_hse_rtc' and 'ck_rtc' into one clock

[gabriel.fernandez]

From: Gabriel Fernandez 

'ck_rtc' has multiple clocks as input (ck_hsi, ck_lsi, and ck_hse).
A divider is available only on the specific rtc input for ck_hse.
This Merge will facilitate to have a more coherent clock tree
in no trusted / trusted world.

Signed-off-by: Gabriel Fernandez 
---
 drivers/clk/clk-stm32mp1.c | 54 +-
 1 file changed, 48 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index 35d5aee8f9b0..a7c244fd0b03 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -245,7 +245,7 @@ static const char * const dsi_src[] = {
 };
 
 static const char * const rtc_src[] = {
-   "off", "ck_lse", "ck_lsi", "ck_hse_rtc"
+   "off", "ck_lse", "ck_lsi", "ck_hse"
 };
 
 static const char * const mco1_src[] = {
@@ -1031,6 +1031,47 @@ static struct clk_hw *clk_register_cktim(struct device 
*dev, const char *name,
return hw;
 }
 
+/* The divider of RTC clock concerns only ck_hse clock */
+#define HSE_RTC 3
+
+static unsigned long clk_divider_rtc_recalc_rate(struct clk_hw *hw,
+unsigned long parent_rate)
+{
+   if (clk_hw_get_parent(hw) == clk_hw_get_parent_by_index(hw, HSE_RTC))
+   return clk_divider_ops.recalc_rate(hw, parent_rate);
+
+   return parent_rate;
+}
+
+static int clk_divider_rtc_set_rate(struct clk_hw *hw, unsigned long rate,
+   unsigned long parent_rate)
+{
+   if (clk_hw_get_parent(hw) == clk_hw_get_parent_by_index(hw, HSE_RTC))
+   return clk_divider_ops.set_rate(hw, rate, parent_rate);
+
+   return parent_rate;
+}
+
+static int clk_divider_rtc_determine_rate(struct clk_hw *hw, struct 
clk_rate_request *req)
+{
+   unsigned long best_parent_rate = req->best_parent_rate;
+
+   if (req->best_parent_hw == clk_hw_get_parent_by_index(hw, HSE_RTC)) {
+   req->rate = clk_divider_ops.round_rate(hw, req->rate, 
_parent_rate);
+   req->best_parent_rate = best_parent_rate;
+   } else {
+   req->rate = best_parent_rate;
+   }
+
+   return 0;
+}
+
+static const struct clk_ops rtc_div_clk_ops = {
+   .recalc_rate= clk_divider_rtc_recalc_rate,
+   .set_rate   = clk_divider_rtc_set_rate,
+   .determine_rate = clk_divider_rtc_determine_rate
+};
+
 struct stm32_pll_cfg {
u32 offset;
 };
@@ -1243,6 +1284,10 @@ _clk_stm32_register_composite(struct device *dev,
_STM32_DIV(_div_offset, _div_shift, _div_width,\
   _div_flags, _div_table, NULL)\
 
+#define _DIV_RTC(_div_offset, _div_shift, _div_width, _div_flags, _div_table)\
+   _STM32_DIV(_div_offset, _div_shift, _div_width,\
+  _div_flags, _div_table, _div_clk_ops)
+
 #define _STM32_MUX(_offset, _shift, _width, _mux_flags, _mmux, _ops)\
.mux = &(struct stm32_mux_cfg) {\
&(struct mux_cfg) {\
@@ -1965,13 +2010,10 @@ static const struct clock_config stm32mp1_clock_cfg[] = 
{
  _DIV(RCC_ETHCKSELR, 4, 4, 0, NULL)),
 
/* RTC clock */
-   DIV(NO_ID, "ck_hse_rtc", "ck_hse", 0, RCC_RTCDIVR, 0, 6, 0),
-
-   COMPOSITE(RTC, "ck_rtc", rtc_src, CLK_OPS_PARENT_ENABLE |
-  CLK_SET_RATE_PARENT,
+   COMPOSITE(RTC, "ck_rtc", rtc_src, CLK_OPS_PARENT_ENABLE,
  _GATE(RCC_BDCR, 20, 0),
  _MUX(RCC_BDCR, 16, 2, 0),
- _NO_DIV),
+ _DIV_RTC(RCC_RTCDIVR, 0, 6, 0, NULL)),
 
/* MCO clocks */
COMPOSITE(CK_MCO1, "ck_mco1", mco1_src, CLK_OPS_PARENT_ENABLE |
-- 
2.17.1

[PATCH v3 09/11] dt-bindings: reset: add MCU HOLD BOOT ID for SCMI reset domains on stm32mp15

[gabriel.fernandez]

From: Gabriel Fernandez 

Add ID to SCMI0 to exposes reset controller for the MCU HOLD BOOT resource.

Signed-off-by: Arnaud Pouliquen 
Signed-off-by: Gabriel Fernandez 
Acked-by: Rob Herring 
---
 include/dt-bindings/reset/stm32mp1-resets.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/dt-bindings/reset/stm32mp1-resets.h 
b/include/dt-bindings/reset/stm32mp1-resets.h
index bc71924faa54..f3a0ed317835 100644
--- a/include/dt-bindings/reset/stm32mp1-resets.h
+++ b/include/dt-bindings/reset/stm32mp1-resets.h
@@ -7,6 +7,7 @@
 #ifndef _DT_BINDINGS_STM32MP1_RESET_H_
 #define _DT_BINDINGS_STM32MP1_RESET_H_
 
+#define MCU_HOLD_BOOT_R2144
 #define LTDC_R 3072
 #define DSI_R  3076
 #define DDRPERFM_R 3080
@@ -117,5 +118,6 @@
 #define RST_SCMI0_RNG1 8
 #define RST_SCMI0_MDMA 9
 #define RST_SCMI0_MCU  10
+#define RST_SCMI0_MCU_HOLD_BOOT11
 
 #endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */
-- 
2.17.1

[PATCH v3 00/11] Introduce STM32MP1 RCC in secured mode

[gabriel.fernandez]

From: Gabriel Fernandez 

Platform STM32MP1 can be used in configuration where some clocks and
IP resets can relate as secure resources.
These resources are moved from a RCC clock/reset handle to a SCMI
clock/reset_domain handle.

The RCC clock driver is now dependent of the SCMI driver, then we have
to manage now the probe defering.

v2 -> v3:
  - use determine_rate op instead of round_rate for ck_rtc
  - remove DT patches from patchset to keek Kernel device tree as there are in 
basic boot.
 We will applied scmi clock phandle thanks dtbo in U-boot.
v1 -> v2:
  - fix yamllint warnings.

Gabriel Fernandez (11):
  clk: stm32mp1: merge 'clk-hsi-div' and 'ck_hsi' into one clock
  clk: stm32mp1: merge 'ck_hse_rtc' and 'ck_rtc' into one clock
  clk: stm32mp1: remove intermediate pll clocks
  clk: stm32mp1: convert to module driver
  clk: stm32mp1: move RCC reset controller into RCC clock driver
  reset: stm32mp1: remove stm32mp1 reset
  dt-bindings: clock: add IDs for SCMI clocks on stm32mp15
  dt-bindings: reset: add IDs for SCMI reset domains on stm32mp15
  dt-bindings: reset: add MCU HOLD BOOT ID for SCMI reset domains on
stm32mp15
  dt-bindings: clock: stm32mp1 new compatible for secure rcc
  clk: stm32mp1: new compatible for secure RCC support

 .../bindings/clock/st,stm32mp1-rcc.yaml   |   6 +-
 drivers/clk/Kconfig   |  10 +
 drivers/clk/clk-stm32mp1.c| 500 +++---
 drivers/reset/Kconfig |   6 -
 drivers/reset/Makefile|   1 -
 drivers/reset/reset-stm32mp1.c| 115 
 include/dt-bindings/clock/stm32mp1-clks.h |  27 +
 include/dt-bindings/reset/stm32mp1-resets.h   |  15 +
 8 files changed, 469 insertions(+), 211 deletions(-)
 delete mode 100644 drivers/reset/reset-stm32mp1.c

-- 
2.17.1

[PATCH v3 05/11] clk: stm32mp1: move RCC reset controller into RCC clock driver

[gabriel.fernandez]

From: Gabriel Fernandez 

RCC clock and reset controller shared same memory mapping.
As RCC clock driver is now a module, the best way to register clock
and reset controller is to do it in same driver.

Signed-off-by: Gabriel Fernandez 
---
 drivers/clk/clk-stm32mp1.c | 157 ++---
 1 file changed, 144 insertions(+), 13 deletions(-)

diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index e2e9331f1cba..6d3a36f81b2d 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -14,6 +14,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -2055,16 +2056,18 @@ static const struct clock_config stm32mp1_clock_cfg[] = 
{
  _DIV(RCC_DBGCFGR, 0, 3, 0, ck_trace_div_table)),
 };
 
-struct stm32_clock_match_data {
+struct stm32_rcc_match_data {
const struct clock_config *cfg;
unsigned int num;
unsigned int maxbinding;
+   u32 clear_offset;
 };
 
-static struct stm32_clock_match_data stm32mp1_data = {
+static struct stm32_rcc_match_data stm32mp1_data = {
.cfg= stm32mp1_clock_cfg,
.num= ARRAY_SIZE(stm32mp1_clock_cfg),
.maxbinding = STM32MP1_LAST_CLK,
+   .clear_offset   = RCC_CLR,
 };
 
 static const struct of_device_id stm32mp1_match_data[] = {
@@ -2100,23 +2103,122 @@ static int stm32_register_hw_clk(struct device *dev,
return 0;
 }
 
-static int stm32_rcc_init(struct device *dev, void __iomem *base,
- const struct of_device_id *match_data)
+#define STM32_RESET_ID_MASK GENMASK(15, 0)
+
+struct stm32_reset_data {
+   /* reset lock */
+   spinlock_t  lock;
+   struct reset_controller_dev rcdev;
+   void __iomem*membase;
+   u32 clear_offset;
+};
+
+static inline struct stm32_reset_data *
+to_stm32_reset_data(struct reset_controller_dev *rcdev)
 {
-   struct clk_hw_onecell_data *clk_data;
-   struct clk_hw **hws;
-   const struct of_device_id *match;
-   const struct stm32_clock_match_data *data;
-   int err, n, max_binding;
+   return container_of(rcdev, struct stm32_reset_data, rcdev);
+}
 
-   match = of_match_node(match_data, dev_of_node(dev));
-   if (!match) {
-   dev_err(dev, "match data not found\n");
-   return -ENODEV;
+static int stm32_reset_update(struct reset_controller_dev *rcdev,
+ unsigned long id, bool assert)
+{
+   struct stm32_reset_data *data = to_stm32_reset_data(rcdev);
+   int reg_width = sizeof(u32);
+   int bank = id / (reg_width * BITS_PER_BYTE);
+   int offset = id % (reg_width * BITS_PER_BYTE);
+
+   if (data->clear_offset) {
+   void __iomem *addr;
+
+   addr = data->membase + (bank * reg_width);
+   if (!assert)
+   addr += data->clear_offset;
+
+   writel(BIT(offset), addr);
+
+   } else {
+   unsigned long flags;
+   u32 reg;
+
+   spin_lock_irqsave(>lock, flags);
+
+   reg = readl(data->membase + (bank * reg_width));
+
+   if (assert)
+   reg |= BIT(offset);
+   else
+   reg &= ~BIT(offset);
+
+   writel(reg, data->membase + (bank * reg_width));
+
+   spin_unlock_irqrestore(>lock, flags);
}
 
+   return 0;
+}
+
+static int stm32_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+   return stm32_reset_update(rcdev, id, true);
+}
+
+static int stm32_reset_deassert(struct reset_controller_dev *rcdev,
+   unsigned long id)
+{
+   return stm32_reset_update(rcdev, id, false);
+}
+
+static int stm32_reset_status(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+   struct stm32_reset_data *data = to_stm32_reset_data(rcdev);
+   int reg_width = sizeof(u32);
+   int bank = id / (reg_width * BITS_PER_BYTE);
+   int offset = id % (reg_width * BITS_PER_BYTE);
+   u32 reg;
+
+   reg = readl(data->membase + (bank * reg_width));
+
+   return !!(reg & BIT(offset));
+}
+
+static const struct reset_control_ops stm32_reset_ops = {
+   .assert = stm32_reset_assert,
+   .deassert   = stm32_reset_deassert,
+   .status = stm32_reset_status,
+};
+
+static int stm32_rcc_reset_init(struct device *dev, void __iomem *base,
+   const struct of_device_id *match)
+{
+   const struct stm32_rcc_match_data *data = match->data;
+   struct stm32_reset_data *reset_data = NULL;
+
data = match->data;
 
+   reset_data = kzalloc(sizeof(*reset_data), GFP_KERNEL);
+   if (!reset_data)
+   return -ENOMEM;
+
+   reset_data->membase = base;
+   

[PATCH v3 03/11] clk: stm32mp1: remove intermediate pll clocks

[gabriel.fernandez]

From: Gabriel Fernandez 

This patch is to prepare STM32MP1 clocks in trusted mode.
Integrate the mux clock into pll clock will facilitate to have a more
coherent clock tree in no trusted / trusted mode.

Signed-off-by: Gabriel Fernandez 
---
 drivers/clk/clk-stm32mp1.c | 65 --
 1 file changed, 42 insertions(+), 23 deletions(-)

diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index a7c244fd0b03..24d99da07fc8 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -731,6 +731,7 @@ struct stm32_pll_obj {
spinlock_t *lock;
void __iomem *reg;
struct clk_hw hw;
+   struct clk_mux mux;
 };
 
 #define to_pll(_hw) container_of(_hw, struct stm32_pll_obj, hw)
@@ -745,6 +746,8 @@ struct stm32_pll_obj {
 #define FRAC_MASK  0x1FFF
 #define FRAC_SHIFT 3
 #define FRACLE BIT(16)
+#define PLL_MUX_SHIFT  0
+#define PLL_MUX_MASK   3
 
 static int __pll_is_enabled(struct clk_hw *hw)
 {
@@ -856,16 +859,29 @@ static int pll_is_enabled(struct clk_hw *hw)
return ret;
 }
 
+static u8 pll_get_parent(struct clk_hw *hw)
+{
+   struct stm32_pll_obj *clk_elem = to_pll(hw);
+   struct clk_hw *mux_hw = _elem->mux.hw;
+
+   __clk_hw_set_clk(mux_hw, hw);
+
+   return clk_mux_ops.get_parent(mux_hw);
+}
+
 static const struct clk_ops pll_ops = {
.enable = pll_enable,
.disable= pll_disable,
.recalc_rate= pll_recalc_rate,
.is_enabled = pll_is_enabled,
+   .get_parent = pll_get_parent,
 };
 
 static struct clk_hw *clk_register_pll(struct device *dev, const char *name,
-  const char *parent_name,
+  const char * const *parent_names,
+  int num_parents,
   void __iomem *reg,
+  void __iomem *mux_reg,
   unsigned long flags,
   spinlock_t *lock)
 {
@@ -881,8 +897,15 @@ static struct clk_hw *clk_register_pll(struct device *dev, 
const char *name,
init.name = name;
init.ops = _ops;
init.flags = flags;
-   init.parent_names = _name;
-   init.num_parents = 1;
+   init.parent_names = parent_names;
+   init.num_parents = num_parents;
+
+   element->mux.lock = lock;
+   element->mux.reg =  mux_reg;
+   element->mux.shift = PLL_MUX_SHIFT;
+   element->mux.mask =  PLL_MUX_MASK;
+   element->mux.flags =  CLK_MUX_READ_ONLY;
+   element->mux.reg =  mux_reg;
 
element->hw.init = 
element->reg = reg;
@@ -1074,6 +1097,7 @@ static const struct clk_ops rtc_div_clk_ops = {
 
 struct stm32_pll_cfg {
u32 offset;
+   u32 muxoff;
 };
 
 static struct clk_hw *_clk_register_pll(struct device *dev,
@@ -1083,8 +1107,11 @@ static struct clk_hw *_clk_register_pll(struct device 
*dev,
 {
struct stm32_pll_cfg *stm_pll_cfg = cfg->cfg;
 
-   return clk_register_pll(dev, cfg->name, cfg->parent_name,
-   base + stm_pll_cfg->offset, cfg->flags, lock);
+   return clk_register_pll(dev, cfg->name, cfg->parent_names,
+   cfg->num_parents,
+   base + stm_pll_cfg->offset,
+   base + stm_pll_cfg->muxoff,
+   cfg->flags, lock);
 }
 
 struct stm32_cktim_cfg {
@@ -1194,14 +1221,16 @@ _clk_stm32_register_composite(struct device *dev,
.func   = _clk_hw_register_mux,\
 }
 
-#define PLL(_id, _name, _parent, _flags, _offset)\
+#define PLL(_id, _name, _parents, _flags, _offset_p, _offset_mux)\
 {\
.id = _id,\
.name   = _name,\
-   .parent_name= _parent,\
-   .flags  = _flags,\
+   .parent_names   = _parents,\
+   .num_parents= ARRAY_SIZE(_parents),\
+   .flags  = CLK_IGNORE_UNUSED | (_flags),\
.cfg=  &(struct stm32_pll_cfg) {\
-   .offset = _offset,\
+   .offset = _offset_p,\
+   .muxoff = _offset_mux,\
},\
.func   = _clk_register_pll,\
 }
@@ -1717,21 +1746,11 @@ static const struct clock_config stm32mp1_clock_cfg[] = 
{
 
FIXED_FACTOR(CK_HSE_DIV2, "clk-hse-div2", "ck_hse", 0, 1, 2),
 
-   /* ref clock pll */
-   MUX(NO_ID, "ref1", ref12_parents, CLK_OPS_PARENT_ENABLE, RCC_RCK12SELR,
-   0, 2, CLK_MUX_READ_ONLY),
-
-   MUX(NO_ID, "ref3", ref3_parents, CLK_OPS_PARENT_ENABLE, RCC_RCK3SELR,
-   0, 2, CLK_MUX_READ_ONLY),
-
-   MUX(NO_ID, "ref4", ref4_parents, CLK_OPS_PARENT_ENABLE, RCC_RCK4SELR,
-   0, 2, CLK_MUX_READ_ONLY),
-
/* PLLs */
-   PLL(PLL1, "pll1", "ref1", CLK_IGNORE_UNUSED, RCC_PLL1CR),
-   PLL(PLL2, "pll2", "ref1", CLK_IGNORE_UNUSED, RCC_PLL2CR),
-   

[PATCH v3 01/11] clk: stm32mp1: merge 'clk-hsi-div' and 'ck_hsi' into one clock

[gabriel.fernandez]

From: Gabriel Fernandez 

This patch is to prepare STM32MP1 clocks in trusted mode.
This Merge will facilitate to have a more coherent clock tree
in no trusted / trusted world.

Signed-off-by: Gabriel Fernandez 
---
 drivers/clk/clk-stm32mp1.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index a875649df8b8..35d5aee8f9b0 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -1657,16 +1657,16 @@ static const struct stm32_mux_cfg ker_mux_cfg[M_LAST] = 
{
 };
 
 static const struct clock_config stm32mp1_clock_cfg[] = {
-   /* Oscillator divider */
-   DIV(NO_ID, "clk-hsi-div", "clk-hsi", CLK_DIVIDER_POWER_OF_TWO,
-   RCC_HSICFGR, 0, 2, CLK_DIVIDER_READ_ONLY),
-
/*  External / Internal Oscillators */
GATE_MP1(CK_HSE, "ck_hse", "clk-hse", 0, RCC_OCENSETR, 8, 0),
/* ck_csi is used by IO compensation and should be critical */
GATE_MP1(CK_CSI, "ck_csi", "clk-csi", CLK_IS_CRITICAL,
 RCC_OCENSETR, 4, 0),
-   GATE_MP1(CK_HSI, "ck_hsi", "clk-hsi-div", 0, RCC_OCENSETR, 0, 0),
+   COMPOSITE(CK_HSI, "ck_hsi", PARENT("clk-hsi"), 0,
+ _GATE_MP1(RCC_OCENSETR, 0, 0),
+ _NO_MUX,
+ _DIV(RCC_HSICFGR, 0, 2, CLK_DIVIDER_POWER_OF_TWO |
+  CLK_DIVIDER_READ_ONLY, NULL)),
GATE(CK_LSI, "ck_lsi", "clk-lsi", 0, RCC_RDLSICR, 0, 0),
GATE(CK_LSE, "ck_lse", "clk-lse", 0, RCC_BDCR, 0, 0),
 
-- 
2.17.1

[PATCH v3 04/11] clk: stm32mp1: convert to module driver

[gabriel.fernandez]

From: Gabriel Fernandez 

Adds support for  probe deferral in way to prepare
integration of the security in RCC clock and reset
drivers.
Some kernel clocks will be provided by the SCMI drivers.
Since RCC clock driver create clocks which parents
are SCMI clocks, RCC clock driver probe can be deferred.

Signed-off-by: Etienne Carriere 
Signed-off-by: Gabriel Fernandez 
---
 drivers/clk/clk-stm32mp1.c | 121 -
 1 file changed, 78 insertions(+), 43 deletions(-)

diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index 24d99da07fc8..e2e9331f1cba 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -10,8 +10,10 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -469,7 +471,7 @@ static const struct clk_ops mp1_gate_clk_ops = {
.is_enabled = clk_gate_is_enabled,
 };
 
-static struct clk_hw *_get_stm32_mux(void __iomem *base,
+static struct clk_hw *_get_stm32_mux(struct device *dev, void __iomem *base,
 const struct stm32_mux_cfg *cfg,
 spinlock_t *lock)
 {
@@ -478,7 +480,7 @@ static struct clk_hw *_get_stm32_mux(void __iomem *base,
struct clk_hw *mux_hw;
 
if (cfg->mmux) {
-   mmux = kzalloc(sizeof(*mmux), GFP_KERNEL);
+   mmux = devm_kzalloc(dev, sizeof(*mmux), GFP_KERNEL);
if (!mmux)
return ERR_PTR(-ENOMEM);
 
@@ -493,7 +495,7 @@ static struct clk_hw *_get_stm32_mux(void __iomem *base,
cfg->mmux->hws[cfg->mmux->nbr_clk++] = mux_hw;
 
} else {
-   mux = kzalloc(sizeof(*mux), GFP_KERNEL);
+   mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
if (!mux)
return ERR_PTR(-ENOMEM);
 
@@ -509,13 +511,13 @@ static struct clk_hw *_get_stm32_mux(void __iomem *base,
return mux_hw;
 }
 
-static struct clk_hw *_get_stm32_div(void __iomem *base,
+static struct clk_hw *_get_stm32_div(struct device *dev, void __iomem *base,
 const struct stm32_div_cfg *cfg,
 spinlock_t *lock)
 {
struct clk_divider *div;
 
-   div = kzalloc(sizeof(*div), GFP_KERNEL);
+   div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
 
if (!div)
return ERR_PTR(-ENOMEM);
@@ -530,16 +532,16 @@ static struct clk_hw *_get_stm32_div(void __iomem *base,
return >hw;
 }
 
-static struct clk_hw *
-_get_stm32_gate(void __iomem *base,
-   const struct stm32_gate_cfg *cfg, spinlock_t *lock)
+static struct clk_hw *_get_stm32_gate(struct device *dev, void __iomem *base,
+ const struct stm32_gate_cfg *cfg,
+ spinlock_t *lock)
 {
struct stm32_clk_mgate *mgate;
struct clk_gate *gate;
struct clk_hw *gate_hw;
 
if (cfg->mgate) {
-   mgate = kzalloc(sizeof(*mgate), GFP_KERNEL);
+   mgate = devm_kzalloc(dev, sizeof(*mgate), GFP_KERNEL);
if (!mgate)
return ERR_PTR(-ENOMEM);
 
@@ -554,7 +556,7 @@ _get_stm32_gate(void __iomem *base,
gate_hw = >gate.hw;
 
} else {
-   gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+   gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL);
if (!gate)
return ERR_PTR(-ENOMEM);
 
@@ -592,7 +594,7 @@ clk_stm32_register_gate_ops(struct device *dev,
if (cfg->ops)
init.ops = cfg->ops;
 
-   hw = _get_stm32_gate(base, cfg, lock);
+   hw = _get_stm32_gate(dev, base, cfg, lock);
if (IS_ERR(hw))
return ERR_PTR(-ENOMEM);
 
@@ -623,7 +625,7 @@ clk_stm32_register_composite(struct device *dev,
gate_ops = NULL;
 
if (cfg->mux) {
-   mux_hw = _get_stm32_mux(base, cfg->mux, lock);
+   mux_hw = _get_stm32_mux(dev, base, cfg->mux, lock);
 
if (!IS_ERR(mux_hw)) {
mux_ops = _mux_ops;
@@ -634,7 +636,7 @@ clk_stm32_register_composite(struct device *dev,
}
 
if (cfg->div) {
-   div_hw = _get_stm32_div(base, cfg->div, lock);
+   div_hw = _get_stm32_div(dev, base, cfg->div, lock);
 
if (!IS_ERR(div_hw)) {
div_ops = _divider_ops;
@@ -645,7 +647,7 @@ clk_stm32_register_composite(struct device *dev,
}
 
if (cfg->gate) {
-   gate_hw = _get_stm32_gate(base, cfg->gate, lock);
+   gate_hw = _get_stm32_gate(dev, base, cfg->gate, lock);
 
if (!IS_ERR(gate_hw)) {
gate_ops = _gate_ops;
@@ -890,7 +892,7 @@ static struct clk_hw *clk_register_pll(struct device *dev, 
const char *name,
struct clk_hw *hw;
int err;
 
-   

[PATCH v3 07/11] dt-bindings: clock: add IDs for SCMI clocks on stm32mp15

[gabriel.fernandez]

From: Gabriel Fernandez 

stm32mp15 TZ secure firmware provides SCMI clocks for oscillators, some
PLL output and few secure aware interfaces.
This change defines the SCMI clock identifiers used by SCMI agents
and servers.
Server SCMI0 exposes clocks and reset controllers for resources under
RCC[TZEN] configuration control.
Server SCMI1 exposes clocks for resources under RCC[MCKPROT] control.

Signed-off-by: Etienne Carriere 
Signed-off-by: Gabriel Fernandez 
Acked-by: Rob Herring 
---
 include/dt-bindings/clock/stm32mp1-clks.h | 27 +++
 1 file changed, 27 insertions(+)

diff --git a/include/dt-bindings/clock/stm32mp1-clks.h 
b/include/dt-bindings/clock/stm32mp1-clks.h
index 4cdaf135829c..e02770b98e6c 100644
--- a/include/dt-bindings/clock/stm32mp1-clks.h
+++ b/include/dt-bindings/clock/stm32mp1-clks.h
@@ -248,4 +248,31 @@
 
 #define STM32MP1_LAST_CLK 232
 
+/* SCMI clock identifiers */
+#define CK_SCMI0_HSE   0
+#define CK_SCMI0_HSI   1
+#define CK_SCMI0_CSI   2
+#define CK_SCMI0_LSE   3
+#define CK_SCMI0_LSI   4
+#define CK_SCMI0_PLL2_Q5
+#define CK_SCMI0_PLL2_R6
+#define CK_SCMI0_MPU   7
+#define CK_SCMI0_AXI   8
+#define CK_SCMI0_BSEC  9
+#define CK_SCMI0_CRYP1 10
+#define CK_SCMI0_GPIOZ 11
+#define CK_SCMI0_HASH1 12
+#define CK_SCMI0_I2C4  13
+#define CK_SCMI0_I2C6  14
+#define CK_SCMI0_IWDG1 15
+#define CK_SCMI0_RNG1  16
+#define CK_SCMI0_RTC   17
+#define CK_SCMI0_RTCAPB18
+#define CK_SCMI0_SPI6  19
+#define CK_SCMI0_USART120
+
+#define CK_SCMI1_PLL3_Q0
+#define CK_SCMI1_PLL3_R1
+#define CK_SCMI1_MCU   2
+
 #endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */
-- 
2.17.1

[PATCH v3 06/11] reset: stm32mp1: remove stm32mp1 reset

[gabriel.fernandez]

From: Gabriel Fernandez 

st32mp1 RCC reset driver was moved into stm32mp1 RCC clock driver.

Signed-off-by: Gabriel Fernandez 
---
 drivers/reset/Kconfig  |   6 --
 drivers/reset/Makefile |   1 -
 drivers/reset/reset-stm32mp1.c | 115 -
 3 files changed, 122 deletions(-)
 delete mode 100644 drivers/reset/reset-stm32mp1.c

diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 4171c6f76385..8c26f7af70a4 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -198,12 +198,6 @@ config RESET_SIMPLE
   - Allwinner SoCs
   - ZTE's zx2967 family
 
-config RESET_STM32MP157
-   bool "STM32MP157 Reset Driver" if COMPILE_TEST
-   default MACH_STM32MP157
-   help
- This enables the RCC reset controller driver for STM32 MPUs.
-
 config RESET_SOCFPGA
bool "SoCFPGA Reset Driver" if COMPILE_TEST && !ARCH_SOCFPGA
default ARCH_SOCFPGA
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 65a118a91b27..ac3e612ad953 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -26,7 +26,6 @@ obj-$(CONFIG_RESET_QCOM_PDC) += reset-qcom-pdc.o
 obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o
 obj-$(CONFIG_RESET_SCMI) += reset-scmi.o
 obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
-obj-$(CONFIG_RESET_STM32MP157) += reset-stm32mp1.o
 obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
 obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
 obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
diff --git a/drivers/reset/reset-stm32mp1.c b/drivers/reset/reset-stm32mp1.c
deleted file mode 100644
index b221a28041fa..
--- a/drivers/reset/reset-stm32mp1.c
+++ /dev/null
@@ -1,115 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
- * Author: Gabriel Fernandez  for STMicroelectronics.
- */
-
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-#define CLR_OFFSET 0x4
-
-struct stm32_reset_data {
-   struct reset_controller_dev rcdev;
-   void __iomem*membase;
-};
-
-static inline struct stm32_reset_data *
-to_stm32_reset_data(struct reset_controller_dev *rcdev)
-{
-   return container_of(rcdev, struct stm32_reset_data, rcdev);
-}
-
-static int stm32_reset_update(struct reset_controller_dev *rcdev,
- unsigned long id, bool assert)
-{
-   struct stm32_reset_data *data = to_stm32_reset_data(rcdev);
-   int reg_width = sizeof(u32);
-   int bank = id / (reg_width * BITS_PER_BYTE);
-   int offset = id % (reg_width * BITS_PER_BYTE);
-   void __iomem *addr;
-
-   addr = data->membase + (bank * reg_width);
-   if (!assert)
-   addr += CLR_OFFSET;
-
-   writel(BIT(offset), addr);
-
-   return 0;
-}
-
-static int stm32_reset_assert(struct reset_controller_dev *rcdev,
- unsigned long id)
-{
-   return stm32_reset_update(rcdev, id, true);
-}
-
-static int stm32_reset_deassert(struct reset_controller_dev *rcdev,
-   unsigned long id)
-{
-   return stm32_reset_update(rcdev, id, false);
-}
-
-static int stm32_reset_status(struct reset_controller_dev *rcdev,
- unsigned long id)
-{
-   struct stm32_reset_data *data = to_stm32_reset_data(rcdev);
-   int reg_width = sizeof(u32);
-   int bank = id / (reg_width * BITS_PER_BYTE);
-   int offset = id % (reg_width * BITS_PER_BYTE);
-   u32 reg;
-
-   reg = readl(data->membase + (bank * reg_width));
-
-   return !!(reg & BIT(offset));
-}
-
-static const struct reset_control_ops stm32_reset_ops = {
-   .assert = stm32_reset_assert,
-   .deassert   = stm32_reset_deassert,
-   .status = stm32_reset_status,
-};
-
-static const struct of_device_id stm32_reset_dt_ids[] = {
-   { .compatible = "st,stm32mp1-rcc"},
-   { /* sentinel */ },
-};
-
-static int stm32_reset_probe(struct platform_device *pdev)
-{
-   struct device *dev = >dev;
-   struct stm32_reset_data *data;
-   void __iomem *membase;
-   struct resource *res;
-
-   data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
-   if (!data)
-   return -ENOMEM;
-
-   res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-   membase = devm_ioremap_resource(dev, res);
-   if (IS_ERR(membase))
-   return PTR_ERR(membase);
-
-   data->membase = membase;
-   data->rcdev.owner = THIS_MODULE;
-   data->rcdev.nr_resets = resource_size(res) * BITS_PER_BYTE;
-   data->rcdev.ops = _reset_ops;
-   data->rcdev.of_node = dev->of_node;
-
-   return devm_reset_controller_register(dev, >rcdev);
-}
-
-static struct platform_driver stm32_reset_driver = {
-   .probe  = stm32_reset_probe,
-   .driver = {
-   .name   = "stm32mp1-reset",
-   .of_match_table = stm32_reset_dt_ids,
-   },
-};
-

[PATCH v3 08/11] dt-bindings: reset: add IDs for SCMI reset domains on stm32mp15

[gabriel.fernandez]

From: Gabriel Fernandez 

stm32mp15 TZ secure firmware provides SCMI reset domains for
secure resources. This change defines the SCMI reset domain
identifiers used by SCMI agents and servers.

Stm32mp15 TZ secure firmware provides SCMI clocks for oscillators, some
PLL output and few secure aware interfaces. This change defines the
SCMI clock identifiers used by SCMI agents and servers.

Server SCMI0 exposes reset controllers for resources under RCC[TZEN]
configuration control.

Signed-off-by: Etienne Carriere 
Signed-off-by: Gabriel Fernandez 
Acked-by: Rob Herring 
---
 include/dt-bindings/reset/stm32mp1-resets.h | 13 +
 1 file changed, 13 insertions(+)

diff --git a/include/dt-bindings/reset/stm32mp1-resets.h 
b/include/dt-bindings/reset/stm32mp1-resets.h
index f0c3aaef67a0..bc71924faa54 100644
--- a/include/dt-bindings/reset/stm32mp1-resets.h
+++ b/include/dt-bindings/reset/stm32mp1-resets.h
@@ -105,4 +105,17 @@
 #define GPIOJ_R19785
 #define GPIOK_R19786
 
+/* SCMI reset domain identifiers */
+#define RST_SCMI0_SPI6 0
+#define RST_SCMI0_I2C4 1
+#define RST_SCMI0_I2C6 2
+#define RST_SCMI0_USART1   3
+#define RST_SCMI0_STGEN4
+#define RST_SCMI0_GPIOZ5
+#define RST_SCMI0_CRYP16
+#define RST_SCMI0_HASH17
+#define RST_SCMI0_RNG1 8
+#define RST_SCMI0_MDMA 9
+#define RST_SCMI0_MCU  10
+
 #endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */
-- 
2.17.1

[PATCH v2 14/14] ARM: dts: stm32: introduce basic boot include on stm32mp15x board

[gabriel.fernandez]

From: Gabriel Fernandez 

Include this .dtsi file to be backward compatible with old basic bootchain.

For example add:
include "stm32mp15-no-scmi.dtsi" in a stm32mp157c*.dts file.

Signed-off-by: Gabriel Fernandez 
---
 arch/arm/boot/dts/stm32mp15-no-scmi.dtsi | 158 +++
 1 file changed, 158 insertions(+)
 create mode 100644 arch/arm/boot/dts/stm32mp15-no-scmi.dtsi

diff --git a/arch/arm/boot/dts/stm32mp15-no-scmi.dtsi 
b/arch/arm/boot/dts/stm32mp15-no-scmi.dtsi
new file mode 100644
index ..4939f96da739
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp15-no-scmi.dtsi
@@ -0,0 +1,158 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2020 - All Rights Reserved
+ * Author: Gabriel Fernandez  for STMicroelectronics.
+ */
+
+/ {
+
+   clocks {
+   clk_hse: clk-hse {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <2400>;
+   };
+
+   clk_hsi: clk-hsi {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <6400>;
+   };
+
+   clk_lse: clk-lse {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <32768>;
+   };
+
+   clk_lsi: clk-lsi {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <32000>;
+   };
+
+   clk_csi: clk-csi {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <400>;
+   };
+   };
+
+   cpus {
+   cpu0: cpu@0 {
+   clocks = < CK_MPU>;
+   };
+
+   cpu1: cpu@1 {
+   clocks = < CK_MPU>;
+   };
+   };
+
+   reboot {
+   compatible = "syscon-reboot";
+   regmap = <>;
+   offset = <0x404>;
+   mask = <0x1>;
+   };
+
+   soc {
+   m_can1: can@4400e000 {
+   clocks = < CK_HSE>, < FDCAN_K>;
+   };
+
+   m_can2: can@4400f000 {
+   clocks = < CK_HSE>, < FDCAN_K>;
+   };
+
+   cryp1: cryp@54001000 {
+   clocks = < CRYP1>;
+   resets = < CRYP1_R>;
+   };
+
+   dsi: dsi@5a00 {
+   clocks = < DSI_K>, <_hse>, < DSI_PX>;
+   };
+   };
+
+   ahb {
+   m4_rproc: m4@1000 {
+   resets = < MCU_R>, < MCU_HOLD_BOOT_R>;
+
+   m4_system_resources {
+   m4_cec: cec@40016000 {
+   clocks = < CEC_K>, < CK_LSE>;
+   };
+
+   m4_m_can1: can@4400e000 {
+   clocks = < CK_HSE>, < FDCAN_K>;
+   };
+
+   m4_m_can2: can@4400f000 {
+   clocks = < CK_HSE>, < FDCAN_K>;
+   };
+   };
+   };
+   };
+
+   firmware {
+   /delete-node/ scmi0;
+   /delete-node/ scmi1;
+   };
+   /delete-node/ sram@2000;
+};
+
+ {
+   clocks = < CEC_K>, <_lse>;
+};
+
+ {
+   clocks = < GPIOZ>;
+};
+
+ {
+   clocks = < HASH1>;
+   resets = < HASH1_R>;
+};
+
+ {
+   clocks = < I2C4_K>;
+   resets = < I2C4_R>;
+};
+
+ {
+   clocks = < I2C6_K>;
+   resets = < I2C6_R>;
+};
+
+ {
+   clocks = < IWDG2>, < CK_LSI>;
+};
+
+ {
+   clocks = < MDMA>;
+   resets = < MDMA_R>;
+};
+
+ {
+   compatible = "st,stm32mp1-rcc", "syscon";
+   clocks = <_hse>, <_hsi>, <_csi>, <_lse>, <_lsi>;
+};
+
+ {
+   clocks = < RNG1_K>;
+   resets = < RNG1_R>;
+};
+
+ {
+   clocks = < RTCAPB>, < RTC>;
+};
+
+ {
+   clocks = < SPI6_K>;
+   resets = < SPI6_R>;
+};
+
+ {
+   clocks = < USART1_K>;
+   resets = < USART1_R>;
+};
-- 
2.17.1

[PATCH v2 12/14] ARM: dts: stm32: move clocks/resets to SCMI resources for stm32mp15

[gabriel.fernandez]

From: Gabriel Fernandez 

This change reflects board hardware configuration where RCC security
features are configured for RCC[TZEN]=1 and RCC[MCKPROT]=0, that is
RCC TrustZone is hardened and RCC MCKPROT is disabled.

Clock and reset controllers that relate to SoC secure resources are
moved from a RCC clock/reset handle to a SCMI clock/reset_domain handle.

These clocks are all the platform oscillators (HSI/LSI/CSI/HSE/LSE),
clocks for few subsystem and peripheral interfaces.

This change add a SCMI clock dependency on RCC clock device since it
registers clocks which parent clocks are provided by the SCMI clock
driver. This change allows the RCC clock device probe to be deferred
until SCMI clocks are fully registered in the system.

Signed-off-by: Etienne Carriere 
Signed-off-by: Gabriel Fernandez 
---
 arch/arm/boot/dts/stm32mp151.dtsi  | 77 +++---
 arch/arm/boot/dts/stm32mp153.dtsi  |  4 +-
 arch/arm/boot/dts/stm32mp157.dtsi  |  2 +-
 arch/arm/boot/dts/stm32mp15xc.dtsi |  4 +-
 4 files changed, 32 insertions(+), 55 deletions(-)

diff --git a/arch/arm/boot/dts/stm32mp151.dtsi 
b/arch/arm/boot/dts/stm32mp151.dtsi
index da3647373365..e06882e0611d 100644
--- a/arch/arm/boot/dts/stm32mp151.dtsi
+++ b/arch/arm/boot/dts/stm32mp151.dtsi
@@ -102,38 +102,6 @@
interrupt-parent = <>;
};
 
-   clocks {
-   clk_hse: clk-hse {
-   #clock-cells = <0>;
-   compatible = "fixed-clock";
-   clock-frequency = <2400>;
-   };
-
-   clk_hsi: clk-hsi {
-   #clock-cells = <0>;
-   compatible = "fixed-clock";
-   clock-frequency = <6400>;
-   };
-
-   clk_lse: clk-lse {
-   #clock-cells = <0>;
-   compatible = "fixed-clock";
-   clock-frequency = <32768>;
-   };
-
-   clk_lsi: clk-lsi {
-   #clock-cells = <0>;
-   compatible = "fixed-clock";
-   clock-frequency = <32000>;
-   };
-
-   clk_csi: clk-csi {
-   #clock-cells = <0>;
-   compatible = "fixed-clock";
-   clock-frequency = <400>;
-   };
-   };
-
thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <0>;
@@ -595,7 +563,7 @@
compatible = "st,stm32-cec";
reg = <0x40016000 0x400>;
interrupts = ;
-   clocks = < CEC_K>, <_lse>;
+   clocks = < CEC_K>, <_clk CK_SCMI0_LSE>;
clock-names = "cec", "hdmi-cec";
status = "disabled";
};
@@ -1156,10 +1124,17 @@
};
 
rcc: rcc@5000 {
-   compatible = "st,stm32mp1-rcc", "syscon";
+   compatible = "st,stm32mp1-rcc-secure", 
"st,stm32mp1-rcc", "syscon";
reg = <0x5000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
+
+   clock-names = "hse", "hsi", "csi", "lse", "lsi";
+   clocks = <_clk CK_SCMI0_HSE>,
+<_clk CK_SCMI0_HSI>,
+<_clk CK_SCMI0_CSI>,
+<_clk CK_SCMI0_LSE>,
+<_clk CK_SCMI0_LSI>;
};
 
pwr_regulators: pwr@50001000 {
@@ -1342,8 +1317,8 @@
compatible = "st,stm32f756-hash";
reg = <0x54002000 0x400>;
interrupts = ;
-   clocks = < HASH1>;
-   resets = < HASH1_R>;
+   clocks = <_clk CK_SCMI0_HASH1>;
+   resets = <_reset RST_SCMI0_HASH1>;
dmas = < 31 0x2 0x1000A02 0x0 0x0>;
dma-names = "in";
dma-maxburst = <2>;
@@ -1353,8 +1328,8 @@
rng1: rng@54003000 {
compatible = "st,stm32-rng";
reg = <0x54003000 0x400>;
-   clocks = < RNG1_K>;
-   resets = < RNG1_R>;
+   clocks = <_clk CK_SCMI0_RNG1>;
+   resets = <_reset RST_SCMI0_RNG1>;
status = "disabled";
};
 
@@ -1363,7 +1338,7 @@
reg = <0x5800 0x1000>;
interrupts = ;
clocks = < MDMA>;
-   resets = < MDMA_R>;
+   resets = <_reset RST_SCMI0_MDMA>;
#dma-cells = <5>;
dma-channels = 

[PATCH v2 13/14] dt-bindings: clock: stm32mp1 new compatible for secure rcc

[gabriel.fernandez]

From: Gabriel Fernandez 

Introduce new compatible string "st,stm32mp1-rcc-secure" for
stm32mp1 clock driver when the device is configured with RCC
security support hardened.

Signed-off-by: Etienne Carriere 
Signed-off-by: Gabriel Fernandez 
---
 .../devicetree/bindings/clock/st,stm32mp1-rcc.yaml  | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml 
b/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml
index 4e385508f516..8b1ecb2ecdd5 100644
--- a/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml
+++ b/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml
@@ -54,7 +54,9 @@ properties:
 
   compatible:
 items:
-  - const: st,stm32mp1-rcc
+  - enum:
+  - st,stm32mp1-rcc-secure
+  - st,stm32mp1-rcc
   - const: syscon
 
   reg:
@@ -71,7 +73,7 @@ additionalProperties: false
 examples:
   - |
 rcc: rcc@5000 {
-compatible = "st,stm32mp1-rcc", "syscon";
+compatible = "st,stm32mp1-rcc-secure", "syscon";
 reg = <0x5000 0x1000>;
 #clock-cells = <1>;
 #reset-cells = <1>;
-- 
2.17.1

[PATCH v2 11/14] ARM: dts: stm32: define SCMI resources on stm32mp15

[gabriel.fernandez]

From: Gabriel Fernandez 

Platform stm32mp15 relies on SCMI resources (clocks and reset domains).
This change adds SCMI resources description in the platform device
tree. SCMI resources uses a mailbox based on some shared memory and
a SMC mailbox notification.

SCMI0 exposes clocks and reset controllers for resources under RCC[TZEN]
configuration control. It is default enabled as SoC default
configuration is RCC[TZEN]=1.

SCMI1 exposes clocks for resources under RCC[MCKPROT] control. The node
is disabled by default as default configuration is RCC[MCKPROT]=0.

Signed-off-by: Etienne Carriere 
Signed-off-by: Gabriel Fernandez 
---
 arch/arm/boot/dts/stm32mp151.dtsi | 50 +++
 1 file changed, 50 insertions(+)

diff --git a/arch/arm/boot/dts/stm32mp151.dtsi 
b/arch/arm/boot/dts/stm32mp151.dtsi
index 3c75abacb374..da3647373365 100644
--- a/arch/arm/boot/dts/stm32mp151.dtsi
+++ b/arch/arm/boot/dts/stm32mp151.dtsi
@@ -30,6 +30,56 @@
interrupt-parent = <>;
};
 
+   scmi_sram: sram@2000 {
+   compatible = "mmio-sram";
+   reg = <0x2000 0x1000>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges = <0 0x2000 0x1000>;
+
+   scmi0_shm: scmi_shm@0 {
+   reg = <0 0x80>;
+   };
+
+   scmi1_shm: scmi_shm@200 {
+   reg = <0x200 0x80>;
+   };
+   };
+
+   firmware {
+   scmi0: scmi0 {
+   compatible = "arm,scmi-smc";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   arm,smc-id = <0x82002000>;
+   shmem = <_shm>;
+
+   scmi0_clk: protocol@14 {
+   reg = <0x14>;
+   #clock-cells = <1>;
+   };
+
+   scmi0_reset: protocol@16 {
+   reg = <0x16>;
+   #reset-cells = <1>;
+   };
+   };
+
+   scmi1: scmi1 {
+   compatible = "arm,scmi-smc";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   arm,smc-id = <0x82002001>;
+   shmem = <_shm>;
+   status = "disabled";
+
+   scmi1_clk: protocol@14 {
+   reg = <0x14>;
+   #clock-cells = <1>;
+   };
+   };
+   };
+
psci {
compatible = "arm,psci-1.0";
method = "smc";
-- 
2.17.1

[PATCH v2 07/14] dt-bindings: clock: add IDs for SCMI clocks on stm32mp15

[gabriel.fernandez]

From: Gabriel Fernandez 

stm32mp15 TZ secure firmware provides SCMI clocks for oscillators, some
PLL output and few secure aware interfaces.
This change defines the SCMI clock identifiers used by SCMI agents
and servers.
Server SCMI0 exposes clocks and reset controllers for resources under
RCC[TZEN] configuration control.
Server SCMI1 exposes clocks for resources under RCC[MCKPROT] control.

Signed-off-by: Etienne Carriere 
Signed-off-by: Gabriel Fernandez 
---
 include/dt-bindings/clock/stm32mp1-clks.h | 27 +++
 1 file changed, 27 insertions(+)

diff --git a/include/dt-bindings/clock/stm32mp1-clks.h 
b/include/dt-bindings/clock/stm32mp1-clks.h
index 4cdaf135829c..e02770b98e6c 100644
--- a/include/dt-bindings/clock/stm32mp1-clks.h
+++ b/include/dt-bindings/clock/stm32mp1-clks.h
@@ -248,4 +248,31 @@
 
 #define STM32MP1_LAST_CLK 232
 
+/* SCMI clock identifiers */
+#define CK_SCMI0_HSE   0
+#define CK_SCMI0_HSI   1
+#define CK_SCMI0_CSI   2
+#define CK_SCMI0_LSE   3
+#define CK_SCMI0_LSI   4
+#define CK_SCMI0_PLL2_Q5
+#define CK_SCMI0_PLL2_R6
+#define CK_SCMI0_MPU   7
+#define CK_SCMI0_AXI   8
+#define CK_SCMI0_BSEC  9
+#define CK_SCMI0_CRYP1 10
+#define CK_SCMI0_GPIOZ 11
+#define CK_SCMI0_HASH1 12
+#define CK_SCMI0_I2C4  13
+#define CK_SCMI0_I2C6  14
+#define CK_SCMI0_IWDG1 15
+#define CK_SCMI0_RNG1  16
+#define CK_SCMI0_RTC   17
+#define CK_SCMI0_RTCAPB18
+#define CK_SCMI0_SPI6  19
+#define CK_SCMI0_USART120
+
+#define CK_SCMI1_PLL3_Q0
+#define CK_SCMI1_PLL3_R1
+#define CK_SCMI1_MCU   2
+
 #endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */
-- 
2.17.1

[PATCH v2 10/14] clk: stm32mp1: new compatible for secure RCC support

[gabriel.fernandez]

From: Gabriel Fernandez 

Platform STM32MP1 can be used in configuration where some clock
resources cannot be accessed by Linux kernel when executing in non-secure
state of the CPU(s).
In such configuration, the RCC clock driver must not register clocks
it cannot access.
They are expected to be registered from another clock driver such
as the SCMI clock driver.
This change uses specific compatible string "st,stm32mp1-rcc-secure"
to specify RCC clock driver configuration where RCC is secure.

Signed-off-by: Etienne Carriere 
Signed-off-by: Gabriel Fernandez 
---
 drivers/clk/Kconfig|  10 
 drivers/clk/clk-stm32mp1.c | 101 -
 2 files changed, 110 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 85856cff506c..52e9cf36731c 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -334,6 +334,16 @@ config COMMON_CLK_STM32MP157
help
  Support for stm32mp157 SoC family clocks
 
+config COMMON_CLK_STM32MP157_SCMI
+   bool "stm32mp157 Clock driver with Trusted Firmware"
+   depends on COMMON_CLK_STM32MP157
+   select COMMON_CLK_SCMI
+   select ARM_SCMI_PROTOCOL
+   default y
+   help
+ Support for stm32mp157 SoC family clocks with Trusted Firmware using
+ SCMI protocol.
+
 config COMMON_CLK_STM32F
def_bool COMMON_CLK && (MACH_STM32F429 || MACH_STM32F469 || 
MACH_STM32F746)
help
diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index 25e3f272344c..132e1dd42dbd 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -2051,11 +2051,61 @@ static const struct clock_config stm32mp1_clock_cfg[] = 
{
  _DIV(RCC_DBGCFGR, 0, 3, 0, ck_trace_div_table)),
 };
 
+static const u32 stm32mp1_clock_secured[] = {
+   CK_HSE,
+   CK_HSI,
+   CK_CSI,
+   CK_LSI,
+   CK_LSE,
+   PLL1,
+   PLL2,
+   PLL1_P,
+   PLL2_P,
+   PLL2_Q,
+   PLL2_R,
+   CK_MPU,
+   CK_AXI,
+   SPI6,
+   I2C4,
+   I2C6,
+   USART1,
+   RTCAPB,
+   TZC1,
+   TZC2,
+   TZPC,
+   IWDG1,
+   BSEC,
+   STGEN,
+   GPIOZ,
+   CRYP1,
+   HASH1,
+   RNG1,
+   BKPSRAM,
+   RNG1_K,
+   STGEN_K,
+   SPI6_K,
+   I2C4_K,
+   I2C6_K,
+   USART1_K,
+   RTC,
+};
+
+static bool stm32_check_security(const struct clock_config *cfg)
+{
+   int i;
+
+   for (i = 0; i < ARRAY_SIZE(stm32mp1_clock_secured); i++)
+   if (cfg->id == stm32mp1_clock_secured[i])
+   return true;
+   return false;
+}
+
 struct stm32_rcc_match_data {
const struct clock_config *cfg;
unsigned int num;
unsigned int maxbinding;
u32 clear_offset;
+   bool (*check_security)(const struct clock_config *cfg);
 };
 
 static struct stm32_rcc_match_data stm32mp1_data = {
@@ -2065,11 +2115,23 @@ static struct stm32_rcc_match_data stm32mp1_data = {
.clear_offset   = RCC_CLR,
 };
 
+static struct stm32_rcc_match_data stm32mp1_data_secure = {
+   .cfg= stm32mp1_clock_cfg,
+   .num= ARRAY_SIZE(stm32mp1_clock_cfg),
+   .maxbinding = STM32MP1_LAST_CLK,
+   .clear_offset   = RCC_CLR,
+   .check_security = _check_security
+};
+
 static const struct of_device_id stm32mp1_match_data[] = {
{
.compatible = "st,stm32mp1-rcc",
.data = _data,
},
+   {
+   .compatible = "st,stm32mp1-rcc-secure",
+   .data = _data_secure,
+   },
{ }
 };
 MODULE_DEVICE_TABLE(of, stm32mp1_match_data);
@@ -2229,6 +2291,9 @@ static int stm32_rcc_clock_init(struct device *dev, void 
__iomem *base,
hws[n] = ERR_PTR(-ENOENT);
 
for (n = 0; n < data->num; n++) {
+   if (data->check_security && data->check_security(>cfg[n]))
+   continue;
+
err = stm32_register_hw_clk(dev, clk_data, base, ,
>cfg[n]);
if (err) {
@@ -2296,11 +2361,45 @@ static int stm32mp1_rcc_init(struct device *dev)
return ret;
 }
 
+static int get_clock_deps(struct device *dev)
+{
+   static const char * const clock_deps_name[] = {
+   "hsi", "hse", "csi", "lsi", "lse",
+   };
+   size_t deps_size = sizeof(struct clk *) * ARRAY_SIZE(clock_deps_name);
+   struct clk **clk_deps;
+   int i;
+
+   clk_deps = devm_kzalloc(dev, deps_size, GFP_KERNEL);
+   if (!clk_deps)
+   return -ENOMEM;
+
+   for (i = 0; i < ARRAY_SIZE(clock_deps_name); i++) {
+   struct clk *clk = of_clk_get_by_name(dev_of_node(dev),
+clock_deps_name[i]);
+
+   if (IS_ERR(clk)) {
+   if (PTR_ERR(clk) != -EINVAL && PTR_ERR(clk) != -ENOENT)
+ 

[PATCH v2 02/14] clk: stm32mp1: merge 'ck_hse_rtc' and 'ck_rtc' into one clock

[gabriel.fernandez]

From: Gabriel Fernandez 

'ck_rtc' has multiple clocks as input (ck_hsi, ck_lsi, and ck_hse).
A divider is available only on the specific rtc input for ck_hse.
This Merge will facilitate to have a more coherent clock tree
in no trusted / trusted world.

Signed-off-by: Gabriel Fernandez 
---
 drivers/clk/clk-stm32mp1.c | 49 +-
 1 file changed, 43 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index 35d5aee8f9b0..0e1d4427a8df 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -245,7 +245,7 @@ static const char * const dsi_src[] = {
 };
 
 static const char * const rtc_src[] = {
-   "off", "ck_lse", "ck_lsi", "ck_hse_rtc"
+   "off", "ck_lse", "ck_lsi", "ck_hse"
 };
 
 static const char * const mco1_src[] = {
@@ -1031,6 +1031,42 @@ static struct clk_hw *clk_register_cktim(struct device 
*dev, const char *name,
return hw;
 }
 
+/* The divider of RTC clock concerns only ck_hse clock */
+#define HSE_RTC 3
+
+static unsigned long clk_divider_rtc_recalc_rate(struct clk_hw *hw,
+unsigned long parent_rate)
+{
+   if (clk_hw_get_parent(hw) == clk_hw_get_parent_by_index(hw, HSE_RTC))
+   return clk_divider_ops.recalc_rate(hw, parent_rate);
+
+   return parent_rate;
+}
+
+static long clk_divider_rtc_round_rate(struct clk_hw *hw, unsigned long rate,
+  unsigned long *prate)
+{
+   if (clk_hw_get_parent(hw) == clk_hw_get_parent_by_index(hw, HSE_RTC))
+   return clk_divider_ops.round_rate(hw, rate, prate);
+
+   return *prate;
+}
+
+static int clk_divider_rtc_set_rate(struct clk_hw *hw, unsigned long rate,
+   unsigned long parent_rate)
+{
+   if (clk_hw_get_parent(hw) == clk_hw_get_parent_by_index(hw, HSE_RTC))
+   return clk_divider_ops.set_rate(hw, rate, parent_rate);
+
+   return parent_rate;
+}
+
+static const struct clk_ops rtc_div_clk_ops = {
+   .recalc_rate= clk_divider_rtc_recalc_rate,
+   .round_rate = clk_divider_rtc_round_rate,
+   .set_rate   = clk_divider_rtc_set_rate,
+};
+
 struct stm32_pll_cfg {
u32 offset;
 };
@@ -1243,6 +1279,10 @@ _clk_stm32_register_composite(struct device *dev,
_STM32_DIV(_div_offset, _div_shift, _div_width,\
   _div_flags, _div_table, NULL)\
 
+#define _DIV_RTC(_div_offset, _div_shift, _div_width, _div_flags, _div_table)\
+   _STM32_DIV(_div_offset, _div_shift, _div_width,\
+  _div_flags, _div_table, _div_clk_ops)
+
 #define _STM32_MUX(_offset, _shift, _width, _mux_flags, _mmux, _ops)\
.mux = &(struct stm32_mux_cfg) {\
&(struct mux_cfg) {\
@@ -1965,13 +2005,10 @@ static const struct clock_config stm32mp1_clock_cfg[] = 
{
  _DIV(RCC_ETHCKSELR, 4, 4, 0, NULL)),
 
/* RTC clock */
-   DIV(NO_ID, "ck_hse_rtc", "ck_hse", 0, RCC_RTCDIVR, 0, 6, 0),
-
-   COMPOSITE(RTC, "ck_rtc", rtc_src, CLK_OPS_PARENT_ENABLE |
-  CLK_SET_RATE_PARENT,
+   COMPOSITE(RTC, "ck_rtc", rtc_src, CLK_OPS_PARENT_ENABLE,
  _GATE(RCC_BDCR, 20, 0),
  _MUX(RCC_BDCR, 16, 2, 0),
- _NO_DIV),
+ _DIV_RTC(RCC_RTCDIVR, 0, 6, 0, NULL)),
 
/* MCO clocks */
COMPOSITE(CK_MCO1, "ck_mco1", mco1_src, CLK_OPS_PARENT_ENABLE |
-- 
2.17.1

[PATCH v2 00/14] Introduce STM32MP1 RCC in secured mode

[gabriel.fernandez]

From: Gabriel Fernandez 

Platform STM32MP1 can be used in configuration where some clocks and
IP resets can relate as secure resources.
These resources are moved from a RCC clock/reset handle to a SCMI
clock/reset_domain handle.

The RCC clock driver is now dependent of the SCMI driver, then we have
to manage now the probe defering.

v1 -> v2:
  - fix yamllint warnings.

Gabriel Fernandez (14):
  clk: stm32mp1: merge 'clk-hsi-div' and 'ck_hsi' into one clock
  clk: stm32mp1: merge 'ck_hse_rtc' and 'ck_rtc' into one clock
  clk: stm32mp1: remove intermediate pll clocks
  clk: stm32mp1: convert to module driver
  clk: stm32mp1: move RCC reset controller into RCC clock driver
  reset: stm32mp1: remove stm32mp1 reset
  dt-bindings: clock: add IDs for SCMI clocks on stm32mp15
  dt-bindings: reset: add IDs for SCMI reset domains on stm32mp15
  dt-bindings: reset: add MCU HOLD BOOT ID for SCMI reset domains on
stm32mp15
  clk: stm32mp1: new compatible for secure RCC support
  ARM: dts: stm32: define SCMI resources on stm32mp15
  ARM: dts: stm32: move clocks/resets to SCMI resources for stm32mp15
  dt-bindings: clock: stm32mp1 new compatible for secure rcc
  ARM: dts: stm32: introduce basic boot include on stm32mp15x board

 .../bindings/clock/st,stm32mp1-rcc.yaml   |   6 +-
 arch/arm/boot/dts/stm32mp15-no-scmi.dtsi  | 158 ++
 arch/arm/boot/dts/stm32mp151.dtsi | 127 +++--
 arch/arm/boot/dts/stm32mp153.dtsi |   4 +-
 arch/arm/boot/dts/stm32mp157.dtsi |   2 +-
 arch/arm/boot/dts/stm32mp15xc.dtsi|   4 +-
 drivers/clk/Kconfig   |  10 +
 drivers/clk/clk-stm32mp1.c| 495 +++---
 drivers/reset/Kconfig |   6 -
 drivers/reset/Makefile|   1 -
 drivers/reset/reset-stm32mp1.c| 115 
 include/dt-bindings/clock/stm32mp1-clks.h |  27 +
 include/dt-bindings/reset/stm32mp1-resets.h   |  15 +
 13 files changed, 704 insertions(+), 266 deletions(-)
 create mode 100644 arch/arm/boot/dts/stm32mp15-no-scmi.dtsi
 delete mode 100644 drivers/reset/reset-stm32mp1.c

-- 
2.17.1

[PATCH v2 09/14] dt-bindings: reset: add MCU HOLD BOOT ID for SCMI reset domains on stm32mp15

[gabriel.fernandez]

From: Gabriel Fernandez 

Add ID to SCMI0 to exposes reset controller for the MCU HOLD BOOT resource.

Signed-off-by: Arnaud Pouliquen 
Signed-off-by: Gabriel Fernandez 
---
 include/dt-bindings/reset/stm32mp1-resets.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/dt-bindings/reset/stm32mp1-resets.h 
b/include/dt-bindings/reset/stm32mp1-resets.h
index bc71924faa54..f3a0ed317835 100644
--- a/include/dt-bindings/reset/stm32mp1-resets.h
+++ b/include/dt-bindings/reset/stm32mp1-resets.h
@@ -7,6 +7,7 @@
 #ifndef _DT_BINDINGS_STM32MP1_RESET_H_
 #define _DT_BINDINGS_STM32MP1_RESET_H_
 
+#define MCU_HOLD_BOOT_R2144
 #define LTDC_R 3072
 #define DSI_R  3076
 #define DDRPERFM_R 3080
@@ -117,5 +118,6 @@
 #define RST_SCMI0_RNG1 8
 #define RST_SCMI0_MDMA 9
 #define RST_SCMI0_MCU  10
+#define RST_SCMI0_MCU_HOLD_BOOT11
 
 #endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */
-- 
2.17.1

[PATCH v2 06/14] reset: stm32mp1: remove stm32mp1 reset

[gabriel.fernandez]

From: Gabriel Fernandez 

st32mp1 RCC reset driver was moved into stm32mp1 RCC clock driver.

Signed-off-by: Gabriel Fernandez 
---
 drivers/reset/Kconfig  |   6 --
 drivers/reset/Makefile |   1 -
 drivers/reset/reset-stm32mp1.c | 115 -
 3 files changed, 122 deletions(-)
 delete mode 100644 drivers/reset/reset-stm32mp1.c

diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 71ab75a46491..6c58056f1732 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -188,12 +188,6 @@ config RESET_SIMPLE
   - Allwinner SoCs
   - ZTE's zx2967 family
 
-config RESET_STM32MP157
-   bool "STM32MP157 Reset Driver" if COMPILE_TEST
-   default MACH_STM32MP157
-   help
- This enables the RCC reset controller driver for STM32 MPUs.
-
 config RESET_SOCFPGA
bool "SoCFPGA Reset Driver" if COMPILE_TEST && !ARCH_SOCFPGA
default ARCH_SOCFPGA
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 1054123fd187..c17f5b3c641e 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -25,7 +25,6 @@ obj-$(CONFIG_RESET_QCOM_PDC) += reset-qcom-pdc.o
 obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o
 obj-$(CONFIG_RESET_SCMI) += reset-scmi.o
 obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
-obj-$(CONFIG_RESET_STM32MP157) += reset-stm32mp1.o
 obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
 obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
 obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
diff --git a/drivers/reset/reset-stm32mp1.c b/drivers/reset/reset-stm32mp1.c
deleted file mode 100644
index b221a28041fa..
--- a/drivers/reset/reset-stm32mp1.c
+++ /dev/null
@@ -1,115 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
- * Author: Gabriel Fernandez  for STMicroelectronics.
- */
-
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-#define CLR_OFFSET 0x4
-
-struct stm32_reset_data {
-   struct reset_controller_dev rcdev;
-   void __iomem*membase;
-};
-
-static inline struct stm32_reset_data *
-to_stm32_reset_data(struct reset_controller_dev *rcdev)
-{
-   return container_of(rcdev, struct stm32_reset_data, rcdev);
-}
-
-static int stm32_reset_update(struct reset_controller_dev *rcdev,
- unsigned long id, bool assert)
-{
-   struct stm32_reset_data *data = to_stm32_reset_data(rcdev);
-   int reg_width = sizeof(u32);
-   int bank = id / (reg_width * BITS_PER_BYTE);
-   int offset = id % (reg_width * BITS_PER_BYTE);
-   void __iomem *addr;
-
-   addr = data->membase + (bank * reg_width);
-   if (!assert)
-   addr += CLR_OFFSET;
-
-   writel(BIT(offset), addr);
-
-   return 0;
-}
-
-static int stm32_reset_assert(struct reset_controller_dev *rcdev,
- unsigned long id)
-{
-   return stm32_reset_update(rcdev, id, true);
-}
-
-static int stm32_reset_deassert(struct reset_controller_dev *rcdev,
-   unsigned long id)
-{
-   return stm32_reset_update(rcdev, id, false);
-}
-
-static int stm32_reset_status(struct reset_controller_dev *rcdev,
- unsigned long id)
-{
-   struct stm32_reset_data *data = to_stm32_reset_data(rcdev);
-   int reg_width = sizeof(u32);
-   int bank = id / (reg_width * BITS_PER_BYTE);
-   int offset = id % (reg_width * BITS_PER_BYTE);
-   u32 reg;
-
-   reg = readl(data->membase + (bank * reg_width));
-
-   return !!(reg & BIT(offset));
-}
-
-static const struct reset_control_ops stm32_reset_ops = {
-   .assert = stm32_reset_assert,
-   .deassert   = stm32_reset_deassert,
-   .status = stm32_reset_status,
-};
-
-static const struct of_device_id stm32_reset_dt_ids[] = {
-   { .compatible = "st,stm32mp1-rcc"},
-   { /* sentinel */ },
-};
-
-static int stm32_reset_probe(struct platform_device *pdev)
-{
-   struct device *dev = >dev;
-   struct stm32_reset_data *data;
-   void __iomem *membase;
-   struct resource *res;
-
-   data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
-   if (!data)
-   return -ENOMEM;
-
-   res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-   membase = devm_ioremap_resource(dev, res);
-   if (IS_ERR(membase))
-   return PTR_ERR(membase);
-
-   data->membase = membase;
-   data->rcdev.owner = THIS_MODULE;
-   data->rcdev.nr_resets = resource_size(res) * BITS_PER_BYTE;
-   data->rcdev.ops = _reset_ops;
-   data->rcdev.of_node = dev->of_node;
-
-   return devm_reset_controller_register(dev, >rcdev);
-}
-
-static struct platform_driver stm32_reset_driver = {
-   .probe  = stm32_reset_probe,
-   .driver = {
-   .name   = "stm32mp1-reset",
-   .of_match_table = stm32_reset_dt_ids,
-   },
-};
-

[PATCH v2 03/14] clk: stm32mp1: remove intermediate pll clocks

[gabriel.fernandez]

From: Gabriel Fernandez 

This patch is to prepare STM32MP1 clocks in trusted mode.
Integrate the mux clock into pll clock will facilitate to have a more
coherent clock tree in no trusted / trusted mode.

Signed-off-by: Gabriel Fernandez 
---
 drivers/clk/clk-stm32mp1.c | 65 --
 1 file changed, 42 insertions(+), 23 deletions(-)

diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index 0e1d4427a8df..ee6968a2ad57 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -731,6 +731,7 @@ struct stm32_pll_obj {
spinlock_t *lock;
void __iomem *reg;
struct clk_hw hw;
+   struct clk_mux mux;
 };
 
 #define to_pll(_hw) container_of(_hw, struct stm32_pll_obj, hw)
@@ -745,6 +746,8 @@ struct stm32_pll_obj {
 #define FRAC_MASK  0x1FFF
 #define FRAC_SHIFT 3
 #define FRACLE BIT(16)
+#define PLL_MUX_SHIFT  0
+#define PLL_MUX_MASK   3
 
 static int __pll_is_enabled(struct clk_hw *hw)
 {
@@ -856,16 +859,29 @@ static int pll_is_enabled(struct clk_hw *hw)
return ret;
 }
 
+static u8 pll_get_parent(struct clk_hw *hw)
+{
+   struct stm32_pll_obj *clk_elem = to_pll(hw);
+   struct clk_hw *mux_hw = _elem->mux.hw;
+
+   __clk_hw_set_clk(mux_hw, hw);
+
+   return clk_mux_ops.get_parent(mux_hw);
+}
+
 static const struct clk_ops pll_ops = {
.enable = pll_enable,
.disable= pll_disable,
.recalc_rate= pll_recalc_rate,
.is_enabled = pll_is_enabled,
+   .get_parent = pll_get_parent,
 };
 
 static struct clk_hw *clk_register_pll(struct device *dev, const char *name,
-  const char *parent_name,
+  const char * const *parent_names,
+  int num_parents,
   void __iomem *reg,
+  void __iomem *mux_reg,
   unsigned long flags,
   spinlock_t *lock)
 {
@@ -881,8 +897,15 @@ static struct clk_hw *clk_register_pll(struct device *dev, 
const char *name,
init.name = name;
init.ops = _ops;
init.flags = flags;
-   init.parent_names = _name;
-   init.num_parents = 1;
+   init.parent_names = parent_names;
+   init.num_parents = num_parents;
+
+   element->mux.lock = lock;
+   element->mux.reg =  mux_reg;
+   element->mux.shift = PLL_MUX_SHIFT;
+   element->mux.mask =  PLL_MUX_MASK;
+   element->mux.flags =  CLK_MUX_READ_ONLY;
+   element->mux.reg =  mux_reg;
 
element->hw.init = 
element->reg = reg;
@@ -1069,6 +1092,7 @@ static const struct clk_ops rtc_div_clk_ops = {
 
 struct stm32_pll_cfg {
u32 offset;
+   u32 muxoff;
 };
 
 static struct clk_hw *_clk_register_pll(struct device *dev,
@@ -1078,8 +1102,11 @@ static struct clk_hw *_clk_register_pll(struct device 
*dev,
 {
struct stm32_pll_cfg *stm_pll_cfg = cfg->cfg;
 
-   return clk_register_pll(dev, cfg->name, cfg->parent_name,
-   base + stm_pll_cfg->offset, cfg->flags, lock);
+   return clk_register_pll(dev, cfg->name, cfg->parent_names,
+   cfg->num_parents,
+   base + stm_pll_cfg->offset,
+   base + stm_pll_cfg->muxoff,
+   cfg->flags, lock);
 }
 
 struct stm32_cktim_cfg {
@@ -1189,14 +1216,16 @@ _clk_stm32_register_composite(struct device *dev,
.func   = _clk_hw_register_mux,\
 }
 
-#define PLL(_id, _name, _parent, _flags, _offset)\
+#define PLL(_id, _name, _parents, _flags, _offset_p, _offset_mux)\
 {\
.id = _id,\
.name   = _name,\
-   .parent_name= _parent,\
-   .flags  = _flags,\
+   .parent_names   = _parents,\
+   .num_parents= ARRAY_SIZE(_parents),\
+   .flags  = CLK_IGNORE_UNUSED | (_flags),\
.cfg=  &(struct stm32_pll_cfg) {\
-   .offset = _offset,\
+   .offset = _offset_p,\
+   .muxoff = _offset_mux,\
},\
.func   = _clk_register_pll,\
 }
@@ -1712,21 +1741,11 @@ static const struct clock_config stm32mp1_clock_cfg[] = 
{
 
FIXED_FACTOR(CK_HSE_DIV2, "clk-hse-div2", "ck_hse", 0, 1, 2),
 
-   /* ref clock pll */
-   MUX(NO_ID, "ref1", ref12_parents, CLK_OPS_PARENT_ENABLE, RCC_RCK12SELR,
-   0, 2, CLK_MUX_READ_ONLY),
-
-   MUX(NO_ID, "ref3", ref3_parents, CLK_OPS_PARENT_ENABLE, RCC_RCK3SELR,
-   0, 2, CLK_MUX_READ_ONLY),
-
-   MUX(NO_ID, "ref4", ref4_parents, CLK_OPS_PARENT_ENABLE, RCC_RCK4SELR,
-   0, 2, CLK_MUX_READ_ONLY),
-
/* PLLs */
-   PLL(PLL1, "pll1", "ref1", CLK_IGNORE_UNUSED, RCC_PLL1CR),
-   PLL(PLL2, "pll2", "ref1", CLK_IGNORE_UNUSED, RCC_PLL2CR),
-   

[PATCH v2 01/14] clk: stm32mp1: merge 'clk-hsi-div' and 'ck_hsi' into one clock

[gabriel.fernandez]

From: Gabriel Fernandez 

This patch is to prepare STM32MP1 clocks in trusted mode.
This Merge will facilitate to have a more coherent clock tree
in no trusted / trusted world.

Signed-off-by: Gabriel Fernandez 
---
 drivers/clk/clk-stm32mp1.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index a875649df8b8..35d5aee8f9b0 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -1657,16 +1657,16 @@ static const struct stm32_mux_cfg ker_mux_cfg[M_LAST] = 
{
 };
 
 static const struct clock_config stm32mp1_clock_cfg[] = {
-   /* Oscillator divider */
-   DIV(NO_ID, "clk-hsi-div", "clk-hsi", CLK_DIVIDER_POWER_OF_TWO,
-   RCC_HSICFGR, 0, 2, CLK_DIVIDER_READ_ONLY),
-
/*  External / Internal Oscillators */
GATE_MP1(CK_HSE, "ck_hse", "clk-hse", 0, RCC_OCENSETR, 8, 0),
/* ck_csi is used by IO compensation and should be critical */
GATE_MP1(CK_CSI, "ck_csi", "clk-csi", CLK_IS_CRITICAL,
 RCC_OCENSETR, 4, 0),
-   GATE_MP1(CK_HSI, "ck_hsi", "clk-hsi-div", 0, RCC_OCENSETR, 0, 0),
+   COMPOSITE(CK_HSI, "ck_hsi", PARENT("clk-hsi"), 0,
+ _GATE_MP1(RCC_OCENSETR, 0, 0),
+ _NO_MUX,
+ _DIV(RCC_HSICFGR, 0, 2, CLK_DIVIDER_POWER_OF_TWO |
+  CLK_DIVIDER_READ_ONLY, NULL)),
GATE(CK_LSI, "ck_lsi", "clk-lsi", 0, RCC_RDLSICR, 0, 0),
GATE(CK_LSE, "ck_lse", "clk-lse", 0, RCC_BDCR, 0, 0),
 
-- 
2.17.1

[PATCH v2 04/14] clk: stm32mp1: convert to module driver

[gabriel.fernandez]

From: Gabriel Fernandez 

Adds support for  probe deferral in way to prepare
integration of the security in RCC clock and reset
drivers.
Some kernel clocks will be provided by the SCMI drivers.
Since RCC clock driver create clocks which parents
are SCMI clocks, RCC clock driver probe can be deferred.

Signed-off-by: Etienne Carriere 
Signed-off-by: Gabriel Fernandez 
---
 drivers/clk/clk-stm32mp1.c | 121 -
 1 file changed, 78 insertions(+), 43 deletions(-)

diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index ee6968a2ad57..530babc4c4b6 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -10,8 +10,10 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -469,7 +471,7 @@ static const struct clk_ops mp1_gate_clk_ops = {
.is_enabled = clk_gate_is_enabled,
 };
 
-static struct clk_hw *_get_stm32_mux(void __iomem *base,
+static struct clk_hw *_get_stm32_mux(struct device *dev, void __iomem *base,
 const struct stm32_mux_cfg *cfg,
 spinlock_t *lock)
 {
@@ -478,7 +480,7 @@ static struct clk_hw *_get_stm32_mux(void __iomem *base,
struct clk_hw *mux_hw;
 
if (cfg->mmux) {
-   mmux = kzalloc(sizeof(*mmux), GFP_KERNEL);
+   mmux = devm_kzalloc(dev, sizeof(*mmux), GFP_KERNEL);
if (!mmux)
return ERR_PTR(-ENOMEM);
 
@@ -493,7 +495,7 @@ static struct clk_hw *_get_stm32_mux(void __iomem *base,
cfg->mmux->hws[cfg->mmux->nbr_clk++] = mux_hw;
 
} else {
-   mux = kzalloc(sizeof(*mux), GFP_KERNEL);
+   mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
if (!mux)
return ERR_PTR(-ENOMEM);
 
@@ -509,13 +511,13 @@ static struct clk_hw *_get_stm32_mux(void __iomem *base,
return mux_hw;
 }
 
-static struct clk_hw *_get_stm32_div(void __iomem *base,
+static struct clk_hw *_get_stm32_div(struct device *dev, void __iomem *base,
 const struct stm32_div_cfg *cfg,
 spinlock_t *lock)
 {
struct clk_divider *div;
 
-   div = kzalloc(sizeof(*div), GFP_KERNEL);
+   div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
 
if (!div)
return ERR_PTR(-ENOMEM);
@@ -530,16 +532,16 @@ static struct clk_hw *_get_stm32_div(void __iomem *base,
return >hw;
 }
 
-static struct clk_hw *
-_get_stm32_gate(void __iomem *base,
-   const struct stm32_gate_cfg *cfg, spinlock_t *lock)
+static struct clk_hw *_get_stm32_gate(struct device *dev, void __iomem *base,
+ const struct stm32_gate_cfg *cfg,
+ spinlock_t *lock)
 {
struct stm32_clk_mgate *mgate;
struct clk_gate *gate;
struct clk_hw *gate_hw;
 
if (cfg->mgate) {
-   mgate = kzalloc(sizeof(*mgate), GFP_KERNEL);
+   mgate = devm_kzalloc(dev, sizeof(*mgate), GFP_KERNEL);
if (!mgate)
return ERR_PTR(-ENOMEM);
 
@@ -554,7 +556,7 @@ _get_stm32_gate(void __iomem *base,
gate_hw = >gate.hw;
 
} else {
-   gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+   gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL);
if (!gate)
return ERR_PTR(-ENOMEM);
 
@@ -592,7 +594,7 @@ clk_stm32_register_gate_ops(struct device *dev,
if (cfg->ops)
init.ops = cfg->ops;
 
-   hw = _get_stm32_gate(base, cfg, lock);
+   hw = _get_stm32_gate(dev, base, cfg, lock);
if (IS_ERR(hw))
return ERR_PTR(-ENOMEM);
 
@@ -623,7 +625,7 @@ clk_stm32_register_composite(struct device *dev,
gate_ops = NULL;
 
if (cfg->mux) {
-   mux_hw = _get_stm32_mux(base, cfg->mux, lock);
+   mux_hw = _get_stm32_mux(dev, base, cfg->mux, lock);
 
if (!IS_ERR(mux_hw)) {
mux_ops = _mux_ops;
@@ -634,7 +636,7 @@ clk_stm32_register_composite(struct device *dev,
}
 
if (cfg->div) {
-   div_hw = _get_stm32_div(base, cfg->div, lock);
+   div_hw = _get_stm32_div(dev, base, cfg->div, lock);
 
if (!IS_ERR(div_hw)) {
div_ops = _divider_ops;
@@ -645,7 +647,7 @@ clk_stm32_register_composite(struct device *dev,
}
 
if (cfg->gate) {
-   gate_hw = _get_stm32_gate(base, cfg->gate, lock);
+   gate_hw = _get_stm32_gate(dev, base, cfg->gate, lock);
 
if (!IS_ERR(gate_hw)) {
gate_ops = _gate_ops;
@@ -890,7 +892,7 @@ static struct clk_hw *clk_register_pll(struct device *dev, 
const char *name,
struct clk_hw *hw;
int err;
 
-   

[PATCH v2 08/14] dt-bindings: reset: add IDs for SCMI reset domains on stm32mp15

[gabriel.fernandez]

From: Gabriel Fernandez 

stm32mp15 TZ secure firmware provides SCMI reset domains for
secure resources. This change defines the SCMI reset domain
identifiers used by SCMI agents and servers.

Stm32mp15 TZ secure firmware provides SCMI clocks for oscillators, some
PLL output and few secure aware interfaces. This change defines the
SCMI clock identifiers used by SCMI agents and servers.

Server SCMI0 exposes reset controllers for resources under RCC[TZEN]
configuration control.

Signed-off-by: Etienne Carriere 
Signed-off-by: Gabriel Fernandez 
---
 include/dt-bindings/reset/stm32mp1-resets.h | 13 +
 1 file changed, 13 insertions(+)

diff --git a/include/dt-bindings/reset/stm32mp1-resets.h 
b/include/dt-bindings/reset/stm32mp1-resets.h
index f0c3aaef67a0..bc71924faa54 100644
--- a/include/dt-bindings/reset/stm32mp1-resets.h
+++ b/include/dt-bindings/reset/stm32mp1-resets.h
@@ -105,4 +105,17 @@
 #define GPIOJ_R19785
 #define GPIOK_R19786
 
+/* SCMI reset domain identifiers */
+#define RST_SCMI0_SPI6 0
+#define RST_SCMI0_I2C4 1
+#define RST_SCMI0_I2C6 2
+#define RST_SCMI0_USART1   3
+#define RST_SCMI0_STGEN4
+#define RST_SCMI0_GPIOZ5
+#define RST_SCMI0_CRYP16
+#define RST_SCMI0_HASH17
+#define RST_SCMI0_RNG1 8
+#define RST_SCMI0_MDMA 9
+#define RST_SCMI0_MCU  10
+
 #endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */
-- 
2.17.1

[PATCH v2 05/14] clk: stm32mp1: move RCC reset controller into RCC clock driver

[gabriel.fernandez]

From: Gabriel Fernandez 

RCC clock and reset controller shared same memory mapping.
As RCC clock driver is now a module, the best way to register clock
and reset controller is to do it in same driver.

Signed-off-by: Gabriel Fernandez 
---
 drivers/clk/clk-stm32mp1.c | 157 ++---
 1 file changed, 144 insertions(+), 13 deletions(-)

diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index 530babc4c4b6..25e3f272344c 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -14,6 +14,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -2050,16 +2051,18 @@ static const struct clock_config stm32mp1_clock_cfg[] = 
{
  _DIV(RCC_DBGCFGR, 0, 3, 0, ck_trace_div_table)),
 };
 
-struct stm32_clock_match_data {
+struct stm32_rcc_match_data {
const struct clock_config *cfg;
unsigned int num;
unsigned int maxbinding;
+   u32 clear_offset;
 };
 
-static struct stm32_clock_match_data stm32mp1_data = {
+static struct stm32_rcc_match_data stm32mp1_data = {
.cfg= stm32mp1_clock_cfg,
.num= ARRAY_SIZE(stm32mp1_clock_cfg),
.maxbinding = STM32MP1_LAST_CLK,
+   .clear_offset   = RCC_CLR,
 };
 
 static const struct of_device_id stm32mp1_match_data[] = {
@@ -2095,23 +2098,122 @@ static int stm32_register_hw_clk(struct device *dev,
return 0;
 }
 
-static int stm32_rcc_init(struct device *dev, void __iomem *base,
- const struct of_device_id *match_data)
+#define STM32_RESET_ID_MASK GENMASK(15, 0)
+
+struct stm32_reset_data {
+   /* reset lock */
+   spinlock_t  lock;
+   struct reset_controller_dev rcdev;
+   void __iomem*membase;
+   u32 clear_offset;
+};
+
+static inline struct stm32_reset_data *
+to_stm32_reset_data(struct reset_controller_dev *rcdev)
 {
-   struct clk_hw_onecell_data *clk_data;
-   struct clk_hw **hws;
-   const struct of_device_id *match;
-   const struct stm32_clock_match_data *data;
-   int err, n, max_binding;
+   return container_of(rcdev, struct stm32_reset_data, rcdev);
+}
 
-   match = of_match_node(match_data, dev_of_node(dev));
-   if (!match) {
-   dev_err(dev, "match data not found\n");
-   return -ENODEV;
+static int stm32_reset_update(struct reset_controller_dev *rcdev,
+ unsigned long id, bool assert)
+{
+   struct stm32_reset_data *data = to_stm32_reset_data(rcdev);
+   int reg_width = sizeof(u32);
+   int bank = id / (reg_width * BITS_PER_BYTE);
+   int offset = id % (reg_width * BITS_PER_BYTE);
+
+   if (data->clear_offset) {
+   void __iomem *addr;
+
+   addr = data->membase + (bank * reg_width);
+   if (!assert)
+   addr += data->clear_offset;
+
+   writel(BIT(offset), addr);
+
+   } else {
+   unsigned long flags;
+   u32 reg;
+
+   spin_lock_irqsave(>lock, flags);
+
+   reg = readl(data->membase + (bank * reg_width));
+
+   if (assert)
+   reg |= BIT(offset);
+   else
+   reg &= ~BIT(offset);
+
+   writel(reg, data->membase + (bank * reg_width));
+
+   spin_unlock_irqrestore(>lock, flags);
}
 
+   return 0;
+}
+
+static int stm32_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+   return stm32_reset_update(rcdev, id, true);
+}
+
+static int stm32_reset_deassert(struct reset_controller_dev *rcdev,
+   unsigned long id)
+{
+   return stm32_reset_update(rcdev, id, false);
+}
+
+static int stm32_reset_status(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+   struct stm32_reset_data *data = to_stm32_reset_data(rcdev);
+   int reg_width = sizeof(u32);
+   int bank = id / (reg_width * BITS_PER_BYTE);
+   int offset = id % (reg_width * BITS_PER_BYTE);
+   u32 reg;
+
+   reg = readl(data->membase + (bank * reg_width));
+
+   return !!(reg & BIT(offset));
+}
+
+static const struct reset_control_ops stm32_reset_ops = {
+   .assert = stm32_reset_assert,
+   .deassert   = stm32_reset_deassert,
+   .status = stm32_reset_status,
+};
+
+static int stm32_rcc_reset_init(struct device *dev, void __iomem *base,
+   const struct of_device_id *match)
+{
+   const struct stm32_rcc_match_data *data = match->data;
+   struct stm32_reset_data *reset_data = NULL;
+
data = match->data;
 
+   reset_data = kzalloc(sizeof(*reset_data), GFP_KERNEL);
+   if (!reset_data)
+   return -ENOMEM;
+
+   reset_data->membase = base;
+   

[PATCH 12/14] ARM: dts: stm32: move clocks/resets to SCMI resources for stm32mp15

[gabriel.fernandez]

From: Gabriel Fernandez 

This change reflects board hardware configuration where RCC security
features are configured for RCC[TZEN]=1 and RCC[MCKPROT]=0, that is
RCC TrustZone is hardened and RCC MCKPROT is disabled.

Clock and reset controllers that relate to SoC secure resources are
moved from a RCC clock/reset handle to a SCMI clock/reset_domain handle.

These clocks are all the platform oscillators (HSI/LSI/CSI/HSE/LSE),
clocks for few subsystem and peripheral interfaces.

This change add a SCMI clock dependency on RCC clock device since it
registers clocks which parent clocks are provided by the SCMI clock
driver. This change allows the RCC clock device probe to be deferred
until SCMI clocks are fully registered in the system.

Signed-off-by: Etienne Carriere 
Signed-off-by: Gabriel Fernandez 
---
 arch/arm/boot/dts/stm32mp151.dtsi  | 77 +++---
 arch/arm/boot/dts/stm32mp153.dtsi  |  4 +-
 arch/arm/boot/dts/stm32mp157.dtsi  |  2 +-
 arch/arm/boot/dts/stm32mp15xc.dtsi |  4 +-
 4 files changed, 32 insertions(+), 55 deletions(-)

diff --git a/arch/arm/boot/dts/stm32mp151.dtsi 
b/arch/arm/boot/dts/stm32mp151.dtsi
index da3647373365..e06882e0611d 100644
--- a/arch/arm/boot/dts/stm32mp151.dtsi
+++ b/arch/arm/boot/dts/stm32mp151.dtsi
@@ -102,38 +102,6 @@
interrupt-parent = <>;
};
 
-   clocks {
-   clk_hse: clk-hse {
-   #clock-cells = <0>;
-   compatible = "fixed-clock";
-   clock-frequency = <2400>;
-   };
-
-   clk_hsi: clk-hsi {
-   #clock-cells = <0>;
-   compatible = "fixed-clock";
-   clock-frequency = <6400>;
-   };
-
-   clk_lse: clk-lse {
-   #clock-cells = <0>;
-   compatible = "fixed-clock";
-   clock-frequency = <32768>;
-   };
-
-   clk_lsi: clk-lsi {
-   #clock-cells = <0>;
-   compatible = "fixed-clock";
-   clock-frequency = <32000>;
-   };
-
-   clk_csi: clk-csi {
-   #clock-cells = <0>;
-   compatible = "fixed-clock";
-   clock-frequency = <400>;
-   };
-   };
-
thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <0>;
@@ -595,7 +563,7 @@
compatible = "st,stm32-cec";
reg = <0x40016000 0x400>;
interrupts = ;
-   clocks = < CEC_K>, <_lse>;
+   clocks = < CEC_K>, <_clk CK_SCMI0_LSE>;
clock-names = "cec", "hdmi-cec";
status = "disabled";
};
@@ -1156,10 +1124,17 @@
};
 
rcc: rcc@5000 {
-   compatible = "st,stm32mp1-rcc", "syscon";
+   compatible = "st,stm32mp1-rcc-secure", 
"st,stm32mp1-rcc", "syscon";
reg = <0x5000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
+
+   clock-names = "hse", "hsi", "csi", "lse", "lsi";
+   clocks = <_clk CK_SCMI0_HSE>,
+<_clk CK_SCMI0_HSI>,
+<_clk CK_SCMI0_CSI>,
+<_clk CK_SCMI0_LSE>,
+<_clk CK_SCMI0_LSI>;
};
 
pwr_regulators: pwr@50001000 {
@@ -1342,8 +1317,8 @@
compatible = "st,stm32f756-hash";
reg = <0x54002000 0x400>;
interrupts = ;
-   clocks = < HASH1>;
-   resets = < HASH1_R>;
+   clocks = <_clk CK_SCMI0_HASH1>;
+   resets = <_reset RST_SCMI0_HASH1>;
dmas = < 31 0x2 0x1000A02 0x0 0x0>;
dma-names = "in";
dma-maxburst = <2>;
@@ -1353,8 +1328,8 @@
rng1: rng@54003000 {
compatible = "st,stm32-rng";
reg = <0x54003000 0x400>;
-   clocks = < RNG1_K>;
-   resets = < RNG1_R>;
+   clocks = <_clk CK_SCMI0_RNG1>;
+   resets = <_reset RST_SCMI0_RNG1>;
status = "disabled";
};
 
@@ -1363,7 +1338,7 @@
reg = <0x5800 0x1000>;
interrupts = ;
clocks = < MDMA>;
-   resets = < MDMA_R>;
+   resets = <_reset RST_SCMI0_MDMA>;
#dma-cells = <5>;
dma-channels = 

[PATCH 11/14] ARM: dts: stm32: define SCMI resources on stm32mp15

[gabriel.fernandez]

From: Gabriel Fernandez 

Platform stm32mp15 relies on SCMI resources (clocks and reset domains).
This change adds SCMI resources description in the platform device
tree. SCMI resources uses a mailbox based on some shared memory and
a SMC mailbox notification.

SCMI0 exposes clocks and reset controllers for resources under RCC[TZEN]
configuration control. It is default enabled as SoC default
configuration is RCC[TZEN]=1.

SCMI1 exposes clocks for resources under RCC[MCKPROT] control. The node
is disabled by default as default configuration is RCC[MCKPROT]=0.

Signed-off-by: Etienne Carriere 
Signed-off-by: Gabriel Fernandez 
---
 arch/arm/boot/dts/stm32mp151.dtsi | 50 +++
 1 file changed, 50 insertions(+)

diff --git a/arch/arm/boot/dts/stm32mp151.dtsi 
b/arch/arm/boot/dts/stm32mp151.dtsi
index 3c75abacb374..da3647373365 100644
--- a/arch/arm/boot/dts/stm32mp151.dtsi
+++ b/arch/arm/boot/dts/stm32mp151.dtsi
@@ -30,6 +30,56 @@
interrupt-parent = <>;
};
 
+   scmi_sram: sram@2000 {
+   compatible = "mmio-sram";
+   reg = <0x2000 0x1000>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges = <0 0x2000 0x1000>;
+
+   scmi0_shm: scmi_shm@0 {
+   reg = <0 0x80>;
+   };
+
+   scmi1_shm: scmi_shm@200 {
+   reg = <0x200 0x80>;
+   };
+   };
+
+   firmware {
+   scmi0: scmi0 {
+   compatible = "arm,scmi-smc";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   arm,smc-id = <0x82002000>;
+   shmem = <_shm>;
+
+   scmi0_clk: protocol@14 {
+   reg = <0x14>;
+   #clock-cells = <1>;
+   };
+
+   scmi0_reset: protocol@16 {
+   reg = <0x16>;
+   #reset-cells = <1>;
+   };
+   };
+
+   scmi1: scmi1 {
+   compatible = "arm,scmi-smc";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   arm,smc-id = <0x82002001>;
+   shmem = <_shm>;
+   status = "disabled";
+
+   scmi1_clk: protocol@14 {
+   reg = <0x14>;
+   #clock-cells = <1>;
+   };
+   };
+   };
+
psci {
compatible = "arm,psci-1.0";
method = "smc";
-- 
2.17.1

[PATCH 13/14] dt-bindings: clock: stm32mp1 new compatible for secure rcc

[gabriel.fernandez]

From: Gabriel Fernandez 

Introduce new compatible string "st,stm32mp1-rcc-secure" for
stm32mp1 clock driver when the device is configured with RCC
security support hardened.

Signed-off-by: Etienne Carriere 
Signed-off-by: Gabriel Fernandez 
---
 Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml 
b/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml
index 4e385508f516..95f5990775c4 100644
--- a/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml
+++ b/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml
@@ -54,6 +54,7 @@ properties:
 
   compatible:
 items:
+  - const: st,stm32mp1-rcc-secure
   - const: st,stm32mp1-rcc
   - const: syscon
 
@@ -71,7 +72,7 @@ additionalProperties: false
 examples:
   - |
 rcc: rcc@5000 {
-compatible = "st,stm32mp1-rcc", "syscon";
+compatible = "st,stm32mp1-rcc-secure", "syscon";
 reg = <0x5000 0x1000>;
 #clock-cells = <1>;
 #reset-cells = <1>;
-- 
2.17.1

[PATCH 14/14] ARM: dts: stm32: introduce basic boot include on stm32mp15x board

[gabriel.fernandez]

From: Gabriel Fernandez 

Include this .dtsi file to be backward compatible with old basic bootchain.

For example add:
#include "stm32mp15-no-scmi.dtsi" in a stm32mp157c*.dts file.

Signed-off-by: Gabriel Fernandez 
---
 arch/arm/boot/dts/stm32mp15-no-scmi.dtsi | 158 +++
 1 file changed, 158 insertions(+)
 create mode 100644 arch/arm/boot/dts/stm32mp15-no-scmi.dtsi

diff --git a/arch/arm/boot/dts/stm32mp15-no-scmi.dtsi 
b/arch/arm/boot/dts/stm32mp15-no-scmi.dtsi
new file mode 100644
index ..4939f96da739
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp15-no-scmi.dtsi
@@ -0,0 +1,158 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2020 - All Rights Reserved
+ * Author: Gabriel Fernandez  for STMicroelectronics.
+ */
+
+/ {
+
+   clocks {
+   clk_hse: clk-hse {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <2400>;
+   };
+
+   clk_hsi: clk-hsi {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <6400>;
+   };
+
+   clk_lse: clk-lse {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <32768>;
+   };
+
+   clk_lsi: clk-lsi {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <32000>;
+   };
+
+   clk_csi: clk-csi {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <400>;
+   };
+   };
+
+   cpus {
+   cpu0: cpu@0 {
+   clocks = < CK_MPU>;
+   };
+
+   cpu1: cpu@1 {
+   clocks = < CK_MPU>;
+   };
+   };
+
+   reboot {
+   compatible = "syscon-reboot";
+   regmap = <>;
+   offset = <0x404>;
+   mask = <0x1>;
+   };
+
+   soc {
+   m_can1: can@4400e000 {
+   clocks = < CK_HSE>, < FDCAN_K>;
+   };
+
+   m_can2: can@4400f000 {
+   clocks = < CK_HSE>, < FDCAN_K>;
+   };
+
+   cryp1: cryp@54001000 {
+   clocks = < CRYP1>;
+   resets = < CRYP1_R>;
+   };
+
+   dsi: dsi@5a00 {
+   clocks = < DSI_K>, <_hse>, < DSI_PX>;
+   };
+   };
+
+   ahb {
+   m4_rproc: m4@1000 {
+   resets = < MCU_R>, < MCU_HOLD_BOOT_R>;
+
+   m4_system_resources {
+   m4_cec: cec@40016000 {
+   clocks = < CEC_K>, < CK_LSE>;
+   };
+
+   m4_m_can1: can@4400e000 {
+   clocks = < CK_HSE>, < FDCAN_K>;
+   };
+
+   m4_m_can2: can@4400f000 {
+   clocks = < CK_HSE>, < FDCAN_K>;
+   };
+   };
+   };
+   };
+
+   firmware {
+   /delete-node/ scmi0;
+   /delete-node/ scmi1;
+   };
+   /delete-node/ sram@2000;
+};
+
+ {
+   clocks = < CEC_K>, <_lse>;
+};
+
+ {
+   clocks = < GPIOZ>;
+};
+
+ {
+   clocks = < HASH1>;
+   resets = < HASH1_R>;
+};
+
+ {
+   clocks = < I2C4_K>;
+   resets = < I2C4_R>;
+};
+
+ {
+   clocks = < I2C6_K>;
+   resets = < I2C6_R>;
+};
+
+ {
+   clocks = < IWDG2>, < CK_LSI>;
+};
+
+ {
+   clocks = < MDMA>;
+   resets = < MDMA_R>;
+};
+
+ {
+   compatible = "st,stm32mp1-rcc", "syscon";
+   clocks = <_hse>, <_hsi>, <_csi>, <_lse>, <_lsi>;
+};
+
+ {
+   clocks = < RNG1_K>;
+   resets = < RNG1_R>;
+};
+
+ {
+   clocks = < RTCAPB>, < RTC>;
+};
+
+ {
+   clocks = < SPI6_K>;
+   resets = < SPI6_R>;
+};
+
+ {
+   clocks = < USART1_K>;
+   resets = < USART1_R>;
+};
-- 
2.17.1

[PATCH 10/14] clk: stm32mp1: new compatible for secure RCC support

[gabriel.fernandez]

From: Gabriel Fernandez 

Platform STM32MP1 can be used in configuration where some clock
resources cannot be accessed by Linux kernel when executing in non-secure
state of the CPU(s).
In such configuration, the RCC clock driver must not register clocks
it cannot access.
They are expected to be registered from another clock driver such
as the SCMI clock driver.
This change uses specific compatible string "st,stm32mp1-rcc-secure"
to specify RCC clock driver configuration where RCC is secure.

Signed-off-by: Etienne Carriere 
Signed-off-by: Gabriel Fernandez 
---
 drivers/clk/Kconfig|  10 
 drivers/clk/clk-stm32mp1.c | 101 -
 2 files changed, 110 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 85856cff506c..ee61aec3b490 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -334,6 +334,16 @@ config COMMON_CLK_STM32MP157
help
  Support for stm32mp157 SoC family clocks
 
+config COMMON_CLK_STM32MP157_SCMI
+   bool "stm32mp157 Clock diver with Trusted Firmware"
+   depends on COMMON_CLK_STM32MP157
+   select COMMON_CLK_SCMI
+   select ARM_SCMI_PROTOCOL
+   default y
+   help
+ Support for stm32mp157 SoC family clocks with Trusted Firmware using
+ SCMI protocol.
+
 config COMMON_CLK_STM32F
def_bool COMMON_CLK && (MACH_STM32F429 || MACH_STM32F469 || 
MACH_STM32F746)
help
diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index 25e3f272344c..132e1dd42dbd 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -2051,11 +2051,61 @@ static const struct clock_config stm32mp1_clock_cfg[] = 
{
  _DIV(RCC_DBGCFGR, 0, 3, 0, ck_trace_div_table)),
 };
 
+static const u32 stm32mp1_clock_secured[] = {
+   CK_HSE,
+   CK_HSI,
+   CK_CSI,
+   CK_LSI,
+   CK_LSE,
+   PLL1,
+   PLL2,
+   PLL1_P,
+   PLL2_P,
+   PLL2_Q,
+   PLL2_R,
+   CK_MPU,
+   CK_AXI,
+   SPI6,
+   I2C4,
+   I2C6,
+   USART1,
+   RTCAPB,
+   TZC1,
+   TZC2,
+   TZPC,
+   IWDG1,
+   BSEC,
+   STGEN,
+   GPIOZ,
+   CRYP1,
+   HASH1,
+   RNG1,
+   BKPSRAM,
+   RNG1_K,
+   STGEN_K,
+   SPI6_K,
+   I2C4_K,
+   I2C6_K,
+   USART1_K,
+   RTC,
+};
+
+static bool stm32_check_security(const struct clock_config *cfg)
+{
+   int i;
+
+   for (i = 0; i < ARRAY_SIZE(stm32mp1_clock_secured); i++)
+   if (cfg->id == stm32mp1_clock_secured[i])
+   return true;
+   return false;
+}
+
 struct stm32_rcc_match_data {
const struct clock_config *cfg;
unsigned int num;
unsigned int maxbinding;
u32 clear_offset;
+   bool (*check_security)(const struct clock_config *cfg);
 };
 
 static struct stm32_rcc_match_data stm32mp1_data = {
@@ -2065,11 +2115,23 @@ static struct stm32_rcc_match_data stm32mp1_data = {
.clear_offset   = RCC_CLR,
 };
 
+static struct stm32_rcc_match_data stm32mp1_data_secure = {
+   .cfg= stm32mp1_clock_cfg,
+   .num= ARRAY_SIZE(stm32mp1_clock_cfg),
+   .maxbinding = STM32MP1_LAST_CLK,
+   .clear_offset   = RCC_CLR,
+   .check_security = _check_security
+};
+
 static const struct of_device_id stm32mp1_match_data[] = {
{
.compatible = "st,stm32mp1-rcc",
.data = _data,
},
+   {
+   .compatible = "st,stm32mp1-rcc-secure",
+   .data = _data_secure,
+   },
{ }
 };
 MODULE_DEVICE_TABLE(of, stm32mp1_match_data);
@@ -2229,6 +2291,9 @@ static int stm32_rcc_clock_init(struct device *dev, void 
__iomem *base,
hws[n] = ERR_PTR(-ENOENT);
 
for (n = 0; n < data->num; n++) {
+   if (data->check_security && data->check_security(>cfg[n]))
+   continue;
+
err = stm32_register_hw_clk(dev, clk_data, base, ,
>cfg[n]);
if (err) {
@@ -2296,11 +2361,45 @@ static int stm32mp1_rcc_init(struct device *dev)
return ret;
 }
 
+static int get_clock_deps(struct device *dev)
+{
+   static const char * const clock_deps_name[] = {
+   "hsi", "hse", "csi", "lsi", "lse",
+   };
+   size_t deps_size = sizeof(struct clk *) * ARRAY_SIZE(clock_deps_name);
+   struct clk **clk_deps;
+   int i;
+
+   clk_deps = devm_kzalloc(dev, deps_size, GFP_KERNEL);
+   if (!clk_deps)
+   return -ENOMEM;
+
+   for (i = 0; i < ARRAY_SIZE(clock_deps_name); i++) {
+   struct clk *clk = of_clk_get_by_name(dev_of_node(dev),
+clock_deps_name[i]);
+
+   if (IS_ERR(clk)) {
+   if (PTR_ERR(clk) != -EINVAL && PTR_ERR(clk) != -ENOENT)
+  

[PATCH 06/14] reset: stm32mp1: remove stm32mp1 reset

[gabriel.fernandez]

From: Gabriel Fernandez 

st32mp1 RCC reset driver was moved into stm32mp1 RCC clock driver.

Signed-off-by: Gabriel Fernandez 
---
 drivers/reset/Kconfig  |   6 --
 drivers/reset/Makefile |   1 -
 drivers/reset/reset-stm32mp1.c | 115 -
 3 files changed, 122 deletions(-)
 delete mode 100644 drivers/reset/reset-stm32mp1.c

diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index df2725e1798e..97c9acc2064e 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -198,12 +198,6 @@ config RESET_SIMPLE
   - Allwinner SoCs
   - ZTE's zx2967 family
 
-config RESET_STM32MP157
-   bool "STM32MP157 Reset Driver" if COMPILE_TEST
-   default MACH_STM32MP157
-   help
- This enables the RCC reset controller driver for STM32 MPUs.
-
 config RESET_SOCFPGA
bool "SoCFPGA Reset Driver" if COMPILE_TEST && !ARCH_SOCFPGA
default ARCH_SOCFPGA
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 65a118a91b27..ac3e612ad953 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -26,7 +26,6 @@ obj-$(CONFIG_RESET_QCOM_PDC) += reset-qcom-pdc.o
 obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o
 obj-$(CONFIG_RESET_SCMI) += reset-scmi.o
 obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
-obj-$(CONFIG_RESET_STM32MP157) += reset-stm32mp1.o
 obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
 obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
 obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
diff --git a/drivers/reset/reset-stm32mp1.c b/drivers/reset/reset-stm32mp1.c
deleted file mode 100644
index b221a28041fa..
--- a/drivers/reset/reset-stm32mp1.c
+++ /dev/null
@@ -1,115 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
- * Author: Gabriel Fernandez  for STMicroelectronics.
- */
-
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-#define CLR_OFFSET 0x4
-
-struct stm32_reset_data {
-   struct reset_controller_dev rcdev;
-   void __iomem*membase;
-};
-
-static inline struct stm32_reset_data *
-to_stm32_reset_data(struct reset_controller_dev *rcdev)
-{
-   return container_of(rcdev, struct stm32_reset_data, rcdev);
-}
-
-static int stm32_reset_update(struct reset_controller_dev *rcdev,
- unsigned long id, bool assert)
-{
-   struct stm32_reset_data *data = to_stm32_reset_data(rcdev);
-   int reg_width = sizeof(u32);
-   int bank = id / (reg_width * BITS_PER_BYTE);
-   int offset = id % (reg_width * BITS_PER_BYTE);
-   void __iomem *addr;
-
-   addr = data->membase + (bank * reg_width);
-   if (!assert)
-   addr += CLR_OFFSET;
-
-   writel(BIT(offset), addr);
-
-   return 0;
-}
-
-static int stm32_reset_assert(struct reset_controller_dev *rcdev,
- unsigned long id)
-{
-   return stm32_reset_update(rcdev, id, true);
-}
-
-static int stm32_reset_deassert(struct reset_controller_dev *rcdev,
-   unsigned long id)
-{
-   return stm32_reset_update(rcdev, id, false);
-}
-
-static int stm32_reset_status(struct reset_controller_dev *rcdev,
- unsigned long id)
-{
-   struct stm32_reset_data *data = to_stm32_reset_data(rcdev);
-   int reg_width = sizeof(u32);
-   int bank = id / (reg_width * BITS_PER_BYTE);
-   int offset = id % (reg_width * BITS_PER_BYTE);
-   u32 reg;
-
-   reg = readl(data->membase + (bank * reg_width));
-
-   return !!(reg & BIT(offset));
-}
-
-static const struct reset_control_ops stm32_reset_ops = {
-   .assert = stm32_reset_assert,
-   .deassert   = stm32_reset_deassert,
-   .status = stm32_reset_status,
-};
-
-static const struct of_device_id stm32_reset_dt_ids[] = {
-   { .compatible = "st,stm32mp1-rcc"},
-   { /* sentinel */ },
-};
-
-static int stm32_reset_probe(struct platform_device *pdev)
-{
-   struct device *dev = >dev;
-   struct stm32_reset_data *data;
-   void __iomem *membase;
-   struct resource *res;
-
-   data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
-   if (!data)
-   return -ENOMEM;
-
-   res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-   membase = devm_ioremap_resource(dev, res);
-   if (IS_ERR(membase))
-   return PTR_ERR(membase);
-
-   data->membase = membase;
-   data->rcdev.owner = THIS_MODULE;
-   data->rcdev.nr_resets = resource_size(res) * BITS_PER_BYTE;
-   data->rcdev.ops = _reset_ops;
-   data->rcdev.of_node = dev->of_node;
-
-   return devm_reset_controller_register(dev, >rcdev);
-}
-
-static struct platform_driver stm32_reset_driver = {
-   .probe  = stm32_reset_probe,
-   .driver = {
-   .name   = "stm32mp1-reset",
-   .of_match_table = stm32_reset_dt_ids,
-   },
-};
-

[PATCH 03/14] clk: stm32mp1: remove intermediate pll clocks

[gabriel.fernandez]

From: Gabriel Fernandez 

This patch is to prepare STM32MP1 clocks in trusted mode.
Integrate the mux clock into pll clock will facilitate to have a more
coherent clock tree in no trusted / trusted mode.

Signed-off-by: Gabriel Fernandez 
---
 drivers/clk/clk-stm32mp1.c | 65 --
 1 file changed, 42 insertions(+), 23 deletions(-)

diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index 0e1d4427a8df..ee6968a2ad57 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -731,6 +731,7 @@ struct stm32_pll_obj {
spinlock_t *lock;
void __iomem *reg;
struct clk_hw hw;
+   struct clk_mux mux;
 };
 
 #define to_pll(_hw) container_of(_hw, struct stm32_pll_obj, hw)
@@ -745,6 +746,8 @@ struct stm32_pll_obj {
 #define FRAC_MASK  0x1FFF
 #define FRAC_SHIFT 3
 #define FRACLE BIT(16)
+#define PLL_MUX_SHIFT  0
+#define PLL_MUX_MASK   3
 
 static int __pll_is_enabled(struct clk_hw *hw)
 {
@@ -856,16 +859,29 @@ static int pll_is_enabled(struct clk_hw *hw)
return ret;
 }
 
+static u8 pll_get_parent(struct clk_hw *hw)
+{
+   struct stm32_pll_obj *clk_elem = to_pll(hw);
+   struct clk_hw *mux_hw = _elem->mux.hw;
+
+   __clk_hw_set_clk(mux_hw, hw);
+
+   return clk_mux_ops.get_parent(mux_hw);
+}
+
 static const struct clk_ops pll_ops = {
.enable = pll_enable,
.disable= pll_disable,
.recalc_rate= pll_recalc_rate,
.is_enabled = pll_is_enabled,
+   .get_parent = pll_get_parent,
 };
 
 static struct clk_hw *clk_register_pll(struct device *dev, const char *name,
-  const char *parent_name,
+  const char * const *parent_names,
+  int num_parents,
   void __iomem *reg,
+  void __iomem *mux_reg,
   unsigned long flags,
   spinlock_t *lock)
 {
@@ -881,8 +897,15 @@ static struct clk_hw *clk_register_pll(struct device *dev, 
const char *name,
init.name = name;
init.ops = _ops;
init.flags = flags;
-   init.parent_names = _name;
-   init.num_parents = 1;
+   init.parent_names = parent_names;
+   init.num_parents = num_parents;
+
+   element->mux.lock = lock;
+   element->mux.reg =  mux_reg;
+   element->mux.shift = PLL_MUX_SHIFT;
+   element->mux.mask =  PLL_MUX_MASK;
+   element->mux.flags =  CLK_MUX_READ_ONLY;
+   element->mux.reg =  mux_reg;
 
element->hw.init = 
element->reg = reg;
@@ -1069,6 +1092,7 @@ static const struct clk_ops rtc_div_clk_ops = {
 
 struct stm32_pll_cfg {
u32 offset;
+   u32 muxoff;
 };
 
 static struct clk_hw *_clk_register_pll(struct device *dev,
@@ -1078,8 +1102,11 @@ static struct clk_hw *_clk_register_pll(struct device 
*dev,
 {
struct stm32_pll_cfg *stm_pll_cfg = cfg->cfg;
 
-   return clk_register_pll(dev, cfg->name, cfg->parent_name,
-   base + stm_pll_cfg->offset, cfg->flags, lock);
+   return clk_register_pll(dev, cfg->name, cfg->parent_names,
+   cfg->num_parents,
+   base + stm_pll_cfg->offset,
+   base + stm_pll_cfg->muxoff,
+   cfg->flags, lock);
 }
 
 struct stm32_cktim_cfg {
@@ -1189,14 +1216,16 @@ _clk_stm32_register_composite(struct device *dev,
.func   = _clk_hw_register_mux,\
 }
 
-#define PLL(_id, _name, _parent, _flags, _offset)\
+#define PLL(_id, _name, _parents, _flags, _offset_p, _offset_mux)\
 {\
.id = _id,\
.name   = _name,\
-   .parent_name= _parent,\
-   .flags  = _flags,\
+   .parent_names   = _parents,\
+   .num_parents= ARRAY_SIZE(_parents),\
+   .flags  = CLK_IGNORE_UNUSED | (_flags),\
.cfg=  &(struct stm32_pll_cfg) {\
-   .offset = _offset,\
+   .offset = _offset_p,\
+   .muxoff = _offset_mux,\
},\
.func   = _clk_register_pll,\
 }
@@ -1712,21 +1741,11 @@ static const struct clock_config stm32mp1_clock_cfg[] = 
{
 
FIXED_FACTOR(CK_HSE_DIV2, "clk-hse-div2", "ck_hse", 0, 1, 2),
 
-   /* ref clock pll */
-   MUX(NO_ID, "ref1", ref12_parents, CLK_OPS_PARENT_ENABLE, RCC_RCK12SELR,
-   0, 2, CLK_MUX_READ_ONLY),
-
-   MUX(NO_ID, "ref3", ref3_parents, CLK_OPS_PARENT_ENABLE, RCC_RCK3SELR,
-   0, 2, CLK_MUX_READ_ONLY),
-
-   MUX(NO_ID, "ref4", ref4_parents, CLK_OPS_PARENT_ENABLE, RCC_RCK4SELR,
-   0, 2, CLK_MUX_READ_ONLY),
-
/* PLLs */
-   PLL(PLL1, "pll1", "ref1", CLK_IGNORE_UNUSED, RCC_PLL1CR),
-   PLL(PLL2, "pll2", "ref1", CLK_IGNORE_UNUSED, RCC_PLL2CR),
-   

[PATCH 04/14] clk: stm32mp1: convert to module driver

[gabriel.fernandez]

From: Gabriel Fernandez 

Adds support for  probe deferral in way to prepare
integration of the security in RCC clock and reset
drivers.
Some kernel clocks will be provided by the SCMI drivers.
Since RCC clock driver create clocks which parents
are SCMI clocks, RCC clock driver probe can be deferred.

Signed-off-by: Etienne Carriere 
Signed-off-by: Gabriel Fernandez 
---
 drivers/clk/clk-stm32mp1.c | 121 -
 1 file changed, 78 insertions(+), 43 deletions(-)

diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index ee6968a2ad57..530babc4c4b6 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -10,8 +10,10 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -469,7 +471,7 @@ static const struct clk_ops mp1_gate_clk_ops = {
.is_enabled = clk_gate_is_enabled,
 };
 
-static struct clk_hw *_get_stm32_mux(void __iomem *base,
+static struct clk_hw *_get_stm32_mux(struct device *dev, void __iomem *base,
 const struct stm32_mux_cfg *cfg,
 spinlock_t *lock)
 {
@@ -478,7 +480,7 @@ static struct clk_hw *_get_stm32_mux(void __iomem *base,
struct clk_hw *mux_hw;
 
if (cfg->mmux) {
-   mmux = kzalloc(sizeof(*mmux), GFP_KERNEL);
+   mmux = devm_kzalloc(dev, sizeof(*mmux), GFP_KERNEL);
if (!mmux)
return ERR_PTR(-ENOMEM);
 
@@ -493,7 +495,7 @@ static struct clk_hw *_get_stm32_mux(void __iomem *base,
cfg->mmux->hws[cfg->mmux->nbr_clk++] = mux_hw;
 
} else {
-   mux = kzalloc(sizeof(*mux), GFP_KERNEL);
+   mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
if (!mux)
return ERR_PTR(-ENOMEM);
 
@@ -509,13 +511,13 @@ static struct clk_hw *_get_stm32_mux(void __iomem *base,
return mux_hw;
 }
 
-static struct clk_hw *_get_stm32_div(void __iomem *base,
+static struct clk_hw *_get_stm32_div(struct device *dev, void __iomem *base,
 const struct stm32_div_cfg *cfg,
 spinlock_t *lock)
 {
struct clk_divider *div;
 
-   div = kzalloc(sizeof(*div), GFP_KERNEL);
+   div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
 
if (!div)
return ERR_PTR(-ENOMEM);
@@ -530,16 +532,16 @@ static struct clk_hw *_get_stm32_div(void __iomem *base,
return >hw;
 }
 
-static struct clk_hw *
-_get_stm32_gate(void __iomem *base,
-   const struct stm32_gate_cfg *cfg, spinlock_t *lock)
+static struct clk_hw *_get_stm32_gate(struct device *dev, void __iomem *base,
+ const struct stm32_gate_cfg *cfg,
+ spinlock_t *lock)
 {
struct stm32_clk_mgate *mgate;
struct clk_gate *gate;
struct clk_hw *gate_hw;
 
if (cfg->mgate) {
-   mgate = kzalloc(sizeof(*mgate), GFP_KERNEL);
+   mgate = devm_kzalloc(dev, sizeof(*mgate), GFP_KERNEL);
if (!mgate)
return ERR_PTR(-ENOMEM);
 
@@ -554,7 +556,7 @@ _get_stm32_gate(void __iomem *base,
gate_hw = >gate.hw;
 
} else {
-   gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+   gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL);
if (!gate)
return ERR_PTR(-ENOMEM);
 
@@ -592,7 +594,7 @@ clk_stm32_register_gate_ops(struct device *dev,
if (cfg->ops)
init.ops = cfg->ops;
 
-   hw = _get_stm32_gate(base, cfg, lock);
+   hw = _get_stm32_gate(dev, base, cfg, lock);
if (IS_ERR(hw))
return ERR_PTR(-ENOMEM);
 
@@ -623,7 +625,7 @@ clk_stm32_register_composite(struct device *dev,
gate_ops = NULL;
 
if (cfg->mux) {
-   mux_hw = _get_stm32_mux(base, cfg->mux, lock);
+   mux_hw = _get_stm32_mux(dev, base, cfg->mux, lock);
 
if (!IS_ERR(mux_hw)) {
mux_ops = _mux_ops;
@@ -634,7 +636,7 @@ clk_stm32_register_composite(struct device *dev,
}
 
if (cfg->div) {
-   div_hw = _get_stm32_div(base, cfg->div, lock);
+   div_hw = _get_stm32_div(dev, base, cfg->div, lock);
 
if (!IS_ERR(div_hw)) {
div_ops = _divider_ops;
@@ -645,7 +647,7 @@ clk_stm32_register_composite(struct device *dev,
}
 
if (cfg->gate) {
-   gate_hw = _get_stm32_gate(base, cfg->gate, lock);
+   gate_hw = _get_stm32_gate(dev, base, cfg->gate, lock);
 
if (!IS_ERR(gate_hw)) {
gate_ops = _gate_ops;
@@ -890,7 +892,7 @@ static struct clk_hw *clk_register_pll(struct device *dev, 
const char *name,
struct clk_hw *hw;
int err;
 
-   

[PATCH 05/14] clk: stm32mp1: move RCC reset controller into RCC clock driver

[gabriel.fernandez]

From: Gabriel Fernandez 

RCC clock and reset controller shared same memory mapping.
As RCC clock driver is now a module, the best way to register clock
and reset controller is to do it in same driver.

Signed-off-by: Gabriel Fernandez 
---
 drivers/clk/clk-stm32mp1.c | 157 ++---
 1 file changed, 144 insertions(+), 13 deletions(-)

diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index 530babc4c4b6..25e3f272344c 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -14,6 +14,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -2050,16 +2051,18 @@ static const struct clock_config stm32mp1_clock_cfg[] = 
{
  _DIV(RCC_DBGCFGR, 0, 3, 0, ck_trace_div_table)),
 };
 
-struct stm32_clock_match_data {
+struct stm32_rcc_match_data {
const struct clock_config *cfg;
unsigned int num;
unsigned int maxbinding;
+   u32 clear_offset;
 };
 
-static struct stm32_clock_match_data stm32mp1_data = {
+static struct stm32_rcc_match_data stm32mp1_data = {
.cfg= stm32mp1_clock_cfg,
.num= ARRAY_SIZE(stm32mp1_clock_cfg),
.maxbinding = STM32MP1_LAST_CLK,
+   .clear_offset   = RCC_CLR,
 };
 
 static const struct of_device_id stm32mp1_match_data[] = {
@@ -2095,23 +2098,122 @@ static int stm32_register_hw_clk(struct device *dev,
return 0;
 }
 
-static int stm32_rcc_init(struct device *dev, void __iomem *base,
- const struct of_device_id *match_data)
+#define STM32_RESET_ID_MASK GENMASK(15, 0)
+
+struct stm32_reset_data {
+   /* reset lock */
+   spinlock_t  lock;
+   struct reset_controller_dev rcdev;
+   void __iomem*membase;
+   u32 clear_offset;
+};
+
+static inline struct stm32_reset_data *
+to_stm32_reset_data(struct reset_controller_dev *rcdev)
 {
-   struct clk_hw_onecell_data *clk_data;
-   struct clk_hw **hws;
-   const struct of_device_id *match;
-   const struct stm32_clock_match_data *data;
-   int err, n, max_binding;
+   return container_of(rcdev, struct stm32_reset_data, rcdev);
+}
 
-   match = of_match_node(match_data, dev_of_node(dev));
-   if (!match) {
-   dev_err(dev, "match data not found\n");
-   return -ENODEV;
+static int stm32_reset_update(struct reset_controller_dev *rcdev,
+ unsigned long id, bool assert)
+{
+   struct stm32_reset_data *data = to_stm32_reset_data(rcdev);
+   int reg_width = sizeof(u32);
+   int bank = id / (reg_width * BITS_PER_BYTE);
+   int offset = id % (reg_width * BITS_PER_BYTE);
+
+   if (data->clear_offset) {
+   void __iomem *addr;
+
+   addr = data->membase + (bank * reg_width);
+   if (!assert)
+   addr += data->clear_offset;
+
+   writel(BIT(offset), addr);
+
+   } else {
+   unsigned long flags;
+   u32 reg;
+
+   spin_lock_irqsave(>lock, flags);
+
+   reg = readl(data->membase + (bank * reg_width));
+
+   if (assert)
+   reg |= BIT(offset);
+   else
+   reg &= ~BIT(offset);
+
+   writel(reg, data->membase + (bank * reg_width));
+
+   spin_unlock_irqrestore(>lock, flags);
}
 
+   return 0;
+}
+
+static int stm32_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+   return stm32_reset_update(rcdev, id, true);
+}
+
+static int stm32_reset_deassert(struct reset_controller_dev *rcdev,
+   unsigned long id)
+{
+   return stm32_reset_update(rcdev, id, false);
+}
+
+static int stm32_reset_status(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+   struct stm32_reset_data *data = to_stm32_reset_data(rcdev);
+   int reg_width = sizeof(u32);
+   int bank = id / (reg_width * BITS_PER_BYTE);
+   int offset = id % (reg_width * BITS_PER_BYTE);
+   u32 reg;
+
+   reg = readl(data->membase + (bank * reg_width));
+
+   return !!(reg & BIT(offset));
+}
+
+static const struct reset_control_ops stm32_reset_ops = {
+   .assert = stm32_reset_assert,
+   .deassert   = stm32_reset_deassert,
+   .status = stm32_reset_status,
+};
+
+static int stm32_rcc_reset_init(struct device *dev, void __iomem *base,
+   const struct of_device_id *match)
+{
+   const struct stm32_rcc_match_data *data = match->data;
+   struct stm32_reset_data *reset_data = NULL;
+
data = match->data;
 
+   reset_data = kzalloc(sizeof(*reset_data), GFP_KERNEL);
+   if (!reset_data)
+   return -ENOMEM;
+
+   reset_data->membase = base;
+   

[PATCH 02/14] clk: stm32mp1: merge 'ck_hse_rtc' and 'ck_rtc' into one clock

[gabriel.fernandez]

From: Gabriel Fernandez 

'ck_rtc' has multiple clocks as input (ck_hsi, ck_lsi, and ck_hse).
A divider is available only on the specific rtc input for ck_hse.
This Merge will facilitate to have a more coherent clock tree
in no trusted / trusted world.

Signed-off-by: Gabriel Fernandez 
---
 drivers/clk/clk-stm32mp1.c | 49 +-
 1 file changed, 43 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index 35d5aee8f9b0..0e1d4427a8df 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -245,7 +245,7 @@ static const char * const dsi_src[] = {
 };
 
 static const char * const rtc_src[] = {
-   "off", "ck_lse", "ck_lsi", "ck_hse_rtc"
+   "off", "ck_lse", "ck_lsi", "ck_hse"
 };
 
 static const char * const mco1_src[] = {
@@ -1031,6 +1031,42 @@ static struct clk_hw *clk_register_cktim(struct device 
*dev, const char *name,
return hw;
 }
 
+/* The divider of RTC clock concerns only ck_hse clock */
+#define HSE_RTC 3
+
+static unsigned long clk_divider_rtc_recalc_rate(struct clk_hw *hw,
+unsigned long parent_rate)
+{
+   if (clk_hw_get_parent(hw) == clk_hw_get_parent_by_index(hw, HSE_RTC))
+   return clk_divider_ops.recalc_rate(hw, parent_rate);
+
+   return parent_rate;
+}
+
+static long clk_divider_rtc_round_rate(struct clk_hw *hw, unsigned long rate,
+  unsigned long *prate)
+{
+   if (clk_hw_get_parent(hw) == clk_hw_get_parent_by_index(hw, HSE_RTC))
+   return clk_divider_ops.round_rate(hw, rate, prate);
+
+   return *prate;
+}
+
+static int clk_divider_rtc_set_rate(struct clk_hw *hw, unsigned long rate,
+   unsigned long parent_rate)
+{
+   if (clk_hw_get_parent(hw) == clk_hw_get_parent_by_index(hw, HSE_RTC))
+   return clk_divider_ops.set_rate(hw, rate, parent_rate);
+
+   return parent_rate;
+}
+
+static const struct clk_ops rtc_div_clk_ops = {
+   .recalc_rate= clk_divider_rtc_recalc_rate,
+   .round_rate = clk_divider_rtc_round_rate,
+   .set_rate   = clk_divider_rtc_set_rate,
+};
+
 struct stm32_pll_cfg {
u32 offset;
 };
@@ -1243,6 +1279,10 @@ _clk_stm32_register_composite(struct device *dev,
_STM32_DIV(_div_offset, _div_shift, _div_width,\
   _div_flags, _div_table, NULL)\
 
+#define _DIV_RTC(_div_offset, _div_shift, _div_width, _div_flags, _div_table)\
+   _STM32_DIV(_div_offset, _div_shift, _div_width,\
+  _div_flags, _div_table, _div_clk_ops)
+
 #define _STM32_MUX(_offset, _shift, _width, _mux_flags, _mmux, _ops)\
.mux = &(struct stm32_mux_cfg) {\
&(struct mux_cfg) {\
@@ -1965,13 +2005,10 @@ static const struct clock_config stm32mp1_clock_cfg[] = 
{
  _DIV(RCC_ETHCKSELR, 4, 4, 0, NULL)),
 
/* RTC clock */
-   DIV(NO_ID, "ck_hse_rtc", "ck_hse", 0, RCC_RTCDIVR, 0, 6, 0),
-
-   COMPOSITE(RTC, "ck_rtc", rtc_src, CLK_OPS_PARENT_ENABLE |
-  CLK_SET_RATE_PARENT,
+   COMPOSITE(RTC, "ck_rtc", rtc_src, CLK_OPS_PARENT_ENABLE,
  _GATE(RCC_BDCR, 20, 0),
  _MUX(RCC_BDCR, 16, 2, 0),
- _NO_DIV),
+ _DIV_RTC(RCC_RTCDIVR, 0, 6, 0, NULL)),
 
/* MCO clocks */
COMPOSITE(CK_MCO1, "ck_mco1", mco1_src, CLK_OPS_PARENT_ENABLE |
-- 
2.17.1

[PATCH 00/14] Introduce STM32MP1 RCC in secured mode

[gabriel.fernandez]

From: Gabriel Fernandez 

Platform STM32MP1 can be used in configuration where some clocks and
IP resets can relate as secure resources.
These resources are moved from a RCC clock/reset handle to a SCMI
clock/reset_domain handle.

The RCC clock driver is now dependant of the SCMI driver, then we have
to manage now the probe defering.

Gabriel Fernandez (14):
  clk: stm32mp1: merge 'clk-hsi-div' and 'ck_hsi' into one clock
  clk: stm32mp1: merge 'ck_hse_rtc' and 'ck_rtc' into one clock
  clk: stm32mp1: remove intermediate pll clocks
  clk: stm32mp1: convert to module driver
  clk: stm32mp1: move RCC reset controller into RCC clock driver
  reset: stm32mp1: remove stm32mp1 reset
  dt-bindings: clock: add IDs for SCMI clocks on stm32mp15
  dt-bindings: reset: add IDs for SCMI reset domains on stm32mp15
  dt-bindings: reset: add MCU HOLD BOOT ID for SCMI reset domains on
stm32mp15
  clk: stm32mp1: new compatible for secure RCC support
  ARM: dts: stm32: define SCMI resources on stm32mp15
  ARM: dts: stm32: move clocks/resets to SCMI resources for stm32mp15
  dt-bindings: clock: stm32mp1 new compatible for secure rcc
  ARM: dts: stm32: introduce basic boot include on stm32mp15x board

 .../bindings/clock/st,stm32mp1-rcc.yaml   |   3 +-
 arch/arm/boot/dts/stm32mp15-no-scmi.dtsi  | 158 ++
 arch/arm/boot/dts/stm32mp151.dtsi | 127 +++--
 arch/arm/boot/dts/stm32mp153.dtsi |   4 +-
 arch/arm/boot/dts/stm32mp157.dtsi |   2 +-
 arch/arm/boot/dts/stm32mp15xc.dtsi|   4 +-
 drivers/clk/Kconfig   |  10 +
 drivers/clk/clk-stm32mp1.c| 495 +++---
 drivers/reset/Kconfig |   6 -
 drivers/reset/Makefile|   1 -
 drivers/reset/reset-stm32mp1.c| 115 
 include/dt-bindings/clock/stm32mp1-clks.h |  27 +
 include/dt-bindings/reset/stm32mp1-resets.h   |  15 +
 13 files changed, 702 insertions(+), 265 deletions(-)
 create mode 100644 arch/arm/boot/dts/stm32mp15-no-scmi.dtsi
 delete mode 100644 drivers/reset/reset-stm32mp1.c

-- 
2.17.1

[PATCH 01/14] clk: stm32mp1: merge 'clk-hsi-div' and 'ck_hsi' into one clock

[gabriel.fernandez]

From: Gabriel Fernandez 

This patch is to prepare STM32MP1 clocks in trusted mode.
This Merge will facilitate to have a more coherent clock tree
in no trusted / trusted world.

Signed-off-by: Gabriel Fernandez 
---
 drivers/clk/clk-stm32mp1.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index a875649df8b8..35d5aee8f9b0 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -1657,16 +1657,16 @@ static const struct stm32_mux_cfg ker_mux_cfg[M_LAST] = 
{
 };
 
 static const struct clock_config stm32mp1_clock_cfg[] = {
-   /* Oscillator divider */
-   DIV(NO_ID, "clk-hsi-div", "clk-hsi", CLK_DIVIDER_POWER_OF_TWO,
-   RCC_HSICFGR, 0, 2, CLK_DIVIDER_READ_ONLY),
-
/*  External / Internal Oscillators */
GATE_MP1(CK_HSE, "ck_hse", "clk-hse", 0, RCC_OCENSETR, 8, 0),
/* ck_csi is used by IO compensation and should be critical */
GATE_MP1(CK_CSI, "ck_csi", "clk-csi", CLK_IS_CRITICAL,
 RCC_OCENSETR, 4, 0),
-   GATE_MP1(CK_HSI, "ck_hsi", "clk-hsi-div", 0, RCC_OCENSETR, 0, 0),
+   COMPOSITE(CK_HSI, "ck_hsi", PARENT("clk-hsi"), 0,
+ _GATE_MP1(RCC_OCENSETR, 0, 0),
+ _NO_MUX,
+ _DIV(RCC_HSICFGR, 0, 2, CLK_DIVIDER_POWER_OF_TWO |
+  CLK_DIVIDER_READ_ONLY, NULL)),
GATE(CK_LSI, "ck_lsi", "clk-lsi", 0, RCC_RDLSICR, 0, 0),
GATE(CK_LSE, "ck_lse", "clk-lse", 0, RCC_BDCR, 0, 0),
 
-- 
2.17.1

[PATCH 07/14] dt-bindings: clock: add IDs for SCMI clocks on stm32mp15

[gabriel.fernandez]

From: Gabriel Fernandez 

stm32mp15 TZ secure firmware provides SCMI clocks for oscillators, some
PLL output and few secure aware interfaces.
This change defines the SCMI clock identifiers used by SCMI agents
and servers.
Server SCMI0 exposes clocks and reset controllers for resources under
RCC[TZEN] configuration control.
Server SCMI1 exposes clocks for resources under RCC[MCKPROT] control.

Signed-off-by: Etienne Carriere 
Signed-off-by: Gabriel Fernandez 
---
 include/dt-bindings/clock/stm32mp1-clks.h | 27 +++
 1 file changed, 27 insertions(+)

diff --git a/include/dt-bindings/clock/stm32mp1-clks.h 
b/include/dt-bindings/clock/stm32mp1-clks.h
index 4cdaf135829c..e02770b98e6c 100644
--- a/include/dt-bindings/clock/stm32mp1-clks.h
+++ b/include/dt-bindings/clock/stm32mp1-clks.h
@@ -248,4 +248,31 @@
 
 #define STM32MP1_LAST_CLK 232
 
+/* SCMI clock identifiers */
+#define CK_SCMI0_HSE   0
+#define CK_SCMI0_HSI   1
+#define CK_SCMI0_CSI   2
+#define CK_SCMI0_LSE   3
+#define CK_SCMI0_LSI   4
+#define CK_SCMI0_PLL2_Q5
+#define CK_SCMI0_PLL2_R6
+#define CK_SCMI0_MPU   7
+#define CK_SCMI0_AXI   8
+#define CK_SCMI0_BSEC  9
+#define CK_SCMI0_CRYP1 10
+#define CK_SCMI0_GPIOZ 11
+#define CK_SCMI0_HASH1 12
+#define CK_SCMI0_I2C4  13
+#define CK_SCMI0_I2C6  14
+#define CK_SCMI0_IWDG1 15
+#define CK_SCMI0_RNG1  16
+#define CK_SCMI0_RTC   17
+#define CK_SCMI0_RTCAPB18
+#define CK_SCMI0_SPI6  19
+#define CK_SCMI0_USART120
+
+#define CK_SCMI1_PLL3_Q0
+#define CK_SCMI1_PLL3_R1
+#define CK_SCMI1_MCU   2
+
 #endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */
-- 
2.17.1

[PATCH 09/14] dt-bindings: reset: add MCU HOLD BOOT ID for SCMI reset domains on stm32mp15

[gabriel.fernandez]

From: Gabriel Fernandez 

Add ID to SCMI0 to exposes reset controller for the MCU HOLD BOOT resource.

Signed-off-by: Arnaud Pouliquen 
Signed-off-by: Gabriel Fernandez 
---
 include/dt-bindings/reset/stm32mp1-resets.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/dt-bindings/reset/stm32mp1-resets.h 
b/include/dt-bindings/reset/stm32mp1-resets.h
index bc71924faa54..f3a0ed317835 100644
--- a/include/dt-bindings/reset/stm32mp1-resets.h
+++ b/include/dt-bindings/reset/stm32mp1-resets.h
@@ -7,6 +7,7 @@
 #ifndef _DT_BINDINGS_STM32MP1_RESET_H_
 #define _DT_BINDINGS_STM32MP1_RESET_H_
 
+#define MCU_HOLD_BOOT_R2144
 #define LTDC_R 3072
 #define DSI_R  3076
 #define DDRPERFM_R 3080
@@ -117,5 +118,6 @@
 #define RST_SCMI0_RNG1 8
 #define RST_SCMI0_MDMA 9
 #define RST_SCMI0_MCU  10
+#define RST_SCMI0_MCU_HOLD_BOOT11
 
 #endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */
-- 
2.17.1

[PATCH 08/14] dt-bindings: reset: add IDs for SCMI reset domains on stm32mp15

[gabriel.fernandez]

From: Gabriel Fernandez 

stm32mp15 TZ secure firmware provides SCMI reset domains for
secure resources. This change defines the SCMI reset domain
identifiers used by SCMI agents and servers.

Stm32mp15 TZ secure firmware provides SCMI clocks for oscillators, some
PLL output and few secure aware interfaces. This change defines the
SCMI clock identifiers used by SCMI agents and servers.

Server SCMI0 exposes reset controllers for resources under RCC[TZEN]
configuration control.

Signed-off-by: Etienne Carriere 
Signed-off-by: Gabriel Fernandez 
---
 include/dt-bindings/reset/stm32mp1-resets.h | 13 +
 1 file changed, 13 insertions(+)

diff --git a/include/dt-bindings/reset/stm32mp1-resets.h 
b/include/dt-bindings/reset/stm32mp1-resets.h
index f0c3aaef67a0..bc71924faa54 100644
--- a/include/dt-bindings/reset/stm32mp1-resets.h
+++ b/include/dt-bindings/reset/stm32mp1-resets.h
@@ -105,4 +105,17 @@
 #define GPIOJ_R19785
 #define GPIOK_R19786
 
+/* SCMI reset domain identifiers */
+#define RST_SCMI0_SPI6 0
+#define RST_SCMI0_I2C4 1
+#define RST_SCMI0_I2C6 2
+#define RST_SCMI0_USART1   3
+#define RST_SCMI0_STGEN4
+#define RST_SCMI0_GPIOZ5
+#define RST_SCMI0_CRYP16
+#define RST_SCMI0_HASH17
+#define RST_SCMI0_RNG1 8
+#define RST_SCMI0_MDMA 9
+#define RST_SCMI0_MCU  10
+
 #endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */
-- 
2.17.1

[PATCH v2] dt-bindings: clock: remove unused definition for stm32mp1

[gabriel.fernandez]

From: Gabriel Fernandez 

A copy of LTDC_PX and ETHCK_K (LTDC_K and ETHMAC_K) was introduced in
stm32mp1 dt-bindings file by mistake.
These bindings are not used and shouldn't be use to be conform with
convention name of the stm32mp1 clock IP.

Signed-off-by: Gabriel Fernandez 
---
 include/dt-bindings/clock/stm32mp1-clks.h | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/include/dt-bindings/clock/stm32mp1-clks.h 
b/include/dt-bindings/clock/stm32mp1-clks.h
index 90ec780bfc68..4cdaf135829c 100644
--- a/include/dt-bindings/clock/stm32mp1-clks.h
+++ b/include/dt-bindings/clock/stm32mp1-clks.h
@@ -248,7 +248,4 @@
 
 #define STM32MP1_LAST_CLK 232
 
-#define LTDC_K LTDC_PX
-#define ETHMAC_K   ETHCK_K
-
 #endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */
-- 
2.17.0

[PATCH v2 7/7] clk: stm32mp1: fix bit width of hse_rtc divider

[gabriel.fernandez]

From: Gabriel Fernandez 

Fix the bit width of the hse rtc divider because it's off by one.

Fixes: 2c87c9d33117 ("clk: stm32mp1: add RTC clock")
Signed-off-by: Gabriel Fernandez 
---
 drivers/clk/clk-stm32mp1.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index ca987632564e..a0ae8dc16909 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -1962,7 +1962,7 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
  _DIV(RCC_ETHCKSELR, 4, 4, 0, NULL)),
 
/* RTC clock */
-   DIV(NO_ID, "ck_hse_rtc", "ck_hse", 0, RCC_RTCDIVR, 0, 7, 0),
+   DIV(NO_ID, "ck_hse_rtc", "ck_hse", 0, RCC_RTCDIVR, 0, 6, 0),
 
COMPOSITE(RTC, "ck_rtc", rtc_src, CLK_OPS_PARENT_ENABLE |
   CLK_SET_RATE_PARENT,
-- 
2.17.0

[PATCH v2 6/7] clk: stm32mp1: remove unnecessary CLK_DIVIDER_ALLOW_ZERO flag

[gabriel.fernandez]

From: Gabriel Fernandez 

The divisor of ethptp_k and ck_hse_rtc clocks is: 'value register
plus one'.
Then CLK_DIVIDER_ALLOW_ZERO flag has no effect and is useless here.

Signed-off-by: Gabriel Fernandez 
---
 drivers/clk/clk-stm32mp1.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index 8958bc11ff05..ca987632564e 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -1959,11 +1959,10 @@ static const struct clock_config stm32mp1_clock_cfg[] = 
{
  CLK_SET_RATE_NO_REPARENT,
  _NO_GATE,
  _MMUX(M_ETHCK),
- _DIV(RCC_ETHCKSELR, 4, 4, CLK_DIVIDER_ALLOW_ZERO, NULL)),
+ _DIV(RCC_ETHCKSELR, 4, 4, 0, NULL)),
 
/* RTC clock */
-   DIV(NO_ID, "ck_hse_rtc", "ck_hse", 0, RCC_RTCDIVR, 0, 7,
-   CLK_DIVIDER_ALLOW_ZERO),
+   DIV(NO_ID, "ck_hse_rtc", "ck_hse", 0, RCC_RTCDIVR, 0, 7, 0),
 
COMPOSITE(RTC, "ck_rtc", rtc_src, CLK_OPS_PARENT_ENABLE |
   CLK_SET_RATE_PARENT,
-- 
2.17.0

[PATCH v2 3/7] clk: stm32mp1: set ck_csi as critical clock

[gabriel.fernandez]

From: Gabriel Fernandez 

ck_csi is used for IO compensation so it should be
considered as "always-on" and kept on.

Signed-off-by: Gabriel Fernandez 
---
 drivers/clk/clk-stm32mp1.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index e72079de83f4..f9b7d5e9491d 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -1661,7 +1661,9 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
 
/*  External / Internal Oscillators */
GATE_MP1(CK_HSE, "ck_hse", "clk-hse", 0, RCC_OCENSETR, 8, 0),
-   GATE_MP1(CK_CSI, "ck_csi", "clk-csi", 0, RCC_OCENSETR, 4, 0),
+   /* ck_csi is used by IO compensation and should be critical */
+   GATE_MP1(CK_CSI, "ck_csi", "clk-csi", CLK_IS_CRITICAL,
+RCC_OCENSETR, 4, 0),
GATE_MP1(CK_HSI, "ck_hsi", "clk-hsi-div", 0, RCC_OCENSETR, 0, 0),
GATE(CK_LSI, "ck_lsi", "clk-lsi", 0, RCC_RDLSICR, 0, 0),
GATE(CK_LSE, "ck_lse", "clk-lse", 0, RCC_BDCR, 0, 0),
-- 
2.17.0

[PATCH v2 0/7] update STM32MP1 clocks

[gabriel.fernandez]

From: Gabriel Fernandez 

Changes:
v2:
- add more explanation in commit mesages
- add one comment to the code

This patch-set fixes minor corrections (fixes and documentation alignment)
- add missing parent clocks
- don't change parent on set rate for kernel clocks
- set ck_csi clock as critical
- fix divider configuration



Gabriel Fernandez (7):
  clk: stm32mp1: parent clocks update
  clk: stm32mp1: add CLK_SET_RATE_NO_REPARENT to Kernel clocks
  clk: stm32mp1: set ck_csi as critical clock
  clk: stm32mp1: fix mcu divider table
  clk: stm32mp1: fix HSI divider flag
  clk: stm32mp1: remove unnecessary CLK_DIVIDER_ALLOW_ZERO flag
  clk: stm32mp1: fix bit width of hse_rtc divider

 drivers/clk/clk-stm32mp1.c | 37 -
 1 file changed, 20 insertions(+), 17 deletions(-)

-- 
2.17.0

[PATCH v2 2/7] clk: stm32mp1: add CLK_SET_RATE_NO_REPARENT to Kernel clocks

[gabriel.fernandez]

From: Gabriel Fernandez 

STM32MP1 clock IP offers lots of Kernel clocks that are shared
by multiple IP's at the same time.
Then boot loader applies a clock tree that allows to use all IP's
at same time and with the maximum of performance.
Not change parents on a change rate on kernel clocks ensures
the integrity of the system.

Signed-off-by: Gabriel Fernandez 
---
 drivers/clk/clk-stm32mp1.c | 12 +++-
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index be2ed35977ca..e72079de83f4 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -1286,10 +1286,11 @@ _clk_stm32_register_composite(struct device *dev,
MGATE_MP1(_id, _name, _parent, _flags, _mgate)
 
 #define KCLK(_id, _name, _parents, _flags, _mgate, _mmux)\
-COMPOSITE(_id, _name, _parents, CLK_OPS_PARENT_ENABLE | _flags,\
- _MGATE_MP1(_mgate),\
- _MMUX(_mmux),\
- _NO_DIV)
+COMPOSITE(_id, _name, _parents, CLK_OPS_PARENT_ENABLE |\
+  CLK_SET_RATE_NO_REPARENT | _flags,\
+  _MGATE_MP1(_mgate),\
+  _MMUX(_mmux),\
+  _NO_DIV)
 
 enum {
G_SAI1,
@@ -1952,7 +1953,8 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
MGATE_MP1(GPU_K, "gpu_k", "pll2_q", 0, G_GPU),
MGATE_MP1(DAC12_K, "dac12_k", "ck_lsi", 0, G_DAC12),
 
-   COMPOSITE(ETHPTP_K, "ethptp_k", eth_src, CLK_OPS_PARENT_ENABLE,
+   COMPOSITE(ETHPTP_K, "ethptp_k", eth_src, CLK_OPS_PARENT_ENABLE |
+ CLK_SET_RATE_NO_REPARENT,
  _NO_GATE,
  _MMUX(M_ETHCK),
  _DIV(RCC_ETHCKSELR, 4, 4, CLK_DIVIDER_ALLOW_ZERO, NULL)),
-- 
2.17.0

[PATCH v2 1/7] clk: stm32mp1: parent clocks update

[gabriel.fernandez]

From: Gabriel Fernandez 

Fixes parent clock for axi, fdcan, sai and adc12 clocks.

Fixes: e51d297e9a92 ("clk: stm32mp1: add Sub System clocks")
Signed-off-by: Gabriel Fernandez 
---
 drivers/clk/clk-stm32mp1.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index 6a31f7f434ce..be2ed35977ca 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -121,7 +121,7 @@ static const char * const cpu_src[] = {
 };
 
 static const char * const axi_src[] = {
-   "ck_hsi", "ck_hse", "pll2_p", "pll3_p"
+   "ck_hsi", "ck_hse", "pll2_p"
 };
 
 static const char * const per_src[] = {
@@ -225,19 +225,19 @@ static const char * const usart6_src[] = {
 };
 
 static const char * const fdcan_src[] = {
-   "ck_hse", "pll3_q", "pll4_q"
+   "ck_hse", "pll3_q", "pll4_q", "pll4_r"
 };
 
 static const char * const sai_src[] = {
-   "pll4_q", "pll3_q", "i2s_ckin", "ck_per"
+   "pll4_q", "pll3_q", "i2s_ckin", "ck_per", "pll3_r"
 };
 
 static const char * const sai2_src[] = {
-   "pll4_q", "pll3_q", "i2s_ckin", "ck_per", "spdif_ck_symb"
+   "pll4_q", "pll3_q", "i2s_ckin", "ck_per", "spdif_ck_symb", "pll3_r"
 };
 
 static const char * const adc12_src[] = {
-   "pll4_q", "ck_per"
+   "pll4_r", "ck_per", "pll3_q"
 };
 
 static const char * const dsi_src[] = {
-- 
2.17.0

[PATCH v2 5/7] clk: stm32mp1: fix HSI divider flag

[gabriel.fernandez]

From: Gabriel Fernandez 

The divider of HSI (clk-hsi-div) is power of two divider.

Fixes: 9bee94e7b7da ("clk: stm32mp1: Introduce STM32MP1 clock driver")
Signed-off-by: Gabriel Fernandez 
---
 drivers/clk/clk-stm32mp1.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index 8b4e01af4848..8958bc11ff05 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -1656,8 +1656,8 @@ static const struct stm32_mux_cfg ker_mux_cfg[M_LAST] = {
 
 static const struct clock_config stm32mp1_clock_cfg[] = {
/* Oscillator divider */
-   DIV(NO_ID, "clk-hsi-div", "clk-hsi", 0, RCC_HSICFGR, 0, 2,
-   CLK_DIVIDER_READ_ONLY),
+   DIV(NO_ID, "clk-hsi-div", "clk-hsi", CLK_DIVIDER_POWER_OF_TWO,
+   RCC_HSICFGR, 0, 2, CLK_DIVIDER_READ_ONLY),
 
/*  External / Internal Oscillators */
GATE_MP1(CK_HSE, "ck_hse", "clk-hse", 0, RCC_OCENSETR, 8, 0),
-- 
2.17.0

[PATCH v2 4/7] clk: stm32mp1: fix mcu divider table

[gabriel.fernandez]

From: Gabriel Fernandez 

index 8: ck_mcu is divided by 256 (not 512)

Fixes: e51d297e9a92 ("clk: stm32mp1: add Sub System clocks")
Signed-off-by: Gabriel Fernandez 
---
 drivers/clk/clk-stm32mp1.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index f9b7d5e9491d..8b4e01af4848 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -269,7 +269,7 @@ static const struct clk_div_table axi_div_table[] = {
 static const struct clk_div_table mcu_div_table[] = {
{ 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 },
{ 4, 16 }, { 5, 32 }, { 6, 64 }, { 7, 128 },
-   { 8, 512 }, { 9, 512 }, { 10, 512}, { 11, 512 },
+   { 8, 256 }, { 9, 512 }, { 10, 512}, { 11, 512 },
{ 12, 512 }, { 13, 512 }, { 14, 512}, { 15, 512 },
{ 0 },
 };
-- 
2.17.0

[PATCH] dt-bindings: clock: remove unused definition for stm32mp1

[gabriel.fernandez]

From: Gabriel Fernandez 

LTDC_K and ETHMAC_K are not used.

Signed-off-by: Gabriel Fernandez 
---
 include/dt-bindings/clock/stm32mp1-clks.h | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/include/dt-bindings/clock/stm32mp1-clks.h 
b/include/dt-bindings/clock/stm32mp1-clks.h
index 90ec780bfc68..4cdaf135829c 100644
--- a/include/dt-bindings/clock/stm32mp1-clks.h
+++ b/include/dt-bindings/clock/stm32mp1-clks.h
@@ -248,7 +248,4 @@
 
 #define STM32MP1_LAST_CLK 232
 
-#define LTDC_K LTDC_PX
-#define ETHMAC_K   ETHCK_K
-
 #endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */
-- 
2.17.0

[PATCH v1] Input: st-keyscan - fix potential zalloc NULL dereference

[gabriel.fernandez]

From: Gabriel Fernandez 

This patch fixes the following static checker warning:

drivers/input/keyboard/st-keyscan.c:156 keyscan_probe()
error: potential zalloc NULL dereference: 'keypad_data->input_dev'

Reported-by: Dan Carpenter 
Signed-off-by: Gabriel Fernandez 
---
 drivers/input/keyboard/st-keyscan.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/input/keyboard/st-keyscan.c 
b/drivers/input/keyboard/st-keyscan.c
index babcfb165e4f..3b85631fde91 100644
--- a/drivers/input/keyboard/st-keyscan.c
+++ b/drivers/input/keyboard/st-keyscan.c
@@ -153,6 +153,8 @@ static int keyscan_probe(struct platform_device *pdev)
 
input_dev->id.bustype = BUS_HOST;
 
+   keypad_data->input_dev = input_dev;
+
error = keypad_matrix_key_parse_dt(keypad_data);
if (error)
return error;
@@ -168,8 +170,6 @@ static int keyscan_probe(struct platform_device *pdev)
 
input_set_drvdata(input_dev, keypad_data);
 
-   keypad_data->input_dev = input_dev;
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
keypad_data->base = devm_ioremap_resource(>dev, res);
if (IS_ERR(keypad_data->base))
-- 
2.17.0

[PATCH] Input: st-keyscan - fix potential zalloc NULL dereference

[gabriel.fernandez]

From: Gabriel Fernandez 

This patch fixes the following static checker warning:

drivers/input/keyboard/st-keyscan.c:156 keyscan_probe()
error: potential zalloc NULL dereference: 'keypad_data->input_dev'

Reported-by: Dan Carpenter 
Signed-off-by: Gabriel Fernandez 
---
 drivers/input/keyboard/st-keyscan.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/input/keyboard/st-keyscan.c 
b/drivers/input/keyboard/st-keyscan.c
index babcfb165e4f..3b85631fde91 100644
--- a/drivers/input/keyboard/st-keyscan.c
+++ b/drivers/input/keyboard/st-keyscan.c
@@ -153,6 +153,8 @@ static int keyscan_probe(struct platform_device *pdev)
 
input_dev->id.bustype = BUS_HOST;
 
+   keypad_data->input_dev = input_dev;
+
error = keypad_matrix_key_parse_dt(keypad_data);
if (error)
return error;
@@ -168,8 +170,6 @@ static int keyscan_probe(struct platform_device *pdev)
 
input_set_drvdata(input_dev, keypad_data);
 
-   keypad_data->input_dev = input_dev;
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
keypad_data->base = devm_ioremap_resource(>dev, res);
if (IS_ERR(keypad_data->base))
-- 
2.17.0

[PATCH 7/7] clk: stm32mp1: fix bit width of hse_rtc divider

[gabriel.fernandez]

From: Gabriel Fernandez 

This patch fixes the bit width of the hse rtc divider.

Signed-off-by: Gabriel Fernandez 
---
 drivers/clk/clk-stm32mp1.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index 6c99950c6135..fc75cf12f0e5 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -1961,7 +1961,7 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
  _DIV(RCC_ETHCKSELR, 4, 4, 0, NULL)),
 
/* RTC clock */
-   DIV(NO_ID, "ck_hse_rtc", "ck_hse", 0, RCC_RTCDIVR, 0, 7, 0),
+   DIV(NO_ID, "ck_hse_rtc", "ck_hse", 0, RCC_RTCDIVR, 0, 6, 0),
 
COMPOSITE(RTC, "ck_rtc", rtc_src, CLK_OPS_PARENT_ENABLE |
   CLK_SET_RATE_PARENT,
-- 
2.17.0

[PATCH 0/7] update STM32MP1 clocks

[gabriel.fernandez]

From: Gabriel Fernandez 

This patch-set fixes minor corrections (fixes and documentation alignment)
- add missing parent clocks
- don't change parent on set rate for kernel clocks
- set ck_csi clock as critical
- fix divider configuration



Gabriel Fernandez (7):
  clk: stm32mp1: parent clocks update
  clk: stm32mp1: add CLK_SET_RATE_NO_REPARENT to Kernel clocks
  clk: stm32mp1: set ck_csi as critical clock
  clk: stm32mp1: fix mcu divider table
  clk: stm32mp1: fix HSI divider flag
  clk: stm32mp1: remove unnecessary CLK_DIVIDER_ALLOW_ZERO flag
  clk: stm32mp1: fix bit width of hse_rtc divider

 drivers/clk/clk-stm32mp1.c | 36 +++-
 1 file changed, 19 insertions(+), 17 deletions(-)

-- 
2.17.0

[PATCH 2/7] clk: stm32mp1: add CLK_SET_RATE_NO_REPARENT to Kernel clocks

[gabriel.fernandez]

From: Gabriel Fernandez 

Don't change parent during a set rate for Kernel clocks.

Signed-off-by: Gabriel Fernandez 
---
 drivers/clk/clk-stm32mp1.c | 12 +++-
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index be2ed35977ca..e72079de83f4 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -1286,10 +1286,11 @@ _clk_stm32_register_composite(struct device *dev,
MGATE_MP1(_id, _name, _parent, _flags, _mgate)
 
 #define KCLK(_id, _name, _parents, _flags, _mgate, _mmux)\
-COMPOSITE(_id, _name, _parents, CLK_OPS_PARENT_ENABLE | _flags,\
- _MGATE_MP1(_mgate),\
- _MMUX(_mmux),\
- _NO_DIV)
+COMPOSITE(_id, _name, _parents, CLK_OPS_PARENT_ENABLE |\
+  CLK_SET_RATE_NO_REPARENT | _flags,\
+  _MGATE_MP1(_mgate),\
+  _MMUX(_mmux),\
+  _NO_DIV)
 
 enum {
G_SAI1,
@@ -1952,7 +1953,8 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
MGATE_MP1(GPU_K, "gpu_k", "pll2_q", 0, G_GPU),
MGATE_MP1(DAC12_K, "dac12_k", "ck_lsi", 0, G_DAC12),
 
-   COMPOSITE(ETHPTP_K, "ethptp_k", eth_src, CLK_OPS_PARENT_ENABLE,
+   COMPOSITE(ETHPTP_K, "ethptp_k", eth_src, CLK_OPS_PARENT_ENABLE |
+ CLK_SET_RATE_NO_REPARENT,
  _NO_GATE,
  _MMUX(M_ETHCK),
  _DIV(RCC_ETHCKSELR, 4, 4, CLK_DIVIDER_ALLOW_ZERO, NULL)),
-- 
2.17.0

[PATCH 3/7] clk: stm32mp1: set ck_csi as critical clock

[gabriel.fernandez]

From: Gabriel Fernandez 

ck_csi is used for IO compensation so it should be
considered as "always-on" and kept on.

Signed-off-by: Gabriel Fernandez 
---
 drivers/clk/clk-stm32mp1.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index e72079de83f4..5b30e4eeca2c 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -1661,7 +1661,8 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
 
/*  External / Internal Oscillators */
GATE_MP1(CK_HSE, "ck_hse", "clk-hse", 0, RCC_OCENSETR, 8, 0),
-   GATE_MP1(CK_CSI, "ck_csi", "clk-csi", 0, RCC_OCENSETR, 4, 0),
+   GATE_MP1(CK_CSI, "ck_csi", "clk-csi", CLK_IS_CRITICAL,
+RCC_OCENSETR, 4, 0),
GATE_MP1(CK_HSI, "ck_hsi", "clk-hsi-div", 0, RCC_OCENSETR, 0, 0),
GATE(CK_LSI, "ck_lsi", "clk-lsi", 0, RCC_RDLSICR, 0, 0),
GATE(CK_LSE, "ck_lse", "clk-lse", 0, RCC_BDCR, 0, 0),
-- 
2.17.0

[PATCH 6/7] clk: stm32mp1: remove unnecessary CLK_DIVIDER_ALLOW_ZERO flag

[gabriel.fernandez]

From: Gabriel Fernandez 

This patch removes unnecessary CLK_DIVIDER_ALLOW_ZERO flag of
ethptp_k and ck_hse_rtc clocks.

Signed-off-by: Gabriel Fernandez 
---
 drivers/clk/clk-stm32mp1.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index 863586a71d49..6c99950c6135 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -1958,11 +1958,10 @@ static const struct clock_config stm32mp1_clock_cfg[] = 
{
  CLK_SET_RATE_NO_REPARENT,
  _NO_GATE,
  _MMUX(M_ETHCK),
- _DIV(RCC_ETHCKSELR, 4, 4, CLK_DIVIDER_ALLOW_ZERO, NULL)),
+ _DIV(RCC_ETHCKSELR, 4, 4, 0, NULL)),
 
/* RTC clock */
-   DIV(NO_ID, "ck_hse_rtc", "ck_hse", 0, RCC_RTCDIVR, 0, 7,
-   CLK_DIVIDER_ALLOW_ZERO),
+   DIV(NO_ID, "ck_hse_rtc", "ck_hse", 0, RCC_RTCDIVR, 0, 7, 0),
 
COMPOSITE(RTC, "ck_rtc", rtc_src, CLK_OPS_PARENT_ENABLE |
   CLK_SET_RATE_PARENT,
-- 
2.17.0

[PATCH 4/7] clk: stm32mp1: fix mcu divider table

[gabriel.fernandez]

From: Gabriel Fernandez 

index 8: ck_mcuss divided by 256 (not 512)

Signed-off-by: Gabriel Fernandez 
---
 drivers/clk/clk-stm32mp1.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index 5b30e4eeca2c..385dac678a7f 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -269,7 +269,7 @@ static const struct clk_div_table axi_div_table[] = {
 static const struct clk_div_table mcu_div_table[] = {
{ 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 },
{ 4, 16 }, { 5, 32 }, { 6, 64 }, { 7, 128 },
-   { 8, 512 }, { 9, 512 }, { 10, 512}, { 11, 512 },
+   { 8, 256 }, { 9, 512 }, { 10, 512}, { 11, 512 },
{ 12, 512 }, { 13, 512 }, { 14, 512}, { 15, 512 },
{ 0 },
 };
-- 
2.17.0

[PATCH 5/7] clk: stm32mp1: fix HSI divider flag

[gabriel.fernandez]

From: Gabriel Fernandez 

The divider of HSI (clk-hsi-div) is power of two divider.

Signed-off-by: Gabriel Fernandez 
---
 drivers/clk/clk-stm32mp1.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index 385dac678a7f..863586a71d49 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -1656,8 +1656,8 @@ static const struct stm32_mux_cfg ker_mux_cfg[M_LAST] = {
 
 static const struct clock_config stm32mp1_clock_cfg[] = {
/* Oscillator divider */
-   DIV(NO_ID, "clk-hsi-div", "clk-hsi", 0, RCC_HSICFGR, 0, 2,
-   CLK_DIVIDER_READ_ONLY),
+   DIV(NO_ID, "clk-hsi-div", "clk-hsi", CLK_DIVIDER_POWER_OF_TWO,
+   RCC_HSICFGR, 0, 2, CLK_DIVIDER_READ_ONLY),
 
/*  External / Internal Oscillators */
GATE_MP1(CK_HSE, "ck_hse", "clk-hse", 0, RCC_OCENSETR, 8, 0),
-- 
2.17.0

[PATCH 1/7] clk: stm32mp1: parent clocks update

[gabriel.fernandez]

From: Gabriel Fernandez 

This patch updates parent clocks for axi, fdcan, sai and adc12.

Signed-off-by: Gabriel Fernandez 
---
 drivers/clk/clk-stm32mp1.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index 6a31f7f434ce..be2ed35977ca 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -121,7 +121,7 @@ static const char * const cpu_src[] = {
 };
 
 static const char * const axi_src[] = {
-   "ck_hsi", "ck_hse", "pll2_p", "pll3_p"
+   "ck_hsi", "ck_hse", "pll2_p"
 };
 
 static const char * const per_src[] = {
@@ -225,19 +225,19 @@ static const char * const usart6_src[] = {
 };
 
 static const char * const fdcan_src[] = {
-   "ck_hse", "pll3_q", "pll4_q"
+   "ck_hse", "pll3_q", "pll4_q", "pll4_r"
 };
 
 static const char * const sai_src[] = {
-   "pll4_q", "pll3_q", "i2s_ckin", "ck_per"
+   "pll4_q", "pll3_q", "i2s_ckin", "ck_per", "pll3_r"
 };
 
 static const char * const sai2_src[] = {
-   "pll4_q", "pll3_q", "i2s_ckin", "ck_per", "spdif_ck_symb"
+   "pll4_q", "pll3_q", "i2s_ckin", "ck_per", "spdif_ck_symb", "pll3_r"
 };
 
 static const char * const adc12_src[] = {
-   "pll4_q", "ck_per"
+   "pll4_r", "ck_per", "pll3_q"
 };
 
 static const char * const dsi_src[] = {
-- 
2.17.0

[RESEND PATCH] clk: stm32: fix: stm32 clock drivers are not compiled by default

[gabriel.fernandez]

From: Gabriel Fernandez 

Clock driver is mandatory if the machine is selected.
Then don't use 'bool' and 'depends on' commands, but 'def_bool'
with the machine(s).

Fixes: da32d3539fca ("clk: stm32: add configuration flags for each of the stm32 
drivers")

Signed-off-by: Gabriel Fernandez 
Acked-by: Alexandre TORGUE 
---
 drivers/clk/Kconfig | 6 ++
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 24a5bc3..721572a 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -266,15 +266,13 @@ config COMMON_CLK_STM32MP157
  Support for stm32mp157 SoC family clocks
 
 config COMMON_CLK_STM32F
-   bool "Clock driver for stm32f4 and stm32f7 SoC families"
-   depends on MACH_STM32F429 || MACH_STM32F469 || MACH_STM32F746
+   def_bool COMMON_CLK && (MACH_STM32F429 || MACH_STM32F469 || 
MACH_STM32F746)
help
---help---
  Support for stm32f4 and stm32f7 SoC families clocks
 
 config COMMON_CLK_STM32H7
-   bool "Clock driver for stm32h7 SoC family"
-   depends on MACH_STM32H743
+   def_bool COMMON_CLK && MACH_STM32H743
help
---help---
  Support for stm32h7 SoC family clocks
-- 
1.9.1

[RESEND PATCH] clk: stm32: fix: stm32 clock drivers are not compiled by default

[gabriel.fernandez]

From: Gabriel Fernandez 

Clock driver is mandatory if the machine is selected.
Then don't use 'bool' and 'depends on' commands, but 'def_bool'
with the machine(s).

Fixes: da32d3539fca ("clk: stm32: add configuration flags for each of the stm32 
drivers")

Signed-off-by: Gabriel Fernandez 
Acked-by: Alexandre TORGUE 
---
 drivers/clk/Kconfig | 6 ++
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 24a5bc3..721572a 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -266,15 +266,13 @@ config COMMON_CLK_STM32MP157
  Support for stm32mp157 SoC family clocks
 
 config COMMON_CLK_STM32F
-   bool "Clock driver for stm32f4 and stm32f7 SoC families"
-   depends on MACH_STM32F429 || MACH_STM32F469 || MACH_STM32F746
+   def_bool COMMON_CLK && (MACH_STM32F429 || MACH_STM32F469 || 
MACH_STM32F746)
help
---help---
  Support for stm32f4 and stm32f7 SoC families clocks
 
 config COMMON_CLK_STM32H7
-   bool "Clock driver for stm32h7 SoC family"
-   depends on MACH_STM32H743
+   def_bool COMMON_CLK && MACH_STM32H743
help
---help---
  Support for stm32h7 SoC family clocks
-- 
1.9.1

[PATCH] clk: stm32mp1: Add CLK_IGNORE_UNUSED to ck_sys_dbg clock

[gabriel.fernandez]

From: Gabriel Fernandez 

Don't disable the dbg clock if was set by bootloader.

Signed-off-by: Gabriel Fernandez 
---
 drivers/clk/clk-stm32mp1.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index edd3cf4..35dabf1 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -1988,7 +1988,8 @@ enum {
  _DIV(RCC_MCO2CFGR, 4, 4, 0, NULL)),
 
/* Debug clocks */
-   GATE(CK_DBG, "ck_sys_dbg", "ck_axi", 0, RCC_DBGCFGR, 8, 0),
+   GATE(CK_DBG, "ck_sys_dbg", "ck_axi", CLK_IGNORE_UNUSED,
+RCC_DBGCFGR, 8, 0),
 
COMPOSITE(CK_TRACE, "ck_trace", ck_trace_src, CLK_OPS_PARENT_ENABLE,
  _GATE(RCC_DBGCFGR, 9, 0),
-- 
1.9.1

[PATCH] clk: stm32mp1: Add CLK_IGNORE_UNUSED to ck_sys_dbg clock

[gabriel.fernandez]

From: Gabriel Fernandez 

Don't disable the dbg clock if was set by bootloader.

Signed-off-by: Gabriel Fernandez 
---
 drivers/clk/clk-stm32mp1.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index edd3cf4..35dabf1 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -1988,7 +1988,8 @@ enum {
  _DIV(RCC_MCO2CFGR, 4, 4, 0, NULL)),
 
/* Debug clocks */
-   GATE(CK_DBG, "ck_sys_dbg", "ck_axi", 0, RCC_DBGCFGR, 8, 0),
+   GATE(CK_DBG, "ck_sys_dbg", "ck_axi", CLK_IGNORE_UNUSED,
+RCC_DBGCFGR, 8, 0),
 
COMPOSITE(CK_TRACE, "ck_trace", ck_trace_src, CLK_OPS_PARENT_ENABLE,
  _GATE(RCC_DBGCFGR, 9, 0),
-- 
1.9.1

[PATCH] ARM: dts: stm32: add reset binding on stm32mp157c

[gabriel.fernandez]

From: Gabriel Fernandez 

This patch adds reset binding file.

Signed-off-by: Gabriel Fernandez 
---
 arch/arm/boot/dts/stm32mp157c.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi 
b/arch/arm/boot/dts/stm32mp157c.dtsi
index bc3eddc..7e91fd6 100644
--- a/arch/arm/boot/dts/stm32mp157c.dtsi
+++ b/arch/arm/boot/dts/stm32mp157c.dtsi
@@ -5,6 +5,7 @@
  */
 #include 
 #include 
+#include 
 
 / {
#address-cells = <1>;
-- 
1.9.1

[PATCH] ARM: dts: stm32: add reset binding on stm32mp157c

[gabriel.fernandez]

From: Gabriel Fernandez 

This patch adds reset binding file.

Signed-off-by: Gabriel Fernandez 
---
 arch/arm/boot/dts/stm32mp157c.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi 
b/arch/arm/boot/dts/stm32mp157c.dtsi
index bc3eddc..7e91fd6 100644
--- a/arch/arm/boot/dts/stm32mp157c.dtsi
+++ b/arch/arm/boot/dts/stm32mp157c.dtsi
@@ -5,6 +5,7 @@
  */
 #include 
 #include 
+#include 
 
 / {
#address-cells = <1>;
-- 
1.9.1

[PATCH] clk: stm32: fix: stm32 clock drivers are not compiled by default

[gabriel.fernandez]

From: Gabriel Fernandez 

Clock driver is mandatory if the machine is selected.
Then don't use 'bool' and 'depends on' commands, but 'def_bool'
with the machine(s).

Fixes: da32d3539fca ("clk: stm32: add configuration flags for each of the stm32 
drivers")


Signed-off-by: Gabriel Fernandez 
---
 drivers/clk/Kconfig | 6 ++
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 41492e9..34968a3 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -266,15 +266,13 @@ config COMMON_CLK_STM32MP157
  Support for stm32mp157 SoC family clocks
 
 config COMMON_CLK_STM32F
-   bool "Clock driver for stm32f4 and stm32f7 SoC families"
-   depends on MACH_STM32F429 || MACH_STM32F469 || MACH_STM32F746
+   def_bool COMMON_CLK && (MACH_STM32F429 || MACH_STM32F469 || 
MACH_STM32F746)
help
---help---
  Support for stm32f4 and stm32f7 SoC families clocks
 
 config COMMON_CLK_STM32H7
-   bool "Clock driver for stm32h7 SoC family"
-   depends on MACH_STM32H743
+   def_bool COMMON_CLK && MACH_STM32H743
help
---help---
  Support for stm32h7 SoC family clocks
-- 
1.9.1

[PATCH] clk: stm32: fix: stm32 clock drivers are not compiled by default

[gabriel.fernandez]

From: Gabriel Fernandez 

Clock driver is mandatory if the machine is selected.
Then don't use 'bool' and 'depends on' commands, but 'def_bool'
with the machine(s).

Fixes: da32d3539fca ("clk: stm32: add configuration flags for each of the stm32 
drivers")


Signed-off-by: Gabriel Fernandez 
---
 drivers/clk/Kconfig | 6 ++
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 41492e9..34968a3 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -266,15 +266,13 @@ config COMMON_CLK_STM32MP157
  Support for stm32mp157 SoC family clocks
 
 config COMMON_CLK_STM32F
-   bool "Clock driver for stm32f4 and stm32f7 SoC families"
-   depends on MACH_STM32F429 || MACH_STM32F469 || MACH_STM32F746
+   def_bool COMMON_CLK && (MACH_STM32F429 || MACH_STM32F469 || 
MACH_STM32F746)
help
---help---
  Support for stm32f4 and stm32f7 SoC families clocks
 
 config COMMON_CLK_STM32H7
-   bool "Clock driver for stm32h7 SoC family"
-   depends on MACH_STM32H743
+   def_bool COMMON_CLK && MACH_STM32H743
help
---help---
  Support for stm32h7 SoC family clocks
-- 
1.9.1

[PATCH 2/6] clk: stm32mp1: remove unused dfsdm_src[] const

[gabriel.fernandez]

From: Gabriel Fernandez 

This patch remove unused constant.

Signed-off-by: Gabriel Fernandez 
---
 drivers/clk/clk-stm32mp1.c | 4 
 1 file changed, 4 deletions(-)

diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index 62f172c..9a67b1c 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -224,10 +224,6 @@
"pclk2", "pll4_q", "ck_hsi", "ck_csi", "ck_hse"
 };
 
-static const char * const dfsdm_src[] = {
-   "pclk2", "ck_mcu"
-};
-
 static const char * const fdcan_src[] = {
"ck_hse", "pll3_q", "pll4_q"
 };
-- 
1.9.1

[PATCH 6/6] clk: stm32mp1: remove ck_apb_dbg clock

[gabriel.fernandez]

From: Gabriel Fernandez 

It's recommended to use only clk_sys_dbg clock instead to activate
debug IP.

Signed-off-by: Gabriel Fernandez 
---
 drivers/clk/clk-stm32mp1.c| 4 
 include/dt-bindings/clock/stm32mp1-clks.h | 1 -
 2 files changed, 5 deletions(-)

diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index b7b5361..edd3cf4 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -1988,10 +1988,6 @@ enum {
  _DIV(RCC_MCO2CFGR, 4, 4, 0, NULL)),
 
/* Debug clocks */
-   FIXED_FACTOR(NO_ID, "ck_axi_div2", "ck_axi", 0, 1, 2),
-
-   GATE(DBG, "ck_apb_dbg", "ck_axi_div2", 0, RCC_DBGCFGR, 8, 0),
-
GATE(CK_DBG, "ck_sys_dbg", "ck_axi", 0, RCC_DBGCFGR, 8, 0),
 
COMPOSITE(CK_TRACE, "ck_trace", ck_trace_src, CLK_OPS_PARENT_ENABLE,
diff --git a/include/dt-bindings/clock/stm32mp1-clks.h 
b/include/dt-bindings/clock/stm32mp1-clks.h
index 6c807fd..90ec780 100644
--- a/include/dt-bindings/clock/stm32mp1-clks.h
+++ b/include/dt-bindings/clock/stm32mp1-clks.h
@@ -229,7 +229,6 @@
 #define CK_MCO2212
 
 /* TRACE & DEBUG clocks */
-#define DBG213
 #define CK_DBG 214
 #define CK_TRACE   215
 
-- 
1.9.1

[PATCH 3/6] clk: stm32mp1: fix SAI3 & SAI4 clocks

[gabriel.fernandez]

From: Gabriel Fernandez 

fix bad copy / paste.
SAI3 & SAI4 used gate of SAI2 instead SAI3 & SAI4

Signed-off-by: Gabriel Fernandez 
---
 drivers/clk/clk-stm32mp1.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index 9a67b1c..eefed49 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -1942,8 +1942,8 @@ enum {
KCLK(FDCAN_K, "fdcan_k", fdcan_src, 0, G_FDCAN, M_FDCAN),
KCLK(SAI1_K, "sai1_k", sai_src, 0, G_SAI1, M_SAI1),
KCLK(SAI2_K, "sai2_k", sai2_src, 0, G_SAI2, M_SAI2),
-   KCLK(SAI3_K, "sai3_k", sai_src, 0, G_SAI2, M_SAI3),
-   KCLK(SAI4_K, "sai4_k", sai_src, 0, G_SAI2, M_SAI4),
+   KCLK(SAI3_K, "sai3_k", sai_src, 0, G_SAI3, M_SAI3),
+   KCLK(SAI4_K, "sai4_k", sai_src, 0, G_SAI4, M_SAI4),
KCLK(ADC12_K, "adc12_k", adc12_src, 0, G_ADC12, M_ADC12),
KCLK(DSI_K, "dsi_k", dsi_src, 0, G_DSI, M_DSI),
KCLK(ADFSDM_K, "adfsdm_k", sai_src, 0, G_ADFSDM, M_SAI1),
-- 
1.9.1

[PATCH 2/6] clk: stm32mp1: remove unused dfsdm_src[] const

[gabriel.fernandez]

From: Gabriel Fernandez 

This patch remove unused constant.

Signed-off-by: Gabriel Fernandez 
---
 drivers/clk/clk-stm32mp1.c | 4 
 1 file changed, 4 deletions(-)

diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index 62f172c..9a67b1c 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -224,10 +224,6 @@
"pclk2", "pll4_q", "ck_hsi", "ck_csi", "ck_hse"
 };
 
-static const char * const dfsdm_src[] = {
-   "pclk2", "ck_mcu"
-};
-
 static const char * const fdcan_src[] = {
"ck_hse", "pll3_q", "pll4_q"
 };
-- 
1.9.1

[PATCH 6/6] clk: stm32mp1: remove ck_apb_dbg clock

[gabriel.fernandez]

From: Gabriel Fernandez 

It's recommended to use only clk_sys_dbg clock instead to activate
debug IP.

Signed-off-by: Gabriel Fernandez 
---
 drivers/clk/clk-stm32mp1.c| 4 
 include/dt-bindings/clock/stm32mp1-clks.h | 1 -
 2 files changed, 5 deletions(-)

diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index b7b5361..edd3cf4 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -1988,10 +1988,6 @@ enum {
  _DIV(RCC_MCO2CFGR, 4, 4, 0, NULL)),
 
/* Debug clocks */
-   FIXED_FACTOR(NO_ID, "ck_axi_div2", "ck_axi", 0, 1, 2),
-
-   GATE(DBG, "ck_apb_dbg", "ck_axi_div2", 0, RCC_DBGCFGR, 8, 0),
-
GATE(CK_DBG, "ck_sys_dbg", "ck_axi", 0, RCC_DBGCFGR, 8, 0),
 
COMPOSITE(CK_TRACE, "ck_trace", ck_trace_src, CLK_OPS_PARENT_ENABLE,
diff --git a/include/dt-bindings/clock/stm32mp1-clks.h 
b/include/dt-bindings/clock/stm32mp1-clks.h
index 6c807fd..90ec780 100644
--- a/include/dt-bindings/clock/stm32mp1-clks.h
+++ b/include/dt-bindings/clock/stm32mp1-clks.h
@@ -229,7 +229,6 @@
 #define CK_MCO2212
 
 /* TRACE & DEBUG clocks */
-#define DBG213
 #define CK_DBG 214
 #define CK_TRACE   215
 
-- 
1.9.1

[PATCH 3/6] clk: stm32mp1: fix SAI3 & SAI4 clocks

[gabriel.fernandez]

From: Gabriel Fernandez 

fix bad copy / paste.
SAI3 & SAI4 used gate of SAI2 instead SAI3 & SAI4

Signed-off-by: Gabriel Fernandez 
---
 drivers/clk/clk-stm32mp1.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index 9a67b1c..eefed49 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -1942,8 +1942,8 @@ enum {
KCLK(FDCAN_K, "fdcan_k", fdcan_src, 0, G_FDCAN, M_FDCAN),
KCLK(SAI1_K, "sai1_k", sai_src, 0, G_SAI1, M_SAI1),
KCLK(SAI2_K, "sai2_k", sai2_src, 0, G_SAI2, M_SAI2),
-   KCLK(SAI3_K, "sai3_k", sai_src, 0, G_SAI2, M_SAI3),
-   KCLK(SAI4_K, "sai4_k", sai_src, 0, G_SAI2, M_SAI4),
+   KCLK(SAI3_K, "sai3_k", sai_src, 0, G_SAI3, M_SAI3),
+   KCLK(SAI4_K, "sai4_k", sai_src, 0, G_SAI4, M_SAI4),
KCLK(ADC12_K, "adc12_k", adc12_src, 0, G_ADC12, M_ADC12),
KCLK(DSI_K, "dsi_k", dsi_src, 0, G_DSI, M_DSI),
KCLK(ADFSDM_K, "adfsdm_k", sai_src, 0, G_ADFSDM, M_SAI1),
-- 
1.9.1

[PATCH 0/6] stm32mp1 clock update

[gabriel.fernandez]

From: Gabriel Fernandez 

This patch-set adds minor corrections
- sparse corections
- add tzc2 missing clock
- remove unused constant
- fix SAI3 & SAI4 clocks
- set stgen_k clock as critical
- remove not useful ck_apb_dbg clock

Gabriel Fernandez (6):
  clk: stm32mp1: add missing static
  clk: stm32mp1: remove unused dfsdm_src[] const
  clk: stm32mp1: fix SAI3 & SAI4 clocks
  clk: stm32mp1: add missing tzc2 clock
  clk: stm32mp1: set stgen_k clock as critical
  clk: stm32mp1: remove unuseless ck_apb_dbg clock

 drivers/clk/clk-stm32mp1.c| 54 +--
 include/dt-bindings/clock/stm32mp1-clks.h |  4 +--
 2 files changed, 25 insertions(+), 33 deletions(-)

-- 
1.9.1

[PATCH 0/6] stm32mp1 clock update

[gabriel.fernandez]

From: Gabriel Fernandez 

This patch-set adds minor corrections
- sparse corections
- add tzc2 missing clock
- remove unused constant
- fix SAI3 & SAI4 clocks
- set stgen_k clock as critical
- remove not useful ck_apb_dbg clock

Gabriel Fernandez (6):
  clk: stm32mp1: add missing static
  clk: stm32mp1: remove unused dfsdm_src[] const
  clk: stm32mp1: fix SAI3 & SAI4 clocks
  clk: stm32mp1: add missing tzc2 clock
  clk: stm32mp1: set stgen_k clock as critical
  clk: stm32mp1: remove unuseless ck_apb_dbg clock

 drivers/clk/clk-stm32mp1.c| 54 +--
 include/dt-bindings/clock/stm32mp1-clks.h |  4 +--
 2 files changed, 25 insertions(+), 33 deletions(-)

-- 
1.9.1

[PATCH 1/6] clk: stm32mp1: add missing static

[gabriel.fernandez]

From: Gabriel Fernandez 

Add missing static for const parent names and clock ops.

Signed-off-by: Gabriel Fernandez 
---
 drivers/clk/clk-stm32mp1.c | 30 ++
 1 file changed, 14 insertions(+), 16 deletions(-)

diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index f1d5967..62f172c 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -216,7 +216,7 @@
"pclk5", "pll3_q", "ck_hsi", "ck_csi", "pll4_q", "ck_hse"
 };
 
-const char * const usart234578_src[] = {
+static const char * const usart234578_src[] = {
"pclk1", "pll4_q", "ck_hsi", "ck_csi", "ck_hse"
 };
 
@@ -316,10 +316,8 @@ struct stm32_clk_mgate {
 struct clock_config {
u32 id;
const char *name;
-   union {
-   const char *parent_name;
-   const char * const *parent_names;
-   };
+   const char *parent_name;
+   const char * const *parent_names;
int num_parents;
unsigned long flags;
void *cfg;
@@ -469,7 +467,7 @@ static void mp1_gate_clk_disable(struct clk_hw *hw)
}
 }
 
-const struct clk_ops mp1_gate_clk_ops = {
+static const struct clk_ops mp1_gate_clk_ops = {
.enable = mp1_gate_clk_enable,
.disable= mp1_gate_clk_disable,
.is_enabled = clk_gate_is_enabled,
@@ -698,7 +696,7 @@ static void mp1_mgate_clk_disable(struct clk_hw *hw)
mp1_gate_clk_disable(hw);
 }
 
-const struct clk_ops mp1_mgate_clk_ops = {
+static const struct clk_ops mp1_mgate_clk_ops = {
.enable = mp1_mgate_clk_enable,
.disable= mp1_mgate_clk_disable,
.is_enabled = clk_gate_is_enabled,
@@ -732,7 +730,7 @@ static int clk_mmux_set_parent(struct clk_hw *hw, u8 index)
return 0;
 }
 
-const struct clk_ops clk_mmux_ops = {
+static const struct clk_ops clk_mmux_ops = {
.get_parent = clk_mmux_get_parent,
.set_parent = clk_mmux_set_parent,
.determine_rate = __clk_mux_determine_rate,
@@ -1048,10 +1046,10 @@ struct stm32_pll_cfg {
u32 offset;
 };
 
-struct clk_hw *_clk_register_pll(struct device *dev,
-struct clk_hw_onecell_data *clk_data,
-void __iomem *base, spinlock_t *lock,
-const struct clock_config *cfg)
+static struct clk_hw *_clk_register_pll(struct device *dev,
+   struct clk_hw_onecell_data *clk_data,
+   void __iomem *base, spinlock_t *lock,
+   const struct clock_config *cfg)
 {
struct stm32_pll_cfg *stm_pll_cfg = cfg->cfg;
 
@@ -1417,7 +1415,7 @@ enum {
G_LAST
 };
 
-struct stm32_mgate mp1_mgate[G_LAST];
+static struct stm32_mgate mp1_mgate[G_LAST];
 
 #define _K_GATE(_id, _gate_offset, _gate_bit_idx, _gate_flags,\
   _mgate, _ops)\
@@ -1440,7 +1438,7 @@ enum {
   _mgate[_id], _mgate_clk_ops)
 
 /* Peripheral gates */
-struct stm32_gate_cfg per_gate_cfg[G_LAST] = {
+static struct stm32_gate_cfg per_gate_cfg[G_LAST] = {
/* Multi gates */
K_GATE(G_MDIO,  RCC_APB1ENSETR, 31, 0),
K_MGATE(G_DAC12,RCC_APB1ENSETR, 29, 0),
@@ -1600,7 +1598,7 @@ enum {
M_LAST
 };
 
-struct stm32_mmux ker_mux[M_LAST];
+static struct stm32_mmux ker_mux[M_LAST];
 
 #define _K_MUX(_id, _offset, _shift, _width, _mux_flags, _mmux, _ops)\
[_id] = {\
@@ -1623,7 +1621,7 @@ enum {
_K_MUX(_id, _offset, _shift, _width, _mux_flags,\
_mux[_id], _mmux_ops)
 
-const struct stm32_mux_cfg ker_mux_cfg[M_LAST] = {
+static const struct stm32_mux_cfg ker_mux_cfg[M_LAST] = {
/* Kernel multi mux */
K_MMUX(M_SDMMC12, RCC_SDMMC12CKSELR, 0, 3, 0),
K_MMUX(M_SPI23, RCC_SPI2S23CKSELR, 0, 3, 0),
-- 
1.9.1

[PATCH 1/6] clk: stm32mp1: add missing static

[gabriel.fernandez]

From: Gabriel Fernandez 

Add missing static for const parent names and clock ops.

Signed-off-by: Gabriel Fernandez 
---
 drivers/clk/clk-stm32mp1.c | 30 ++
 1 file changed, 14 insertions(+), 16 deletions(-)

diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index f1d5967..62f172c 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -216,7 +216,7 @@
"pclk5", "pll3_q", "ck_hsi", "ck_csi", "pll4_q", "ck_hse"
 };
 
-const char * const usart234578_src[] = {
+static const char * const usart234578_src[] = {
"pclk1", "pll4_q", "ck_hsi", "ck_csi", "ck_hse"
 };
 
@@ -316,10 +316,8 @@ struct stm32_clk_mgate {
 struct clock_config {
u32 id;
const char *name;
-   union {
-   const char *parent_name;
-   const char * const *parent_names;
-   };
+   const char *parent_name;
+   const char * const *parent_names;
int num_parents;
unsigned long flags;
void *cfg;
@@ -469,7 +467,7 @@ static void mp1_gate_clk_disable(struct clk_hw *hw)
}
 }
 
-const struct clk_ops mp1_gate_clk_ops = {
+static const struct clk_ops mp1_gate_clk_ops = {
.enable = mp1_gate_clk_enable,
.disable= mp1_gate_clk_disable,
.is_enabled = clk_gate_is_enabled,
@@ -698,7 +696,7 @@ static void mp1_mgate_clk_disable(struct clk_hw *hw)
mp1_gate_clk_disable(hw);
 }
 
-const struct clk_ops mp1_mgate_clk_ops = {
+static const struct clk_ops mp1_mgate_clk_ops = {
.enable = mp1_mgate_clk_enable,
.disable= mp1_mgate_clk_disable,
.is_enabled = clk_gate_is_enabled,
@@ -732,7 +730,7 @@ static int clk_mmux_set_parent(struct clk_hw *hw, u8 index)
return 0;
 }
 
-const struct clk_ops clk_mmux_ops = {
+static const struct clk_ops clk_mmux_ops = {
.get_parent = clk_mmux_get_parent,
.set_parent = clk_mmux_set_parent,
.determine_rate = __clk_mux_determine_rate,
@@ -1048,10 +1046,10 @@ struct stm32_pll_cfg {
u32 offset;
 };
 
-struct clk_hw *_clk_register_pll(struct device *dev,
-struct clk_hw_onecell_data *clk_data,
-void __iomem *base, spinlock_t *lock,
-const struct clock_config *cfg)
+static struct clk_hw *_clk_register_pll(struct device *dev,
+   struct clk_hw_onecell_data *clk_data,
+   void __iomem *base, spinlock_t *lock,
+   const struct clock_config *cfg)
 {
struct stm32_pll_cfg *stm_pll_cfg = cfg->cfg;
 
@@ -1417,7 +1415,7 @@ enum {
G_LAST
 };
 
-struct stm32_mgate mp1_mgate[G_LAST];
+static struct stm32_mgate mp1_mgate[G_LAST];
 
 #define _K_GATE(_id, _gate_offset, _gate_bit_idx, _gate_flags,\
   _mgate, _ops)\
@@ -1440,7 +1438,7 @@ enum {
   _mgate[_id], _mgate_clk_ops)
 
 /* Peripheral gates */
-struct stm32_gate_cfg per_gate_cfg[G_LAST] = {
+static struct stm32_gate_cfg per_gate_cfg[G_LAST] = {
/* Multi gates */
K_GATE(G_MDIO,  RCC_APB1ENSETR, 31, 0),
K_MGATE(G_DAC12,RCC_APB1ENSETR, 29, 0),
@@ -1600,7 +1598,7 @@ enum {
M_LAST
 };
 
-struct stm32_mmux ker_mux[M_LAST];
+static struct stm32_mmux ker_mux[M_LAST];
 
 #define _K_MUX(_id, _offset, _shift, _width, _mux_flags, _mmux, _ops)\
[_id] = {\
@@ -1623,7 +1621,7 @@ enum {
_K_MUX(_id, _offset, _shift, _width, _mux_flags,\
_mux[_id], _mmux_ops)
 
-const struct stm32_mux_cfg ker_mux_cfg[M_LAST] = {
+static const struct stm32_mux_cfg ker_mux_cfg[M_LAST] = {
/* Kernel multi mux */
K_MMUX(M_SDMMC12, RCC_SDMMC12CKSELR, 0, 3, 0),
K_MMUX(M_SPI23, RCC_SPI2S23CKSELR, 0, 3, 0),
-- 
1.9.1

[PATCH 5/6] clk: stm32mp1: set stgen_k clock as critical

[gabriel.fernandez]

From: Gabriel Fernandez 

stgen_k should be declared as critical to avoid blocking console
when ck_hsi is not used.

Signed-off-by: Gabriel Fernandez 
---
 drivers/clk/clk-stm32mp1.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index e32fc23..b7b5361 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -1913,8 +1913,7 @@ enum {
KCLK(RNG1_K, "rng1_k", rng_src, 0, G_RNG1, M_RNG1),
KCLK(RNG2_K, "rng2_k", rng_src, 0, G_RNG2, M_RNG2),
KCLK(USBPHY_K, "usbphy_k", usbphy_src, 0, G_USBPHY, M_USBPHY),
-   KCLK(STGEN_K, "stgen_k",  stgen_src, CLK_IGNORE_UNUSED,
-G_STGEN, M_STGEN),
+   KCLK(STGEN_K, "stgen_k", stgen_src, CLK_IS_CRITICAL, G_STGEN, M_STGEN),
KCLK(SPDIF_K, "spdif_k", spdif_src, 0, G_SPDIF, M_SPDIF),
KCLK(SPI1_K, "spi1_k", spi123_src, 0, G_SPI1, M_SPI1),
KCLK(SPI2_K, "spi2_k", spi123_src, 0, G_SPI2, M_SPI23),
-- 
1.9.1

[PATCH 4/6] clk: stm32mp1: add missing tzc2 clock

[gabriel.fernandez]

From: Gabriel Fernandez 

This patch adds tzc2 clock and rename tzc clock into tzc1

Signed-off-by: Gabriel Fernandez 
---
 drivers/clk/clk-stm32mp1.c| 9 ++---
 include/dt-bindings/clock/stm32mp1-clks.h | 3 ++-
 2 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index eefed49..e32fc23 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -1399,7 +1399,8 @@ enum {
G_USBH,
G_ETHSTP,
G_RTCAPB,
-   G_TZC,
+   G_TZC1,
+   G_TZC2,
G_TZPC,
G_IWDG1,
G_BSEC,
@@ -1500,7 +1501,8 @@ enum {
K_GATE(G_BSEC,  RCC_APB5ENSETR, 16, 0),
K_GATE(G_IWDG1, RCC_APB5ENSETR, 15, 0),
K_GATE(G_TZPC,  RCC_APB5ENSETR, 13, 0),
-   K_GATE(G_TZC,   RCC_APB5ENSETR, 12, 0),
+   K_GATE(G_TZC2,  RCC_APB5ENSETR, 12, 0),
+   K_GATE(G_TZC1,  RCC_APB5ENSETR, 11, 0),
K_GATE(G_RTCAPB,RCC_APB5ENSETR, 8, 0),
K_MGATE(G_USART1,   RCC_APB5ENSETR, 4, 0),
K_MGATE(G_I2C6, RCC_APB5ENSETR, 3, 0),
@@ -1854,7 +1856,8 @@ enum {
PCLK(USART1, "usart1", "pclk5", 0, G_USART1),
PCLK(RTCAPB, "rtcapb", "pclk5", CLK_IGNORE_UNUSED |
 CLK_IS_CRITICAL, G_RTCAPB),
-   PCLK(TZC, "tzc", "pclk5", CLK_IGNORE_UNUSED, G_TZC),
+   PCLK(TZC1, "tzc1", "ck_axi", CLK_IGNORE_UNUSED, G_TZC1),
+   PCLK(TZC2, "tzc2", "ck_axi", CLK_IGNORE_UNUSED, G_TZC2),
PCLK(TZPC, "tzpc", "pclk5", CLK_IGNORE_UNUSED, G_TZPC),
PCLK(IWDG1, "iwdg1", "pclk5", 0, G_IWDG1),
PCLK(BSEC, "bsec", "pclk5", CLK_IGNORE_UNUSED, G_BSEC),
diff --git a/include/dt-bindings/clock/stm32mp1-clks.h 
b/include/dt-bindings/clock/stm32mp1-clks.h
index 86e3ec6..6c807fd 100644
--- a/include/dt-bindings/clock/stm32mp1-clks.h
+++ b/include/dt-bindings/clock/stm32mp1-clks.h
@@ -76,7 +76,7 @@
 #define I2C6   63
 #define USART1 64
 #define RTCAPB 65
-#define TZC66
+#define TZC1   66
 #define TZPC   67
 #define IWDG1  68
 #define BSEC   69
@@ -123,6 +123,7 @@
 #define CRC1   110
 #define USBH   111
 #define ETHSTP 112
+#define TZC2   113
 
 /* Kernel clocks */
 #define SDMMC1_K   118
-- 
1.9.1

[PATCH 4/6] clk: stm32mp1: add missing tzc2 clock

[gabriel.fernandez]

From: Gabriel Fernandez 

This patch adds tzc2 clock and rename tzc clock into tzc1

Signed-off-by: Gabriel Fernandez 
---
 drivers/clk/clk-stm32mp1.c| 9 ++---
 include/dt-bindings/clock/stm32mp1-clks.h | 3 ++-
 2 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index eefed49..e32fc23 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -1399,7 +1399,8 @@ enum {
G_USBH,
G_ETHSTP,
G_RTCAPB,
-   G_TZC,
+   G_TZC1,
+   G_TZC2,
G_TZPC,
G_IWDG1,
G_BSEC,
@@ -1500,7 +1501,8 @@ enum {
K_GATE(G_BSEC,  RCC_APB5ENSETR, 16, 0),
K_GATE(G_IWDG1, RCC_APB5ENSETR, 15, 0),
K_GATE(G_TZPC,  RCC_APB5ENSETR, 13, 0),
-   K_GATE(G_TZC,   RCC_APB5ENSETR, 12, 0),
+   K_GATE(G_TZC2,  RCC_APB5ENSETR, 12, 0),
+   K_GATE(G_TZC1,  RCC_APB5ENSETR, 11, 0),
K_GATE(G_RTCAPB,RCC_APB5ENSETR, 8, 0),
K_MGATE(G_USART1,   RCC_APB5ENSETR, 4, 0),
K_MGATE(G_I2C6, RCC_APB5ENSETR, 3, 0),
@@ -1854,7 +1856,8 @@ enum {
PCLK(USART1, "usart1", "pclk5", 0, G_USART1),
PCLK(RTCAPB, "rtcapb", "pclk5", CLK_IGNORE_UNUSED |
 CLK_IS_CRITICAL, G_RTCAPB),
-   PCLK(TZC, "tzc", "pclk5", CLK_IGNORE_UNUSED, G_TZC),
+   PCLK(TZC1, "tzc1", "ck_axi", CLK_IGNORE_UNUSED, G_TZC1),
+   PCLK(TZC2, "tzc2", "ck_axi", CLK_IGNORE_UNUSED, G_TZC2),
PCLK(TZPC, "tzpc", "pclk5", CLK_IGNORE_UNUSED, G_TZPC),
PCLK(IWDG1, "iwdg1", "pclk5", 0, G_IWDG1),
PCLK(BSEC, "bsec", "pclk5", CLK_IGNORE_UNUSED, G_BSEC),
diff --git a/include/dt-bindings/clock/stm32mp1-clks.h 
b/include/dt-bindings/clock/stm32mp1-clks.h
index 86e3ec6..6c807fd 100644
--- a/include/dt-bindings/clock/stm32mp1-clks.h
+++ b/include/dt-bindings/clock/stm32mp1-clks.h
@@ -76,7 +76,7 @@
 #define I2C6   63
 #define USART1 64
 #define RTCAPB 65
-#define TZC66
+#define TZC1   66
 #define TZPC   67
 #define IWDG1  68
 #define BSEC   69
@@ -123,6 +123,7 @@
 #define CRC1   110
 #define USBH   111
 #define ETHSTP 112
+#define TZC2   113
 
 /* Kernel clocks */
 #define SDMMC1_K   118
-- 
1.9.1

[PATCH 5/6] clk: stm32mp1: set stgen_k clock as critical

[gabriel.fernandez]

From: Gabriel Fernandez 

stgen_k should be declared as critical to avoid blocking console
when ck_hsi is not used.

Signed-off-by: Gabriel Fernandez 
---
 drivers/clk/clk-stm32mp1.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index e32fc23..b7b5361 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -1913,8 +1913,7 @@ enum {
KCLK(RNG1_K, "rng1_k", rng_src, 0, G_RNG1, M_RNG1),
KCLK(RNG2_K, "rng2_k", rng_src, 0, G_RNG2, M_RNG2),
KCLK(USBPHY_K, "usbphy_k", usbphy_src, 0, G_USBPHY, M_USBPHY),
-   KCLK(STGEN_K, "stgen_k",  stgen_src, CLK_IGNORE_UNUSED,
-G_STGEN, M_STGEN),
+   KCLK(STGEN_K, "stgen_k", stgen_src, CLK_IS_CRITICAL, G_STGEN, M_STGEN),
KCLK(SPDIF_K, "spdif_k", spdif_src, 0, G_SPDIF, M_SPDIF),
KCLK(SPI1_K, "spi1_k", spi123_src, 0, G_SPI1, M_SPI1),
KCLK(SPI2_K, "spi2_k", spi123_src, 0, G_SPI2, M_SPI23),
-- 
1.9.1

[PATCH v3 1/2] dt-bindings: reset: add STM32MP1 resets

[gabriel.fernandez]

From: Gabriel Fernandez 

This patch adds the reset binding entry for STM32MP1

Signed-off-by: Gabriel Fernandez 
Reviewed-by: Rob Herring 
---
 .../devicetree/bindings/reset/st,stm32mp1-rcc.txt  |   6 ++
 include/dt-bindings/reset/stm32mp1-resets.h| 108 +
 2 files changed, 114 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/reset/st,stm32mp1-rcc.txt
 create mode 100644 include/dt-bindings/reset/stm32mp1-resets.h

diff --git a/Documentation/devicetree/bindings/reset/st,stm32mp1-rcc.txt 
b/Documentation/devicetree/bindings/reset/st,stm32mp1-rcc.txt
new file mode 100644
index 000..b4edaf7
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/st,stm32mp1-rcc.txt
@@ -0,0 +1,6 @@
+STMicroelectronics STM32MP1 Peripheral Reset Controller
+===
+
+The RCC IP is both a reset and a clock controller.
+
+Please see Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.txt
diff --git a/include/dt-bindings/reset/stm32mp1-resets.h 
b/include/dt-bindings/reset/stm32mp1-resets.h
new file mode 100644
index 000..f0c3aae
--- /dev/null
+++ b/include/dt-bindings/reset/stm32mp1-resets.h
@@ -0,0 +1,108 @@
+/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
+/*
+ * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
+ * Author: Gabriel Fernandez  for STMicroelectronics.
+ */
+
+#ifndef _DT_BINDINGS_STM32MP1_RESET_H_
+#define _DT_BINDINGS_STM32MP1_RESET_H_
+
+#define LTDC_R 3072
+#define DSI_R  3076
+#define DDRPERFM_R 3080
+#define USBPHY_R   3088
+#define SPI6_R 3136
+#define I2C4_R 3138
+#define I2C6_R 3139
+#define USART1_R   3140
+#define STGEN_R3156
+#define GPIOZ_R3200
+#define CRYP1_R3204
+#define HASH1_R3205
+#define RNG1_R 3206
+#define AXIM_R 3216
+#define GPU_R  3269
+#define ETHMAC_R   3274
+#define FMC_R  3276
+#define QSPI_R 3278
+#define SDMMC1_R   3280
+#define SDMMC2_R   3281
+#define CRC1_R 3284
+#define USBH_R 3288
+#define MDMA_R 3328
+#define MCU_R  8225
+#define TIM2_R 19456
+#define TIM3_R 19457
+#define TIM4_R 19458
+#define TIM5_R 19459
+#define TIM6_R 19460
+#define TIM7_R 19461
+#define TIM12_R16462
+#define TIM13_R16463
+#define TIM14_R16464
+#define LPTIM1_R   19465
+#define SPI2_R 19467
+#define SPI3_R 19468
+#define USART2_R   19470
+#define USART3_R   19471
+#define UART4_R19472
+#define UART5_R19473
+#define UART7_R19474
+#define UART8_R19475
+#define I2C1_R 19477
+#define I2C2_R 19478
+#define I2C3_R 19479
+#define I2C5_R 19480
+#define SPDIF_R19482
+#define CEC_R  19483
+#define DAC12_R19485
+#define MDIO_R 19847
+#define TIM1_R 19520
+#define TIM8_R 19521
+#define TIM15_R19522
+#define TIM16_R19523
+#define TIM17_R19524
+#define SPI1_R 19528
+#define SPI4_R 19529
+#define SPI5_R 19530
+#define USART6_R   19533
+#define SAI1_R 19536
+#define SAI2_R 19537
+#define SAI3_R 19538
+#define DFSDM_R19540
+#define FDCAN_R19544
+#define LPTIM2_R   19584
+#define LPTIM3_R   19585
+#define LPTIM4_R   19586
+#define LPTIM5_R   19587
+#define SAI4_R 19592
+#define SYSCFG_R   19595
+#define VREF_R 19597
+#define TMPSENS_R  19600
+#define PMBCTRL_R  19601
+#define DMA1_R 19648
+#define DMA2_R 19649
+#define DMAMUX_R   19650
+#define ADC12_R19653
+#define USBO_R 19656
+#define SDMMC3_R   19664
+#define CAMITF_R   19712
+#define CRYP2_R19716
+#define HASH2_R19717
+#define RNG2_R 19718
+#define CRC2_R 19719
+#define HSEM_R 19723
+#define MBOX_R 19724
+#define GPIOA_R19776
+#define GPIOB_R19777
+#define GPIOC_R19778
+#define GPIOD_R19779
+#define GPIOE_R19780
+#define GPIOF_R19781
+#define GPIOG_R19782
+#define GPIOH_R19783
+#define GPIOI_R19784
+#define GPIOJ_R19785
+#define GPIOK_R19786
+
+#endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */
-- 
1.9.1

[PATCH v3 2/2] reset: stm32mp1: Enable stm32mp1 reset driver

[gabriel.fernandez]

From: Gabriel Fernandez 

stm32mp1 RCC IP 1 has a reset SET register and a reset CLEAR register.

Writing '0' on reset SET register has no effect
Writing '1' on reset SET register
activates the reset of the corresponding peripheral

Writing '0' on reset CLEAR register has no effect
Writing '1' on reset CLEAR register
releases the reset of the corresponding peripheral

See Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.txt

Signed-off-by: Gabriel Fernandez 
---
 drivers/reset/Kconfig  |   6 +++
 drivers/reset/Makefile |   1 +
 drivers/reset/reset-stm32mp1.c | 115 +
 3 files changed, 122 insertions(+)
 create mode 100644 drivers/reset/reset-stm32mp1.c

diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 1efbc6c..c0b292b 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -97,6 +97,12 @@ config RESET_SIMPLE
   - Allwinner SoCs
   - ZTE's zx2967 family
 
+config RESET_STM32MP157
+   bool "STM32MP157 Reset Driver" if COMPILE_TEST
+   default MACH_STM32MP157
+   help
+ This enables the RCC reset controller driver for STM32 MPUs.
+
 config RESET_SUNXI
bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI
default ARCH_SUNXI
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 132c24f..c1261dc 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_RESET_MESON) += reset-meson.o
 obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
 obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o
 obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
+obj-$(CONFIG_RESET_STM32MP157) += reset-stm32mp1.o
 obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
 obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
 obj-$(CONFIG_RESET_TI_SYSCON) += reset-ti-syscon.o
diff --git a/drivers/reset/reset-stm32mp1.c b/drivers/reset/reset-stm32mp1.c
new file mode 100644
index 000..b221a28
--- /dev/null
+++ b/drivers/reset/reset-stm32mp1.c
@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
+ * Author: Gabriel Fernandez  for STMicroelectronics.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define CLR_OFFSET 0x4
+
+struct stm32_reset_data {
+   struct reset_controller_dev rcdev;
+   void __iomem*membase;
+};
+
+static inline struct stm32_reset_data *
+to_stm32_reset_data(struct reset_controller_dev *rcdev)
+{
+   return container_of(rcdev, struct stm32_reset_data, rcdev);
+}
+
+static int stm32_reset_update(struct reset_controller_dev *rcdev,
+ unsigned long id, bool assert)
+{
+   struct stm32_reset_data *data = to_stm32_reset_data(rcdev);
+   int reg_width = sizeof(u32);
+   int bank = id / (reg_width * BITS_PER_BYTE);
+   int offset = id % (reg_width * BITS_PER_BYTE);
+   void __iomem *addr;
+
+   addr = data->membase + (bank * reg_width);
+   if (!assert)
+   addr += CLR_OFFSET;
+
+   writel(BIT(offset), addr);
+
+   return 0;
+}
+
+static int stm32_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+   return stm32_reset_update(rcdev, id, true);
+}
+
+static int stm32_reset_deassert(struct reset_controller_dev *rcdev,
+   unsigned long id)
+{
+   return stm32_reset_update(rcdev, id, false);
+}
+
+static int stm32_reset_status(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+   struct stm32_reset_data *data = to_stm32_reset_data(rcdev);
+   int reg_width = sizeof(u32);
+   int bank = id / (reg_width * BITS_PER_BYTE);
+   int offset = id % (reg_width * BITS_PER_BYTE);
+   u32 reg;
+
+   reg = readl(data->membase + (bank * reg_width));
+
+   return !!(reg & BIT(offset));
+}
+
+static const struct reset_control_ops stm32_reset_ops = {
+   .assert = stm32_reset_assert,
+   .deassert   = stm32_reset_deassert,
+   .status = stm32_reset_status,
+};
+
+static const struct of_device_id stm32_reset_dt_ids[] = {
+   { .compatible = "st,stm32mp1-rcc"},
+   { /* sentinel */ },
+};
+
+static int stm32_reset_probe(struct platform_device *pdev)
+{
+   struct device *dev = >dev;
+   struct stm32_reset_data *data;
+   void __iomem *membase;
+   struct resource *res;
+
+   data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
+   if (!data)
+   return -ENOMEM;
+
+   res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+   membase = devm_ioremap_resource(dev, res);
+   if (IS_ERR(membase))
+   return PTR_ERR(membase);
+
+   data->membase = membase;
+   data->rcdev.owner = THIS_MODULE;
+   data->rcdev.nr_resets = 

[PATCH v3 1/2] dt-bindings: reset: add STM32MP1 resets

[gabriel.fernandez]

From: Gabriel Fernandez 

This patch adds the reset binding entry for STM32MP1

Signed-off-by: Gabriel Fernandez 
Reviewed-by: Rob Herring 
---
 .../devicetree/bindings/reset/st,stm32mp1-rcc.txt  |   6 ++
 include/dt-bindings/reset/stm32mp1-resets.h| 108 +
 2 files changed, 114 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/reset/st,stm32mp1-rcc.txt
 create mode 100644 include/dt-bindings/reset/stm32mp1-resets.h

diff --git a/Documentation/devicetree/bindings/reset/st,stm32mp1-rcc.txt 
b/Documentation/devicetree/bindings/reset/st,stm32mp1-rcc.txt
new file mode 100644
index 000..b4edaf7
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/st,stm32mp1-rcc.txt
@@ -0,0 +1,6 @@
+STMicroelectronics STM32MP1 Peripheral Reset Controller
+===
+
+The RCC IP is both a reset and a clock controller.
+
+Please see Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.txt
diff --git a/include/dt-bindings/reset/stm32mp1-resets.h 
b/include/dt-bindings/reset/stm32mp1-resets.h
new file mode 100644
index 000..f0c3aae
--- /dev/null
+++ b/include/dt-bindings/reset/stm32mp1-resets.h
@@ -0,0 +1,108 @@
+/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
+/*
+ * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
+ * Author: Gabriel Fernandez  for STMicroelectronics.
+ */
+
+#ifndef _DT_BINDINGS_STM32MP1_RESET_H_
+#define _DT_BINDINGS_STM32MP1_RESET_H_
+
+#define LTDC_R 3072
+#define DSI_R  3076
+#define DDRPERFM_R 3080
+#define USBPHY_R   3088
+#define SPI6_R 3136
+#define I2C4_R 3138
+#define I2C6_R 3139
+#define USART1_R   3140
+#define STGEN_R3156
+#define GPIOZ_R3200
+#define CRYP1_R3204
+#define HASH1_R3205
+#define RNG1_R 3206
+#define AXIM_R 3216
+#define GPU_R  3269
+#define ETHMAC_R   3274
+#define FMC_R  3276
+#define QSPI_R 3278
+#define SDMMC1_R   3280
+#define SDMMC2_R   3281
+#define CRC1_R 3284
+#define USBH_R 3288
+#define MDMA_R 3328
+#define MCU_R  8225
+#define TIM2_R 19456
+#define TIM3_R 19457
+#define TIM4_R 19458
+#define TIM5_R 19459
+#define TIM6_R 19460
+#define TIM7_R 19461
+#define TIM12_R16462
+#define TIM13_R16463
+#define TIM14_R16464
+#define LPTIM1_R   19465
+#define SPI2_R 19467
+#define SPI3_R 19468
+#define USART2_R   19470
+#define USART3_R   19471
+#define UART4_R19472
+#define UART5_R19473
+#define UART7_R19474
+#define UART8_R19475
+#define I2C1_R 19477
+#define I2C2_R 19478
+#define I2C3_R 19479
+#define I2C5_R 19480
+#define SPDIF_R19482
+#define CEC_R  19483
+#define DAC12_R19485
+#define MDIO_R 19847
+#define TIM1_R 19520
+#define TIM8_R 19521
+#define TIM15_R19522
+#define TIM16_R19523
+#define TIM17_R19524
+#define SPI1_R 19528
+#define SPI4_R 19529
+#define SPI5_R 19530
+#define USART6_R   19533
+#define SAI1_R 19536
+#define SAI2_R 19537
+#define SAI3_R 19538
+#define DFSDM_R19540
+#define FDCAN_R19544
+#define LPTIM2_R   19584
+#define LPTIM3_R   19585
+#define LPTIM4_R   19586
+#define LPTIM5_R   19587
+#define SAI4_R 19592
+#define SYSCFG_R   19595
+#define VREF_R 19597
+#define TMPSENS_R  19600
+#define PMBCTRL_R  19601
+#define DMA1_R 19648
+#define DMA2_R 19649
+#define DMAMUX_R   19650
+#define ADC12_R19653
+#define USBO_R 19656
+#define SDMMC3_R   19664
+#define CAMITF_R   19712
+#define CRYP2_R19716
+#define HASH2_R19717
+#define RNG2_R 19718
+#define CRC2_R 19719
+#define HSEM_R 19723
+#define MBOX_R 19724
+#define GPIOA_R19776
+#define GPIOB_R19777
+#define GPIOC_R19778
+#define GPIOD_R19779
+#define GPIOE_R19780
+#define GPIOF_R19781
+#define GPIOG_R19782
+#define GPIOH_R19783
+#define GPIOI_R19784
+#define GPIOJ_R19785
+#define GPIOK_R19786
+
+#endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */
-- 
1.9.1

[PATCH v3 2/2] reset: stm32mp1: Enable stm32mp1 reset driver

[gabriel.fernandez]

From: Gabriel Fernandez 

stm32mp1 RCC IP 1 has a reset SET register and a reset CLEAR register.

Writing '0' on reset SET register has no effect
Writing '1' on reset SET register
activates the reset of the corresponding peripheral

Writing '0' on reset CLEAR register has no effect
Writing '1' on reset CLEAR register
releases the reset of the corresponding peripheral

See Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.txt

Signed-off-by: Gabriel Fernandez 
---
 drivers/reset/Kconfig  |   6 +++
 drivers/reset/Makefile |   1 +
 drivers/reset/reset-stm32mp1.c | 115 +
 3 files changed, 122 insertions(+)
 create mode 100644 drivers/reset/reset-stm32mp1.c

diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 1efbc6c..c0b292b 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -97,6 +97,12 @@ config RESET_SIMPLE
   - Allwinner SoCs
   - ZTE's zx2967 family
 
+config RESET_STM32MP157
+   bool "STM32MP157 Reset Driver" if COMPILE_TEST
+   default MACH_STM32MP157
+   help
+ This enables the RCC reset controller driver for STM32 MPUs.
+
 config RESET_SUNXI
bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI
default ARCH_SUNXI
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 132c24f..c1261dc 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_RESET_MESON) += reset-meson.o
 obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
 obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o
 obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
+obj-$(CONFIG_RESET_STM32MP157) += reset-stm32mp1.o
 obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
 obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
 obj-$(CONFIG_RESET_TI_SYSCON) += reset-ti-syscon.o
diff --git a/drivers/reset/reset-stm32mp1.c b/drivers/reset/reset-stm32mp1.c
new file mode 100644
index 000..b221a28
--- /dev/null
+++ b/drivers/reset/reset-stm32mp1.c
@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
+ * Author: Gabriel Fernandez  for STMicroelectronics.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define CLR_OFFSET 0x4
+
+struct stm32_reset_data {
+   struct reset_controller_dev rcdev;
+   void __iomem*membase;
+};
+
+static inline struct stm32_reset_data *
+to_stm32_reset_data(struct reset_controller_dev *rcdev)
+{
+   return container_of(rcdev, struct stm32_reset_data, rcdev);
+}
+
+static int stm32_reset_update(struct reset_controller_dev *rcdev,
+ unsigned long id, bool assert)
+{
+   struct stm32_reset_data *data = to_stm32_reset_data(rcdev);
+   int reg_width = sizeof(u32);
+   int bank = id / (reg_width * BITS_PER_BYTE);
+   int offset = id % (reg_width * BITS_PER_BYTE);
+   void __iomem *addr;
+
+   addr = data->membase + (bank * reg_width);
+   if (!assert)
+   addr += CLR_OFFSET;
+
+   writel(BIT(offset), addr);
+
+   return 0;
+}
+
+static int stm32_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+   return stm32_reset_update(rcdev, id, true);
+}
+
+static int stm32_reset_deassert(struct reset_controller_dev *rcdev,
+   unsigned long id)
+{
+   return stm32_reset_update(rcdev, id, false);
+}
+
+static int stm32_reset_status(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+   struct stm32_reset_data *data = to_stm32_reset_data(rcdev);
+   int reg_width = sizeof(u32);
+   int bank = id / (reg_width * BITS_PER_BYTE);
+   int offset = id % (reg_width * BITS_PER_BYTE);
+   u32 reg;
+
+   reg = readl(data->membase + (bank * reg_width));
+
+   return !!(reg & BIT(offset));
+}
+
+static const struct reset_control_ops stm32_reset_ops = {
+   .assert = stm32_reset_assert,
+   .deassert   = stm32_reset_deassert,
+   .status = stm32_reset_status,
+};
+
+static const struct of_device_id stm32_reset_dt_ids[] = {
+   { .compatible = "st,stm32mp1-rcc"},
+   { /* sentinel */ },
+};
+
+static int stm32_reset_probe(struct platform_device *pdev)
+{
+   struct device *dev = >dev;
+   struct stm32_reset_data *data;
+   void __iomem *membase;
+   struct resource *res;
+
+   data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
+   if (!data)
+   return -ENOMEM;
+
+   res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+   membase = devm_ioremap_resource(dev, res);
+   if (IS_ERR(membase))
+   return PTR_ERR(membase);
+
+   data->membase = membase;
+   data->rcdev.owner = THIS_MODULE;
+   data->rcdev.nr_resets = resource_size(res) * BITS_PER_BYTE;
+   data->rcdev.ops = _reset_ops;
+   

[PATCH v3 0/2] Introduce STM32MP1 Reset driver

[gabriel.fernandez]

From: Gabriel Fernandez 

v3:
remove unused includes
fix status ops
fix from Fengguang Wu
for Kbuild test robot: symbol 'stm32_reset_ops' was not declared. 
Should it be static?
use 'builtin_platform_driver' instead 'postcore_initcall'

v2:
Don't use reset-simple driver but a custom reset driver.
add dt-binding documentation.

This patch-set enables the reset of STM32MP1.
STM32MP1 reset IP has a register to assert by writing '1' and another
register to de-assert by writing '1'.

The patch 'dt-bindings: reset: add STM32MP1 resets' could be squashed
with the patch:
'dt-bindings: Document STM32MP1 Reset Clock Controller (RCC) bindings'
commit 3830681d354f

Gabriel Fernandez (2):
  dt-bindings: reset: add STM32MP1 resets
  reset: stm32mp1: Enable stm32mp1 reset driver

 .../devicetree/bindings/reset/st,stm32mp1-rcc.txt  |   6 ++
 drivers/reset/Kconfig  |   6 ++
 drivers/reset/Makefile |   1 +
 drivers/reset/reset-stm32mp1.c | 115 +
 include/dt-bindings/reset/stm32mp1-resets.h| 108 +++
 5 files changed, 236 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/reset/st,stm32mp1-rcc.txt
 create mode 100644 drivers/reset/reset-stm32mp1.c
 create mode 100644 include/dt-bindings/reset/stm32mp1-resets.h

-- 
1.9.1

[PATCH v3 0/2] Introduce STM32MP1 Reset driver

[gabriel.fernandez]

From: Gabriel Fernandez 

v3:
remove unused includes
fix status ops
fix from Fengguang Wu
for Kbuild test robot: symbol 'stm32_reset_ops' was not declared. 
Should it be static?
use 'builtin_platform_driver' instead 'postcore_initcall'

v2:
Don't use reset-simple driver but a custom reset driver.
add dt-binding documentation.

This patch-set enables the reset of STM32MP1.
STM32MP1 reset IP has a register to assert by writing '1' and another
register to de-assert by writing '1'.

The patch 'dt-bindings: reset: add STM32MP1 resets' could be squashed
with the patch:
'dt-bindings: Document STM32MP1 Reset Clock Controller (RCC) bindings'
commit 3830681d354f

Gabriel Fernandez (2):
  dt-bindings: reset: add STM32MP1 resets
  reset: stm32mp1: Enable stm32mp1 reset driver

 .../devicetree/bindings/reset/st,stm32mp1-rcc.txt  |   6 ++
 drivers/reset/Kconfig  |   6 ++
 drivers/reset/Makefile |   1 +
 drivers/reset/reset-stm32mp1.c | 115 +
 include/dt-bindings/reset/stm32mp1-resets.h| 108 +++
 5 files changed, 236 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/reset/st,stm32mp1-rcc.txt
 create mode 100644 drivers/reset/reset-stm32mp1.c
 create mode 100644 include/dt-bindings/reset/stm32mp1-resets.h

-- 
1.9.1

[PATCH] ARM: dts: stm32: Enable stm32mp1 clock driver on stm32mp157c

[gabriel.fernandez]

From: Gabriel Fernandez 

This patch enables stm32mp1 clock driver.

Signed-off-by: Gabriel Fernandez 
---
 arch/arm/boot/dts/stm32mp157-pinctrl.dtsi | 24 
 arch/arm/boot/dts/stm32mp157c.dtsi| 48 +++
 2 files changed, 28 insertions(+), 44 deletions(-)

diff --git a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi 
b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
index c0743305..6f044100 100644
--- a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
@@ -20,7 +20,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x0 0x400>;
-   clocks = <_pll3_p>;
+   clocks = < GPIOA>;
st,bank-name = "GPIOA";
ngpios = <16>;
gpio-ranges = < 0 0 16>;
@@ -32,7 +32,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x1000 0x400>;
-   clocks = <_pll3_p>;
+   clocks = < GPIOB>;
st,bank-name = "GPIOB";
ngpios = <16>;
gpio-ranges = < 0 16 16>;
@@ -44,7 +44,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x2000 0x400>;
-   clocks = <_pll3_p>;
+   clocks = < GPIOC>;
st,bank-name = "GPIOC";
ngpios = <16>;
gpio-ranges = < 0 32 16>;
@@ -56,7 +56,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x3000 0x400>;
-   clocks = <_pll3_p>;
+   clocks = < GPIOD>;
st,bank-name = "GPIOD";
ngpios = <16>;
gpio-ranges = < 0 48 16>;
@@ -68,7 +68,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x4000 0x400>;
-   clocks = <_pll3_p>;
+   clocks = < GPIOE>;
st,bank-name = "GPIOE";
ngpios = <16>;
gpio-ranges = < 0 64 16>;
@@ -80,7 +80,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x5000 0x400>;
-   clocks = <_pll3_p>;
+   clocks = < GPIOF>;
st,bank-name = "GPIOF";
ngpios = <16>;
gpio-ranges = < 0 80 16>;
@@ -92,7 +92,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x6000 0x400>;
-   clocks = <_pll3_p>;
+   clocks = < GPIOG>;
st,bank-name = "GPIOG";
ngpios = <16>;
gpio-ranges = < 0 96 16>;
@@ -104,7 +104,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x7000 0x400>;
-   clocks = <_pll3_p>;
+   clocks = < GPIOH>;
st,bank-name = "GPIOH";
ngpios = <16>;
gpio-ranges = < 0 112 16>;
@@ -116,7 +116,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x8000 0x400>;
-   clocks = <_pll3_p>;
+   clocks = < GPIOI>;
st,bank-name = "GPIOI";
ngpios = <16>;
gpio-ranges = < 0 128 16>;
@@ -128,7 +128,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x9000 0x400>;
-   clocks = <_pll3_p>;
+   clocks = < GPIOJ>;
st,bank-name = "GPIOJ";
ngpios = <16>;

[PATCH] ARM: dts: stm32: Enable stm32mp1 clock driver on stm32mp157c

[gabriel.fernandez]

From: Gabriel Fernandez 

This patch enables stm32mp1 clock driver.

Signed-off-by: Gabriel Fernandez 
---
 arch/arm/boot/dts/stm32mp157-pinctrl.dtsi | 24 
 arch/arm/boot/dts/stm32mp157c.dtsi| 48 +++
 2 files changed, 28 insertions(+), 44 deletions(-)

diff --git a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi 
b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
index c0743305..6f044100 100644
--- a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
@@ -20,7 +20,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x0 0x400>;
-   clocks = <_pll3_p>;
+   clocks = < GPIOA>;
st,bank-name = "GPIOA";
ngpios = <16>;
gpio-ranges = < 0 0 16>;
@@ -32,7 +32,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x1000 0x400>;
-   clocks = <_pll3_p>;
+   clocks = < GPIOB>;
st,bank-name = "GPIOB";
ngpios = <16>;
gpio-ranges = < 0 16 16>;
@@ -44,7 +44,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x2000 0x400>;
-   clocks = <_pll3_p>;
+   clocks = < GPIOC>;
st,bank-name = "GPIOC";
ngpios = <16>;
gpio-ranges = < 0 32 16>;
@@ -56,7 +56,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x3000 0x400>;
-   clocks = <_pll3_p>;
+   clocks = < GPIOD>;
st,bank-name = "GPIOD";
ngpios = <16>;
gpio-ranges = < 0 48 16>;
@@ -68,7 +68,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x4000 0x400>;
-   clocks = <_pll3_p>;
+   clocks = < GPIOE>;
st,bank-name = "GPIOE";
ngpios = <16>;
gpio-ranges = < 0 64 16>;
@@ -80,7 +80,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x5000 0x400>;
-   clocks = <_pll3_p>;
+   clocks = < GPIOF>;
st,bank-name = "GPIOF";
ngpios = <16>;
gpio-ranges = < 0 80 16>;
@@ -92,7 +92,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x6000 0x400>;
-   clocks = <_pll3_p>;
+   clocks = < GPIOG>;
st,bank-name = "GPIOG";
ngpios = <16>;
gpio-ranges = < 0 96 16>;
@@ -104,7 +104,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x7000 0x400>;
-   clocks = <_pll3_p>;
+   clocks = < GPIOH>;
st,bank-name = "GPIOH";
ngpios = <16>;
gpio-ranges = < 0 112 16>;
@@ -116,7 +116,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x8000 0x400>;
-   clocks = <_pll3_p>;
+   clocks = < GPIOI>;
st,bank-name = "GPIOI";
ngpios = <16>;
gpio-ranges = < 0 128 16>;
@@ -128,7 +128,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x9000 0x400>;
-   clocks = <_pll3_p>;
+   clocks = < GPIOJ>;
st,bank-name = "GPIOJ";
ngpios = <16>;
gpio-ranges = < 0 144 16>;

[PATCH v2 2/2] reset: stm32mp1: Enable stm32mp1 reset driver

[gabriel.fernandez]

From: Gabriel Fernandez 

stm32mp1 RCC IP 1 has a reset SET register and a reset CLEAR register.

Writing '0' on reset SET register has no effect
Writing '1' on reset SET register
activates the reset of the corresponding peripheral

Writing '0' on reset CLEAR register has no effect
Writing '1' on reset CLEAR register
releases the reset of the corresponding peripheral

See Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.txt

Signed-off-by: Gabriel Fernandez 
---
 drivers/reset/Kconfig  |   6 ++
 drivers/reset/Makefile |   1 +
 drivers/reset/reset-stm32mp1.c | 122 +
 3 files changed, 129 insertions(+)
 create mode 100644 drivers/reset/reset-stm32mp1.c

diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 1efbc6c..c0b292b 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -97,6 +97,12 @@ config RESET_SIMPLE
   - Allwinner SoCs
   - ZTE's zx2967 family
 
+config RESET_STM32MP157
+   bool "STM32MP157 Reset Driver" if COMPILE_TEST
+   default MACH_STM32MP157
+   help
+ This enables the RCC reset controller driver for STM32 MPUs.
+
 config RESET_SUNXI
bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI
default ARCH_SUNXI
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 132c24f..c1261dc 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_RESET_MESON) += reset-meson.o
 obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
 obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o
 obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
+obj-$(CONFIG_RESET_STM32MP157) += reset-stm32mp1.o
 obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
 obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
 obj-$(CONFIG_RESET_TI_SYSCON) += reset-ti-syscon.o
diff --git a/drivers/reset/reset-stm32mp1.c b/drivers/reset/reset-stm32mp1.c
new file mode 100644
index 000..5e25388
--- /dev/null
+++ b/drivers/reset/reset-stm32mp1.c
@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
+ * Author: Gabriel Fernandez  for STMicroelectronics.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define CLR_OFFSET 0x4
+
+struct stm32_reset_data {
+   struct reset_controller_dev rcdev;
+   void __iomem*membase;
+};
+
+static inline struct stm32_reset_data *
+to_stm32_reset_data(struct reset_controller_dev *rcdev)
+{
+   return container_of(rcdev, struct stm32_reset_data, rcdev);
+}
+
+static int stm32_reset_update(struct reset_controller_dev *rcdev,
+ unsigned long id, bool assert)
+{
+   struct stm32_reset_data *data = to_stm32_reset_data(rcdev);
+   int reg_width = sizeof(u32);
+   int bank = id / (reg_width * BITS_PER_BYTE);
+   int offset = id % (reg_width * BITS_PER_BYTE);
+   void __iomem *addr;
+
+   addr = data->membase + (bank * reg_width);
+   if (!assert)
+   addr += CLR_OFFSET;
+
+   writel(BIT(offset), addr);
+
+   return 0;
+}
+
+static int stm32_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+   return stm32_reset_update(rcdev, id, true);
+}
+
+static int stm32_reset_deassert(struct reset_controller_dev *rcdev,
+   unsigned long id)
+{
+   return stm32_reset_update(rcdev, id, false);
+}
+
+static int stm32_reset_status(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+   struct stm32_reset_data *data = to_stm32_reset_data(rcdev);
+   int reg_width = sizeof(u32);
+   int bank = id / (reg_width * BITS_PER_BYTE);
+   int offset = id % (reg_width * BITS_PER_BYTE);
+   u32 reg;
+
+   reg = readl(data->membase + (bank * reg_width));
+
+   return !(reg & BIT(offset));
+}
+
+const struct reset_control_ops stm32_reset_ops = {
+   .assert = stm32_reset_assert,
+   .deassert   = stm32_reset_deassert,
+   .status = stm32_reset_status,
+};
+
+static const struct of_device_id stm32_reset_dt_ids[] = {
+   { .compatible = "st,stm32mp1-rcc"},
+   { /* sentinel */ },
+};
+
+static int stm32_reset_probe(struct platform_device *pdev)
+{
+   struct device *dev = >dev;
+   struct stm32_reset_data *data;
+   void __iomem *membase;
+   struct resource *res;
+
+   data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
+   if (!data)
+   return -ENOMEM;
+
+   res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+   membase = devm_ioremap_resource(dev, res);
+   if (IS_ERR(membase))
+   return PTR_ERR(membase);
+
+   data->membase = membase;
+   data->rcdev.owner = THIS_MODULE;
+   data->rcdev.nr_resets 

[PATCH v2 2/2] reset: stm32mp1: Enable stm32mp1 reset driver

[gabriel.fernandez]

From: Gabriel Fernandez 

stm32mp1 RCC IP 1 has a reset SET register and a reset CLEAR register.

Writing '0' on reset SET register has no effect
Writing '1' on reset SET register
activates the reset of the corresponding peripheral

Writing '0' on reset CLEAR register has no effect
Writing '1' on reset CLEAR register
releases the reset of the corresponding peripheral

See Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.txt

Signed-off-by: Gabriel Fernandez 
---
 drivers/reset/Kconfig  |   6 ++
 drivers/reset/Makefile |   1 +
 drivers/reset/reset-stm32mp1.c | 122 +
 3 files changed, 129 insertions(+)
 create mode 100644 drivers/reset/reset-stm32mp1.c

diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 1efbc6c..c0b292b 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -97,6 +97,12 @@ config RESET_SIMPLE
   - Allwinner SoCs
   - ZTE's zx2967 family
 
+config RESET_STM32MP157
+   bool "STM32MP157 Reset Driver" if COMPILE_TEST
+   default MACH_STM32MP157
+   help
+ This enables the RCC reset controller driver for STM32 MPUs.
+
 config RESET_SUNXI
bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI
default ARCH_SUNXI
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 132c24f..c1261dc 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_RESET_MESON) += reset-meson.o
 obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
 obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o
 obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
+obj-$(CONFIG_RESET_STM32MP157) += reset-stm32mp1.o
 obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
 obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
 obj-$(CONFIG_RESET_TI_SYSCON) += reset-ti-syscon.o
diff --git a/drivers/reset/reset-stm32mp1.c b/drivers/reset/reset-stm32mp1.c
new file mode 100644
index 000..5e25388
--- /dev/null
+++ b/drivers/reset/reset-stm32mp1.c
@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
+ * Author: Gabriel Fernandez  for STMicroelectronics.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define CLR_OFFSET 0x4
+
+struct stm32_reset_data {
+   struct reset_controller_dev rcdev;
+   void __iomem*membase;
+};
+
+static inline struct stm32_reset_data *
+to_stm32_reset_data(struct reset_controller_dev *rcdev)
+{
+   return container_of(rcdev, struct stm32_reset_data, rcdev);
+}
+
+static int stm32_reset_update(struct reset_controller_dev *rcdev,
+ unsigned long id, bool assert)
+{
+   struct stm32_reset_data *data = to_stm32_reset_data(rcdev);
+   int reg_width = sizeof(u32);
+   int bank = id / (reg_width * BITS_PER_BYTE);
+   int offset = id % (reg_width * BITS_PER_BYTE);
+   void __iomem *addr;
+
+   addr = data->membase + (bank * reg_width);
+   if (!assert)
+   addr += CLR_OFFSET;
+
+   writel(BIT(offset), addr);
+
+   return 0;
+}
+
+static int stm32_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+   return stm32_reset_update(rcdev, id, true);
+}
+
+static int stm32_reset_deassert(struct reset_controller_dev *rcdev,
+   unsigned long id)
+{
+   return stm32_reset_update(rcdev, id, false);
+}
+
+static int stm32_reset_status(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+   struct stm32_reset_data *data = to_stm32_reset_data(rcdev);
+   int reg_width = sizeof(u32);
+   int bank = id / (reg_width * BITS_PER_BYTE);
+   int offset = id % (reg_width * BITS_PER_BYTE);
+   u32 reg;
+
+   reg = readl(data->membase + (bank * reg_width));
+
+   return !(reg & BIT(offset));
+}
+
+const struct reset_control_ops stm32_reset_ops = {
+   .assert = stm32_reset_assert,
+   .deassert   = stm32_reset_deassert,
+   .status = stm32_reset_status,
+};
+
+static const struct of_device_id stm32_reset_dt_ids[] = {
+   { .compatible = "st,stm32mp1-rcc"},
+   { /* sentinel */ },
+};
+
+static int stm32_reset_probe(struct platform_device *pdev)
+{
+   struct device *dev = >dev;
+   struct stm32_reset_data *data;
+   void __iomem *membase;
+   struct resource *res;
+
+   data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
+   if (!data)
+   return -ENOMEM;
+
+   res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+   membase = devm_ioremap_resource(dev, res);
+   if (IS_ERR(membase))
+   return PTR_ERR(membase);
+
+   data->membase = membase;
+   data->rcdev.owner = THIS_MODULE;
+   data->rcdev.nr_resets = resource_size(res) * BITS_PER_BYTE;
+   data->rcdev.ops = _reset_ops;
+  

[PATCH v2 1/2] dt-bindings: reset: add STM32MP1 resets

[gabriel.fernandez]

From: Gabriel Fernandez 

This patch adds the reset binding entry for STM32MP1

Signed-off-by: Gabriel Fernandez 
---
 .../devicetree/bindings/reset/st,stm32mp1-rcc.txt  |   6 ++
 include/dt-bindings/reset/stm32mp1-resets.h| 108 +
 2 files changed, 114 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/reset/st,stm32mp1-rcc.txt
 create mode 100644 include/dt-bindings/reset/stm32mp1-resets.h

diff --git a/Documentation/devicetree/bindings/reset/st,stm32mp1-rcc.txt 
b/Documentation/devicetree/bindings/reset/st,stm32mp1-rcc.txt
new file mode 100644
index 000..b4edaf7
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/st,stm32mp1-rcc.txt
@@ -0,0 +1,6 @@
+STMicroelectronics STM32MP1 Peripheral Reset Controller
+===
+
+The RCC IP is both a reset and a clock controller.
+
+Please see Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.txt
diff --git a/include/dt-bindings/reset/stm32mp1-resets.h 
b/include/dt-bindings/reset/stm32mp1-resets.h
new file mode 100644
index 000..f0c3aae
--- /dev/null
+++ b/include/dt-bindings/reset/stm32mp1-resets.h
@@ -0,0 +1,108 @@
+/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
+/*
+ * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
+ * Author: Gabriel Fernandez  for STMicroelectronics.
+ */
+
+#ifndef _DT_BINDINGS_STM32MP1_RESET_H_
+#define _DT_BINDINGS_STM32MP1_RESET_H_
+
+#define LTDC_R 3072
+#define DSI_R  3076
+#define DDRPERFM_R 3080
+#define USBPHY_R   3088
+#define SPI6_R 3136
+#define I2C4_R 3138
+#define I2C6_R 3139
+#define USART1_R   3140
+#define STGEN_R3156
+#define GPIOZ_R3200
+#define CRYP1_R3204
+#define HASH1_R3205
+#define RNG1_R 3206
+#define AXIM_R 3216
+#define GPU_R  3269
+#define ETHMAC_R   3274
+#define FMC_R  3276
+#define QSPI_R 3278
+#define SDMMC1_R   3280
+#define SDMMC2_R   3281
+#define CRC1_R 3284
+#define USBH_R 3288
+#define MDMA_R 3328
+#define MCU_R  8225
+#define TIM2_R 19456
+#define TIM3_R 19457
+#define TIM4_R 19458
+#define TIM5_R 19459
+#define TIM6_R 19460
+#define TIM7_R 19461
+#define TIM12_R16462
+#define TIM13_R16463
+#define TIM14_R16464
+#define LPTIM1_R   19465
+#define SPI2_R 19467
+#define SPI3_R 19468
+#define USART2_R   19470
+#define USART3_R   19471
+#define UART4_R19472
+#define UART5_R19473
+#define UART7_R19474
+#define UART8_R19475
+#define I2C1_R 19477
+#define I2C2_R 19478
+#define I2C3_R 19479
+#define I2C5_R 19480
+#define SPDIF_R19482
+#define CEC_R  19483
+#define DAC12_R19485
+#define MDIO_R 19847
+#define TIM1_R 19520
+#define TIM8_R 19521
+#define TIM15_R19522
+#define TIM16_R19523
+#define TIM17_R19524
+#define SPI1_R 19528
+#define SPI4_R 19529
+#define SPI5_R 19530
+#define USART6_R   19533
+#define SAI1_R 19536
+#define SAI2_R 19537
+#define SAI3_R 19538
+#define DFSDM_R19540
+#define FDCAN_R19544
+#define LPTIM2_R   19584
+#define LPTIM3_R   19585
+#define LPTIM4_R   19586
+#define LPTIM5_R   19587
+#define SAI4_R 19592
+#define SYSCFG_R   19595
+#define VREF_R 19597
+#define TMPSENS_R  19600
+#define PMBCTRL_R  19601
+#define DMA1_R 19648
+#define DMA2_R 19649
+#define DMAMUX_R   19650
+#define ADC12_R19653
+#define USBO_R 19656
+#define SDMMC3_R   19664
+#define CAMITF_R   19712
+#define CRYP2_R19716
+#define HASH2_R19717
+#define RNG2_R 19718
+#define CRC2_R 19719
+#define HSEM_R 19723
+#define MBOX_R 19724
+#define GPIOA_R19776
+#define GPIOB_R19777
+#define GPIOC_R19778
+#define GPIOD_R19779
+#define GPIOE_R19780
+#define GPIOF_R19781
+#define GPIOG_R19782
+#define GPIOH_R19783
+#define GPIOI_R19784
+#define GPIOJ_R19785
+#define GPIOK_R19786
+
+#endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */
-- 
1.9.1

[PATCH v2 1/2] dt-bindings: reset: add STM32MP1 resets

[gabriel.fernandez]

From: Gabriel Fernandez 

This patch adds the reset binding entry for STM32MP1

Signed-off-by: Gabriel Fernandez 
---
 .../devicetree/bindings/reset/st,stm32mp1-rcc.txt  |   6 ++
 include/dt-bindings/reset/stm32mp1-resets.h| 108 +
 2 files changed, 114 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/reset/st,stm32mp1-rcc.txt
 create mode 100644 include/dt-bindings/reset/stm32mp1-resets.h

diff --git a/Documentation/devicetree/bindings/reset/st,stm32mp1-rcc.txt 
b/Documentation/devicetree/bindings/reset/st,stm32mp1-rcc.txt
new file mode 100644
index 000..b4edaf7
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/st,stm32mp1-rcc.txt
@@ -0,0 +1,6 @@
+STMicroelectronics STM32MP1 Peripheral Reset Controller
+===
+
+The RCC IP is both a reset and a clock controller.
+
+Please see Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.txt
diff --git a/include/dt-bindings/reset/stm32mp1-resets.h 
b/include/dt-bindings/reset/stm32mp1-resets.h
new file mode 100644
index 000..f0c3aae
--- /dev/null
+++ b/include/dt-bindings/reset/stm32mp1-resets.h
@@ -0,0 +1,108 @@
+/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
+/*
+ * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
+ * Author: Gabriel Fernandez  for STMicroelectronics.
+ */
+
+#ifndef _DT_BINDINGS_STM32MP1_RESET_H_
+#define _DT_BINDINGS_STM32MP1_RESET_H_
+
+#define LTDC_R 3072
+#define DSI_R  3076
+#define DDRPERFM_R 3080
+#define USBPHY_R   3088
+#define SPI6_R 3136
+#define I2C4_R 3138
+#define I2C6_R 3139
+#define USART1_R   3140
+#define STGEN_R3156
+#define GPIOZ_R3200
+#define CRYP1_R3204
+#define HASH1_R3205
+#define RNG1_R 3206
+#define AXIM_R 3216
+#define GPU_R  3269
+#define ETHMAC_R   3274
+#define FMC_R  3276
+#define QSPI_R 3278
+#define SDMMC1_R   3280
+#define SDMMC2_R   3281
+#define CRC1_R 3284
+#define USBH_R 3288
+#define MDMA_R 3328
+#define MCU_R  8225
+#define TIM2_R 19456
+#define TIM3_R 19457
+#define TIM4_R 19458
+#define TIM5_R 19459
+#define TIM6_R 19460
+#define TIM7_R 19461
+#define TIM12_R16462
+#define TIM13_R16463
+#define TIM14_R16464
+#define LPTIM1_R   19465
+#define SPI2_R 19467
+#define SPI3_R 19468
+#define USART2_R   19470
+#define USART3_R   19471
+#define UART4_R19472
+#define UART5_R19473
+#define UART7_R19474
+#define UART8_R19475
+#define I2C1_R 19477
+#define I2C2_R 19478
+#define I2C3_R 19479
+#define I2C5_R 19480
+#define SPDIF_R19482
+#define CEC_R  19483
+#define DAC12_R19485
+#define MDIO_R 19847
+#define TIM1_R 19520
+#define TIM8_R 19521
+#define TIM15_R19522
+#define TIM16_R19523
+#define TIM17_R19524
+#define SPI1_R 19528
+#define SPI4_R 19529
+#define SPI5_R 19530
+#define USART6_R   19533
+#define SAI1_R 19536
+#define SAI2_R 19537
+#define SAI3_R 19538
+#define DFSDM_R19540
+#define FDCAN_R19544
+#define LPTIM2_R   19584
+#define LPTIM3_R   19585
+#define LPTIM4_R   19586
+#define LPTIM5_R   19587
+#define SAI4_R 19592
+#define SYSCFG_R   19595
+#define VREF_R 19597
+#define TMPSENS_R  19600
+#define PMBCTRL_R  19601
+#define DMA1_R 19648
+#define DMA2_R 19649
+#define DMAMUX_R   19650
+#define ADC12_R19653
+#define USBO_R 19656
+#define SDMMC3_R   19664
+#define CAMITF_R   19712
+#define CRYP2_R19716
+#define HASH2_R19717
+#define RNG2_R 19718
+#define CRC2_R 19719
+#define HSEM_R 19723
+#define MBOX_R 19724
+#define GPIOA_R19776
+#define GPIOB_R19777
+#define GPIOC_R19778
+#define GPIOD_R19779
+#define GPIOE_R19780
+#define GPIOF_R19781
+#define GPIOG_R19782
+#define GPIOH_R19783
+#define GPIOI_R19784
+#define GPIOJ_R19785
+#define GPIOK_R19786
+
+#endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */
-- 
1.9.1

[PATCH v2 0/2] Introduce STM32MP1 Reset driver

[gabriel.fernandez]

From: Gabriel Fernandez 

v2:
Don't use reset-simple driver but a custom reset driver.
add dt-binding documentation.

This patch-set enables the reset of STM32MP1.
STM32MP1 reset IP has a register to assert by writing '1' and another
register to de-assert by writing '1'.

The patch 'dt-bindings: reset: add STM32MP1 resets' could be squashed
with the patch:
'dt-bindings: Document STM32MP1 Reset Clock Controller (RCC) bindings'
commit 3830681d354f

Gabriel Fernandez (2):
  dt-bindings: reset: add STM32MP1 resets
  reset: stm32mp1: Enable stm32mp1 reset driver

 .../devicetree/bindings/reset/st,stm32mp1-rcc.txt  |   6 +
 drivers/reset/Kconfig  |   6 +
 drivers/reset/Makefile |   1 +
 drivers/reset/reset-stm32mp1.c | 122 +
 include/dt-bindings/reset/stm32mp1-resets.h| 108 ++
 5 files changed, 243 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/reset/st,stm32mp1-rcc.txt
 create mode 100644 drivers/reset/reset-stm32mp1.c
 create mode 100644 include/dt-bindings/reset/stm32mp1-resets.h

-- 
1.9.1

[PATCH v2 0/2] Introduce STM32MP1 Reset driver

[gabriel.fernandez]

From: Gabriel Fernandez 

v2:
Don't use reset-simple driver but a custom reset driver.
add dt-binding documentation.

This patch-set enables the reset of STM32MP1.
STM32MP1 reset IP has a register to assert by writing '1' and another
register to de-assert by writing '1'.

The patch 'dt-bindings: reset: add STM32MP1 resets' could be squashed
with the patch:
'dt-bindings: Document STM32MP1 Reset Clock Controller (RCC) bindings'
commit 3830681d354f

Gabriel Fernandez (2):
  dt-bindings: reset: add STM32MP1 resets
  reset: stm32mp1: Enable stm32mp1 reset driver

 .../devicetree/bindings/reset/st,stm32mp1-rcc.txt  |   6 +
 drivers/reset/Kconfig  |   6 +
 drivers/reset/Makefile |   1 +
 drivers/reset/reset-stm32mp1.c | 122 +
 include/dt-bindings/reset/stm32mp1-resets.h| 108 ++
 5 files changed, 243 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/reset/st,stm32mp1-rcc.txt
 create mode 100644 drivers/reset/reset-stm32mp1.c
 create mode 100644 include/dt-bindings/reset/stm32mp1-resets.h

-- 
1.9.1

[PATCH 2/2] reset: simple: Enable stm32mp1 reset driver

[gabriel.fernandez]

From: Gabriel Fernandez 

The stm32mp1 reset driver is quite similar to simple reset driver.
The difference is that stm32mp1 has a reset SET register and
a reset CLEAR register.

Writing '0' on reset SET register has no effect
Writing '1' on reset SET register
activates the reset of the corresponding peripheral

Writing '0' on reset CLEAR register has no effect
Writing '1' on reset CLEAR register
releases the reset of the corresponding peripheral

Signed-off-by: Gabriel Fernandez 
---
 drivers/reset/reset-simple.c | 27 +--
 drivers/reset/reset-simple.h |  1 +
 2 files changed, 22 insertions(+), 6 deletions(-)

diff --git a/drivers/reset/reset-simple.c b/drivers/reset/reset-simple.c
index f7ce891..57ecb49 100644
--- a/drivers/reset/reset-simple.c
+++ b/drivers/reset/reset-simple.c
@@ -41,15 +41,23 @@ static int reset_simple_update(struct reset_controller_dev 
*rcdev,
int offset = id % (reg_width * BITS_PER_BYTE);
unsigned long flags;
u32 reg;
+   void __iomem *addr;
 
spin_lock_irqsave(>lock, flags);
 
-   reg = readl(data->membase + (bank * reg_width));
-   if (assert ^ data->active_low)
-   reg |= BIT(offset);
-   else
-   reg &= ~BIT(offset);
-   writel(reg, data->membase + (bank * reg_width));
+   addr = data->membase + (bank * reg_width);
+   if (data->clr_offset) {
+   reg = BIT(offset);
+   if (!assert)
+   addr += data->clr_offset;
+   } else {
+   reg = readl(addr);
+   if (assert ^ data->active_low)
+   reg |= BIT(offset);
+   else
+   reg &= ~BIT(offset);
+   }
+   writel(reg, addr);
 
spin_unlock_irqrestore(>lock, flags);
 
@@ -103,6 +111,7 @@ struct reset_simple_devdata {
u32 nr_resets;
bool active_low;
bool status_active_low;
+   u32 clr_offset;
 };
 
 #define SOCFPGA_NR_BANKS   8
@@ -118,9 +127,14 @@ struct reset_simple_devdata {
.status_active_low = true,
 };
 
+struct reset_simple_devdata reset_stm32mp1 = {
+   .clr_offset = 0x4,
+};
+
 static const struct of_device_id reset_simple_dt_ids[] = {
{ .compatible = "altr,rst-mgr", .data = _simple_socfpga },
{ .compatible = "st,stm32-rcc", },
+   { .compatible = "st,stm32mp1-rcc", .data = _stm32mp1},
{ .compatible = "allwinner,sun6i-a31-clock-reset",
.data = _simple_active_low },
{ .compatible = "zte,zx296718-reset",
@@ -163,6 +177,7 @@ static int reset_simple_probe(struct platform_device *pdev)
data->rcdev.nr_resets = devdata->nr_resets;
data->active_low = devdata->active_low;
data->status_active_low = devdata->status_active_low;
+   data->clr_offset = devdata->clr_offset;
}
 
if (of_device_is_compatible(dev->of_node, "altr,rst-mgr") &&
diff --git a/drivers/reset/reset-simple.h b/drivers/reset/reset-simple.h
index 8a49602..0bbdd34 100644
--- a/drivers/reset/reset-simple.h
+++ b/drivers/reset/reset-simple.h
@@ -38,6 +38,7 @@ struct reset_simple_data {
struct reset_controller_dev rcdev;
boolactive_low;
boolstatus_active_low;
+   u32 clr_offset;
 };
 
 extern const struct reset_control_ops reset_simple_ops;
-- 
1.9.1

[PATCH 2/2] reset: simple: Enable stm32mp1 reset driver

[gabriel.fernandez]

From: Gabriel Fernandez 

The stm32mp1 reset driver is quite similar to simple reset driver.
The difference is that stm32mp1 has a reset SET register and
a reset CLEAR register.

Writing '0' on reset SET register has no effect
Writing '1' on reset SET register
activates the reset of the corresponding peripheral

Writing '0' on reset CLEAR register has no effect
Writing '1' on reset CLEAR register
releases the reset of the corresponding peripheral

Signed-off-by: Gabriel Fernandez 
---
 drivers/reset/reset-simple.c | 27 +--
 drivers/reset/reset-simple.h |  1 +
 2 files changed, 22 insertions(+), 6 deletions(-)

diff --git a/drivers/reset/reset-simple.c b/drivers/reset/reset-simple.c
index f7ce891..57ecb49 100644
--- a/drivers/reset/reset-simple.c
+++ b/drivers/reset/reset-simple.c
@@ -41,15 +41,23 @@ static int reset_simple_update(struct reset_controller_dev 
*rcdev,
int offset = id % (reg_width * BITS_PER_BYTE);
unsigned long flags;
u32 reg;
+   void __iomem *addr;
 
spin_lock_irqsave(>lock, flags);
 
-   reg = readl(data->membase + (bank * reg_width));
-   if (assert ^ data->active_low)
-   reg |= BIT(offset);
-   else
-   reg &= ~BIT(offset);
-   writel(reg, data->membase + (bank * reg_width));
+   addr = data->membase + (bank * reg_width);
+   if (data->clr_offset) {
+   reg = BIT(offset);
+   if (!assert)
+   addr += data->clr_offset;
+   } else {
+   reg = readl(addr);
+   if (assert ^ data->active_low)
+   reg |= BIT(offset);
+   else
+   reg &= ~BIT(offset);
+   }
+   writel(reg, addr);
 
spin_unlock_irqrestore(>lock, flags);
 
@@ -103,6 +111,7 @@ struct reset_simple_devdata {
u32 nr_resets;
bool active_low;
bool status_active_low;
+   u32 clr_offset;
 };
 
 #define SOCFPGA_NR_BANKS   8
@@ -118,9 +127,14 @@ struct reset_simple_devdata {
.status_active_low = true,
 };
 
+struct reset_simple_devdata reset_stm32mp1 = {
+   .clr_offset = 0x4,
+};
+
 static const struct of_device_id reset_simple_dt_ids[] = {
{ .compatible = "altr,rst-mgr", .data = _simple_socfpga },
{ .compatible = "st,stm32-rcc", },
+   { .compatible = "st,stm32mp1-rcc", .data = _stm32mp1},
{ .compatible = "allwinner,sun6i-a31-clock-reset",
.data = _simple_active_low },
{ .compatible = "zte,zx296718-reset",
@@ -163,6 +177,7 @@ static int reset_simple_probe(struct platform_device *pdev)
data->rcdev.nr_resets = devdata->nr_resets;
data->active_low = devdata->active_low;
data->status_active_low = devdata->status_active_low;
+   data->clr_offset = devdata->clr_offset;
}
 
if (of_device_is_compatible(dev->of_node, "altr,rst-mgr") &&
diff --git a/drivers/reset/reset-simple.h b/drivers/reset/reset-simple.h
index 8a49602..0bbdd34 100644
--- a/drivers/reset/reset-simple.h
+++ b/drivers/reset/reset-simple.h
@@ -38,6 +38,7 @@ struct reset_simple_data {
struct reset_controller_dev rcdev;
boolactive_low;
boolstatus_active_low;
+   u32 clr_offset;
 };
 
 extern const struct reset_control_ops reset_simple_ops;
-- 
1.9.1