Dear Doug,
在 2018年05月11日 05:01, Doug Anderson 写道:
Hi,
On Wed, May 9, 2018 at 3:11 AM, William Wu wrote:
The commit 3bc04e28a030 ("usb: dwc2: host: Get aligned DMA in
a more supported way") rips out a lot of code to simply the
allocation of aligned DMA. However, it
Dear Doug,
在 2018年05月11日 05:01, Doug Anderson 写道:
Hi,
On Wed, May 9, 2018 at 3:11 AM, William Wu wrote:
The commit 3bc04e28a030 ("usb: dwc2: host: Get aligned DMA in
a more supported way") rips out a lot of code to simply the
allocation of aligned DMA. However, it also introduces a new
issue
Dear Doug,
在 2018年05月11日 04:59, Doug Anderson 写道:
Hi,
On Wed, May 9, 2018 at 1:55 AM, wlf <w...@rock-chips.com> wrote:
+ } else if (hsotg->params.host_dma) {
Are you sure this is "else if"? Can't you have descriptor DMA enabled
in the controller and still need
Dear Doug,
在 2018年05月11日 04:59, Doug Anderson 写道:
Hi,
On Wed, May 9, 2018 at 1:55 AM, wlf wrote:
+ } else if (hsotg->params.host_dma) {
Are you sure this is "else if"? Can't you have descriptor DMA enabled
in the controller and still need to do a normal DMA transfe
Dear Doug,
在 2018年05月08日 23:29, Doug Anderson 写道:
Hi,
On Tue, May 8, 2018 at 12:43 AM, wlf <w...@rock-chips.com> wrote:
Dear Doug,
在 2018年05月08日 13:11, Doug Anderson 写道:
Hi,
On Mon, May 7, 2018 at 8:07 PM, William Wu <william...@rock-chips.com>
wrote:
Dear Doug,
在 2018年05月08日 23:29, Doug Anderson 写道:
Hi,
On Tue, May 8, 2018 at 12:43 AM, wlf wrote:
Dear Doug,
在 2018年05月08日 13:11, Doug Anderson 写道:
Hi,
On Mon, May 7, 2018 at 8:07 PM, William Wu
wrote:
+static int dwc2_alloc_split_dma_aligned_buf(struct dwc2_hsotg *hsotg
Dear Doug,
在 2018年05月08日 13:11, Doug Anderson 写道:
Hi,
On Mon, May 7, 2018 at 8:07 PM, William Wu wrote:
+static int dwc2_alloc_split_dma_aligned_buf(struct dwc2_hsotg *hsotg,
+ struct dwc2_qh *qh,
+
Dear Doug,
在 2018年05月08日 13:11, Doug Anderson 写道:
Hi,
On Mon, May 7, 2018 at 8:07 PM, William Wu wrote:
+static int dwc2_alloc_split_dma_aligned_buf(struct dwc2_hsotg *hsotg,
+ struct dwc2_qh *qh,
+ struct
Dear Doug,
在 2018年05月08日 13:13, Doug Anderson 写道:
Hi,
On Mon, May 7, 2018 at 8:07 PM, William Wu wrote:
If isoc split in transfer with no data (the length of DATA0
packet is zero), we can't simply return immediately. Because
the DATA0 can be the first transaction
Dear Doug,
在 2018年05月08日 13:13, Doug Anderson 写道:
Hi,
On Mon, May 7, 2018 at 8:07 PM, William Wu wrote:
If isoc split in transfer with no data (the length of DATA0
packet is zero), we can't simply return immediately. Because
the DATA0 can be the first transaction or the second transaction
Dear Doug,
在 2018年05月07日 15:19, Allen Hsu (許嘉銘) 写道:
Add more:
Best regards,
BU4 EE
Allen Hsu
QCI 886-3-327-2345 ext 15410
-Original Message-
From: Doug Anderson [mailto:diand...@google.com]
Sent: Friday, May 4, 2018 11:58 PM
To: wlf <w...@rock-chips.com>
Cc: William Wu &l
Dear Doug,
在 2018年05月07日 15:19, Allen Hsu (許嘉銘) 写道:
Add more:
Best regards,
BU4 EE
Allen Hsu
QCI 886-3-327-2345 ext 15410
-Original Message-
From: Doug Anderson [mailto:diand...@google.com]
Sent: Friday, May 4, 2018 11:58 PM
To: wlf
Cc: William Wu ; hmi...@synopsys.com; felipe.ba
Dear Doug,
在 2018年05月02日 13:02, Doug Anderson 写道:
Hi,
On Tue, May 1, 2018 at 8:04 PM, William Wu wrote:
If isoc split in transfer with no data (the length of DATA0
packet is zero), we can't simply return immediately. Because
the DATA0 can be the first transaction
Dear Doug,
在 2018年05月02日 13:02, Doug Anderson 写道:
Hi,
On Tue, May 1, 2018 at 8:04 PM, William Wu wrote:
If isoc split in transfer with no data (the length of DATA0
packet is zero), we can't simply return immediately. Because
the DATA0 can be the first transaction or the second transaction
Dear Doug,
在 2018年05月02日 12:33, Doug Anderson 写道:
Hi,
On Tue, May 1, 2018 at 8:04 PM, William Wu wrote:
The commit 3bc04e28a030 ("usb: dwc2: host: Get aligned DMA in
a more supported way") rips out a lot of code to simply the
allocation of aligned DMA. However, it
Dear Doug,
在 2018年05月02日 12:33, Doug Anderson 写道:
Hi,
On Tue, May 1, 2018 at 8:04 PM, William Wu wrote:
The commit 3bc04e28a030 ("usb: dwc2: host: Get aligned DMA in
a more supported way") rips out a lot of code to simply the
allocation of aligned DMA. However, it also introduces a new
Dear Sergei,
在 2018年04月24日 16:27, Sergei Shtylyov 写道:
Hello!
On 4/24/2018 5:43 AM, William Wu wrote:
If isoc split in transfer with no data (the length of DATA0
packet is 0), we can't simply return immediately. Because the
DATA0 can be the first transaction or the second transaction for
the
Dear Sergei,
在 2018年04月24日 16:27, Sergei Shtylyov 写道:
Hello!
On 4/24/2018 5:43 AM, William Wu wrote:
If isoc split in transfer with no data (the length of DATA0
packet is 0), we can't simply return immediately. Because the
DATA0 can be the first transaction or the second transaction for
the
Dear Heiko,
在 2018年02月11日 03:55, Heiko Stuebner 写道:
Hi Wulf,
Am Montag, 22. Januar 2018, 12:33:05 CET schrieb wlf:
在 2018年01月20日 05:49, Rob Herring 写道:
On Thu, Jan 18, 2018 at 09:47:50AM -0800, Brian Norris wrote:
On Thu, Jan 18, 2018 at 06:20:09PM +0100, Enric Balletbo Serra wrote
Dear Heiko,
在 2018年02月11日 03:55, Heiko Stuebner 写道:
Hi Wulf,
Am Montag, 22. Januar 2018, 12:33:05 CET schrieb wlf:
在 2018年01月20日 05:49, Rob Herring 写道:
On Thu, Jan 18, 2018 at 09:47:50AM -0800, Brian Norris wrote:
On Thu, Jan 18, 2018 at 06:20:09PM +0100, Enric Balletbo Serra wrote
Hi Jack,
在 2018年02月06日 02:17, Jack Pham 写道:
Hi William,
On Mon, Feb 05, 2018 at 07:33:38PM +0800, William Wu wrote:
Refer to the USB 3.0 spec '9.6.7 SuperSpeed Endpoint Companion',
the companion descriptor follows the standard endpoint descriptor.
This descriptor is only defined for
Hi Jack,
在 2018年02月06日 02:17, Jack Pham 写道:
Hi William,
On Mon, Feb 05, 2018 at 07:33:38PM +0800, William Wu wrote:
Refer to the USB 3.0 spec '9.6.7 SuperSpeed Endpoint Companion',
the companion descriptor follows the standard endpoint descriptor.
This descriptor is only defined for
Hi Alan,
在 2017年11月07日 23:18, Alan Stern 写道:
On Tue, 7 Nov 2017, wlf wrote:
That sounds like a good idea. Minas, does the following patch fix your
problem?
In theory we could do this calculation for every isochronous URB, not
just those coming from usbfs. But I don't think there's any
Hi Alan,
在 2017年11月07日 23:18, Alan Stern 写道:
On Tue, 7 Nov 2017, wlf wrote:
That sounds like a good idea. Minas, does the following patch fix your
problem?
In theory we could do this calculation for every isochronous URB, not
just those coming from usbfs. But I don't think there's any
Hi Alan,
在 2017年11月07日 03:17, Alan Stern 写道:
On Mon, 6 Nov 2017, wlf wrote:
Hi Minas,
在 2017年11月06日 17:28, Minas Harutyunyan 写道:
Hi,
On 11/6/2017 12:46 PM, William Wu wrote:
The actual_length in dwc2_hcd_urb structure is used
to indicate the total data length transferred so far
Hi Alan,
在 2017年11月07日 03:17, Alan Stern 写道:
On Mon, 6 Nov 2017, wlf wrote:
Hi Minas,
在 2017年11月06日 17:28, Minas Harutyunyan 写道:
Hi,
On 11/6/2017 12:46 PM, William Wu wrote:
The actual_length in dwc2_hcd_urb structure is used
to indicate the total data length transferred so far
Hi Minas,
在 2017年11月06日 17:28, Minas Harutyunyan 写道:
Hi,
On 11/6/2017 12:46 PM, William Wu wrote:
The actual_length in dwc2_hcd_urb structure is used
to indicate the total data length transferred so far,
but in dwc2_update_isoc_urb_state(), it just updates
the actual_length of isoc frame, and
Hi Minas,
在 2017年11月06日 17:28, Minas Harutyunyan 写道:
Hi,
On 11/6/2017 12:46 PM, William Wu wrote:
The actual_length in dwc2_hcd_urb structure is used
to indicate the total data length transferred so far,
but in dwc2_update_isoc_urb_state(), it just updates
the actual_length of isoc frame, and
Dear Balbi & Gregkh,
在 2017年08月21日 21:36, William Wu 写道:
Adds the device tree bindings description for RK3328 and
compatible USB DWC3 controller.
Signed-off-by: William Wu
---
Changes in v3:
- Add this for separate usb dt-bindings patch.
Changes in v2:
- None
Dear Balbi & Gregkh,
在 2017年08月21日 21:36, William Wu 写道:
Adds the device tree bindings description for RK3328 and
compatible USB DWC3 controller.
Signed-off-by: William Wu
---
Changes in v3:
- Add this for separate usb dt-bindings patch.
Changes in v2:
- None
Dear Heiko,
在 2017年08月18日 17:24, Heiko Stuebner 写道:
Hi William,
Am Donnerstag, 17. August 2017, 15:54:49 CEST schrieb William Wu:
RK3328 has one USB 3.0 OTG controller which uses DWC_USB3
core's general architecture. It can act as static xHCI host
controller, static device controller, USB
Dear Heiko,
在 2017年08月18日 17:24, Heiko Stuebner 写道:
Hi William,
Am Donnerstag, 17. August 2017, 15:54:49 CEST schrieb William Wu:
RK3328 has one USB 3.0 OTG controller which uses DWC_USB3
core's general architecture. It can act as static xHCI host
controller, static device controller, USB
Dear Heiko,
在 2017年06月02日 04:22, Heiko Stuebner 写道:
Hi William,
Am Mittwoch, 31. Mai 2017, 09:21:23 CEST schrieb William Wu:
This patch adds usb otg/host controllers and phys nodes on rk322x.
Signed-off-by: William Wu
---
arch/arm/boot/dts/rk322x.dtsi | 138
Dear Heiko,
在 2017年06月02日 04:22, Heiko Stuebner 写道:
Hi William,
Am Mittwoch, 31. Mai 2017, 09:21:23 CEST schrieb William Wu:
This patch adds usb otg/host controllers and phys nodes on rk322x.
Signed-off-by: William Wu
---
arch/arm/boot/dts/rk322x.dtsi | 138
Dear Guenter,
在 2017年04月19日 13:15, Guenter Roeck 写道:
On Tue, Apr 18, 2017 at 8:59 PM, wlf <w...@rock-chips.com> wrote:
Dear Guenter,
在 2017年04月18日 21:18, Guenter Roeck 写道:
On Mon, Apr 17, 2017 at 10:17 PM, William Wu <william...@rock-chips.com>
wrote:
This patch adds a quir
Dear Guenter,
在 2017年04月19日 13:15, Guenter Roeck 写道:
On Tue, Apr 18, 2017 at 8:59 PM, wlf wrote:
Dear Guenter,
在 2017年04月18日 21:18, Guenter Roeck 写道:
On Mon, Apr 17, 2017 at 10:17 PM, William Wu
wrote:
This patch adds a quirk to disable USB 2.0 MAC linestate check
during HS transmit
Dear Guenter,
在 2017年04月18日 21:18, Guenter Roeck 写道:
On Mon, Apr 17, 2017 at 10:17 PM, William Wu wrote:
This patch adds a quirk to disable USB 2.0 MAC linestate check
during HS transmit. Refer the dwc3 databook, we can use it for
some special platforms if the
Dear Guenter,
在 2017年04月18日 21:18, Guenter Roeck 写道:
On Mon, Apr 17, 2017 at 10:17 PM, William Wu wrote:
This patch adds a quirk to disable USB 2.0 MAC linestate check
during HS transmit. Refer the dwc3 databook, we can use it for
some special platforms if the linestate not reflect the
Hi Roger,
在 2017年01月13日 19:02, Roger Quadros 写道:
Hi,
On 13/01/17 05:18, William Wu wrote:
From: William wu
The commit 4ac53087d6d4 ("usb: xhci: plat: Create both
HCDs before adding them") move add hcd to the end of
probe, this cause hcc_params uninitiated, because
Hi Roger,
在 2017年01月13日 19:02, Roger Quadros 写道:
Hi,
On 13/01/17 05:18, William Wu wrote:
From: William wu
The commit 4ac53087d6d4 ("usb: xhci: plat: Create both
HCDs before adding them") move add hcd to the end of
probe, this cause hcc_params uninitiated, because xHCI
driver sets
Hi Roger,
在 2017年01月12日 23:38, Roger Quadros 写道:
On 12/01/17 17:33, Alan Stern wrote:
On Thu, 12 Jan 2017, Roger Quadros wrote:
William,
On 12/01/17 14:03, William Wu wrote:
From: William wu
On some platforms(e.g. rk3399 board), we can call hcd_add/remove
Hi Roger,
在 2017年01月12日 23:38, Roger Quadros 写道:
On 12/01/17 17:33, Alan Stern wrote:
On Thu, 12 Jan 2017, Roger Quadros wrote:
William,
On 12/01/17 14:03, William Wu wrote:
From: William wu
On some platforms(e.g. rk3399 board), we can call hcd_add/remove
consecutively without calling
Dear Doug & Xing Zheng,
在 2016年12月22日 08:47, Doug Anderson 写道:
Hi,
On Wed, Dec 21, 2016 at 2:41 AM, Xing Zheng wrote:
From: William wu
We found that the suspend process was blocked when it run into
ehci/ohci module due to clk-480m of usb2-phy
Dear Doug & Xing Zheng,
在 2016年12月22日 08:47, Doug Anderson 写道:
Hi,
On Wed, Dec 21, 2016 at 2:41 AM, Xing Zheng wrote:
From: William wu
We found that the suspend process was blocked when it run into
ehci/ohci module due to clk-480m of usb2-phy was disabled.
The root cause is that usb2-phy
Hi Arnd,
在 2016年11月16日 22:22, Arnd Bergmann 写道:
The newly added OTG support has an obvious uninitialized variable
access that gcc warns about:
drivers/phy/phy-rockchip-inno-usb2.c: In function 'rockchip_chg_detect_work':
drivers/phy/phy-rockchip-inno-usb2.c:717:7: error: 'tmout' may be used
Hi Arnd,
在 2016年11月16日 22:22, Arnd Bergmann 写道:
The newly added OTG support has an obvious uninitialized variable
access that gcc warns about:
drivers/phy/phy-rockchip-inno-usb2.c: In function 'rockchip_chg_detect_work':
drivers/phy/phy-rockchip-inno-usb2.c:717:7: error: 'tmout' may be used
Hi Stephen,
在 2016年11月16日 11:00, Stephen Rothwell 写道:
Hi Kishon,
After merging the phy-next tree, today's linux-next build (x86_64
allmodconfig) produced this warning:
drivers/phy/phy-rockchip-inno-usb2.c: In function 'rockchip_chg_detect_work':
drivers/phy/phy-rockchip-inno-usb2.c:717:7:
Hi Stephen,
在 2016年11月16日 11:00, Stephen Rothwell 写道:
Hi Kishon,
After merging the phy-next tree, today's linux-next build (x86_64
allmodconfig) produced this warning:
drivers/phy/phy-rockchip-inno-usb2.c: In function 'rockchip_chg_detect_work':
drivers/phy/phy-rockchip-inno-usb2.c:717:7:
Hi Doug,
在 2016年11月15日 02:17, Doug Anderson 写道:
William,
On Mon, Nov 14, 2016 at 1:27 AM, William Wu wrote:
We found that the system crashed due to 480MHz output clock of
USB2 PHY was unstable after clock had been enabled by gpu module.
Theoretically, 1 millisecond is a
Hi Doug,
在 2016年11月15日 02:17, Doug Anderson 写道:
William,
On Mon, Nov 14, 2016 at 1:27 AM, William Wu wrote:
We found that the system crashed due to 480MHz output clock of
USB2 PHY was unstable after clock had been enabled by gpu module.
Theoretically, 1 millisecond is a critical value for
Hi Doug,
在 2016年11月15日 02:15, Doug Anderson 写道:
William
On Sun, Nov 13, 2016 at 11:01 PM, William Wu wrote:
Since we needs to delay ~1ms to wait for 480MHz output clock
of USB2 PHY to become stable after turn on it, the delay time
is pretty long for something that's
Hi Doug,
在 2016年11月15日 02:15, Doug Anderson 写道:
William
On Sun, Nov 13, 2016 at 11:01 PM, William Wu wrote:
Since we needs to delay ~1ms to wait for 480MHz output clock
of USB2 PHY to become stable after turn on it, the delay time
is pretty long for something that's supposed to be "atomic"
Hi Heiko,
在 2016年11月10日 17:21, Heiko Stübner 写道:
Am Donnerstag, 10. November 2016, 10:54:49 schrieb wlf:
Hi Doug,
在 2016年11月10日 04:54, Doug Anderson 写道:
Hi,
On Mon, Nov 7, 2016 at 5:00 AM, William Wu <w...@rock-chips.com> wrote:
We found that the system crashed due to 480MHz output
Hi Heiko,
在 2016年11月10日 17:21, Heiko Stübner 写道:
Am Donnerstag, 10. November 2016, 10:54:49 schrieb wlf:
Hi Doug,
在 2016年11月10日 04:54, Doug Anderson 写道:
Hi,
On Mon, Nov 7, 2016 at 5:00 AM, William Wu wrote:
We found that the system crashed due to 480MHz output clock of
USB2 PHY
Hi Doug,
在 2016年11月10日 04:54, Doug Anderson 写道:
Hi,
On Mon, Nov 7, 2016 at 5:00 AM, William Wu wrote:
We found that the system crashed due to 480MHz output clock of
USB2 PHY was unstable after clock had been enabled by gpu module.
Theoretically, 1 millisecond is a
Hi Doug,
在 2016年11月10日 04:54, Doug Anderson 写道:
Hi,
On Mon, Nov 7, 2016 at 5:00 AM, William Wu wrote:
We found that the system crashed due to 480MHz output clock of
USB2 PHY was unstable after clock had been enabled by gpu module.
Theoretically, 1 millisecond is a critical value for 480MHz
Hi Kishon,
在 2016年11月04日 01:17, Kishon Vijay Abraham I 写道:
On Thursday 03 November 2016 07:36 AM, William Wu wrote:
The rk3399 SoC USB2 PHY is comprised of one Host port and
one OTG port. And OTG port is for USB2.0 part of USB3.0 OTG
controller, as a part to construct a fully feature Type-C
Hi Kishon,
在 2016年11月04日 01:17, Kishon Vijay Abraham I 写道:
On Thursday 03 November 2016 07:36 AM, William Wu wrote:
The rk3399 SoC USB2 PHY is comprised of one Host port and
one OTG port. And OTG port is for USB2.0 part of USB3.0 OTG
controller, as a part to construct a fully feature Type-C
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