subject:"\[PATCH v2 00\/11\] perf events patches for improved ARM64 support"

On 05/03/2018 15:39, William Cohen wrote:

On 03/05/2018 06:24 AM, John Garry wrote:

I am seeing issue(log below) with this patchset on our platfrom.
i have tried using your v2 branch [1]

root@borg-1>perf_acme>> ./perf --version
perf version 4.16.rc1.g087f7ca
root@borg-1>perf_acme>> ./perf stat -e bus_access_rd sleep 1

Performance counter stats for 'sleep 1':

23,099 bus_access_rd

1.000708516 seconds time elapsed

root@borg-1>perf_acme>> cd -
/ganapat/perf/linux-hisi/tools/perf
root@borg-1>perf>> ./perf --version
perf version 4.16.rc1.gcb5a74
root@borg-1>perf>> ./perf stat -e bus_access_rd sleep 1

Performance counter stats for 'sleep 1':

0 bus_access_rd

1.000709162 seconds time elapsed

root@borg-1>perf>>

[1] https://github.com/hisilicon/linux-hisi.git

Hi,

Hi Will Cohen, Ganapatrao,

I took a slightly different tack and compared the output of "perf list
--details" to see if the event numbers numbers were the same. For the common events
borrowed from the armv8-recommended.json all the events are 0 for the cortex a53. That
would explain why the bus_access_rd above were counts were different if it was counting
the SW_INCR event instead of bus_access_rd.

Thanks for this. I see the problem. At the end I missed bringing across
something from v1. Easily fixed.

Why not key the matching of common events off the "EventName" rather than "EventCode"?
The EventName would be more descriptive. Then the json files could eliminate the "BriefDescription"
and just have the EventName with nothing else for each event. This would further reduce the amount of
redundant fields between the specific implementations and the common set.

I did consider it and it could work. But it all depends on whether the "EventName" only is always
readable/descriptive enough in the JSON, without requiring the "BriefDescription". The "EventName"
can be rather succinct for any arch. And we need to guarantee that the "EventName" is unique.

Here's a sample:
[
{
"ArchStdEvent": "L1D_CACHE_RD",
},
{
"ArchStdEvent": "L1D_CACHE_WR",
},

vs.

[
{
"ArchStdEvent": "0x40",
"BriefDescription": "L1D cache access, read"
},
{
"ArchStdEvent": "0x41",
"BriefDescription": "L1D cache access, write"
},

Opinion?

Hi Will,

Hi John,

The "ArchStdEvent" version is more concise by avoiding the duplication
of "BriefDescription" field and possible differences in
"BriefDescription" due to typos. Would it make easier for people coding
up descriptions for specific processors? It would depend on how the
documentation is written up. For the armv8 documentation in "D5.10.3
Common event numbers" list the event mnemonic in "Table D5-8 PMU common
architectural and microarchitectural event numbers" so just using the
event names seems like it would be pretty clear.

Fine. ***If anyone disagrees on this then please say so.***

For different Intel

ia64 microarchitecture implementations there are different event coding
to implement the same event name. Not sure how would handle the
universe of different families of ia64 processor implementations.

I think for this example, if we were to use the "EventName" as the
matching field, then it may be still possible to support by overriding
the "EventCode" in the platform JSON.

The support in this patchset allows fields to be overriden; the
following is a sample of how it would look:

{
"ArchStdEvent": "L1D_CACHE_RD", // Arch EventCode 0x40
"EventCode": "0x123456" // override the eventcode
},

Is the armv8-common.json being used as a template that fills out the
fields of the json elements that match up an entry in the
armv8-common.json? Or does it only use the information from the
armv8-common.json. If the code treated the armv8-common.json as default
values, then if something differs in the architecture specific entry it
could overwrite the default value from the template.

Yes, this is supported. By default, the values in template
armv8-common.json are used (I called it armv8-recommended.json);
however, any fields defined in the platform JSON for a matching event
are prioritized, as above.

-Will Cohen

Thanks,
John

Re: [PATCH v2 00/11] perf events patches for improved ARM64 support

On 05/03/2018 15:39, William Cohen wrote:

On 03/05/2018 06:24 AM, John Garry wrote:

I am seeing issue(log below) with this patchset on our platfrom.
i have tried using your v2 branch [1]

root@borg-1>perf_acme>> ./perf --version
perf version 4.16.rc1.g087f7ca
root@borg-1>perf_acme>> ./perf stat -e bus_access_rd sleep 1

Performance counter stats for 'sleep 1':

23,099 bus_access_rd

1.000708516 seconds time elapsed

root@borg-1>perf_acme>> cd -
/ganapat/perf/linux-hisi/tools/perf
root@borg-1>perf>> ./perf --version
perf version 4.16.rc1.gcb5a74
root@borg-1>perf>> ./perf stat -e bus_access_rd sleep 1

Performance counter stats for 'sleep 1':

0 bus_access_rd

1.000709162 seconds time elapsed

root@borg-1>perf>>

[1] https://github.com/hisilicon/linux-hisi.git

Hi,

Hi Will Cohen, Ganapatrao,

Thanks for this. I see the problem. At the end I missed bringing across
something from v1. Easily fixed.

Here's a sample:
[
{
"ArchStdEvent": "L1D_CACHE_RD",
},
{
"ArchStdEvent": "L1D_CACHE_WR",
},

vs.

[
{
"ArchStdEvent": "0x40",
"BriefDescription": "L1D cache access, read"
},
{
"ArchStdEvent": "0x41",
"BriefDescription": "L1D cache access, write"
},

Opinion?

Hi Will,

Hi John,

Fine. ***If anyone disagrees on this then please say so.***

For different Intel

I think for this example, if we were to use the "EventName" as the
matching field, then it may be still possible to support by overriding
the "EventCode" in the platform JSON.

The support in this patchset allows fields to be overriden; the
following is a sample of how it would look:

{
"ArchStdEvent": "L1D_CACHE_RD", // Arch EventCode 0x40
"EventCode": "0x123456" // override the eventcode
},

-Will Cohen

Thanks,
John

Re: [PATCH v2 00/11] perf events patches for improved ARM64 support

2018-03-05 Thread William Cohen

On 03/05/2018 06:24 AM, John Garry wrote:
>>> I am seeing issue(log below) with this patchset on our platfrom.
>>> i have tried using your v2 branch [1]
>>>
>>> root@borg-1>perf_acme>> ./perf --version
>>> perf version 4.16.rc1.g087f7ca
>>> root@borg-1>perf_acme>> ./perf stat -e bus_access_rd sleep 1
>>>
>>>  Performance counter stats for 'sleep 1':
>>>
>>>     23,099  bus_access_rd
>>>
>>>    1.000708516 seconds time elapsed
>>>
>>> root@borg-1>perf_acme>> cd -
>>> /ganapat/perf/linux-hisi/tools/perf
>>> root@borg-1>perf>> ./perf --version
>>> perf version 4.16.rc1.gcb5a74
>>> root@borg-1>perf>> ./perf stat -e bus_access_rd sleep 1
>>>
>>>  Performance counter stats for 'sleep 1':
>>>
>>>  0  bus_access_rd
>>>
>>>    1.000709162 seconds time elapsed
>>>
>>> root@borg-1>perf>>
>>>
>>>
>>> [1] https://github.com/hisilicon/linux-hisi.git
>>>
>> Hi,
> 
> Hi Will Cohen, Ganapatrao,
> 
>>
>> I took a slightly different tack and compared the output of "perf list 
>> --details" to see if the event numbers numbers were the same.  For the 
>> common events borrowed from the armv8-recommended.json all the events are 0 
>> for the cortex a53.  That would explain why the bus_access_rd above were 
>> counts were different if it was counting the SW_INCR event instead of 
>> bus_access_rd.
>>
> 
> Thanks for this. I see the problem. At the end I missed bringing across 
> something from v1. Easily fixed.
> 
>> Why not key the matching of common events off the "EventName" rather than 
>> "EventCode"? The EventName would be more descriptive. Then the json files 
>> could eliminate the "BriefDescription" and just have the EventName with 
>> nothing else for each event.  This would further reduce the amount of 
>> redundant fields between the specific implementations and the common set.
>>
> 
> I did consider it and it could work. But it all depends on whether the 
> "EventName" only is always readable/descriptive enough in the JSON, without 
> requiring the "BriefDescription". The "EventName" can be rather succinct for 
> any arch. And we need to guarantee that the "EventName" is unique.
> 
> Here's a sample:
> [
>     {
>     "ArchStdEvent": "L1D_CACHE_RD",
>     },
>     {
>     "ArchStdEvent": "L1D_CACHE_WR",
>     },
> 
> vs.
> 
> [
>     {
>     "ArchStdEvent": "0x40",
>     "BriefDescription": "L1D cache access, read"
>     },
>     {
>     "ArchStdEvent": "0x41",
>     "BriefDescription": "L1D cache access, write"
>     },
> 
> 
> Opinion?

Hi John,

The "ArchStdEvent" version is more concise by avoiding the duplication of 
"BriefDescription" field and possible differences in "BriefDescription" due to 
typos.  Would it make easier for people coding up descriptions for specific 
processors?  It would depend on how the documentation is written up.  For the 
armv8 documentation in "D5.10.3 Common event numbers" list the event mnemonic 
in "Table D5-8 PMU common architectural and microarchitectural event numbers" 
so just using the event names seems like it would be pretty clear.  For 
different Intel ia64 microarchitecture implementations there are different 
event coding to implement the same event name.  Not sure how would handle the 
universe of different families of ia64 processor implementations.

Is the armv8-common.json being used as a template that fills out the fields of 
the json elements that match up an entry in the armv8-common.json? Or does it 
only use the information from the armv8-common.json.  If the code treated the 
armv8-common.json as default values, then if something differs in the 
architecture specific entry it could overwrite the default value from the 
template.

-Will Cohen

Re: [PATCH v2 00/11] perf events patches for improved ARM64 support

2018-03-05 Thread William Cohen

On 03/05/2018 06:24 AM, John Garry wrote:
>>> I am seeing issue(log below) with this patchset on our platfrom.
>>> i have tried using your v2 branch [1]
>>>
>>> root@borg-1>perf_acme>> ./perf --version
>>> perf version 4.16.rc1.g087f7ca
>>> root@borg-1>perf_acme>> ./perf stat -e bus_access_rd sleep 1
>>>
>>>  Performance counter stats for 'sleep 1':
>>>
>>>     23,099  bus_access_rd
>>>
>>>    1.000708516 seconds time elapsed
>>>
>>> root@borg-1>perf_acme>> cd -
>>> /ganapat/perf/linux-hisi/tools/perf
>>> root@borg-1>perf>> ./perf --version
>>> perf version 4.16.rc1.gcb5a74
>>> root@borg-1>perf>> ./perf stat -e bus_access_rd sleep 1
>>>
>>>  Performance counter stats for 'sleep 1':
>>>
>>>  0  bus_access_rd
>>>
>>>    1.000709162 seconds time elapsed
>>>
>>> root@borg-1>perf>>
>>>
>>>
>>> [1] https://github.com/hisilicon/linux-hisi.git
>>>
>> Hi,
> 
> Hi Will Cohen, Ganapatrao,
> 
>>
>> I took a slightly different tack and compared the output of "perf list 
>> --details" to see if the event numbers numbers were the same.  For the 
>> common events borrowed from the armv8-recommended.json all the events are 0 
>> for the cortex a53.  That would explain why the bus_access_rd above were 
>> counts were different if it was counting the SW_INCR event instead of 
>> bus_access_rd.
>>
> 
> Thanks for this. I see the problem. At the end I missed bringing across 
> something from v1. Easily fixed.
> 
>> Why not key the matching of common events off the "EventName" rather than 
>> "EventCode"? The EventName would be more descriptive. Then the json files 
>> could eliminate the "BriefDescription" and just have the EventName with 
>> nothing else for each event.  This would further reduce the amount of 
>> redundant fields between the specific implementations and the common set.
>>
> 
> I did consider it and it could work. But it all depends on whether the 
> "EventName" only is always readable/descriptive enough in the JSON, without 
> requiring the "BriefDescription". The "EventName" can be rather succinct for 
> any arch. And we need to guarantee that the "EventName" is unique.
> 
> Here's a sample:
> [
>     {
>     "ArchStdEvent": "L1D_CACHE_RD",
>     },
>     {
>     "ArchStdEvent": "L1D_CACHE_WR",
>     },
> 
> vs.
> 
> [
>     {
>     "ArchStdEvent": "0x40",
>     "BriefDescription": "L1D cache access, read"
>     },
>     {
>     "ArchStdEvent": "0x41",
>     "BriefDescription": "L1D cache access, write"
>     },
> 
> 
> Opinion?

Hi John,

The "ArchStdEvent" version is more concise by avoiding the duplication of 
"BriefDescription" field and possible differences in "BriefDescription" due to 
typos.  Would it make easier for people coding up descriptions for specific 
processors?  It would depend on how the documentation is written up.  For the 
armv8 documentation in "D5.10.3 Common event numbers" list the event mnemonic 
in "Table D5-8 PMU common architectural and microarchitectural event numbers" 
so just using the event names seems like it would be pretty clear.  For 
different Intel ia64 microarchitecture implementations there are different 
event coding to implement the same event name.  Not sure how would handle the 
universe of different families of ia64 processor implementations.

Is the armv8-common.json being used as a template that fills out the fields of 
the json elements that match up an entry in the armv8-common.json? Or does it 
only use the information from the armv8-common.json.  If the code treated the 
armv8-common.json as default values, then if something differs in the 
architecture specific entry it could overwrite the default value from the 
template.

-Will Cohen

Re: [PATCH v2 00/11] perf events patches for improved ARM64 support


I am seeing issue(log below) with this patchset on our platfrom.
i have tried using your v2 branch [1]

root@borg-1>perf_acme>> ./perf --version
perf version 4.16.rc1.g087f7ca
root@borg-1>perf_acme>> ./perf stat -e bus_access_rd sleep 1

 Performance counter stats for 'sleep 1':

23,099  bus_access_rd

   1.000708516 seconds time elapsed

root@borg-1>perf_acme>> cd -
/ganapat/perf/linux-hisi/tools/perf
root@borg-1>perf>> ./perf --version
perf version 4.16.rc1.gcb5a74
root@borg-1>perf>> ./perf stat -e bus_access_rd sleep 1

 Performance counter stats for 'sleep 1':

 0  bus_access_rd

   1.000709162 seconds time elapsed

root@borg-1>perf>>


[1] https://github.com/hisilicon/linux-hisi.git


Hi,


Hi Will Cohen, Ganapatrao,



I took a slightly different tack and compared the output of "perf list 
--details" to see if the event numbers numbers were the same.  For the common events 
borrowed from the armv8-recommended.json all the events are 0 for the cortex a53.  That 
would explain why the bus_access_rd above were counts were different if it was counting 
the SW_INCR event instead of bus_access_rd.



Thanks for this. I see the problem. At the end I missed bringing across 
something from v1. Easily fixed.



Why not key the matching of common events off the "EventName" rather than "EventCode"? 
The EventName would be more descriptive. Then the json files could eliminate the "BriefDescription" 
and just have the EventName with nothing else for each event.  This would further reduce the amount of 
redundant fields between the specific implementations and the common set.



I did consider it and it could work. But it all depends on whether the 
"EventName" only is always readable/descriptive enough in the JSON, 
without requiring the "BriefDescription". The "EventName" can be rather 
succinct for any arch. And we need to guarantee that the "EventName" is 
unique.


Here's a sample:
[
{
"ArchStdEvent": "L1D_CACHE_RD",
},
{
"ArchStdEvent": "L1D_CACHE_WR",
},

vs.

[
{
"ArchStdEvent": "0x40",
"BriefDescription": "L1D cache access, read"
},
{
"ArchStdEvent": "0x41",
"BriefDescription": "L1D cache access, write"
},


Opinion?

John


-Will

.



thanks,
John

Re: [PATCH v2 00/11] perf events patches for improved ARM64 support


I am seeing issue(log below) with this patchset on our platfrom.
i have tried using your v2 branch [1]

root@borg-1>perf_acme>> ./perf --version
perf version 4.16.rc1.g087f7ca
root@borg-1>perf_acme>> ./perf stat -e bus_access_rd sleep 1

 Performance counter stats for 'sleep 1':

23,099  bus_access_rd

   1.000708516 seconds time elapsed

root@borg-1>perf_acme>> cd -
/ganapat/perf/linux-hisi/tools/perf
root@borg-1>perf>> ./perf --version
perf version 4.16.rc1.gcb5a74
root@borg-1>perf>> ./perf stat -e bus_access_rd sleep 1

 Performance counter stats for 'sleep 1':

 0  bus_access_rd

   1.000709162 seconds time elapsed

root@borg-1>perf>>


[1] https://github.com/hisilicon/linux-hisi.git


Hi,


Hi Will Cohen, Ganapatrao,



I took a slightly different tack and compared the output of "perf list 
--details" to see if the event numbers numbers were the same.  For the common events 
borrowed from the armv8-recommended.json all the events are 0 for the cortex a53.  That 
would explain why the bus_access_rd above were counts were different if it was counting 
the SW_INCR event instead of bus_access_rd.



Thanks for this. I see the problem. At the end I missed bringing across 
something from v1. Easily fixed.



Why not key the matching of common events off the "EventName" rather than "EventCode"? 
The EventName would be more descriptive. Then the json files could eliminate the "BriefDescription" 
and just have the EventName with nothing else for each event.  This would further reduce the amount of 
redundant fields between the specific implementations and the common set.



I did consider it and it could work. But it all depends on whether the 
"EventName" only is always readable/descriptive enough in the JSON, 
without requiring the "BriefDescription". The "EventName" can be rather 
succinct for any arch. And we need to guarantee that the "EventName" is 
unique.


Here's a sample:
[
{
"ArchStdEvent": "L1D_CACHE_RD",
},
{
"ArchStdEvent": "L1D_CACHE_WR",
},

vs.

[
{
"ArchStdEvent": "0x40",
"BriefDescription": "L1D cache access, read"
},
{
"ArchStdEvent": "0x41",
"BriefDescription": "L1D cache access, write"
},


Opinion?

John


-Will

.



thanks,
John

Re: [PATCH v2 00/11] perf events patches for improved ARM64 support

On 03/02/2018 11:35 AM, Ganapatrao Kulkarni wrote:
> Hi John,
> 
> On Fri, Mar 2, 2018 at 9:35 PM, William Cohen  wrote:
>> On 03/02/2018 03:24 AM, John Garry wrote:
>>> On 27/02/2018 09:50, Jiri Olsa wrote:
 On Sat, Feb 24, 2018 at 12:05:21AM +0800, John Garry wrote:
> This patchset adds support for some perf events features,
> targeted at ARM64, implemented in a generic fashion.
>
> The two main features are as follows:
> - support for arch/vendor/platform pmu events directory structure
>- to support this, topic subdirectory support needs to be dropped
> - support for parsing standard architecture pmu events
>
> On the back of these, the Cavium ThunderX2, ARM Cortex-A53,
> and HiSilicon hip08 JSONs are relocated/added/updated.
>
> In addition, there is a patch to drop mutli-mapfile.csv support and
> also a bugfix in jevents.c for an error code value.
>
> Differences to v1:
> - Address coding issues from Jiri Olsa in adding arch std event
>support (https://lkml.org/lkml/2018/2/6/501)
> - add patch to drop topic subdirectory support
> - add patch for bug fix in json_events()
> - add review tags from Jiri Olsa

 can't tell if those json file changes are ok, but for all the code changes:

>>>
>>> Hi William, Ganapatrao,
>>>
>>> Can you check the modifications to the ARM64 JSONs you originally submitted 
>>> in the patchset please?>
>>> If they are not checked, I'll have to see if the maintainers will accept 
>>> without your review. If not, I'll have to drop them.
> 
> I am seeing issue(log below) with this patchset on our platfrom.
> i have tried using your v2 branch [1]
> 
> root@borg-1>perf_acme>> ./perf --version
> perf version 4.16.rc1.g087f7ca
> root@borg-1>perf_acme>> ./perf stat -e bus_access_rd sleep 1
> 
>  Performance counter stats for 'sleep 1':
> 
> 23,099  bus_access_rd
> 
>1.000708516 seconds time elapsed
> 
> root@borg-1>perf_acme>> cd -
> /ganapat/perf/linux-hisi/tools/perf
> root@borg-1>perf>> ./perf --version
> perf version 4.16.rc1.gcb5a74
> root@borg-1>perf>> ./perf stat -e bus_access_rd sleep 1
> 
>  Performance counter stats for 'sleep 1':
> 
>  0  bus_access_rd
> 
>1.000709162 seconds time elapsed
> 
> root@borg-1>perf>>
> 
> 
> [1] https://github.com/hisilicon/linux-hisi.git
> 
Hi,

I took a slightly different tack and compared the output of "perf list 
--details" to see if the event numbers numbers were the same.  For the common 
events borrowed from the armv8-recommended.json all the events are 0 for the 
cortex a53.  That would explain why the bus_access_rd above were counts were 
different if it was counting the SW_INCR event instead of bus_access_rd.

Why not key the matching of common events off the "EventName" rather than 
"EventCode"? The EventName would be more descriptive. Then the json files could 
eliminate the "BriefDescription" and just have the EventName with nothing else 
for each event.  This would further reduce the amount of redundant fields 
between the specific implementations and the common set.

-Will

Re: [PATCH v2 00/11] perf events patches for improved ARM64 support

On 03/02/2018 11:35 AM, Ganapatrao Kulkarni wrote:
> Hi John,
> 
> On Fri, Mar 2, 2018 at 9:35 PM, William Cohen  wrote:
>> On 03/02/2018 03:24 AM, John Garry wrote:
>>> On 27/02/2018 09:50, Jiri Olsa wrote:
 On Sat, Feb 24, 2018 at 12:05:21AM +0800, John Garry wrote:
> This patchset adds support for some perf events features,
> targeted at ARM64, implemented in a generic fashion.
>
> The two main features are as follows:
> - support for arch/vendor/platform pmu events directory structure
>- to support this, topic subdirectory support needs to be dropped
> - support for parsing standard architecture pmu events
>
> On the back of these, the Cavium ThunderX2, ARM Cortex-A53,
> and HiSilicon hip08 JSONs are relocated/added/updated.
>
> In addition, there is a patch to drop mutli-mapfile.csv support and
> also a bugfix in jevents.c for an error code value.
>
> Differences to v1:
> - Address coding issues from Jiri Olsa in adding arch std event
>support (https://lkml.org/lkml/2018/2/6/501)
> - add patch to drop topic subdirectory support
> - add patch for bug fix in json_events()
> - add review tags from Jiri Olsa

 can't tell if those json file changes are ok, but for all the code changes:

>>>
>>> Hi William, Ganapatrao,
>>>
>>> Can you check the modifications to the ARM64 JSONs you originally submitted 
>>> in the patchset please?>
>>> If they are not checked, I'll have to see if the maintainers will accept 
>>> without your review. If not, I'll have to drop them.
> 
> I am seeing issue(log below) with this patchset on our platfrom.
> i have tried using your v2 branch [1]
> 
> root@borg-1>perf_acme>> ./perf --version
> perf version 4.16.rc1.g087f7ca
> root@borg-1>perf_acme>> ./perf stat -e bus_access_rd sleep 1
> 
>  Performance counter stats for 'sleep 1':
> 
> 23,099  bus_access_rd
> 
>1.000708516 seconds time elapsed
> 
> root@borg-1>perf_acme>> cd -
> /ganapat/perf/linux-hisi/tools/perf
> root@borg-1>perf>> ./perf --version
> perf version 4.16.rc1.gcb5a74
> root@borg-1>perf>> ./perf stat -e bus_access_rd sleep 1
> 
>  Performance counter stats for 'sleep 1':
> 
>  0  bus_access_rd
> 
>1.000709162 seconds time elapsed
> 
> root@borg-1>perf>>
> 
> 
> [1] https://github.com/hisilicon/linux-hisi.git
> 
Hi,

I took a slightly different tack and compared the output of "perf list 
--details" to see if the event numbers numbers were the same.  For the common 
events borrowed from the armv8-recommended.json all the events are 0 for the 
cortex a53.  That would explain why the bus_access_rd above were counts were 
different if it was counting the SW_INCR event instead of bus_access_rd.

Why not key the matching of common events off the "EventName" rather than 
"EventCode"? The EventName would be more descriptive. Then the json files could 
eliminate the "BriefDescription" and just have the EventName with nothing else 
for each event.  This would further reduce the amount of redundant fields 
between the specific implementations and the common set.

-Will

Re: [PATCH v2 00/11] perf events patches for improved ARM64 support


Can you check the modifications to the ARM64 JSONs you originally submitted in the 
patchset please?>
If they are not checked, I'll have to see if the maintainers will accept 
without your review. If not, I'll have to drop them.


I am seeing issue(log below) with this patchset on our platfrom.
i have tried using your v2 branch [1]

root@borg-1>perf_acme>> ./perf --version
perf version 4.16.rc1.g087f7ca
root@borg-1>perf_acme>> ./perf stat -e bus_access_rd sleep 1

 Performance counter stats for 'sleep 1':

23,099  bus_access_rd

   1.000708516 seconds time elapsed

root@borg-1>perf_acme>> cd -
/ganapat/perf/linux-hisi/tools/perf
root@borg-1>perf>> ./perf --version
perf version 4.16.rc1.gcb5a74
root@borg-1>perf>> ./perf stat -e bus_access_rd sleep 1

 Performance counter stats for 'sleep 1':

 0  bus_access_rd

   1.000709162 seconds time elapsed

root@borg-1>perf>>


[1] https://github.com/hisilicon/linux-hisi.git


Hi Ganapatrao,

Thanks for the notification. Let me check this.

Regards,
John





Hi John,

I will take a look at the patches this weekend and give feedback beginning of 
next week. -Will



Thanks,
John


Acked-by: Jiri Olsa 

thanks,
jirka

.


thanks
Ganapat








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.

Re: [PATCH v2 00/11] perf events patches for improved ARM64 support


Can you check the modifications to the ARM64 JSONs you originally submitted in the 
patchset please?>
If they are not checked, I'll have to see if the maintainers will accept 
without your review. If not, I'll have to drop them.


I am seeing issue(log below) with this patchset on our platfrom.
i have tried using your v2 branch [1]

root@borg-1>perf_acme>> ./perf --version
perf version 4.16.rc1.g087f7ca
root@borg-1>perf_acme>> ./perf stat -e bus_access_rd sleep 1

 Performance counter stats for 'sleep 1':

23,099  bus_access_rd

   1.000708516 seconds time elapsed

root@borg-1>perf_acme>> cd -
/ganapat/perf/linux-hisi/tools/perf
root@borg-1>perf>> ./perf --version
perf version 4.16.rc1.gcb5a74
root@borg-1>perf>> ./perf stat -e bus_access_rd sleep 1

 Performance counter stats for 'sleep 1':

 0  bus_access_rd

   1.000709162 seconds time elapsed

root@borg-1>perf>>


[1] https://github.com/hisilicon/linux-hisi.git


Hi Ganapatrao,

Thanks for the notification. Let me check this.

Regards,
John





Hi John,

I will take a look at the patches this weekend and give feedback beginning of 
next week. -Will



Thanks,
John


Acked-by: Jiri Olsa 

thanks,
jirka

.


thanks
Ganapat








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.

Re: [PATCH v2 00/11] perf events patches for improved ARM64 support

Hi John,

On Fri, Mar 2, 2018 at 9:35 PM, William Cohen  wrote:
> On 03/02/2018 03:24 AM, John Garry wrote:
>> On 27/02/2018 09:50, Jiri Olsa wrote:
>>> On Sat, Feb 24, 2018 at 12:05:21AM +0800, John Garry wrote:
 This patchset adds support for some perf events features,
 targeted at ARM64, implemented in a generic fashion.

 The two main features are as follows:
 - support for arch/vendor/platform pmu events directory structure
- to support this, topic subdirectory support needs to be dropped
 - support for parsing standard architecture pmu events

 On the back of these, the Cavium ThunderX2, ARM Cortex-A53,
 and HiSilicon hip08 JSONs are relocated/added/updated.

 In addition, there is a patch to drop mutli-mapfile.csv support and
 also a bugfix in jevents.c for an error code value.

 Differences to v1:
 - Address coding issues from Jiri Olsa in adding arch std event
support (https://lkml.org/lkml/2018/2/6/501)
 - add patch to drop topic subdirectory support
 - add patch for bug fix in json_events()
 - add review tags from Jiri Olsa
>>>
>>> can't tell if those json file changes are ok, but for all the code changes:
>>>
>>
>> Hi William, Ganapatrao,
>>
>> Can you check the modifications to the ARM64 JSONs you originally submitted 
>> in the patchset please?>
>> If they are not checked, I'll have to see if the maintainers will accept 
>> without your review. If not, I'll have to drop them.

I am seeing issue(log below) with this patchset on our platfrom.
i have tried using your v2 branch [1]

root@borg-1>perf_acme>> ./perf --version
perf version 4.16.rc1.g087f7ca
root@borg-1>perf_acme>> ./perf stat -e bus_access_rd sleep 1

 Performance counter stats for 'sleep 1':

23,099  bus_access_rd

   1.000708516 seconds time elapsed

root@borg-1>perf_acme>> cd -
/ganapat/perf/linux-hisi/tools/perf
root@borg-1>perf>> ./perf --version
perf version 4.16.rc1.gcb5a74
root@borg-1>perf>> ./perf stat -e bus_access_rd sleep 1

 Performance counter stats for 'sleep 1':

 0  bus_access_rd

   1.000709162 seconds time elapsed

root@borg-1>perf>>


[1] https://github.com/hisilicon/linux-hisi.git

>
> Hi John,
>
> I will take a look at the patches this weekend and give feedback beginning of 
> next week. -Will
>
>>
>> Thanks,
>> John
>>
>>> Acked-by: Jiri Olsa 
>>>
>>> thanks,
>>> jirka
>>>
>>> .

thanks
Ganapat
>>>
>>
>>
>
>
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Re: [PATCH v2 00/11] perf events patches for improved ARM64 support

Hi John,

On Fri, Mar 2, 2018 at 9:35 PM, William Cohen  wrote:
> On 03/02/2018 03:24 AM, John Garry wrote:
>> On 27/02/2018 09:50, Jiri Olsa wrote:
>>> On Sat, Feb 24, 2018 at 12:05:21AM +0800, John Garry wrote:
 This patchset adds support for some perf events features,
 targeted at ARM64, implemented in a generic fashion.

 The two main features are as follows:
 - support for arch/vendor/platform pmu events directory structure
- to support this, topic subdirectory support needs to be dropped
 - support for parsing standard architecture pmu events

 On the back of these, the Cavium ThunderX2, ARM Cortex-A53,
 and HiSilicon hip08 JSONs are relocated/added/updated.

 In addition, there is a patch to drop mutli-mapfile.csv support and
 also a bugfix in jevents.c for an error code value.

 Differences to v1:
 - Address coding issues from Jiri Olsa in adding arch std event
support (https://lkml.org/lkml/2018/2/6/501)
 - add patch to drop topic subdirectory support
 - add patch for bug fix in json_events()
 - add review tags from Jiri Olsa
>>>
>>> can't tell if those json file changes are ok, but for all the code changes:
>>>
>>
>> Hi William, Ganapatrao,
>>
>> Can you check the modifications to the ARM64 JSONs you originally submitted 
>> in the patchset please?>
>> If they are not checked, I'll have to see if the maintainers will accept 
>> without your review. If not, I'll have to drop them.

I am seeing issue(log below) with this patchset on our platfrom.
i have tried using your v2 branch [1]

root@borg-1>perf_acme>> ./perf --version
perf version 4.16.rc1.g087f7ca
root@borg-1>perf_acme>> ./perf stat -e bus_access_rd sleep 1

 Performance counter stats for 'sleep 1':

23,099  bus_access_rd

   1.000708516 seconds time elapsed

root@borg-1>perf_acme>> cd -
/ganapat/perf/linux-hisi/tools/perf
root@borg-1>perf>> ./perf --version
perf version 4.16.rc1.gcb5a74
root@borg-1>perf>> ./perf stat -e bus_access_rd sleep 1

 Performance counter stats for 'sleep 1':

 0  bus_access_rd

   1.000709162 seconds time elapsed

root@borg-1>perf>>


[1] https://github.com/hisilicon/linux-hisi.git

>
> Hi John,
>
> I will take a look at the patches this weekend and give feedback beginning of 
> next week. -Will
>
>>
>> Thanks,
>> John
>>
>>> Acked-by: Jiri Olsa 
>>>
>>> thanks,
>>> jirka
>>>
>>> .

thanks
Ganapat
>>>
>>
>>
>
>
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Re: [PATCH v2 00/11] perf events patches for improved ARM64 support

On 03/02/2018 03:24 AM, John Garry wrote:
> On 27/02/2018 09:50, Jiri Olsa wrote:
>> On Sat, Feb 24, 2018 at 12:05:21AM +0800, John Garry wrote:
>>> This patchset adds support for some perf events features,
>>> targeted at ARM64, implemented in a generic fashion.
>>>
>>> The two main features are as follows:
>>> - support for arch/vendor/platform pmu events directory structure
>>>    - to support this, topic subdirectory support needs to be dropped
>>> - support for parsing standard architecture pmu events
>>>
>>> On the back of these, the Cavium ThunderX2, ARM Cortex-A53,
>>> and HiSilicon hip08 JSONs are relocated/added/updated.
>>>
>>> In addition, there is a patch to drop mutli-mapfile.csv support and
>>> also a bugfix in jevents.c for an error code value.
>>>
>>> Differences to v1:
>>> - Address coding issues from Jiri Olsa in adding arch std event
>>>    support (https://lkml.org/lkml/2018/2/6/501)
>>> - add patch to drop topic subdirectory support
>>> - add patch for bug fix in json_events()
>>> - add review tags from Jiri Olsa
>>
>> can't tell if those json file changes are ok, but for all the code changes:
>>
> 
> Hi William, Ganapatrao,
> 
> Can you check the modifications to the ARM64 JSONs you originally submitted 
> in the patchset please?> 
> If they are not checked, I'll have to see if the maintainers will accept 
> without your review. If not, I'll have to drop them.

Hi John,

I will take a look at the patches this weekend and give feedback beginning of 
next week. -Will

> 
> Thanks,
> John
> 
>> Acked-by: Jiri Olsa 
>>
>> thanks,
>> jirka
>>
>> .
>>
> 
>

Re: [PATCH v2 00/11] perf events patches for improved ARM64 support

On 03/02/2018 03:24 AM, John Garry wrote:
> On 27/02/2018 09:50, Jiri Olsa wrote:
>> On Sat, Feb 24, 2018 at 12:05:21AM +0800, John Garry wrote:
>>> This patchset adds support for some perf events features,
>>> targeted at ARM64, implemented in a generic fashion.
>>>
>>> The two main features are as follows:
>>> - support for arch/vendor/platform pmu events directory structure
>>>    - to support this, topic subdirectory support needs to be dropped
>>> - support for parsing standard architecture pmu events
>>>
>>> On the back of these, the Cavium ThunderX2, ARM Cortex-A53,
>>> and HiSilicon hip08 JSONs are relocated/added/updated.
>>>
>>> In addition, there is a patch to drop mutli-mapfile.csv support and
>>> also a bugfix in jevents.c for an error code value.
>>>
>>> Differences to v1:
>>> - Address coding issues from Jiri Olsa in adding arch std event
>>>    support (https://lkml.org/lkml/2018/2/6/501)
>>> - add patch to drop topic subdirectory support
>>> - add patch for bug fix in json_events()
>>> - add review tags from Jiri Olsa
>>
>> can't tell if those json file changes are ok, but for all the code changes:
>>
> 
> Hi William, Ganapatrao,
> 
> Can you check the modifications to the ARM64 JSONs you originally submitted 
> in the patchset please?> 
> If they are not checked, I'll have to see if the maintainers will accept 
> without your review. If not, I'll have to drop them.

Hi John,

I will take a look at the patches this weekend and give feedback beginning of 
next week. -Will

> 
> Thanks,
> John
> 
>> Acked-by: Jiri Olsa 
>>
>> thanks,
>> jirka
>>
>> .
>>
> 
>

Re: [PATCH v2 00/11] perf events patches for improved ARM64 support

Hi John,

On Fri, Mar 2, 2018 at 1:54 PM, John Garry  wrote:
> On 27/02/2018 09:50, Jiri Olsa wrote:
>>
>> On Sat, Feb 24, 2018 at 12:05:21AM +0800, John Garry wrote:
>>>
>>> This patchset adds support for some perf events features,
>>> targeted at ARM64, implemented in a generic fashion.
>>>
>>> The two main features are as follows:
>>> - support for arch/vendor/platform pmu events directory structure
>>>- to support this, topic subdirectory support needs to be dropped
>>> - support for parsing standard architecture pmu events
>>>
>>> On the back of these, the Cavium ThunderX2, ARM Cortex-A53,
>>> and HiSilicon hip08 JSONs are relocated/added/updated.
>>>
>>> In addition, there is a patch to drop mutli-mapfile.csv support and
>>> also a bugfix in jevents.c for an error code value.
>>>
>>> Differences to v1:
>>> - Address coding issues from Jiri Olsa in adding arch std event
>>>support (https://lkml.org/lkml/2018/2/6/501)
>>> - add patch to drop topic subdirectory support
>>> - add patch for bug fix in json_events()
>>> - add review tags from Jiri Olsa
>>
>>
>> can't tell if those json file changes are ok, but for all the code
>> changes:
>>
>
> Hi William, Ganapatrao,
>
> Can you check the modifications to the ARM64 JSONs you originally submitted
> in the patchset please?

Sorry,  i have missed to notice. I will go through this series and
share my feedback in couple of days.

>
> If they are not checked, I'll have to see if the maintainers will accept
> without your review. If not, I'll have to drop them.
>
> Thanks,
> John
>
>> Acked-by: Jiri Olsa 
>>
>> thanks,
>> jirka
>>
>> .

thanks
Ganapat
>>
>
>
>
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Re: [PATCH v2 00/11] perf events patches for improved ARM64 support

Hi John,

On Fri, Mar 2, 2018 at 1:54 PM, John Garry  wrote:
> On 27/02/2018 09:50, Jiri Olsa wrote:
>>
>> On Sat, Feb 24, 2018 at 12:05:21AM +0800, John Garry wrote:
>>>
>>> This patchset adds support for some perf events features,
>>> targeted at ARM64, implemented in a generic fashion.
>>>
>>> The two main features are as follows:
>>> - support for arch/vendor/platform pmu events directory structure
>>>- to support this, topic subdirectory support needs to be dropped
>>> - support for parsing standard architecture pmu events
>>>
>>> On the back of these, the Cavium ThunderX2, ARM Cortex-A53,
>>> and HiSilicon hip08 JSONs are relocated/added/updated.
>>>
>>> In addition, there is a patch to drop mutli-mapfile.csv support and
>>> also a bugfix in jevents.c for an error code value.
>>>
>>> Differences to v1:
>>> - Address coding issues from Jiri Olsa in adding arch std event
>>>support (https://lkml.org/lkml/2018/2/6/501)
>>> - add patch to drop topic subdirectory support
>>> - add patch for bug fix in json_events()
>>> - add review tags from Jiri Olsa
>>
>>
>> can't tell if those json file changes are ok, but for all the code
>> changes:
>>
>
> Hi William, Ganapatrao,
>
> Can you check the modifications to the ARM64 JSONs you originally submitted
> in the patchset please?

Sorry,  i have missed to notice. I will go through this series and
share my feedback in couple of days.

>
> If they are not checked, I'll have to see if the maintainers will accept
> without your review. If not, I'll have to drop them.
>
> Thanks,
> John
>
>> Acked-by: Jiri Olsa 
>>
>> thanks,
>> jirka
>>
>> .

thanks
Ganapat
>>
>
>
>
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Re: [PATCH v2 00/11] perf events patches for improved ARM64 support


On 27/02/2018 09:50, Jiri Olsa wrote:

On Sat, Feb 24, 2018 at 12:05:21AM +0800, John Garry wrote:

This patchset adds support for some perf events features,
targeted at ARM64, implemented in a generic fashion.

The two main features are as follows:
- support for arch/vendor/platform pmu events directory structure
   - to support this, topic subdirectory support needs to be dropped
- support for parsing standard architecture pmu events

On the back of these, the Cavium ThunderX2, ARM Cortex-A53,
and HiSilicon hip08 JSONs are relocated/added/updated.

In addition, there is a patch to drop mutli-mapfile.csv support and
also a bugfix in jevents.c for an error code value.

Differences to v1:
- Address coding issues from Jiri Olsa in adding arch std event
   support (https://lkml.org/lkml/2018/2/6/501)
- add patch to drop topic subdirectory support
- add patch for bug fix in json_events()
- add review tags from Jiri Olsa


can't tell if those json file changes are ok, but for all the code changes:



Hi William, Ganapatrao,

Can you check the modifications to the ARM64 JSONs you originally 
submitted in the patchset please?


If they are not checked, I'll have to see if the maintainers will accept 
without your review. If not, I'll have to drop them.


Thanks,
John


Acked-by: Jiri Olsa 

thanks,
jirka

.

Re: [PATCH v2 00/11] perf events patches for improved ARM64 support