Re: [RESEND PATCH 4/4] EDAC: add support for reduced-width Armada-XP SDRAM

2017-08-13 Thread Chris Packham
On 11/08/17 21:14, Borislav Petkov wrote: > On Mon, Aug 07, 2017 at 01:46:41PM +1200, Chris Packham wrote: >> Some integrated Armada XP SoCs use a reduced pin count so the width of >> the SDRAM interface is smaller than the traditional discrete SoCs. This >> means that the definition of "full" and

Re: [RESEND PATCH 4/4] EDAC: add support for reduced-width Armada-XP SDRAM

2017-08-13 Thread Chris Packham
On 11/08/17 21:14, Borislav Petkov wrote: > On Mon, Aug 07, 2017 at 01:46:41PM +1200, Chris Packham wrote: >> Some integrated Armada XP SoCs use a reduced pin count so the width of >> the SDRAM interface is smaller than the traditional discrete SoCs. This >> means that the definition of "full" and

Re: [RESEND PATCH 4/4] EDAC: add support for reduced-width Armada-XP SDRAM

2017-08-11 Thread Borislav Petkov
On Mon, Aug 07, 2017 at 01:46:41PM +1200, Chris Packham wrote: > Some integrated Armada XP SoCs use a reduced pin count so the width of > the SDRAM interface is smaller than the traditional discrete SoCs. This > means that the definition of "full" and "half" width is further reduced. > >

Re: [RESEND PATCH 4/4] EDAC: add support for reduced-width Armada-XP SDRAM

2017-08-11 Thread Borislav Petkov
On Mon, Aug 07, 2017 at 01:46:41PM +1200, Chris Packham wrote: > Some integrated Armada XP SoCs use a reduced pin count so the width of > the SDRAM interface is smaller than the traditional discrete SoCs. This > means that the definition of "full" and "half" width is further reduced. > >

[RESEND PATCH 4/4] EDAC: add support for reduced-width Armada-XP SDRAM

2017-08-06 Thread Chris Packham
Some integrated Armada XP SoCs use a reduced pin count so the width of the SDRAM interface is smaller than the traditional discrete SoCs. This means that the definition of "full" and "half" width is further reduced. Signed-off-by: Chris Packham ---

[RESEND PATCH 4/4] EDAC: add support for reduced-width Armada-XP SDRAM

2017-08-06 Thread Chris Packham
Some integrated Armada XP SoCs use a reduced pin count so the width of the SDRAM interface is smaller than the traditional discrete SoCs. This means that the definition of "full" and "half" width is further reduced. Signed-off-by: Chris Packham --- drivers/edac/armada_xp_edac.c | 3 +++ 1 file