[PATCH 0/2] arm64: perf: Add L2 cache events for ARMv8 PMuv3 and A53

Hi, While investigating why there were no L2 cache events generated for a Cortex A53-like PMU, it turned out that none of the L2 cache events were mapped. This is also the case for ARMv8 PMUv3, which seems a little odd considering they are defined. Thanks! Florian Fainelli (2): arm64: perf:

[PATCH 0/2] arm64: perf: Add L2 cache events for ARMv8 PMuv3 and A53

Hi, While investigating why there were no L2 cache events generated for a Cortex A53-like PMU, it turned out that none of the L2 cache events were mapped. This is also the case for ARMv8 PMUv3, which seems a little odd considering they are defined. Thanks! Florian Fainelli (2): arm64: perf: