Hi Thomas,
On Fri, Jun 28, 2013 at 04:02:23PM +0200, Thomas Gleixner wrote:
> On Fri, 28 Jun 2013, 张猛 wrote:
> > > The A10 manual from http://free-electrons.com/~maxime/pub/datasheet/
> > > does not seem to contain any details about what bad things may happen
> > > if we try to read CNT64_LO_REG
On Fri, Jun 28, 2013 at 01:29:12PM +0300, Siarhei Siamashka wrote:
> > NOTICE: This e-mail and any included attachments are intended only
> > for the sole use of named and intended recipient (s) only. If you
> > are the named and intended recipient, please note that the
> > information contained
On Fri, 28 Jun 2013, 张猛 wrote:
> > The A10 manual from http://free-electrons.com/~maxime/pub/datasheet/
> > does not seem to contain any details about what bad things may happen
> > if we try to read CNT64_LO_REG while latching is still in progress and
> > CNT64_RL_EN bit in CNT64_CTRL_REG has not
On Fri, 28 Jun 2013 12:26:10 +0200 (CEST)
Thomas Gleixner wrote:
> On Fri, 28 Jun 2013, Siarhei Siamashka wrote:
> > On Fri, 28 Jun 2013 09:43:37 +0800
> > 张猛 wrote:
> >
> > > > The A10 manual from http://free-electrons.com/~maxime/pub/datasheet/
> > > > does not seem to contain any details
Hi Hans,
On Thu, Jun 27, 2013 at 08:13:56PM +0200, Hans de Goede wrote:
> >Siarhei however notes that even higher-end SoCs like the exynos5 have
> >similar performances with that regard. So I'm not sure we can do
> >something about it, except what is suggested in the above mail, which
> >looks
On Fri, 28 Jun 2013, Siarhei Siamashka wrote:
> On Fri, 28 Jun 2013 09:43:37 +0800
> 张猛 wrote:
>
> > > The A10 manual from http://free-electrons.com/~maxime/pub/datasheet/
> > > does not seem to contain any details about what bad things may happen
> > > if we try to read CNT64_LO_REG while
Hi,
On 06/27/2013 10:26 PM, Siarhei Siamashka wrote:
On Thu, 27 Jun 2013 18:54:36 +0200
Maxime Ripard wrote:
On Thu, Jun 27, 2013 at 11:54:11AM +0200, Hans de Goede wrote:
I notice that unlike the sunxi-3.4 code you don't do any locking,
so how do you stop 2 clocksource calls from racing
Hi,
On 06/27/2013 10:26 PM, Siarhei Siamashka wrote:
On Thu, 27 Jun 2013 18:54:36 +0200
Maxime Ripard maxime.rip...@free-electrons.com wrote:
On Thu, Jun 27, 2013 at 11:54:11AM +0200, Hans de Goede wrote:
I notice that unlike the sunxi-3.4 code you don't do any locking,
so how do you stop 2
On Fri, 28 Jun 2013, Siarhei Siamashka wrote:
On Fri, 28 Jun 2013 09:43:37 +0800
张猛 ke...@allwinnertech.com wrote:
The A10 manual from http://free-electrons.com/~maxime/pub/datasheet/
does not seem to contain any details about what bad things may happen
if we try to read CNT64_LO_REG
Hi Hans,
On Thu, Jun 27, 2013 at 08:13:56PM +0200, Hans de Goede wrote:
Siarhei however notes that even higher-end SoCs like the exynos5 have
similar performances with that regard. So I'm not sure we can do
something about it, except what is suggested in the above mail, which
looks rather
On Fri, 28 Jun 2013 12:26:10 +0200 (CEST)
Thomas Gleixner t...@linutronix.de wrote:
On Fri, 28 Jun 2013, Siarhei Siamashka wrote:
On Fri, 28 Jun 2013 09:43:37 +0800
张猛 ke...@allwinnertech.com wrote:
The A10 manual from http://free-electrons.com/~maxime/pub/datasheet/
does not seem
On Fri, 28 Jun 2013, 张猛 wrote:
The A10 manual from http://free-electrons.com/~maxime/pub/datasheet/
does not seem to contain any details about what bad things may happen
if we try to read CNT64_LO_REG while latching is still in progress and
CNT64_RL_EN bit in CNT64_CTRL_REG has not changed
On Fri, Jun 28, 2013 at 01:29:12PM +0300, Siarhei Siamashka wrote:
NOTICE: This e-mail and any included attachments are intended only
for the sole use of named and intended recipient (s) only. If you
are the named and intended recipient, please note that the
information contained in this
Hi Thomas,
On Fri, Jun 28, 2013 at 04:02:23PM +0200, Thomas Gleixner wrote:
On Fri, 28 Jun 2013, 张猛 wrote:
The A10 manual from http://free-electrons.com/~maxime/pub/datasheet/
does not seem to contain any details about what bad things may happen
if we try to read CNT64_LO_REG while
On Thu, 27 Jun 2013 18:54:36 +0200
Maxime Ripard wrote:
> On Thu, Jun 27, 2013 at 11:54:11AM +0200, Hans de Goede wrote:
> > I notice that unlike the sunxi-3.4 code you don't do any locking,
> > so how do you stop 2 clocksource calls from racing (and thus
> > getting a possible wrong value
Hi,
On 06/27/2013 06:54 PM, Maxime Ripard wrote:
On Thu, Jun 27, 2013 at 11:54:11AM +0200, Hans de Goede wrote:
Hi,
On 06/27/2013 11:43 AM, Maxime Ripard wrote:
On Thu, Jun 27, 2013 at 11:27:02AM +0200, Hans de Goede wrote:
Hi,
On 06/26/2013 11:16 PM, Maxime Ripard wrote:
Hi everyone,
On Thu, Jun 27, 2013 at 11:54:11AM +0200, Hans de Goede wrote:
> Hi,
>
> On 06/27/2013 11:43 AM, Maxime Ripard wrote:
> >On Thu, Jun 27, 2013 at 11:27:02AM +0200, Hans de Goede wrote:
> >>Hi,
> >>
> >>On 06/26/2013 11:16 PM, Maxime Ripard wrote:
> >>>Hi everyone,
> >>>
> >>
> >>
> >>
> >>>It also
Hi,
On 06/27/2013 11:43 AM, Maxime Ripard wrote:
On Thu, Jun 27, 2013 at 11:27:02AM +0200, Hans de Goede wrote:
Hi,
On 06/26/2013 11:16 PM, Maxime Ripard wrote:
Hi everyone,
It also finally adds a clocksource from the free running counter found in the
A10/A13 SoCs.
Hmm, have you
On Thu, Jun 27, 2013 at 11:27:02AM +0200, Hans de Goede wrote:
> Hi,
>
> On 06/26/2013 11:16 PM, Maxime Ripard wrote:
> >Hi everyone,
> >
>
>
>
> >It also finally adds a clocksource from the free running counter found in the
> >A10/A13 SoCs.
>
> Hmm, have you benchmarked this? There have been
Hi,
On 06/26/2013 11:16 PM, Maxime Ripard wrote:
Hi everyone,
It also finally adds a clocksource from the free running counter found in the
A10/A13 SoCs.
Hmm, have you benchmarked this? There have been reports from linux-sunxi kernel
users (xbmc project) that the waiting for the latch
Hi,
On 06/26/2013 11:16 PM, Maxime Ripard wrote:
Hi everyone,
snip
It also finally adds a clocksource from the free running counter found in the
A10/A13 SoCs.
Hmm, have you benchmarked this? There have been reports from linux-sunxi kernel
users (xbmc project) that the waiting for the
On Thu, Jun 27, 2013 at 11:27:02AM +0200, Hans de Goede wrote:
Hi,
On 06/26/2013 11:16 PM, Maxime Ripard wrote:
Hi everyone,
snip
It also finally adds a clocksource from the free running counter found in the
A10/A13 SoCs.
Hmm, have you benchmarked this? There have been reports
Hi,
On 06/27/2013 11:43 AM, Maxime Ripard wrote:
On Thu, Jun 27, 2013 at 11:27:02AM +0200, Hans de Goede wrote:
Hi,
On 06/26/2013 11:16 PM, Maxime Ripard wrote:
Hi everyone,
snip
It also finally adds a clocksource from the free running counter found in the
A10/A13 SoCs.
Hmm, have you
On Thu, Jun 27, 2013 at 11:54:11AM +0200, Hans de Goede wrote:
Hi,
On 06/27/2013 11:43 AM, Maxime Ripard wrote:
On Thu, Jun 27, 2013 at 11:27:02AM +0200, Hans de Goede wrote:
Hi,
On 06/26/2013 11:16 PM, Maxime Ripard wrote:
Hi everyone,
snip
It also finally adds a clocksource
Hi,
On 06/27/2013 06:54 PM, Maxime Ripard wrote:
On Thu, Jun 27, 2013 at 11:54:11AM +0200, Hans de Goede wrote:
Hi,
On 06/27/2013 11:43 AM, Maxime Ripard wrote:
On Thu, Jun 27, 2013 at 11:27:02AM +0200, Hans de Goede wrote:
Hi,
On 06/26/2013 11:16 PM, Maxime Ripard wrote:
Hi everyone,
On Thu, 27 Jun 2013 18:54:36 +0200
Maxime Ripard maxime.rip...@free-electrons.com wrote:
On Thu, Jun 27, 2013 at 11:54:11AM +0200, Hans de Goede wrote:
I notice that unlike the sunxi-3.4 code you don't do any locking,
so how do you stop 2 clocksource calls from racing (and thus
getting a
Hi everyone,
The first timer code we merged when adding support for the A13 some time back
was mostly a clean up from the source drop we had, without any documentation.
This happened to work, but the code merged in turned out to be far from
perfect, and had several flaws.
This patchset hopefully
Hi everyone,
The first timer code we merged when adding support for the A13 some time back
was mostly a clean up from the source drop we had, without any documentation.
This happened to work, but the code merged in turned out to be far from
perfect, and had several flaws.
This patchset hopefully
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