On Mon, 25 Jan 2016, Peter Tyser wrote:
>
> On Mon, 2016-01-25 at 12:44 +, Lee Jones wrote:
> > On Sat, 23 Jan 2016, Antoine Tenart wrote:
> >
> > > The GPIO base address is read from the GPIOBASE register. The first
> > > bit must be cleared as it can be hardwired to 1 to represent the i/o
On Mon, 25 Jan 2016, Peter Tyser wrote:
>
> On Mon, 2016-01-25 at 12:44 +, Lee Jones wrote:
> > On Sat, 23 Jan 2016, Antoine Tenart wrote:
> >
> > > The GPIO base address is read from the GPIOBASE register. The first
> > > bit must be cleared as it can be hardwired to 1 to represent the i/o
On Mon, 2016-01-25 at 12:44 +, Lee Jones wrote:
> On Sat, 23 Jan 2016, Antoine Tenart wrote:
>
> > The GPIO base address is read from the GPIOBASE register. The first
> > bit must be cleared as it can be hardwired to 1 to represent the i/o
> > space. Other bits are either containing the base
On Sat, 23 Jan 2016, Antoine Tenart wrote:
> The GPIO base address is read from the GPIOBASE register. The first
> bit must be cleared as it can be hardwired to 1 to represent the i/o
> space. Other bits are either containing the base address of are
> reserved. They should not be cleared as all
On Sat, 23 Jan 2016, Antoine Tenart wrote:
> The GPIO base address is read from the GPIOBASE register. The first
> bit must be cleared as it can be hardwired to 1 to represent the i/o
> space. Other bits are either containing the base address of are
> reserved. They should not be cleared as all
On Mon, 2016-01-25 at 12:44 +, Lee Jones wrote:
> On Sat, 23 Jan 2016, Antoine Tenart wrote:
>
> > The GPIO base address is read from the GPIOBASE register. The first
> > bit must be cleared as it can be hardwired to 1 to represent the i/o
> > space. Other bits are either containing the base
The GPIO base address is read from the GPIOBASE register. The first
bit must be cleared as it can be hardwired to 1 to represent the i/o
space. Other bits are either containing the base address of are
reserved. They should not be cleared as all the chipsets do not have
the same reserved bits.
The GPIO base address is read from the GPIOBASE register. The first
bit must be cleared as it can be hardwired to 1 to represent the i/o
space. Other bits are either containing the base address of are
reserved. They should not be cleared as all the chipsets do not have
the same reserved bits.
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