Re: [PATCH tip/locking/core v4 1/6] powerpc: atomic: Make *xchg and *cmpxchg a full barrier

2015-10-26 Thread Boqun Feng
On Mon, Oct 26, 2015 at 02:20:21PM +1100, Paul Mackerras wrote: > On Wed, Oct 21, 2015 at 10:18:33AM +0200, Peter Zijlstra wrote: > > On Tue, Oct 20, 2015 at 02:28:35PM -0700, Paul E. McKenney wrote: > > > I am not seeing a sync there, but I really have to defer to the > > > maintainers on this one

Re: [PATCH tip/locking/core v4 1/6] powerpc: atomic: Make *xchg and *cmpxchg a full barrier

2015-10-26 Thread Boqun Feng
On Mon, Oct 26, 2015 at 11:20:01AM +0900, Michael Ellerman wrote: > > Sorry guys, these threads are so long I tend not to read them very actively :} > > Looking at the system call path, the straight line path does not include any > barriers. I can't see any hidden in macros either. > > We also h

Re: [PATCH tip/locking/core v4 1/6] powerpc: atomic: Make *xchg and *cmpxchg a full barrier

2015-10-25 Thread Paul Mackerras
On Wed, Oct 21, 2015 at 10:18:33AM +0200, Peter Zijlstra wrote: > On Tue, Oct 20, 2015 at 02:28:35PM -0700, Paul E. McKenney wrote: > > I am not seeing a sync there, but I really have to defer to the > > maintainers on this one. I could easily have missed one. > > So x86 implies a full barrier fo

Re: [PATCH tip/locking/core v4 1/6] powerpc: atomic: Make *xchg and *cmpxchg a full barrier

2015-10-25 Thread Michael Ellerman
On Wed, 2015-10-21 at 12:36 -0700, Paul E. McKenney wrote: > On Wed, Oct 21, 2015 at 10:18:33AM +0200, Peter Zijlstra wrote: > > On Tue, Oct 20, 2015 at 02:28:35PM -0700, Paul E. McKenney wrote: > > > I am not seeing a sync there, but I really have to defer to the > > > maintainers on this one.

Re: [PATCH tip/locking/core v4 1/6] powerpc: atomic: Make *xchg and *cmpxchg a full barrier

2015-10-25 Thread Boqun Feng
On Wed, Oct 21, 2015 at 12:36:38PM -0700, Paul E. McKenney wrote: > On Wed, Oct 21, 2015 at 10:18:33AM +0200, Peter Zijlstra wrote: > > On Tue, Oct 20, 2015 at 02:28:35PM -0700, Paul E. McKenney wrote: > > > I am not seeing a sync there, but I really have to defer to the > > > maintainers on this o

Re: [PATCH tip/locking/core v4 1/6] powerpc: atomic: Make *xchg and *cmpxchg a full barrier

2015-10-25 Thread Boqun Feng
On Sat, Oct 24, 2015 at 07:53:56PM +0800, Boqun Feng wrote: > On Sat, Oct 24, 2015 at 12:26:27PM +0200, Peter Zijlstra wrote: > > > > Right, futexes are a pain; and I think we all agreed we didn't want to > > go rely on implementation details unless we absolutely _have_ to. > > > > Agreed. > >

Re: [PATCH tip/locking/core v4 1/6] powerpc: atomic: Make *xchg and *cmpxchg a full barrier

2015-10-24 Thread Boqun Feng
On Sat, Oct 24, 2015 at 12:26:27PM +0200, Peter Zijlstra wrote: > On Thu, Oct 22, 2015 at 08:07:16PM +0800, Boqun Feng wrote: > > On Wed, Oct 21, 2015 at 09:48:25PM +0200, Peter Zijlstra wrote: > > > On Wed, Oct 21, 2015 at 12:35:23PM -0700, Paul E. McKenney wrote: > > > > > > > > I ask this becaus

Re: [PATCH tip/locking/core v4 1/6] powerpc: atomic: Make *xchg and *cmpxchg a full barrier

2015-10-24 Thread Peter Zijlstra
On Thu, Oct 22, 2015 at 08:07:16PM +0800, Boqun Feng wrote: > On Wed, Oct 21, 2015 at 09:48:25PM +0200, Peter Zijlstra wrote: > > On Wed, Oct 21, 2015 at 12:35:23PM -0700, Paul E. McKenney wrote: > > > > > > > I ask this because I recall Peter once bought up a discussion: > > > > > > > > > > > > >

Re: [PATCH tip/locking/core v4 1/6] powerpc: atomic: Make *xchg and *cmpxchg a full barrier

2015-10-22 Thread Boqun Feng
On Wed, Oct 21, 2015 at 09:48:25PM +0200, Peter Zijlstra wrote: > On Wed, Oct 21, 2015 at 12:35:23PM -0700, Paul E. McKenney wrote: > > > > > > I ask this because I recall Peter once bought up a discussion: > > > > > > > > > > > > https://lkml.org/lkml/2015/8/26/596 > > > > So a full barrier on o

Re: [PATCH tip/locking/core v4 1/6] powerpc: atomic: Make *xchg and *cmpxchg a full barrier

2015-10-21 Thread Peter Zijlstra
On Wed, Oct 21, 2015 at 12:35:23PM -0700, Paul E. McKenney wrote: > > > > > I ask this because I recall Peter once bought up a discussion: > > > > > > > > > > https://lkml.org/lkml/2015/8/26/596 > > So a full barrier on one side of these operations is enough, I think. > > IOW, there is no need to

Re: [PATCH tip/locking/core v4 1/6] powerpc: atomic: Make *xchg and *cmpxchg a full barrier

2015-10-21 Thread Paul E. McKenney
On Wed, Oct 21, 2015 at 10:18:33AM +0200, Peter Zijlstra wrote: > On Tue, Oct 20, 2015 at 02:28:35PM -0700, Paul E. McKenney wrote: > > I am not seeing a sync there, but I really have to defer to the > > maintainers on this one. I could easily have missed one. > > So x86 implies a full barrier fo

Re: [PATCH tip/locking/core v4 1/6] powerpc: atomic: Make *xchg and *cmpxchg a full barrier

2015-10-21 Thread Paul E. McKenney
On Wed, Oct 21, 2015 at 04:45:03PM +0800, Boqun Feng wrote: > On Tue, Oct 20, 2015 at 02:28:35PM -0700, Paul E. McKenney wrote: > > On Tue, Oct 20, 2015 at 11:21:47AM +0200, Peter Zijlstra wrote: > > > On Tue, Oct 20, 2015 at 03:15:32PM +0800, Boqun Feng wrote: > > > > On Wed, Oct 14, 2015 at 01:19

Re: [PATCH tip/locking/core v4 1/6] powerpc: atomic: Make *xchg and *cmpxchg a full barrier

2015-10-21 Thread Boqun Feng
On Tue, Oct 20, 2015 at 02:28:35PM -0700, Paul E. McKenney wrote: > On Tue, Oct 20, 2015 at 11:21:47AM +0200, Peter Zijlstra wrote: > > On Tue, Oct 20, 2015 at 03:15:32PM +0800, Boqun Feng wrote: > > > On Wed, Oct 14, 2015 at 01:19:17PM -0700, Paul E. McKenney wrote: > > > > > > > > Am I missing s

Re: [PATCH tip/locking/core v4 1/6] powerpc: atomic: Make *xchg and *cmpxchg a full barrier

2015-10-21 Thread Peter Zijlstra
On Tue, Oct 20, 2015 at 02:28:35PM -0700, Paul E. McKenney wrote: > I am not seeing a sync there, but I really have to defer to the > maintainers on this one. I could easily have missed one. So x86 implies a full barrier for everything that changes the CPL; and some form of implied ordering seems

Re: [PATCH tip/locking/core v4 1/6] powerpc: atomic: Make *xchg and *cmpxchg a full barrier

2015-10-20 Thread Paul E. McKenney
On Tue, Oct 20, 2015 at 11:21:47AM +0200, Peter Zijlstra wrote: > On Tue, Oct 20, 2015 at 03:15:32PM +0800, Boqun Feng wrote: > > On Wed, Oct 14, 2015 at 01:19:17PM -0700, Paul E. McKenney wrote: > > > > > > Am I missing something here? If not, it seems to me that you need > > > the leading lwsyn

Re: [PATCH tip/locking/core v4 1/6] powerpc: atomic: Make *xchg and *cmpxchg a full barrier

2015-10-20 Thread Peter Zijlstra
On Tue, Oct 20, 2015 at 03:15:32PM +0800, Boqun Feng wrote: > On Wed, Oct 14, 2015 at 01:19:17PM -0700, Paul E. McKenney wrote: > > > > Am I missing something here? If not, it seems to me that you need > > the leading lwsync to instead be a sync. > > > > Of course, if I am not missing something,

Re: [PATCH tip/locking/core v4 1/6] powerpc: atomic: Make *xchg and *cmpxchg a full barrier

2015-10-20 Thread Boqun Feng
On Wed, Oct 14, 2015 at 01:19:17PM -0700, Paul E. McKenney wrote: > > Am I missing something here? If not, it seems to me that you need > the leading lwsync to instead be a sync. > > Of course, if I am not missing something, then this applies also to the > value-returning RMW atomic operations t

Re: [PATCH tip/locking/core v4 1/6] powerpc: atomic: Make *xchg and *cmpxchg a full barrier

2015-10-18 Thread Boqun Feng
On Thu, Oct 15, 2015 at 09:30:40AM -0700, Paul E. McKenney wrote: > On Thu, Oct 15, 2015 at 12:48:03PM +0800, Boqun Feng wrote: > > On Wed, Oct 14, 2015 at 08:07:05PM -0700, Paul E. McKenney wrote: [snip] > > > > > Why not try creating a longer litmus test that requires P0's write to > > > "a" to

Re: [PATCH tip/locking/core v4 1/6] powerpc: atomic: Make *xchg and *cmpxchg a full barrier

2015-10-15 Thread Paul E. McKenney
On Thu, Oct 15, 2015 at 12:48:03PM +0800, Boqun Feng wrote: > On Wed, Oct 14, 2015 at 08:07:05PM -0700, Paul E. McKenney wrote: > > On Thu, Oct 15, 2015 at 08:53:21AM +0800, Boqun Feng wrote: > [snip] > > > > > > I'm afraid more than that, the above litmus also shows that > > > > > > CPU 0

Re: [PATCH tip/locking/core v4 1/6] powerpc: atomic: Make *xchg and *cmpxchg a full barrier

2015-10-15 Thread Paul E. McKenney
On Thu, Oct 15, 2015 at 03:50:44PM +0100, Will Deacon wrote: > On Thu, Oct 15, 2015 at 11:35:10AM +0100, Will Deacon wrote: > > Dammit guys, it's never simple is it? > > I re-read this and it's even more confusing than I first thought. > > > On Wed, Oct 14, 2015 at 02:44:53PM -0700, Paul E. McKen

Re: [PATCH tip/locking/core v4 1/6] powerpc: atomic: Make *xchg and *cmpxchg a full barrier

2015-10-15 Thread Paul E. McKenney
On Thu, Oct 15, 2015 at 10:49:23PM +0800, Boqun Feng wrote: > On Wed, Oct 14, 2015 at 01:19:17PM -0700, Paul E. McKenney wrote: > > On Wed, Oct 14, 2015 at 11:55:56PM +0800, Boqun Feng wrote: > > > According to memory-barriers.txt, xchg, cmpxchg and their atomic{,64}_ > > > versions all need to imp

Re: [PATCH tip/locking/core v4 1/6] powerpc: atomic: Make *xchg and *cmpxchg a full barrier

2015-10-15 Thread Paul E. McKenney
On Thu, Oct 15, 2015 at 11:35:44AM +0100, Will Deacon wrote: > Dammit guys, it's never simple is it? > > On Wed, Oct 14, 2015 at 02:44:53PM -0700, Paul E. McKenney wrote: > > To that end, the herd tool can make a diagram of what it thought > > happened, and I have attached it. I used this diagram

Re: [PATCH tip/locking/core v4 1/6] powerpc: atomic: Make *xchg and *cmpxchg a full barrier

2015-10-15 Thread Will Deacon
On Thu, Oct 15, 2015 at 11:35:10AM +0100, Will Deacon wrote: > Dammit guys, it's never simple is it? I re-read this and it's even more confusing than I first thought. > On Wed, Oct 14, 2015 at 02:44:53PM -0700, Paul E. McKenney wrote: > > To that end, the herd tool can make a diagram of what it t

Re: [PATCH tip/locking/core v4 1/6] powerpc: atomic: Make *xchg and *cmpxchg a full barrier

2015-10-15 Thread Boqun Feng
On Wed, Oct 14, 2015 at 01:19:17PM -0700, Paul E. McKenney wrote: > On Wed, Oct 14, 2015 at 11:55:56PM +0800, Boqun Feng wrote: > > According to memory-barriers.txt, xchg, cmpxchg and their atomic{,64}_ > > versions all need to imply a full barrier, however they are now just > > RELEASE+ACQUIRE, wh

Re: [PATCH tip/locking/core v4 1/6] powerpc: atomic: Make *xchg and *cmpxchg a full barrier

2015-10-15 Thread Boqun Feng
On Thu, Oct 15, 2015 at 11:35:44AM +0100, Will Deacon wrote: > > So arm64 is ok. Doesn't lwsync order store->store observability for PPC? > I did some litmus and put the result here. My understanding might be wrong, and I think Paul can explain the lwsync and store->store order better ;-) When

Re: [PATCH tip/locking/core v4 1/6] powerpc: atomic: Make *xchg and *cmpxchg a full barrier

2015-10-15 Thread Will Deacon
Dammit guys, it's never simple is it? On Wed, Oct 14, 2015 at 02:44:53PM -0700, Paul E. McKenney wrote: > To that end, the herd tool can make a diagram of what it thought > happened, and I have attached it. I used this diagram to try and force > this scenario at https://www.cl.cam.ac.uk/~pes20/pp

Re: [PATCH tip/locking/core v4 1/6] powerpc: atomic: Make *xchg and *cmpxchg a full barrier

2015-10-14 Thread Boqun Feng
On Wed, Oct 14, 2015 at 08:07:05PM -0700, Paul E. McKenney wrote: > On Thu, Oct 15, 2015 at 08:53:21AM +0800, Boqun Feng wrote: [snip] > > > > I'm afraid more than that, the above litmus also shows that > > > > CPU 0 CPU 1 > > -

Re: [PATCH tip/locking/core v4 1/6] powerpc: atomic: Make *xchg and *cmpxchg a full barrier

2015-10-14 Thread Paul E. McKenney
On Thu, Oct 15, 2015 at 11:11:01AM +0800, Boqun Feng wrote: > Hi Paul, > > On Thu, Oct 15, 2015 at 08:53:21AM +0800, Boqun Feng wrote: > > On Wed, Oct 14, 2015 at 02:44:53PM -0700, Paul E. McKenney wrote: > [snip] > > > To that end, the herd tool can make a diagram of what it thought > > > happene

Re: [PATCH tip/locking/core v4 1/6] powerpc: atomic: Make *xchg and *cmpxchg a full barrier

2015-10-14 Thread Boqun Feng
Hi Paul, On Thu, Oct 15, 2015 at 08:53:21AM +0800, Boqun Feng wrote: > On Wed, Oct 14, 2015 at 02:44:53PM -0700, Paul E. McKenney wrote: [snip] > > To that end, the herd tool can make a diagram of what it thought > > happened, and I have attached it. I used this diagram to try and force > > this

Re: [PATCH tip/locking/core v4 1/6] powerpc: atomic: Make *xchg and *cmpxchg a full barrier

2015-10-14 Thread Paul E. McKenney
On Thu, Oct 15, 2015 at 09:22:26AM +0800, Boqun Feng wrote: > On Thu, Oct 15, 2015 at 08:53:21AM +0800, Boqun Feng wrote: > > On Wed, Oct 14, 2015 at 02:44:53PM -0700, Paul E. McKenney wrote: > > > On Wed, Oct 14, 2015 at 11:04:19PM +0200, Peter Zijlstra wrote: > > > > On Wed, Oct 14, 2015 at 01:19

Re: [PATCH tip/locking/core v4 1/6] powerpc: atomic: Make *xchg and *cmpxchg a full barrier

2015-10-14 Thread Paul E. McKenney
On Thu, Oct 15, 2015 at 08:53:21AM +0800, Boqun Feng wrote: > On Wed, Oct 14, 2015 at 02:44:53PM -0700, Paul E. McKenney wrote: > > On Wed, Oct 14, 2015 at 11:04:19PM +0200, Peter Zijlstra wrote: > > > On Wed, Oct 14, 2015 at 01:19:17PM -0700, Paul E. McKenney wrote: > > > > Suppose we have somethi

Re: [PATCH tip/locking/core v4 1/6] powerpc: atomic: Make *xchg and *cmpxchg a full barrier

2015-10-14 Thread Boqun Feng
On Thu, Oct 15, 2015 at 08:53:21AM +0800, Boqun Feng wrote: > On Wed, Oct 14, 2015 at 02:44:53PM -0700, Paul E. McKenney wrote: > > On Wed, Oct 14, 2015 at 11:04:19PM +0200, Peter Zijlstra wrote: > > > On Wed, Oct 14, 2015 at 01:19:17PM -0700, Paul E. McKenney wrote: > > > > Suppose we have somethi

Re: [PATCH tip/locking/core v4 1/6] powerpc: atomic: Make *xchg and *cmpxchg a full barrier

2015-10-14 Thread Boqun Feng
On Wed, Oct 14, 2015 at 02:44:53PM -0700, Paul E. McKenney wrote: > On Wed, Oct 14, 2015 at 11:04:19PM +0200, Peter Zijlstra wrote: > > On Wed, Oct 14, 2015 at 01:19:17PM -0700, Paul E. McKenney wrote: > > > Suppose we have something like the following, where "a" and "x" are both > > > initially ze

Re: [PATCH tip/locking/core v4 1/6] powerpc: atomic: Make *xchg and *cmpxchg a full barrier

2015-10-14 Thread Paul E. McKenney
On Wed, Oct 14, 2015 at 11:04:19PM +0200, Peter Zijlstra wrote: > On Wed, Oct 14, 2015 at 01:19:17PM -0700, Paul E. McKenney wrote: > > Suppose we have something like the following, where "a" and "x" are both > > initially zero: > > > > CPU 0 CPU 1 > > -

Re: [PATCH tip/locking/core v4 1/6] powerpc: atomic: Make *xchg and *cmpxchg a full barrier

2015-10-14 Thread Peter Zijlstra
On Wed, Oct 14, 2015 at 01:19:17PM -0700, Paul E. McKenney wrote: > Suppose we have something like the following, where "a" and "x" are both > initially zero: > > CPU 0 CPU 1 > - - > > WRITE_ONCE(x, 1); WR

Re: [PATCH tip/locking/core v4 1/6] powerpc: atomic: Make *xchg and *cmpxchg a full barrier

2015-10-14 Thread Paul E. McKenney
On Wed, Oct 14, 2015 at 11:55:56PM +0800, Boqun Feng wrote: > According to memory-barriers.txt, xchg, cmpxchg and their atomic{,64}_ > versions all need to imply a full barrier, however they are now just > RELEASE+ACQUIRE, which is not a full barrier. > > So replace PPC_RELEASE_BARRIER and PPC_ACQ

[PATCH tip/locking/core v4 1/6] powerpc: atomic: Make *xchg and *cmpxchg a full barrier

2015-10-14 Thread Boqun Feng
According to memory-barriers.txt, xchg, cmpxchg and their atomic{,64}_ versions all need to imply a full barrier, however they are now just RELEASE+ACQUIRE, which is not a full barrier. So replace PPC_RELEASE_BARRIER and PPC_ACQUIRE_BARRIER with PPC_ATOMIC_ENTRY_BARRIER and PPC_ATOMIC_EXIT_BARRIER