On 07/03/18 21:36, Saravana Kannan wrote:
On 03/07/2018 06:59 AM, Suzuki K Poulose wrote:
Hi Saravana,
Sorry for the late response, I was out on vacation.
On 05/03/18 22:10, Saravana Kannan wrote:
On 03/05/2018 02:59 AM, Mark Rutland wrote:
On Fri, Mar 02, 2018 at 11:19:56AM -0800,
On 07/03/18 21:36, Saravana Kannan wrote:
On 03/07/2018 06:59 AM, Suzuki K Poulose wrote:
Hi Saravana,
Sorry for the late response, I was out on vacation.
On 05/03/18 22:10, Saravana Kannan wrote:
On 03/05/2018 02:59 AM, Mark Rutland wrote:
On Fri, Mar 02, 2018 at 11:19:56AM -0800,
On Fri, Mar 09, 2018 at 02:49:00PM -0800, Saravana Kannan wrote:
> > > > Looking at the code, I didn't see any specific handling of cluster
> > > > power collapse. AFAIK, the HW counters do not retain config (what event
> > > > they are counting) or value (the current count) across power collapse.
On Fri, Mar 09, 2018 at 02:49:00PM -0800, Saravana Kannan wrote:
> > > > Looking at the code, I didn't see any specific handling of cluster
> > > > power collapse. AFAIK, the HW counters do not retain config (what event
> > > > they are counting) or value (the current count) across power collapse.
On 03/09/2018 05:35 AM, Mark Rutland wrote:
On Fri, Mar 09, 2018 at 10:53:14AM +, Suzuki K Poulose wrote:
+ Cc: Lorenzo, Charles.
On 08/03/18 23:59, Saravana Kannan wrote:
On 01/02/2018 03:25 AM, Suzuki K Poulose wrote:
Add support for the Cluster PMU part of the ARM DynamIQ Shared Unit
On 03/09/2018 05:35 AM, Mark Rutland wrote:
On Fri, Mar 09, 2018 at 10:53:14AM +, Suzuki K Poulose wrote:
+ Cc: Lorenzo, Charles.
On 08/03/18 23:59, Saravana Kannan wrote:
On 01/02/2018 03:25 AM, Suzuki K Poulose wrote:
Add support for the Cluster PMU part of the ARM DynamIQ Shared Unit
On Fri, Mar 09, 2018 at 10:53:14AM +, Suzuki K Poulose wrote:
> + Cc: Lorenzo, Charles.
>
> On 08/03/18 23:59, Saravana Kannan wrote:
> > On 01/02/2018 03:25 AM, Suzuki K Poulose wrote:
> > > Add support for the Cluster PMU part of the ARM DynamIQ Shared Unit (DSU).
> > > The DSU integrates
On Fri, Mar 09, 2018 at 10:53:14AM +, Suzuki K Poulose wrote:
> + Cc: Lorenzo, Charles.
>
> On 08/03/18 23:59, Saravana Kannan wrote:
> > On 01/02/2018 03:25 AM, Suzuki K Poulose wrote:
> > > Add support for the Cluster PMU part of the ARM DynamIQ Shared Unit (DSU).
> > > The DSU integrates
+ Cc: Lorenzo, Charles.
On 08/03/18 23:59, Saravana Kannan wrote:
On 01/02/2018 03:25 AM, Suzuki K Poulose wrote:
Add support for the Cluster PMU part of the ARM DynamIQ Shared Unit (DSU).
The DSU integrates one or more cores with an L3 memory system, control
logic, and external interfaces to
+ Cc: Lorenzo, Charles.
On 08/03/18 23:59, Saravana Kannan wrote:
On 01/02/2018 03:25 AM, Suzuki K Poulose wrote:
Add support for the Cluster PMU part of the ARM DynamIQ Shared Unit (DSU).
The DSU integrates one or more cores with an L3 memory system, control
logic, and external interfaces to
On 01/02/2018 03:25 AM, Suzuki K Poulose wrote:
Add support for the Cluster PMU part of the ARM DynamIQ Shared Unit (DSU).
The DSU integrates one or more cores with an L3 memory system, control
logic, and external interfaces to form a multicore cluster. The PMU
allows counting the various events
On 01/02/2018 03:25 AM, Suzuki K Poulose wrote:
Add support for the Cluster PMU part of the ARM DynamIQ Shared Unit (DSU).
The DSU integrates one or more cores with an L3 memory system, control
logic, and external interfaces to form a multicore cluster. The PMU
allows counting the various events
On Mon, Mar 05, 2018 at 02:10:03PM -0800, Saravana Kannan wrote:
> On 03/05/2018 02:59 AM, Mark Rutland wrote:
> > On Fri, Mar 02, 2018 at 11:19:56AM -0800, Saravana Kannan wrote:
> > > On 03/02/2018 02:42 AM, Mark Rutland wrote:
> > > > It's important to note that the DSU PMU's event_init()
On Mon, Mar 05, 2018 at 02:10:03PM -0800, Saravana Kannan wrote:
> On 03/05/2018 02:59 AM, Mark Rutland wrote:
> > On Fri, Mar 02, 2018 at 11:19:56AM -0800, Saravana Kannan wrote:
> > > On 03/02/2018 02:42 AM, Mark Rutland wrote:
> > > > It's important to note that the DSU PMU's event_init()
On 03/07/2018 06:59 AM, Suzuki K Poulose wrote:
Hi Saravana,
Sorry for the late response, I was out on vacation.
On 05/03/18 22:10, Saravana Kannan wrote:
On 03/05/2018 02:59 AM, Mark Rutland wrote:
On Fri, Mar 02, 2018 at 11:19:56AM -0800, Saravana Kannan wrote:
On 03/02/2018 02:42 AM,
On 03/07/2018 06:59 AM, Suzuki K Poulose wrote:
Hi Saravana,
Sorry for the late response, I was out on vacation.
On 05/03/18 22:10, Saravana Kannan wrote:
On 03/05/2018 02:59 AM, Mark Rutland wrote:
On Fri, Mar 02, 2018 at 11:19:56AM -0800, Saravana Kannan wrote:
On 03/02/2018 02:42 AM,
Hi Saravana,
Sorry for the late response, I was out on vacation.
On 05/03/18 22:10, Saravana Kannan wrote:
On 03/05/2018 02:59 AM, Mark Rutland wrote:
On Fri, Mar 02, 2018 at 11:19:56AM -0800, Saravana Kannan wrote:
On 03/02/2018 02:42 AM, Mark Rutland wrote:
It's important to note that
Hi Saravana,
Sorry for the late response, I was out on vacation.
On 05/03/18 22:10, Saravana Kannan wrote:
On 03/05/2018 02:59 AM, Mark Rutland wrote:
On Fri, Mar 02, 2018 at 11:19:56AM -0800, Saravana Kannan wrote:
On 03/02/2018 02:42 AM, Mark Rutland wrote:
It's important to note that
On 03/05/2018 02:59 AM, Mark Rutland wrote:
On Fri, Mar 02, 2018 at 11:19:56AM -0800, Saravana Kannan wrote:
On 03/02/2018 02:42 AM, Mark Rutland wrote:
It's important to note that the DSU PMU's event_init() ensures events
are affine to a single CPU, and the perf core code serializes
On 03/05/2018 02:59 AM, Mark Rutland wrote:
On Fri, Mar 02, 2018 at 11:19:56AM -0800, Saravana Kannan wrote:
On 03/02/2018 02:42 AM, Mark Rutland wrote:
It's important to note that the DSU PMU's event_init() ensures events
are affine to a single CPU, and the perf core code serializes
On Fri, Mar 02, 2018 at 11:19:56AM -0800, Saravana Kannan wrote:
> On 03/02/2018 02:42 AM, Mark Rutland wrote:
> > It's important to note that the DSU PMU's event_init() ensures events
> > are affine to a single CPU, and the perf core code serializes operations
> > on those events via the context
On Fri, Mar 02, 2018 at 11:19:56AM -0800, Saravana Kannan wrote:
> On 03/02/2018 02:42 AM, Mark Rutland wrote:
> > It's important to note that the DSU PMU's event_init() ensures events
> > are affine to a single CPU, and the perf core code serializes operations
> > on those events via the context
On 03/02/2018 02:42 AM, Mark Rutland wrote:
On Thu, Mar 01, 2018 at 12:35:49PM -0800, Saravana Kannan wrote:
On 03/01/2018 03:49 AM, Mark Rutland wrote:
On Wed, Feb 28, 2018 at 02:17:33PM -0800, Saravana Kannan wrote:
On 02/25/2018 06:36 AM, Mark Rutland wrote:
On Fri, Feb 23, 2018 at
On 03/02/2018 02:42 AM, Mark Rutland wrote:
On Thu, Mar 01, 2018 at 12:35:49PM -0800, Saravana Kannan wrote:
On 03/01/2018 03:49 AM, Mark Rutland wrote:
On Wed, Feb 28, 2018 at 02:17:33PM -0800, Saravana Kannan wrote:
On 02/25/2018 06:36 AM, Mark Rutland wrote:
On Fri, Feb 23, 2018 at
On Thu, Mar 01, 2018 at 12:35:49PM -0800, Saravana Kannan wrote:
> On 03/01/2018 03:49 AM, Mark Rutland wrote:
> > On Wed, Feb 28, 2018 at 02:17:33PM -0800, Saravana Kannan wrote:
> > > On 02/25/2018 06:36 AM, Mark Rutland wrote:
> > > > On Fri, Feb 23, 2018 at 04:53:18PM -0800, Saravana Kannan
On Thu, Mar 01, 2018 at 12:35:49PM -0800, Saravana Kannan wrote:
> On 03/01/2018 03:49 AM, Mark Rutland wrote:
> > On Wed, Feb 28, 2018 at 02:17:33PM -0800, Saravana Kannan wrote:
> > > On 02/25/2018 06:36 AM, Mark Rutland wrote:
> > > > On Fri, Feb 23, 2018 at 04:53:18PM -0800, Saravana Kannan
On 03/01/2018 03:49 AM, Mark Rutland wrote:
On Wed, Feb 28, 2018 at 02:17:33PM -0800, Saravana Kannan wrote:
On 02/25/2018 06:36 AM, Mark Rutland wrote:
On Fri, Feb 23, 2018 at 04:53:18PM -0800, Saravana Kannan wrote:
On 01/02/2018 03:25 AM, Suzuki K Poulose wrote:
+static void
On 03/01/2018 03:49 AM, Mark Rutland wrote:
On Wed, Feb 28, 2018 at 02:17:33PM -0800, Saravana Kannan wrote:
On 02/25/2018 06:36 AM, Mark Rutland wrote:
On Fri, Feb 23, 2018 at 04:53:18PM -0800, Saravana Kannan wrote:
On 01/02/2018 03:25 AM, Suzuki K Poulose wrote:
+static void
On Wed, Feb 28, 2018 at 02:17:33PM -0800, Saravana Kannan wrote:
> On 02/25/2018 06:36 AM, Mark Rutland wrote:
> > On Fri, Feb 23, 2018 at 04:53:18PM -0800, Saravana Kannan wrote:
> > > On 01/02/2018 03:25 AM, Suzuki K Poulose wrote:
> > > > +static void dsu_pmu_event_update(struct perf_event
On Wed, Feb 28, 2018 at 02:17:33PM -0800, Saravana Kannan wrote:
> On 02/25/2018 06:36 AM, Mark Rutland wrote:
> > On Fri, Feb 23, 2018 at 04:53:18PM -0800, Saravana Kannan wrote:
> > > On 01/02/2018 03:25 AM, Suzuki K Poulose wrote:
> > > > +static void dsu_pmu_event_update(struct perf_event
On 02/25/2018 06:36 AM, Mark Rutland wrote:
On Fri, Feb 23, 2018 at 04:53:18PM -0800, Saravana Kannan wrote:
On 01/02/2018 03:25 AM, Suzuki K Poulose wrote:
+static void dsu_pmu_event_update(struct perf_event *event)
+{
+ struct hw_perf_event *hwc = >hw;
+ u64 delta, prev_count,
On 02/25/2018 06:36 AM, Mark Rutland wrote:
On Fri, Feb 23, 2018 at 04:53:18PM -0800, Saravana Kannan wrote:
On 01/02/2018 03:25 AM, Suzuki K Poulose wrote:
+static void dsu_pmu_event_update(struct perf_event *event)
+{
+ struct hw_perf_event *hwc = >hw;
+ u64 delta, prev_count,
On Fri, Feb 23, 2018 at 04:53:18PM -0800, Saravana Kannan wrote:
> On 01/02/2018 03:25 AM, Suzuki K Poulose wrote:
> > +static void dsu_pmu_event_update(struct perf_event *event)
> > +{
> > + struct hw_perf_event *hwc = >hw;
> > + u64 delta, prev_count, new_count;
> > +
> > + do {
> > +
On Fri, Feb 23, 2018 at 04:53:18PM -0800, Saravana Kannan wrote:
> On 01/02/2018 03:25 AM, Suzuki K Poulose wrote:
> > +static void dsu_pmu_event_update(struct perf_event *event)
> > +{
> > + struct hw_perf_event *hwc = >hw;
> > + u64 delta, prev_count, new_count;
> > +
> > + do {
> > +
On 01/02/2018 03:25 AM, Suzuki K Poulose wrote:
Add support for the Cluster PMU part of the ARM DynamIQ Shared Unit (DSU).
The DSU integrates one or more cores with an L3 memory system, control
logic, and external interfaces to form a multicore cluster. The PMU
allows counting the various events
On 01/02/2018 03:25 AM, Suzuki K Poulose wrote:
Add support for the Cluster PMU part of the ARM DynamIQ Shared Unit (DSU).
The DSU integrates one or more cores with an L3 memory system, control
logic, and external interfaces to form a multicore cluster. The PMU
allows counting the various events
On 02/23/2018 03:35 AM, Mark Rutland wrote:
On Thu, Feb 22, 2018 at 12:38:39PM -0800, Saravana Kannan wrote:
On 02/22/2018 03:33 AM, Mark Rutland wrote:
On Wed, Feb 21, 2018 at 06:32:46PM -0800, Saravana Kannan wrote:
I'm not exactly sure if we can add entries to perf_type_id. If that's
On 02/23/2018 03:35 AM, Mark Rutland wrote:
On Thu, Feb 22, 2018 at 12:38:39PM -0800, Saravana Kannan wrote:
On 02/22/2018 03:33 AM, Mark Rutland wrote:
On Wed, Feb 21, 2018 at 06:32:46PM -0800, Saravana Kannan wrote:
I'm not exactly sure if we can add entries to perf_type_id. If that's
On Thu, Feb 22, 2018 at 12:38:39PM -0800, Saravana Kannan wrote:
> On 02/22/2018 03:33 AM, Mark Rutland wrote:
> > On Wed, Feb 21, 2018 at 06:32:46PM -0800, Saravana Kannan wrote:
> > > I'm not exactly sure if we can add entries to perf_type_id. If that's
> > > allowed maybe we need to add
On Thu, Feb 22, 2018 at 12:38:39PM -0800, Saravana Kannan wrote:
> On 02/22/2018 03:33 AM, Mark Rutland wrote:
> > On Wed, Feb 21, 2018 at 06:32:46PM -0800, Saravana Kannan wrote:
> > > I'm not exactly sure if we can add entries to perf_type_id. If that's
> > > allowed maybe we need to add
On 02/22/2018 03:33 AM, Mark Rutland wrote:
On Wed, Feb 21, 2018 at 06:32:46PM -0800, Saravana Kannan wrote:
On 01/02/2018 03:25 AM, Suzuki K Poulose wrote:
+static int dsu_pmu_event_init(struct perf_event *event)
+{
+ struct dsu_pmu *dsu_pmu = to_dsu_pmu(event->pmu);
+
+ if
On 02/22/2018 03:33 AM, Mark Rutland wrote:
On Wed, Feb 21, 2018 at 06:32:46PM -0800, Saravana Kannan wrote:
On 01/02/2018 03:25 AM, Suzuki K Poulose wrote:
+static int dsu_pmu_event_init(struct perf_event *event)
+{
+ struct dsu_pmu *dsu_pmu = to_dsu_pmu(event->pmu);
+
+ if
On Wed, Feb 21, 2018 at 06:32:46PM -0800, Saravana Kannan wrote:
> On 01/02/2018 03:25 AM, Suzuki K Poulose wrote:
> > +static int dsu_pmu_event_init(struct perf_event *event)
> > +{
> > + struct dsu_pmu *dsu_pmu = to_dsu_pmu(event->pmu);
> > +
> > + if (event->attr.type != event->pmu->type)
>
On Wed, Feb 21, 2018 at 06:32:46PM -0800, Saravana Kannan wrote:
> On 01/02/2018 03:25 AM, Suzuki K Poulose wrote:
> > +static int dsu_pmu_event_init(struct perf_event *event)
> > +{
> > + struct dsu_pmu *dsu_pmu = to_dsu_pmu(event->pmu);
> > +
> > + if (event->attr.type != event->pmu->type)
>
On 01/02/2018 03:25 AM, Suzuki K Poulose wrote:
Add support for the Cluster PMU part of the ARM DynamIQ Shared Unit (DSU).
The DSU integrates one or more cores with an L3 memory system, control
logic, and external interfaces to form a multicore cluster. The PMU
allows counting the various events
On 01/02/2018 03:25 AM, Suzuki K Poulose wrote:
Add support for the Cluster PMU part of the ARM DynamIQ Shared Unit (DSU).
The DSU integrates one or more cores with an L3 memory system, control
logic, and external interfaces to form a multicore cluster. The PMU
allows counting the various events
Add support for the Cluster PMU part of the ARM DynamIQ Shared Unit (DSU).
The DSU integrates one or more cores with an L3 memory system, control
logic, and external interfaces to form a multicore cluster. The PMU
allows counting the various events related to L3, SCU etc, along with
providing a
Add support for the Cluster PMU part of the ARM DynamIQ Shared Unit (DSU).
The DSU integrates one or more cores with an L3 memory system, control
logic, and external interfaces to form a multicore cluster. The PMU
allows counting the various events related to L3, SCU etc, along with
providing a
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