RE: [PATCH v3] PCI: cadence: Retrain Link to work around Gen2 training defect.
Hi Kishon, > -Original Message- > From: Kishon Vijay Abraham I > Sent: Thursday, November 26, 2020 7:28 PM > To: Rob Herring > Cc: Athani Nadeem Ladkhan ; > lorenzo.pieral...@arm.com; bhelg...@google.com; linux- > p...@vger.kernel.org; linux-kernel@vger.kernel.org; Tom Joseph > ; Swapnil Kashinath Jakhade > ; Milind Parab > Subject: Re: [PATCH v3] PCI: cadence: Retrain Link to work around Gen2 > training defect. > > EXTERNAL MAIL > > > Hi Tom, Nadeem, > > On 27/10/20 12:50 am, Rob Herring wrote: > > On Fri, Oct 23, 2020 at 1:57 AM Kishon Vijay Abraham I > wrote: > >> > >> Hi Nadeem, > >> > >> On 19/10/20 10:48 pm, Athani Nadeem Ladkhan wrote: > >>> Hi Kishon, > >>> > >>>> -Original Message- > >>>> From: Kishon Vijay Abraham I > >>>> Sent: Monday, October 19, 2020 10:59 AM > >>>> To: Athani Nadeem Ladkhan ; > >>>> lorenzo.pieral...@arm.com; r...@kernel.org; bhelg...@google.com; > >>>> linux- p...@vger.kernel.org; linux-kernel@vger.kernel.org; Tom > >>>> Joseph > >>>> Cc: Swapnil Kashinath Jakhade ; Milind Parab > >>>> > >>>> Subject: Re: [PATCH v3] PCI: cadence: Retrain Link to work around > >>>> Gen2 training defect. > >>>> > >>>> EXTERNAL MAIL > >>>> > >>>> > >>>> Hi Nadeem, > >>>> > >>>> On 30/09/20 11:51 pm, Nadeem Athani wrote: > >>>>> Cadence controller will not initiate autonomous speed change if > >>>>> strapped as Gen2. The Retrain Link bit is set as quirk to enable > >>>>> this speed > >>>> change. > >>>>> > >>>>> Signed-off-by: Nadeem Athani > > Do you have a follow-up patch fixing the review comments? We planned to fix this in coming 3 weeks. > > Thanks > Kishon
Re: [PATCH v3] PCI: cadence: Retrain Link to work around Gen2 training defect.
Hi Tom, Nadeem, On 27/10/20 12:50 am, Rob Herring wrote: > On Fri, Oct 23, 2020 at 1:57 AM Kishon Vijay Abraham I wrote: >> >> Hi Nadeem, >> >> On 19/10/20 10:48 pm, Athani Nadeem Ladkhan wrote: >>> Hi Kishon, >>> >>>> -Original Message- >>>> From: Kishon Vijay Abraham I >>>> Sent: Monday, October 19, 2020 10:59 AM >>>> To: Athani Nadeem Ladkhan ; >>>> lorenzo.pieral...@arm.com; r...@kernel.org; bhelg...@google.com; linux- >>>> p...@vger.kernel.org; linux-kernel@vger.kernel.org; Tom Joseph >>>> >>>> Cc: Swapnil Kashinath Jakhade ; Milind Parab >>>> >>>> Subject: Re: [PATCH v3] PCI: cadence: Retrain Link to work around Gen2 >>>> training defect. >>>> >>>> EXTERNAL MAIL >>>> >>>> >>>> Hi Nadeem, >>>> >>>> On 30/09/20 11:51 pm, Nadeem Athani wrote: >>>>> Cadence controller will not initiate autonomous speed change if >>>>> strapped as Gen2. The Retrain Link bit is set as quirk to enable this >>>>> speed >>>> change. >>>>> >>>>> Signed-off-by: Nadeem Athani Do you have a follow-up patch fixing the review comments? Thanks Kishon
Re: [PATCH v3] PCI: cadence: Retrain Link to work around Gen2 training defect.
On Fri, Oct 23, 2020 at 1:57 AM Kishon Vijay Abraham I wrote:
>
> Hi Nadeem,
>
> On 19/10/20 10:48 pm, Athani Nadeem Ladkhan wrote:
> > Hi Kishon,
> >
> >> -Original Message-
> >> From: Kishon Vijay Abraham I
> >> Sent: Monday, October 19, 2020 10:59 AM
> >> To: Athani Nadeem Ladkhan ;
> >> lorenzo.pieral...@arm.com; r...@kernel.org; bhelg...@google.com; linux-
> >> p...@vger.kernel.org; linux-kernel@vger.kernel.org; Tom Joseph
> >>
> >> Cc: Swapnil Kashinath Jakhade ; Milind Parab
> >>
> >> Subject: Re: [PATCH v3] PCI: cadence: Retrain Link to work around Gen2
> >> training defect.
> >>
> >> EXTERNAL MAIL
> >>
> >>
> >> Hi Nadeem,
> >>
> >> On 30/09/20 11:51 pm, Nadeem Athani wrote:
> >>> Cadence controller will not initiate autonomous speed change if
> >>> strapped as Gen2. The Retrain Link bit is set as quirk to enable this
> >>> speed
> >> change.
> >>>
> >>> Signed-off-by: Nadeem Athani
> >>> ---
> >>> Changes in v3:
> >>> - To set retrain link bit,checking device capability & link status.
> >>> - 32bit read in place of 8bit.
> >>> - Minor correction in patch comment.
> >>> - Change in variable & macro name.
> >>> Changes in v2:
> >>> - 16bit read in place of 8bit.
> >>> drivers/pci/controller/cadence/pcie-cadence-host.c | 31
> >> ++
> >>> drivers/pci/controller/cadence/pcie-cadence.h | 9 ++-
> >>> 2 files changed, 39 insertions(+), 1 deletion(-)
> >>>
> >>> diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c
> >>> b/drivers/pci/controller/cadence/pcie-cadence-host.c
> >>> index 4550e0d469ca..2b2ae4e18032 100644
> >>> --- a/drivers/pci/controller/cadence/pcie-cadence-host.c
> >>> +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
> >>> @@ -77,6 +77,36 @@ static struct pci_ops cdns_pcie_host_ops = {
> >>> .write = pci_generic_config_write,
> >>> };
> >>>
> >>> +static void cdns_pcie_retrain(struct cdns_pcie *pcie) {
> >>> + u32 lnk_cap_sls, pcie_cap_off = CDNS_PCIE_RP_CAP_OFFSET;
> >>> + u16 lnk_stat, lnk_ctl;
> >>> +
> >>> + if (!cdns_pcie_link_up(pcie))
> >>> + return;
> >>> +
> >>
> >> Is there a IP version that can be used to check if that quirk is
> >> applicable?
> > There is no such provision.
Cadence just gives out unversioned IP? There may not be s/w readable
version, but there's still a version. Look at DWC.
> hmm okay. Can we add a DT property to indicate the quirk then since
> AFAIK this is not required in future revisions of IP.
No, add a driver quirk flag, but set flag that based on compatible strings.
> >>> + /*
> >>> +* Set retrain bit if current speed is 2.5 GB/s,
> >>> +* but the PCIe root port support is > 2.5 GB/s.
Though wouldn't setting the retrain bit be harmless even if not needed?
Rob
Re: [PATCH v3] PCI: cadence: Retrain Link to work around Gen2 training defect.
Hi Nadeem,
On 19/10/20 10:48 pm, Athani Nadeem Ladkhan wrote:
> Hi Kishon,
>
>> -Original Message-
>> From: Kishon Vijay Abraham I
>> Sent: Monday, October 19, 2020 10:59 AM
>> To: Athani Nadeem Ladkhan ;
>> lorenzo.pieral...@arm.com; r...@kernel.org; bhelg...@google.com; linux-
>> p...@vger.kernel.org; linux-kernel@vger.kernel.org; Tom Joseph
>>
>> Cc: Swapnil Kashinath Jakhade ; Milind Parab
>>
>> Subject: Re: [PATCH v3] PCI: cadence: Retrain Link to work around Gen2
>> training defect.
>>
>> EXTERNAL MAIL
>>
>>
>> Hi Nadeem,
>>
>> On 30/09/20 11:51 pm, Nadeem Athani wrote:
>>> Cadence controller will not initiate autonomous speed change if
>>> strapped as Gen2. The Retrain Link bit is set as quirk to enable this speed
>> change.
>>>
>>> Signed-off-by: Nadeem Athani
>>> ---
>>> Changes in v3:
>>> - To set retrain link bit,checking device capability & link status.
>>> - 32bit read in place of 8bit.
>>> - Minor correction in patch comment.
>>> - Change in variable & macro name.
>>> Changes in v2:
>>> - 16bit read in place of 8bit.
>>> drivers/pci/controller/cadence/pcie-cadence-host.c | 31
>> ++
>>> drivers/pci/controller/cadence/pcie-cadence.h | 9 ++-
>>> 2 files changed, 39 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c
>>> b/drivers/pci/controller/cadence/pcie-cadence-host.c
>>> index 4550e0d469ca..2b2ae4e18032 100644
>>> --- a/drivers/pci/controller/cadence/pcie-cadence-host.c
>>> +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
>>> @@ -77,6 +77,36 @@ static struct pci_ops cdns_pcie_host_ops = {
>>> .write = pci_generic_config_write,
>>> };
>>>
>>> +static void cdns_pcie_retrain(struct cdns_pcie *pcie) {
>>> + u32 lnk_cap_sls, pcie_cap_off = CDNS_PCIE_RP_CAP_OFFSET;
>>> + u16 lnk_stat, lnk_ctl;
>>> +
>>> + if (!cdns_pcie_link_up(pcie))
>>> + return;
>>> +
>>
>> Is there a IP version that can be used to check if that quirk is applicable?
> There is no such provision.
hmm okay. Can we add a DT property to indicate the quirk then since
AFAIK this is not required in future revisions of IP.
>>> + /*
>>> +* Set retrain bit if current speed is 2.5 GB/s,
>>> +* but the PCIe root port support is > 2.5 GB/s.
>>> +*/
>>> +
>>> + lnk_cap_sls = cdns_pcie_readl(pcie, (CDNS_PCIE_RP_BASE +
>> pcie_cap_off +
>>> + PCI_EXP_LNKCAP));
>>> + if ((lnk_cap_sls & PCI_EXP_LNKCAP_SLS) <=
>> PCI_EXP_LNKCAP_SLS_2_5GB)
>>> + return;
>>> +
>>> + lnk_stat = cdns_pcie_rp_readw(pcie, pcie_cap_off +
>> PCI_EXP_LNKSTA);
>>> + if ((lnk_stat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB)
>> {
>>> + lnk_ctl = cdns_pcie_rp_readw(pcie,
>>> +pcie_cap_off + PCI_EXP_LNKCTL);
>>> + lnk_ctl |= PCI_EXP_LNKCTL_RL;
>>> + cdns_pcie_rp_writew(pcie, pcie_cap_off + PCI_EXP_LNKCTL,
>>> + lnk_ctl);
>>> +
>>> + if (!cdns_pcie_link_up(pcie))
>>
>> Should this rather be a cdns_pcie_host_wait_for_link()?
> The use of this api cdns_pcie_link_up was mentioned in earlier reviews.
> The mentioned api cdns_pcie_host_wait_for_link is a wrapper in which there
> are multiple checks.
> If insist, will replace with it.
yeah, I think we should give some time for the link up to succeed after
re-training.
Thanks
Kishon
RE: [PATCH v3] PCI: cadence: Retrain Link to work around Gen2 training defect.
Hi Kishon,
> -Original Message-
> From: Kishon Vijay Abraham I
> Sent: Monday, October 19, 2020 10:59 AM
> To: Athani Nadeem Ladkhan ;
> lorenzo.pieral...@arm.com; r...@kernel.org; bhelg...@google.com; linux-
> p...@vger.kernel.org; linux-kernel@vger.kernel.org; Tom Joseph
>
> Cc: Swapnil Kashinath Jakhade ; Milind Parab
>
> Subject: Re: [PATCH v3] PCI: cadence: Retrain Link to work around Gen2
> training defect.
>
> EXTERNAL MAIL
>
>
> Hi Nadeem,
>
> On 30/09/20 11:51 pm, Nadeem Athani wrote:
> > Cadence controller will not initiate autonomous speed change if
> > strapped as Gen2. The Retrain Link bit is set as quirk to enable this speed
> change.
> >
> > Signed-off-by: Nadeem Athani
> > ---
> > Changes in v3:
> > - To set retrain link bit,checking device capability & link status.
> > - 32bit read in place of 8bit.
> > - Minor correction in patch comment.
> > - Change in variable & macro name.
> > Changes in v2:
> > - 16bit read in place of 8bit.
> > drivers/pci/controller/cadence/pcie-cadence-host.c | 31
> ++
> > drivers/pci/controller/cadence/pcie-cadence.h | 9 ++-
> > 2 files changed, 39 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c
> > b/drivers/pci/controller/cadence/pcie-cadence-host.c
> > index 4550e0d469ca..2b2ae4e18032 100644
> > --- a/drivers/pci/controller/cadence/pcie-cadence-host.c
> > +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
> > @@ -77,6 +77,36 @@ static struct pci_ops cdns_pcie_host_ops = {
> > .write = pci_generic_config_write,
> > };
> >
> > +static void cdns_pcie_retrain(struct cdns_pcie *pcie) {
> > + u32 lnk_cap_sls, pcie_cap_off = CDNS_PCIE_RP_CAP_OFFSET;
> > + u16 lnk_stat, lnk_ctl;
> > +
> > + if (!cdns_pcie_link_up(pcie))
> > + return;
> > +
>
> Is there a IP version that can be used to check if that quirk is applicable?
There is no such provision.
> > + /*
> > +* Set retrain bit if current speed is 2.5 GB/s,
> > +* but the PCIe root port support is > 2.5 GB/s.
> > +*/
> > +
> > + lnk_cap_sls = cdns_pcie_readl(pcie, (CDNS_PCIE_RP_BASE +
> pcie_cap_off +
> > + PCI_EXP_LNKCAP));
> > + if ((lnk_cap_sls & PCI_EXP_LNKCAP_SLS) <=
> PCI_EXP_LNKCAP_SLS_2_5GB)
> > + return;
> > +
> > + lnk_stat = cdns_pcie_rp_readw(pcie, pcie_cap_off +
> PCI_EXP_LNKSTA);
> > + if ((lnk_stat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB)
> {
> > + lnk_ctl = cdns_pcie_rp_readw(pcie,
> > +pcie_cap_off + PCI_EXP_LNKCTL);
> > + lnk_ctl |= PCI_EXP_LNKCTL_RL;
> > + cdns_pcie_rp_writew(pcie, pcie_cap_off + PCI_EXP_LNKCTL,
> > + lnk_ctl);
> > +
> > + if (!cdns_pcie_link_up(pcie))
>
> Should this rather be a cdns_pcie_host_wait_for_link()?
The use of this api cdns_pcie_link_up was mentioned in earlier reviews.
The mentioned api cdns_pcie_host_wait_for_link is a wrapper in which there are
multiple checks.
If insist, will replace with it.
Thanks,
Nadeem
>
> Thanks
> Kishon
>
> > + return;
> > + }
> > +}
> >
> > static int cdns_pcie_host_init_root_port(struct cdns_pcie_rc *rc) {
> > @@ -115,6 +145,7 @@ static int cdns_pcie_host_init_root_port(struct
> cdns_pcie_rc *rc)
> > cdns_pcie_rp_writeb(pcie, PCI_CLASS_PROG, 0);
> > cdns_pcie_rp_writew(pcie, PCI_CLASS_DEVICE,
> PCI_CLASS_BRIDGE_PCI);
> >
> > + cdns_pcie_retrain(pcie);
> > return 0;
> > }
> >
> > diff --git a/drivers/pci/controller/cadence/pcie-cadence.h
> > b/drivers/pci/controller/cadence/pcie-cadence.h
> > index feed1e3038f4..5f1cf032ae15 100644
> > --- a/drivers/pci/controller/cadence/pcie-cadence.h
> > +++ b/drivers/pci/controller/cadence/pcie-cadence.h
> > @@ -119,7 +119,7 @@
> > * Root Port Registers (PCI configuration space for the root port function)
> > */
> > #define CDNS_PCIE_RP_BASE 0x0020
> > -
> > +#define CDNS_PCIE_RP_CAP_OFFSET 0xc0
> >
> > /*
> > * Address Translation Registers
> > @@ -413,6 +413,13 @@ static inline void cdns_pcie_rp_writew(struct
> cdns_pcie *pcie,
> > cdns_pcie_write_sz(addr, 0x2, value); }
> >
> > +static inline u16 cdns_pcie_rp_readw(struct cdns_pcie *pcie, u32 reg)
> > +{
> > + void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg;
> > +
> > + return cdns_pcie_read_sz(addr, 0x2); }
> > +
> > /* Endpoint Function register access */ static inline void
> > cdns_pcie_ep_fn_writeb(struct cdns_pcie *pcie, u8 fn,
> > u32 reg, u8 value)
> >
Re: [PATCH v3] PCI: cadence: Retrain Link to work around Gen2 training defect.
Hi Nadeem,
On 30/09/20 11:51 pm, Nadeem Athani wrote:
> Cadence controller will not initiate autonomous speed change if strapped
> as Gen2. The Retrain Link bit is set as quirk to enable this speed change.
>
> Signed-off-by: Nadeem Athani
> ---
> Changes in v3:
> - To set retrain link bit,checking device capability & link status.
> - 32bit read in place of 8bit.
> - Minor correction in patch comment.
> - Change in variable & macro name.
> Changes in v2:
> - 16bit read in place of 8bit.
> drivers/pci/controller/cadence/pcie-cadence-host.c | 31
> ++
> drivers/pci/controller/cadence/pcie-cadence.h | 9 ++-
> 2 files changed, 39 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c
> b/drivers/pci/controller/cadence/pcie-cadence-host.c
> index 4550e0d469ca..2b2ae4e18032 100644
> --- a/drivers/pci/controller/cadence/pcie-cadence-host.c
> +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
> @@ -77,6 +77,36 @@ static struct pci_ops cdns_pcie_host_ops = {
> .write = pci_generic_config_write,
> };
>
> +static void cdns_pcie_retrain(struct cdns_pcie *pcie)
> +{
> + u32 lnk_cap_sls, pcie_cap_off = CDNS_PCIE_RP_CAP_OFFSET;
> + u16 lnk_stat, lnk_ctl;
> +
> + if (!cdns_pcie_link_up(pcie))
> + return;
> +
Is there a IP version that can be used to check if that quirk is applicable?
> + /*
> + * Set retrain bit if current speed is 2.5 GB/s,
> + * but the PCIe root port support is > 2.5 GB/s.
> + */
> +
> + lnk_cap_sls = cdns_pcie_readl(pcie, (CDNS_PCIE_RP_BASE + pcie_cap_off +
> + PCI_EXP_LNKCAP));
> + if ((lnk_cap_sls & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB)
> + return;
> +
> + lnk_stat = cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA);
> + if ((lnk_stat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) {
> + lnk_ctl = cdns_pcie_rp_readw(pcie,
> + pcie_cap_off + PCI_EXP_LNKCTL);
> + lnk_ctl |= PCI_EXP_LNKCTL_RL;
> + cdns_pcie_rp_writew(pcie, pcie_cap_off + PCI_EXP_LNKCTL,
> + lnk_ctl);
> +
> + if (!cdns_pcie_link_up(pcie))
Should this rather be a cdns_pcie_host_wait_for_link()?
Thanks
Kishon
> + return;
> + }
> +}
>
> static int cdns_pcie_host_init_root_port(struct cdns_pcie_rc *rc)
> {
> @@ -115,6 +145,7 @@ static int cdns_pcie_host_init_root_port(struct
> cdns_pcie_rc *rc)
> cdns_pcie_rp_writeb(pcie, PCI_CLASS_PROG, 0);
> cdns_pcie_rp_writew(pcie, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI);
>
> + cdns_pcie_retrain(pcie);
> return 0;
> }
>
> diff --git a/drivers/pci/controller/cadence/pcie-cadence.h
> b/drivers/pci/controller/cadence/pcie-cadence.h
> index feed1e3038f4..5f1cf032ae15 100644
> --- a/drivers/pci/controller/cadence/pcie-cadence.h
> +++ b/drivers/pci/controller/cadence/pcie-cadence.h
> @@ -119,7 +119,7 @@
> * Root Port Registers (PCI configuration space for the root port function)
> */
> #define CDNS_PCIE_RP_BASE0x0020
> -
> +#define CDNS_PCIE_RP_CAP_OFFSET 0xc0
>
> /*
> * Address Translation Registers
> @@ -413,6 +413,13 @@ static inline void cdns_pcie_rp_writew(struct cdns_pcie
> *pcie,
> cdns_pcie_write_sz(addr, 0x2, value);
> }
>
> +static inline u16 cdns_pcie_rp_readw(struct cdns_pcie *pcie, u32 reg)
> +{
> + void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg;
> +
> + return cdns_pcie_read_sz(addr, 0x2);
> +}
> +
> /* Endpoint Function register access */
> static inline void cdns_pcie_ep_fn_writeb(struct cdns_pcie *pcie, u8 fn,
> u32 reg, u8 value)
>
[PATCH v3] PCI: cadence: Retrain Link to work around Gen2 training defect.
Cadence controller will not initiate autonomous speed change if strapped
as Gen2. The Retrain Link bit is set as quirk to enable this speed change.
Signed-off-by: Nadeem Athani
---
Changes in v3:
- To set retrain link bit,checking device capability & link status.
- 32bit read in place of 8bit.
- Minor correction in patch comment.
- Change in variable & macro name.
Changes in v2:
- 16bit read in place of 8bit.
drivers/pci/controller/cadence/pcie-cadence-host.c | 31 ++
drivers/pci/controller/cadence/pcie-cadence.h | 9 ++-
2 files changed, 39 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c
b/drivers/pci/controller/cadence/pcie-cadence-host.c
index 4550e0d469ca..2b2ae4e18032 100644
--- a/drivers/pci/controller/cadence/pcie-cadence-host.c
+++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
@@ -77,6 +77,36 @@ static struct pci_ops cdns_pcie_host_ops = {
.write = pci_generic_config_write,
};
+static void cdns_pcie_retrain(struct cdns_pcie *pcie)
+{
+ u32 lnk_cap_sls, pcie_cap_off = CDNS_PCIE_RP_CAP_OFFSET;
+ u16 lnk_stat, lnk_ctl;
+
+ if (!cdns_pcie_link_up(pcie))
+ return;
+
+ /*
+* Set retrain bit if current speed is 2.5 GB/s,
+* but the PCIe root port support is > 2.5 GB/s.
+*/
+
+ lnk_cap_sls = cdns_pcie_readl(pcie, (CDNS_PCIE_RP_BASE + pcie_cap_off +
+ PCI_EXP_LNKCAP));
+ if ((lnk_cap_sls & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB)
+ return;
+
+ lnk_stat = cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA);
+ if ((lnk_stat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) {
+ lnk_ctl = cdns_pcie_rp_readw(pcie,
+pcie_cap_off + PCI_EXP_LNKCTL);
+ lnk_ctl |= PCI_EXP_LNKCTL_RL;
+ cdns_pcie_rp_writew(pcie, pcie_cap_off + PCI_EXP_LNKCTL,
+ lnk_ctl);
+
+ if (!cdns_pcie_link_up(pcie))
+ return;
+ }
+}
static int cdns_pcie_host_init_root_port(struct cdns_pcie_rc *rc)
{
@@ -115,6 +145,7 @@ static int cdns_pcie_host_init_root_port(struct
cdns_pcie_rc *rc)
cdns_pcie_rp_writeb(pcie, PCI_CLASS_PROG, 0);
cdns_pcie_rp_writew(pcie, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI);
+ cdns_pcie_retrain(pcie);
return 0;
}
diff --git a/drivers/pci/controller/cadence/pcie-cadence.h
b/drivers/pci/controller/cadence/pcie-cadence.h
index feed1e3038f4..5f1cf032ae15 100644
--- a/drivers/pci/controller/cadence/pcie-cadence.h
+++ b/drivers/pci/controller/cadence/pcie-cadence.h
@@ -119,7 +119,7 @@
* Root Port Registers (PCI configuration space for the root port function)
*/
#define CDNS_PCIE_RP_BASE 0x0020
-
+#define CDNS_PCIE_RP_CAP_OFFSET 0xc0
/*
* Address Translation Registers
@@ -413,6 +413,13 @@ static inline void cdns_pcie_rp_writew(struct cdns_pcie
*pcie,
cdns_pcie_write_sz(addr, 0x2, value);
}
+static inline u16 cdns_pcie_rp_readw(struct cdns_pcie *pcie, u32 reg)
+{
+ void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg;
+
+ return cdns_pcie_read_sz(addr, 0x2);
+}
+
/* Endpoint Function register access */
static inline void cdns_pcie_ep_fn_writeb(struct cdns_pcie *pcie, u8 fn,
u32 reg, u8 value)
--
2.15.0
