Re: [PATCH v3 03/10] drm/bridge: analogix_dp: correct the register bit define error in ANALOGIX_DP_PLL_REG_1

2016-06-29 Thread Yakir Yang
Sean, On 06/23/2016 10:33 PM, Sean Paul wrote: On Tue, Jun 14, 2016 at 7:46 AM, Yakir Yang wrote: There're an register define error in ANALOGIX_DP_PLL_REG_1 which introduced by commit bcec20fd5ad6 ("drm: bridge: analogix/dp: add some rk3288 special registers setting"). The PHY PLL input clock

Re: [PATCH v3 03/10] drm/bridge: analogix_dp: correct the register bit define error in ANALOGIX_DP_PLL_REG_1

2016-06-23 Thread Sean Paul
On Tue, Jun 14, 2016 at 7:46 AM, Yakir Yang wrote: > There're an register define error in ANALOGIX_DP_PLL_REG_1 which introduced > by commit bcec20fd5ad6 ("drm: bridge: analogix/dp: add some rk3288 special > registers setting"). > > The PHY PLL input clock source is selected by ANALOGIX_DP_PLL_REG

[PATCH v3 03/10] drm/bridge: analogix_dp: correct the register bit define error in ANALOGIX_DP_PLL_REG_1

2016-06-14 Thread Yakir Yang
There're an register define error in ANALOGIX_DP_PLL_REG_1 which introduced by commit bcec20fd5ad6 ("drm: bridge: analogix/dp: add some rk3288 special registers setting"). The PHY PLL input clock source is selected by ANALOGIX_DP_PLL_REG_1 BIT 0, not BIT 1. Signed-off-by: Yakir Yang Reviewed-by: