On Mon, May 04, 2015 at 09:42:25AM +0200, Greg Kroah-Hartman wrote:
On Mon, May 04, 2015 at 09:57:13AM +0300, Jarkko Sakkinen wrote:
On Sun, 2015-05-03 at 20:00 +0200, Greg Kroah-Hartman wrote:
On Sat, May 02, 2015 at 09:10:52PM +0300, Jarkko Sakkinen wrote:
Added a new function
Signed-off-by: Johannes Thumshirn jthumsh...@suse.de
---
MAINTAINERS | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 781e099..2943c62 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3715,7 +3715,7 @@ S:Maintained
F:
On Wed, May 06, 2015 at 07:59:04AM +0300, Kalle Valo wrote:
Okash Khawaja okash.khaw...@gmail.com writes:
The PCI cache line size value was being compared against decimal values
prefixed with 0x.
Fixed the literals to use the correct hex values.
Signed-off-by: Okash Khawaja
Hello Bjorn,
On 05/05/2015 11:42 PM, Bjorn Helgaas wrote:
On Fri, Apr 10, 2015 at 11:12:48AM +0200, Gabriel FERNANDEZ wrote:
This patch adds the pci-st.c pci driver found on STMicroelectronics
SoC's into the STI arch section of the maintainers file.
Signed-off-by: Gabriel Fernandez
Signed-off-by: Yangbo Lu yangbo...@freescale.com
---
arch/powerpc/configs/corenet32_smp_defconfig | 2 ++
arch/powerpc/configs/corenet64_smp_defconfig | 2 ++
2 files changed, 4 insertions(+)
diff --git a/arch/powerpc/configs/corenet32_smp_defconfig
On Wed, 2015-05-06 at 08:52 +0200, Mike Galbraith wrote:
On Tue, 2015-05-05 at 23:06 -0700, Paul E. McKenney wrote:
1 * stat() on isolated cpu
NO_HZ_FULL offinactive housekeepernohz_full
real0m14.266s 0m14.367s0m20.427s 0m27.921s
user
On Tue, 2015-05-05 at 15:08 +0530, Shobhit Kumar wrote:
The Crystalcove PMIC controls PWM signals and this driver exports that
capability as a PWM chip driver. This is platform device implementtaion
of the drivers/mfd cell device for CRC PMIC
v2: Use the existing config callback with duty_ns
This patch implements device_suspend/device_resume entries for xHC driver.
device_suspend will be called when a USB device is about to suspend. It
will issue a stop endpoint command for each endpoint in this device. The
Suspend(SP) bit in the command TRB will set which will give xHC a hint
about
This patch series try to meet a design requirement in xHCI spec.
The xHCI spec is designed to allow an xHC implementation to cache the
endpoint state. Caching endpoint state allows an xHC to reduce latency
when handling ERDYs and other USB asynchronous events. However holding
this state in xHC
There is no need to call xhci_stop_device() and xhci_ring_device() in
hub control and bus suspend functions since all device suspend and
resume have been notified through device_suspend/device_resume interfaces.
Signed-off-by: Lu Baolu baolu...@linux.intel.com
---
drivers/usb/host/xhci-hub.c |
This patch adds two new entries in hc_driver. With these new entries,
USB core can notify host driver when a USB device is about to suspend
or just resumed.
The xHCI spec is designed to allow an xHC implementation to cache the
endpoint state. Caching endpoint state allows an xHC to reduce latency
On Tue, May 05, 2015 at 06:06:08PM -0700, Andrew Bresticker wrote:
On Tue, May 5, 2015 at 4:35 PM, James Hogan james.ho...@imgtec.com wrote:
On Tue, May 05, 2015 at 04:09:31PM -0700, Andrew Bresticker wrote:
On Tue, May 5, 2015 at 3:43 PM, James Hogan james.ho...@imgtec.com wrote:
On Tue,
On 30 April 2015 at 16:53, Alan Stern st...@rowland.harvard.edu wrote:
On Thu, 30 Apr 2015, Ulf Hansson wrote:
I hesitated to send this reply, since it might add confusion. If
that's the case, please ignore it.
I have a long term vision to fully enable support for a runtime PM
centric
Hi Jacek,
On Wed, May 6, 2015 at 9:58 AM, Jacek Anaszewski
j.anaszew...@samsung.com wrote:
Why don't you apply the same modification to all LED Kconfig
entries with GPIOLIB dependency?
LEDS_PCA9532_GPIO is a GPIO provider, not a consumer. There are no
dummies for GPIO providers.
LEDS_GPIO
On Wed, 2015-05-06 at 10:09 +0200, Peter Zijlstra wrote:
But we're not implementing an umbrella right? We're implementing Cache
QoS Enforcement (CQE aka. CAT).
Why confuse things with calling it random other names?
From what I understand the whole RDT thing is the umbrella term for
2015-05-01 9:43 GMT+02:00 Yingjoe Chen yingjoe.c...@mediatek.com:
Add support for booting secondary CPUs on mt6589, mt8127
and mt8135.
Signed-off-by: Yingjoe Chen yingjoe.c...@mediatek.com
---
arch/arm/mach-mediatek/Makefile | 3 +
arch/arm/mach-mediatek/platsmp.c | 145
From: Xudong Chen xudong.c...@mediatek.com
The mediatek SoCs have I2C controller that handle I2C transfer.
This patch include common I2C bus driver.
This driver is compatible with I2C controller on mt65xx/mt81xx.
Signed-off-by: Xudong Chen xudong.c...@mediatek.com
Signed-off-by: Liguo Zhang
Applied. Thanks!
On Tue, May 5, 2015 at 6:30 AM, Guenter Roeck li...@roeck-us.net wrote:
Fix
include/asm-generic/io.h: In function 'readb':
include/asm-generic/io.h:113:2: error:
implicit declaration of function 'bfin_read8'
include/asm-generic/io.h: In function 'readw':
On Wednesday 06 May 2015 11:14:25 Gabriel Fernandez wrote:
+static int __init pcie_init(void)
+{
+ return platform_driver_probe(st_pcie_driver, st_pcie_probe);
+}
+device_initcall(pcie_init);
Can you use module_platform_driver_probe() or module_init() here?
Yes we can use
The Allwinner H3 is a quad-core Cortex-A7-based SoC. It is very similar
to other sun8i family SoCs like the A23.
Signed-off-by: Jens Kuske jensku...@gmail.com
---
Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
arch/arm/mach-sunxi/Kconfig | 2 +-
* Bryan O'Donoghue pure.lo...@nexus-software.ie wrote:
+/**
+ * esram_page_overlay - Overlay a page with fast access eSRAM.
+ *
+ * This function takes a 4 KiB aligned physical address and programs an
+ * eSRAM page to overlay that 4 KiB region. We require and verify that the
+ * target
On 05/05/2015 08:21 AM, Al Viro wrote:
From: Al Viro v...@zeniv.linux.org.uk
Signed-off-by: Al Viro v...@zeniv.linux.org.uk
ACK-by: Boaz Harrosh o...@electrozaur.com
Thanks Al so much nicer (And safer)
Boaz
---
fs/exofs/Kbuild| 2 +-
fs/exofs/exofs.h | 4
fs/exofs/inode.c
* Bryan O'Donoghue pure.lo...@nexus-software.ie wrote:
+config INTEL_ESRAM
+ bool Intel Embedded SRAM (eSRAM) support
+ default n
+ depends on X86_INTEL_QUARK IOSF_MBI
+ select GENERIC_ALLOCATOR
+ ---help---
+ This options provides an API to allocate memory from
On Wed, May 06, 2015 at 11:31:31AM +0200, Jens Kuske wrote:
The H3 SoC has the same dma engine as the A31 (sun6i), with a
reduced amount of endpoints and physical channels. Add the proper
config data and compatible string to support it.
Signed-off-by: Jens Kuske jensku...@gmail.com
On Wed, May 06, 2015 at 11:31:30AM +0200, Jens Kuske wrote:
The H3 uses the same pin controller as previous SoC's from Allwinner.
Add support for the pins controlled by the main PIO controller.
Signed-off-by: Jens Kuske jensku...@gmail.com
---
On Wed, May 06, 2015 at 09:46:49AM +0800, Dave Young wrote:
For the original problem, the key issue is dmar faults cause kdump kernel
hang so that vmcore can not be saved. I do not know the reason why it hangs
I think it is acceptable if kdump kernel boot ok with some dma errors..
It hangs
2015-05-06 9:59 GMT+02:00 Yingjoe Chen yingjoe.c...@mediatek.com:
On Wed, 2015-05-06 at 15:19 +0800, Yingjoe Chen wrote:
Hi Matthias,
...
I tried on the mt8135 eval board but it fails to bring up the CPU.
When booting:
[1.048588] CPU1: failed to come online
[2.049914] CPU2:
2015-05-05 18:54 GMT+02:00 One Thousand Gnomes gno...@lxorguk.ukuu.org.uk:
First what is Secure Data Path ? SDP is a set of hardware features to garanty
that some memories regions could only be read and/or write by specific
hardware
IPs. You can imagine it as a kind of memory firewall which
On Tue, May 05, 2015 at 03:06:03PM -0400, Tejun Heo wrote:
Hello, Peter.
On Tue, May 05, 2015 at 09:00:57PM +0200, Peter Zijlstra wrote:
On Tue, May 05, 2015 at 12:31:12PM -0400, Tejun Heo wrote:
What I don't want to happen is controllers failing migrations
willy-nilly for random
With this patch revision DT string entry is used to set global system_rev
variable. DT revision is expected to be string with one hexadecimal number.
So Revision line in /proc/cpuinfo will be same as revision DT value.
Signed-off-by: Pali Rohár pali.ro...@gmail.com
Acked-by: Pavel Machek
On 05/06/15 10:35, Daniel Vetter wrote:
On Tue, May 05, 2015 at 05:54:05PM +0100, One Thousand Gnomes wrote:
First what is Secure Data Path ? SDP is a set of hardware features to
garanty
that some memories regions could only be read and/or write by specific
hardware
IPs. You can imagine it
The test was updated @
https://docs.google.com/spreadsheets/d/1voffS6dNglwAExSGh3UmG__UAO2qfZ829CkJLPo06aI/edit?usp=sharing.
Please check the tab Dell-rbtnv2
Notes:
1. The systems come and go and I can find some of original ones but I
tests some others
2. Test 3 was done by Test 2 + rmmod
On Tue, 5 May 2015, Tejun Heo wrote:
On Tue, May 05, 2015 at 08:29:28PM +0200, Thomas Gleixner wrote:
As Peter said several times: hard failure is good and desired. It's a
very clear information on which people can act on. If the failures
modes are nilly-willy today, as you wrote somewhere,
On Wed, May 06, 2015 at 10:35:52AM +0200, Daniel Vetter wrote:
On Tue, May 05, 2015 at 05:54:05PM +0100, One Thousand Gnomes wrote:
First what is Secure Data Path ? SDP is a set of hardware features to
garanty
that some memories regions could only be read and/or write by specific
On Wednesday 06 May 2015 10:49:01 Pali Rohár wrote:
With this patch revision DT string entry is used to set global system_rev
variable. DT revision is expected to be string with one hexadecimal number.
So Revision line in /proc/cpuinfo will be same as revision DT value.
Signed-off-by: Pali
Hello Krzysztof,
On 05/06/2015 02:59 AM, Krzysztof Kozlowski wrote:
Dear Kukjin,
I gathered various improvements for upcoming 4.2 merge window.
Description along with a tag.
Best regards,
Krzysztof
The following changes
On Saturday 02 May 2015 01:42:14 Alexandre Belloni wrote:
Hi,
On 14/12/2010 at 16:08:26 +0100, Hans Ulli Kroll wrote :
driver for the rtc device
on Cortina Systems CS3516 or StormlinkSemi SL3516 aka Gemini SoC
Signed-off-by: Hans Ulli Kroll ulli.kr...@googlemail.com
This driver has
Hi,
On Wed, May 6, 2015 at 5:31 PM, Jens Kuske jensku...@gmail.com wrote:
The H3 clock control unit is similar to the those of other sun8i family
members like the A23.
The AHB1 gates got split up into AHB1 and AHB2, with AHB2 clock source
being muxable between AHB1 and PLL6/2, but still
On 05/05/2015 19:17, Radim Krčmář wrote:
2015-04-30 13:36+0200, Paolo Bonzini:
This adds an arch-specific memslot flag that hides slots unless the
VCPU is in system management mode.
Some care is needed in order to limit the overhead of x86_gfn_to_memslot
when compared with gfn_to_memslot.
* Bryan O'Donoghue pure.lo...@nexus-software.ie wrote:
+/**
+ * esram_self_test_time
+ *
+ * This function is carefully constructed to measure and verify the
+ * performance boost provided by eSRAM. We invalidate the cache with a
+ * wbinvd() and then perform a series of reads - each of
Commit-ID: f5d6a52f511157c7476590532a23b5664b1ed877
Gitweb: http://git.kernel.org/tip/f5d6a52f511157c7476590532a23b5664b1ed877
Author: Jan H. Schönherr jscho...@amazon.de
AuthorDate: Mon, 4 May 2015 11:42:34 +0200
Committer: Ingo Molnar mi...@kernel.org
CommitDate: Wed, 6 May 2015
Commit-ID: 1b4574292e9d2d37b3bb437c9e778fd2bba8e170
Gitweb: http://git.kernel.org/tip/1b4574292e9d2d37b3bb437c9e778fd2bba8e170
Author: Aravind Gopalakrishnan aravind.gopalakrish...@amd.com
AuthorDate: Tue, 7 Apr 2015 16:46:37 -0500
Committer: Ingo Molnar mi...@kernel.org
CommitDate: Wed,
Commit-ID: b9d16a2a21aa9c264a29dd84d6f7b03581517a03
Gitweb: http://git.kernel.org/tip/b9d16a2a21aa9c264a29dd84d6f7b03581517a03
Author: Aravind Gopalakrishnan aravind.gopalakrish...@amd.com
AuthorDate: Mon, 27 Apr 2015 10:25:51 -0500
Committer: Ingo Molnar mi...@kernel.org
CommitDate:
Commit-ID: c88d47480d300eaad80c213d50c9bf6077fc49bc
Gitweb: http://git.kernel.org/tip/c88d47480d300eaad80c213d50c9bf6077fc49bc
Author: Bobby Powers bobbypow...@gmail.com
AuthorDate: Mon, 27 Apr 2015 08:10:41 -0700
Committer: Ingo Molnar mi...@kernel.org
CommitDate: Wed, 6 May 2015
On Wed, 6 May 2015, Jiang Liu wrote:
Hi Thomas,
This is the simplified version, which removed the kernel parameter.
Seems much simpler:)
But it can be made even simpler. :)
+enum {
+ /* Allocate CPU vectors from CPUs on device local node */
+ X86_VECTOR_POL_NODE = 0x1,
+
Following what DT already does. If the device does not have ACPI Interrupt
resource but instead it has one or more GpioInt resources listed below it,
we take the first GpioInt resource, convert it to suitable Linux IRQ number
and pass it to the driver instead.
This makes drivers simpler because
ACPI specification knows two types of GPIOs: GpioIo and GpioInt. The latter
is used to describe that a given device interrupt line is connected to a
specific GPIO pin. Typical ACPI _CRS entry for such device looks like
below:
Name (_CRS, ResourceTemplate ()
{
I2cSerialBus (0x004A,
On Wed, May 06, 2015 at 09:51:35AM +0800, Dave Young wrote:
DMA write will modify system ram, if the old data is corrupted it is possible
that DMA operation modify wrong ram regions because of wrong mapping.
Am I missing something and is it not possible?
This might have happened already
On Wed, May 06, 2015 at 03:50:13AM +0300, Laurent Pinchart wrote:
On Tuesday 05 May 2015 09:27:52 Christoph Hellwig wrote:
On Tue, May 05, 2015 at 05:39:57PM +0200, Benjamin Gaignard wrote:
Since few months I'm looking for Linaro to how do Secure Data Path (SPD).
I have tried and
Hi Ben,
There is no need in this patch for 3.2, only beginning from 3.19.
SMBIOSv3 is absent in k3.2, and for previous SMBIOS versions 16-bit dmi len
is enough. It should had been mentioned in the commit/code, sorry.
On 05.05.15 04:16, Ben Hutchings wrote:
3.2.69-rc1 review patch. If anyone
On 05/06/2015 03:39 PM, Stephen Boyd wrote:
drivers/clk/hisilicon/clk-hix5hd2.c:255:13: warning: symbol
'hix5hd2_clk_register_complex' was not declared. Should it be static?
Cc: Zhangfei Gao zhangfei@linaro.org
Signed-off-by: Stephen Boyd sb...@codeaurora.org
Acked-by: Zhangfei Gao
On Tue, May 5, 2015 at 7:54 PM, Shawn Guo shawn@linaro.org wrote:
On Tue, Apr 07, 2015 at 12:34:30PM +0900, Masahiro Yamada wrote:
Hello experts,
I hope this is the correct ML to ask this question.
I am struggling to port Linux-4.0-rc7 onto my SoC/board,
based on ARM cortex-A9 (single
Hello Stephen,
On 05/06/2015 09:39 AM, Stephen Boyd wrote:
drivers/clk/clk-max-gen.c:82:16: warning: symbol 'max_gen_clk_ops' was not
declared. Should it be static?
drivers/clk/clk-max-gen.c:109:5: warning: symbol 'max_gen_clk_probe' was not
declared. Should it be static?
On 2015/5/6 16:20, Hillf Danton wrote:
Hi all:
I meet a kernel problem about the random segmentation fault(x86_64). In my
testcase, the size of local variables exceeds 20MB.
when run the testcase, it will cause segmentation fault(because the default
stack size limit is 8192KB).
when I
On 03/05/15 07:27, pang.xun...@zte.com.cn wrote:
Hi Dietmar,
Dietmar Eggemann dietmar.eggem...@arm.com wrote 2015-03-24 AM 03:19:41:
Re: [RFCv3 PATCH 12/48] sched: Make usage tracking cpu scale-invariant
[...]
In the previous patch-set https://lkml.org/lkml/2014/12/2/332we
cpu-scaled
On 06/05/2015 at 11:39:58 +0200, Arnd Bergmann wrote :
On Saturday 02 May 2015 01:42:14 Alexandre Belloni wrote:
Hi,
On 14/12/2010 at 16:08:26 +0100, Hans Ulli Kroll wrote :
driver for the rtc device
on Cortina Systems CS3516 or StormlinkSemi SL3516 aka Gemini SoC
* Bryan O'Donoghue pure.lo...@nexus-software.ie wrote:
Quark X1000 SoC contains a 512 KiB embedded SRAM (eSRAM) memory that can
be mapped onto an area of DRAM in block or on per-page overlay mode where a
4 KiB aligned region can be overlayed - allowing for broken up mappings
with a 4 KiB
Before this patch, 'make install' installs libraries into bindir:
$ make install DESTDIR=./tree
INSTALL trace_plugins
INSTALL libtraceevent.a
INSTALL libtraceevent.so
$ find ./tree
./tree/
./tree/usr
./tree/usr/local
./tree/usr/local/bin
Hi Suravee,
On 05/05/15 16:12, Suravee Suthikulpanit wrote:
From http://www.uefi.org/sites/default/files/resources/ACPI_6.0.pdf,
section 6.2.17 _CCA states that ARM platforms require ACPI _CCA
object to be specified for DMA-cabpable devices. This patch introduces
ACPI_MUST_HAVE_CCA in arm64
parport subsystem starts using the device-model. drivers using the
device-model has to define probe and should register the device with
parport with parport_register_dev_model()
Signed-off-by: Sudip Mukherjee su...@vectorindia.org
---
v5:
a) addition/removal of ports are now handled.
modify paride driver to use the new parallel port device model.
Signed-off-by: Sudip Mukherjee su...@vectorindia.org
---
in v4 of i2c-parport patch Jean mentioned to use the full name while
in probe. That has been done in other drivers except this one.
The higher layer drivers (pcd , pd etc.)
as of now i2c-parport was connecting to all the available parallel
ports. Lets limit that to maximum of 4 instances and at the same time
define which instance connects to which parallel port
Signed-off-by: Sudip Mukherjee su...@vectorindia.org
---
drivers/i2c/busses/i2c-parport.c | 21
converted to use the new device-model parallel port.
Signed-off-by: Sudip Mukherjee su...@vectorindia.org
---
drivers/staging/panel/panel.c | 20 +++-
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/drivers/staging/panel/panel.c b/drivers/staging/panel/panel.c
modify i2c-parport driver to use the new parallel port device model.
Signed-off-by: Sudip Mukherjee su...@vectorindia.org
---
drivers/i2c/busses/i2c-parport.c | 20 +---
1 file changed, 17 insertions(+), 3 deletions(-)
diff --git a/drivers/i2c/busses/i2c-parport.c
* Srinivas Pandruvada srinivas.pandruv...@linux.intel.com wrote:
diff --git a/arch/x86/kernel/punit_atom_debug.c
b/arch/x86/kernel/punit_atom_debug.c
Please put this somewhere suitable in arch/x86/platform/.
I moved this to arch/x86/platform/intel-mid, but punit is much more
part
On Wed, May 06, 2015 at 08:12:46AM +0100, Mel Gorman wrote:
On Tue, May 05, 2015 at 03:25:49PM -0700, Andrew Morton wrote:
On Tue, 5 May 2015 23:13:29 +0100 Mel Gorman mgor...@suse.de wrote:
Alternatively, the page allocator can go off and synchronously
initialize some pageframes
This is the convention used in most parts of the kernel including DT
counterpart of I2C slave enumeration. To make things consistent do the same
for ACPI I2C slave enumeration path as well.
Signed-off-by: Mika Westerberg mika.westerb...@linux.intel.com
---
drivers/i2c/i2c-core.c | 3 +--
1 file
Hi,
This is second iteration of the series. The previous version can be found
from [1].
Currently drivers for ACPI enumerated devices that have their interrupt
line connected to a GPIO controller instead of IO-APIC are required to do
complete gpiod_get()/gpiod_to_irq() etc. dance themselves.
* Jan H. Schönherr jscho...@amazon.de wrote:
Remove the per-CPU delays during SMP initialization, which seems to be
possible on newer architectures with an x2APIC.
Xen does this since 2011. In fact, this commit is basically a
combination of the following Xen commits. The first removes the
This patchset adds support for the GPIO controller (UPG GIO) used on Broadcom's
various BRCMSTB SoCs (BCM7XXX and others). It uses the basic-mmio-gpio
interface to try to reduce duplication of the base logic.
There is only one IRQ for each GIO IP block (i.e. several register banks share
an IRQ).
This adds support for the GPIO IP UPG GIO used on Broadcom STB SoCs
(BCM7XXX and some others). Uses basic_mmio_gpio to instantiate a
gpio_chip for each bank. The driver assumes that it handles the base
set of GPIOs on the system and that it can start its numbering sequence
from 0, so any GPIO
Create an irq_chip for each GIO block. Uses chained IRQ handling since
known uses of this block have a BCM7120 L2 interrupt controller as a
parent. Supports interrupts for all GPIOs.
Signed-off-by: Gregory Fong gregory.0...@gmail.com
---
drivers/gpio/Kconfig|1 +
Add binding for Broadcom STB UPG GIO GPIO controller.
Signed-off-by: Gregory Fong gregory.0...@gmail.com
---
.../devicetree/bindings/gpio/brcm,brcmstb-gpio.txt | 65
1 file changed, 65 insertions(+)
create mode 100644
ATAG_REVISION is unsigned number and revision in DT is stored as hexadecimal
string value. It means that it will be correctly parsed by kernel.
Signed-off-by: Pali Rohár pali.ro...@gmail.com
Acked-by: Pavel Machek pa...@ucw.cz
---
arch/arm/boot/compressed/atags_to_fdt.c | 37
This patch adds support for DT /revision and convert ATAG_REVISION to DT.
Pali Rohár (2):
arm: devtree: Set system_rev from DT revision
arm: boot: convert ATAG_REVISION to DT revision field
arch/arm/boot/compressed/atags_to_fdt.c | 37 +++
Kirill A. Shutemov kir...@shutemov.name writes:
On Mon, May 04, 2015 at 10:59:16PM +0530, Aneesh Kumar K.V wrote:
Archs like ppc64 require pte_t * to remain stable in some code path.
They use local_irq_disable to prevent a parallel split. Generic code
clear pmd instead of marking it
I agree that the best solution is to have a generic dmabuf allocator
but no only for secure use cases.
If we create a memory allocator dedicated to security it means that
userland will be responsible to use it or not depending of the context
which may change while the pipeline/graph is already
Since Windows 8 requirement asks below, I see a trend that OEM is
moving wireless to HW-control to SW-control. That's also why some new
systems never trigger hard-blocks. I was also told that there may be
no HW-GPIO (my translation - no hard-block) to control wireless in
some of future systems. I
On Mon, May 4, 2015 at 3:00 PM, Adam Goode a...@spicenitz.org wrote:
On Sat, Apr 25, 2015 at 11:00 PM, Adam Goode a...@spicenitz.org wrote:
Here's the problem:
[0.126595] ACPI Error: No handler for Region [CMS0]
(8802658a0438) [SystemCMOS] (20150410/evregion-163)
[0.126597] ACPI
* Oleg Nesterov o...@redhat.com wrote:
--- a/kernel/signal.c
+++ b/kernel/signal.c
@@ -427,6 +427,10 @@ void flush_signals(struct task_struct *t)
{
unsigned long flags;
+ /* Only kthreads are allowed to destroy signals: */
+ if (WARN_ON_ONCE(!(current-flags
On Tue, May 05, 2015 at 02:16:39AM +0100, Ben Hutchings wrote:
3.2.69-rc1 review patch. If anyone has any objections, please let me know.
--
From: Andy Shevchenko andriy.shevche...@linux.intel.com
commit c9dafb27c84412fe4b17c3b94cc4ffeef5df1833 upstream.
When DMA
Hi all:
I meet a kernel problem about the random segmentation fault(x86_64). In my
testcase, the size of local variables exceeds 20MB.
when run the testcase, it will cause segmentation fault(because the default
stack size limit is 8192KB).
when I increase the stack size limit to
On Wed, May 06, 2015 at 05:10:29PM +0900, Sergey Senozhatsky wrote:
On (05/06/15 16:28), Minchan Kim wrote:
from your logs:
...
[ 98.756017] zram: Removed device: zram2
[ 98.757087] [ cut here ]
...
locked zram_index_mutex, removed zram2, unlocked
This series is for Mediatek SoCs I2C controller common bus driver.
Earlier MTK SoC ((for example, MT6589, MT8135)) I2C HW has some limitationes.
New generation SoC like MT8173 fix following limitations:
1. Only support one i2c_msg number. One exception is WRRD (write then read)
mode. WRRD can
From: Xudong Chen xudong.c...@mediatek.com
Add devicetree bindings for Mediatek Soc I2C driver.
Signed-off-by: Xudong Chen xudong.c...@mediatek.com
Signed-off-by: Eddie Huang eddie.hu...@mediatek.com
---
.../devicetree/bindings/i2c/i2c-mt6577.txt | 41 ++
1 file
Add mediatek MT8173 I2C controller driver. Compare to I2C controller
of earlier mediatek SoC, MT8173 fix write-then-read limitation, and
also increase message size to 64kb.
Signed-off-by: Xudong Chen xudong.c...@mediatek.com
Signed-off-by: Liguo Zhang liguo.zh...@mediatek.com
Signed-off-by: Eddie
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Hi Bjorn,
On 6 May 2015 at 00:16, Bjorn Helgaas bhelg...@google.com wrote:
On Fri, Apr 10, 2015 at 11:12:46AM +0200, Gabriel FERNANDEZ wrote:
sti pcie is built around a Synopsis Designware PCIe IP.
Signed-off-by: Fabrice Gasnier fabrice.gasn...@st.com
Signed-off-by: Gabriel Fernandez
On 05/06/2015 12:09 AM, Nishanth Aravamudan wrote:
On 03.04.2015 [10:45:56 -0700], Nishanth Aravamudan wrote:
What I find somewhat worrying though is that we could potentially
break the pfmemalloc_watermark_ok() test in situations where
zone_reclaimable_pages(zone) == 0 is a transient situation
On Wed 2015-05-06 07:19:31, Dr. H. Nikolaus Schaller wrote:
Hi Peter,
Am 05.05.2015 um 21:54 schrieb Peter Hurley pe...@hurleysoftware.com:
Hi Neil,
On 03/18/2015 01:58 AM, NeilBrown wrote:
here is version 3 of support for tty-slaves.
Is there a v4 of this that I missed?
We
On Wed, May 06, 2015 at 08:11:35AM +0200, Johannes Thumshirn wrote:
Signed-off-by: Johannes Thumshirn jthumsh...@suse.de
---
MAINTAINERS | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 781e099..2943c62 100644
--- a/MAINTAINERS
Since clk_register_clkdev() is exported for modules the caller should get a
pointer to the allocated resources. Otherwise the memory leak is guaranteed on
the -remove() stage.
Cc: Tomeu Vizoso tomeu.viz...@collabora.com
Reviewed-by: Mika Westerberg mika.westerb...@linux.intel.com
Acked-by:
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Reply-To: unicredit0trans...@gmail.com
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Sender: UniCredit International Holdings LLC (unicredit0trans...@gmail.com)
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Telephone: +278
On 06/05/15 12:04, Maxime Ripard wrote:
Hi,
On Wed, May 06, 2015 at 11:31:28AM +0200, Jens Kuske wrote:
The Allwinner H3 is a quad-core Cortex-A7-based SoC. It is very similar
to other sun8i family SoCs like the A23.
Signed-off-by: Jens Kuske jensku...@gmail.com
---
Since clk_register_clkdev() is exported for modules the caller should get a
pointer to the allocated resources. Otherwise the memory leak is guaranteed on
the -remove() stage.
The patch changes the prototype of the clk_register_clkdev() to return a
pointer to the allocated resources. The caller
On Tue, May 05, 2015 at 05:54:05PM +0100, One Thousand Gnomes wrote:
First what is Secure Data Path ? SDP is a set of hardware features to
garanty
that some memories regions could only be read and/or write by specific
hardware
IPs. You can imagine it as a kind of memory firewall which
On NUMA systems, an IO device may be associated with a NUMA node.
It may improve IO performance to allocate resources, such as memory
and interrupts, from device local node.
This patch introduces a mechanism to support CPU vector allocation
policies. It tries to allocate CPU vectors from CPUs on
On 6 May 2015 at 10:02, Valentin Rothberg valentinrothb...@gmail.com wrote:
Hi Joachim,
there are two of your commits [1, 2] in today's linux-next (i.e.,
next-20150506). Both of them add Kconfig options that depend on
ARCH_LPC18XX, which is not defined in Kconfig, see:
+ depends
On 06/05/15 01:22, nick wrote:
Greetings All,
I am wondering if in the function,ni_stc_dma_channel_select_bitfield the line:
return 1 channel;
is guaranteed to be below the threshold that guarantees us to not overflow on
a unsigned 32 integer due to bit wise shifting to the left.
Thanks Nick
On Tue, May 05, 2015 at 10:59:34PM +0100, Mark Brown wrote:
On Tue, May 05, 2015 at 02:31:29PM +0100, Richard Fitzgerald wrote:
We can't really tell people what the selection does because that depends on
the external hardware. The A setting might be a headset mic, or a line in,
or a
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