MSI_EN of iMX PCIe RC would be asserted when
PCIEPORTBUS driver is selected.
Thus, the MSI works fine on iMX PCIe before.
Assert it unconditionally when MSI is supported.
Otherwise, the MSI wouldn't be triggered although
the EP is present and the MSIs are assigned.
Signed-off-by: Richard Zhu
---
> On Dec 13, 2018, at 15:39, Pkshih wrote:
>
> On Thu, 2018-12-13 at 13:36 +0800, Kai Heng Feng wrote:
>>> On Dec 13, 2018, at 08:35, Pkshih wrote:
>>>
>>> On Wed, 2018-12-12 at 13:13 +0800, Kai-Heng Feng wrote:
Once BSS STA mode gets started, it can be scanned by other clients but
Hi Jerome,
Thanks for the fully review, we really appreciate your time.
On 2018/12/12 1:16, Jerome Brunet wrote:
> On Tue, 2018-12-11 at 00:04 +0800, Jianxin Pan wrote:
>> When CLK_DIVIDER_ONE_BASED flag is set, the sclk divider will be:
>> one based divider (div = val), and zero value gates the
On Thu, Dec 13, 2018 at 12:45:00AM +0530, Harsh Shandilya wrote:
> On 11 December 2018 9:10:19 PM IST, Greg Kroah-Hartman
> wrote:
> >This is the start of the stable review cycle for the 4.4.167 release.
> >There are 91 patches in this series, all will be posted as a response
> >to this one. If
On Wed, Dec 12, 2018 at 10:50:56AM -0800, Guenter Roeck wrote:
> On Tue, Dec 11, 2018 at 04:40:19PM +0100, Greg Kroah-Hartman wrote:
> > This is the start of the stable review cycle for the 4.19.9 release.
> > There are 118 patches in this series, all will be posted as a response
> > to this one.
Hi Peter, Ingo,
On Fri, 14 Sep 2018 at 18:26, Vincent Guittot
wrote:
>
> On Fri, 14 Sep 2018 at 05:22, Valentin Schneider
> wrote:
> >
> > Hi,
> >
> > On 10/09/18 07:43, Vincent Guittot wrote:
> > > When CPUs have different capacity because of RT/DL tasks or
> > > micro-architecture or max
On Thu, Dec 13, 2018 at 01:08:08AM -0500, sc...@labau.com.tw wrote:
> From: scott
>
> Add device ids to pl2303 for the HP POS pole displays:
> LM920: 03f0:026b
> TD620: 03f0:0956
> LD960TA: 03f0:4439
> LD220TA: 03f0:4349
> LM940: 03f0:5039
>
> Signed-off-by: scott
I doubt you sign legal
When disassembling InstructionTLBError we get the following messy code:
c000138c: 7d 84 63 78 mr r4,r12
c0001390: 75 25 58 00 andis. r5,r9,22528
c0001394: 75 2a 40 00 andis. r10,r9,16384
c0001398: 41 a2 00 08 beq c00013a0
c000139c: 7c 00
Le 12/12/2018 à 14:05, Michael Ellerman a écrit :
Christophe Leroy writes:
When disassembling InstructionTLBError we get the following messy code:
c000138c: 7d 84 63 78 mr r4,r12
c0001390: 75 25 58 00 andis. r5,r9,22528
c0001394: 75 2a 40 00 andis.
Hi Richard,
One more comment that occurred to me only now.
Richard Zhu writes:
> MSI_EN of iMX PCIe RC would be asserted when
> PCIEPORTBUS driver is selected.
> Thus, the MSI works fine on iMX PCIe before.
> Assert it unconditionally when MSI is supported.
> Otherwise, the MSI wouldn't be
On Wed, 12 Dec 2018 18:20:49 +0100,
Gustavo A. R. Silva wrote:
>
> info.mode and info.port are indirectly controlled by user-space,
> hence leading to a potential exploitation of the Spectre variant 1
> vulnerability.
>
> These issues were detected with the help of Smatch:
>
>
On 12/12/2018 7:32 PM, Jarkko Sakkinen wrote:
On Thu, Dec 06, 2018 at 06:56:33PM +0100, Roberto Sassu wrote:
2 PCR selections
hash TPM_ALG_SHA1
TPMS_PCR_SELECTION length 3
ff ff ff
hash TPM_ALG_SHA256
TPMS_PCR_SELECTION length 3
00 00 00
The pcr_select fields -
On Wed, 12 Dec 2018 22:36:28 +0100,
Gustavo A. R. Silva wrote:
>
> stream is indirectly controlled by user-space, hence leading to
> a potential exploitation of the Spectre variant 1 vulnerability.
>
> This issue was detected with the help of Smatch:
>
> sound/core/pcm.c:140
On Wed, 12 Dec 2018 at 13:22, Pavel Machek wrote:
>
> On Wed 2018-12-12 12:16:43, Krzysztof Kozlowski wrote:
> > Multiple LED triggers might need to access default pattern so add a
> > helper for that.
> >
> > Signed-off-by: Krzysztof Kozlowski
>
> Acked-by: Pavel Machek
>
> >
> > New patch in
> -Original Message-
> From: Baruch Siach [mailto:bar...@tkos.co.il]
> Sent: 2018年12月13日 16:13
> To: Richard Zhu
> Cc: bhelg...@google.com; lorenzo.pieral...@arm.com;
> l.st...@pengutronix.de; andrew.smir...@gmail.com;
> linux-...@vger.kernel.org; linux-kernel@vger.kernel.org;
>
> diff --git a/mm/huge_memory.c b/mm/huge_memory.c
> index f2d19e4fe854..aebade83cec9 100644
> --- a/mm/huge_memory.c
> +++ b/mm/huge_memory.c
> @@ -2145,23 +2145,25 @@ static void __split_huge_pmd_locked(struct
> vm_area_struct *vma, pmd_t *pmd,
>*/
> old_pmd =
Quoting Taniya Das (2018-12-12 23:49:53)
> diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt
> b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt
> new file mode 100644
> index 000..2b82965
> --- /dev/null
> +++
Quoting Pavel Machek (2018-12-12 20:29:02)
> Hi!
>
> > > > > > > > There's one similar for nouveau in Bugzilla, but it seems like
> > > > > > > > a genuine
> > > > > > > > memory corruption (1 bit flipped):
> > > > > > > >
> > > > > > > > https://bugs.freedesktop.org/show_bug.cgi?id=84880
> > >
Hi,
Thank you for the patch.
Fabien
On 12/12/2018 5:27 PM, Yangtao Li wrote:
> We already have the DEFINE_SHOW_ATTRIBUTE. There is no need to define
> bdisp_dbg_declare and hva_dbg_declare, so remove them. Also use
> DEFINE_SHOW_ATTRIBUTE to simplify some code.
>
> Signed-off-by: Yangtao Li
On Thu, 13 Dec 2018 00:07:56 +0100,
Ayman Bagabas wrote:
>
> This patch set is based on the new audio LED triggers in topic/leds-trigger
> branch from
> git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound.git
>
> Changes in v11:
> * Minor code changes
>
> Changes in v10:
> * Use
Linus,
please pull sound fixes for v4.20-rc7 from:
git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound.git
tags/sound-4.20-rc7
The topmost commit is 0bea4cc8383519f78f3f74caca7bdebdfb346d3b
sound fixes for 4.20-rc7
This patch removes unused dump functions for crypto_user_stats.
There are remains of the copy/paste of crypto_user_base to
crypto_user_stat and I forgot to remove them.
Signed-off-by: Corentin Labbe
---
crypto/crypto_user_base.c| 4 +---
crypto/crypto_user_stat.c| 33
This patchs adds missing member of stats documentation.
Signed-off-by: Corentin Labbe
---
include/linux/crypto.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/include/linux/crypto.h b/include/linux/crypto.h
index 9850b41e38ae..81e178fb9ed8 100644
--- a/include/linux/crypto.h
+++
On Wed, 12 Dec 2018 at 13:32, Pavel Machek wrote:
>
> On Wed 2018-12-12 12:16:42, Krzysztof Kozlowski wrote:
> > Document new linux,trigger-pattern property for initialization of LED
> > pattern trigger.
> >
> > Signed-off-by: Krzysztof Kozlowski
> > ---
> >
On Wed, Dec 12, 2018 at 7:53 PM Michal Hocko wrote:
>
> On Wed 12-12-18 16:31:35, Pingfan Liu wrote:
> > On Mon, Dec 10, 2018 at 8:37 PM Michal Hocko wrote:
> > >
> > [...]
> > >
> > > In other words. Does the following work? I am sorry to wildguess this
> > > way but I am not able to recreate
So far the PHY ->xlate() callback was checking if the port was
"invalid" before continuing, meaning that the port has not been used
yet. This check is not correct as there is no opposite call to
->xlate() once the PHY is released by the user and the port will
remain "valid" after the first
Hello,
This series adds a new driver to support Armada 3700 COMPHY IP.
The series has been tested on an ESPRESSObin with SATA, PCIe
and USB3 host. For this purpose, patch 1 enumerates the SATA PHY
mode. The SGMII PHY mode that is supported by the IP has been written
(uses SMC calls anyway) but
The SPICC controller in Meson-AXG is capable of driving the CLK/MOSI/SS
signal lines through the idle state (between two transmission operation),
which avoid the signals floating in unexpected state.
Signed-off-by: Sunny Luo
Signed-off-by: Yixun Lan
---
drivers/spi/spi-meson-spicc.c | 28
The SPICC controller in Meson-AXG SoC is capable of using
a linear clock divider to reach a much fine tuned range of clocks,
while the old controller only use a power of two clock divider,
result at a more coarse clock range.
Also convert the clock registration into Common Clock Framework.
Current file describe COMPHY bindings for the IP available on the
CP110 of Armada 7k/8k. Bindings are very close (and serve the same
purpose) as the new Armada 3700 COMPHY driver so update this file to
describe both. Also add an example of how to use this second
compatible (same as for the
add a few enhanced features for the SPICC controller of Meson-AXG SoC.
These patches are actually quite independent from each other, I send them
together in case to avoid the file conflicts.
Changes since v1 at [1]
- Add OF and COMMON_CLK dependence for SPICC in Kconfig to avoid compiling
Add myself as Armada 3700 COMPHY driver/bindings maintainer.
Signed-off-by: Miquel Raynal
---
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 72e930c51fd4..2ef7a60ab24b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8865,6 +8865,12 @@ F:
Add a driver to support COMPHY, a hardware block providing shared
serdes PHYs on Marvell Armada 3700. This driver uses SMC calls and
rely on having an up-to-date firmware.
SATA, PCie and USB3 host mode have been tested successfully with an
ESPRESSObin. (HS)SGMII mode cannot be tested with this
The SPICC controller in Meson-AXG is capable of running at 80M clock.
The ASIC IP is improved and the clock is actually running higher than
previous old SoCs.
Signed-off-by: Sunny Luo
Signed-off-by: Yixun Lan
---
drivers/spi/spi-meson-spicc.c | 37 +
1 file
From: Grzegorz Jaszczyk
Add SATA mode to the PHY framework in preparation of upcoming PHYs
that will handle it. For instance, SATA mode will be used by the
Armada3700 COMPHY driver, which supports configuring SERDES lanes to
be used by various controllers: Ethernet, USB3, SATA and PCIe.
Fix the SATA IP memory area which is only 0x178 bytes long (from
Marvell A3700 specification). Actually, starting from the offset
0xe0178, there is an area dedicated to the COMPHY driver.
Suggested-by: Grzegorz Jaszczyk
Signed-off-by: Miquel Raynal
---
Describe the A3700 COMPHY node. It has three PHYs that can be
configured as follow:
* PCIe or GbE
* USB3 or GbE
* SATA or USB3
Each of them has its own memory area.
Suggested-by: Grzegorz Jaszczyk
Signed-off-by: Miquel Raynal
---
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 29
Some systems, for example embedded systems, do not generate
enough entropy on boot through interrupts, and boot may be blocked for
several minutes waiting for a call to getrandom to complete.
Currently, random data is read from a hwrng when it is registered,
and is loaded into primary_crng. This
On 12 December 2018 at 3:39PM, Christian Zigotzky wrote:
Hi Christoph,
Thanks a lot for your reply. I will test your patches tomorrow.
Cheers,
Christian
Sent from my iPhone
On 12. Dec 2018, at 15:15, Christoph Hellwig wrote:
Thanks for bisecting. I've spent some time going over the
Hi Richard,
Richard Zhu writes:
>> -Original Message-
>> From: Baruch Siach [mailto:bar...@tkos.co.il]
>> Sent: 2018年12月13日 16:13
>> To: Richard Zhu
>> Cc: bhelg...@google.com; lorenzo.pieral...@arm.com;
>> l.st...@pengutronix.de; andrew.smir...@gmail.com;
>> linux-...@vger.kernel.org;
A kernel built for generic UP Alpha had been noted to fail to boot
for quite some time (since the release of 3.18). The kernel either
locks up before printing any messages to the console or just falls
back into the SRM with a HALT instruction again before any messages
are printed to the console.
On Thu, Dec 13, 2018 at 02:48:59PM +1100, NeilBrown wrote:
>
> Yes, you could rcu_free the old one and allocate a new one. Then you
> would have to be ready to deal with memory allocation failure which
> complicates usage (I already don't like that rhashtable_insert() can
> report -ENOMEM!).
On Tue 11-12-18 14:53:12, Oscar Salvador wrote:
> v1 -> v2:
> - Keep branch to decrease refcount and print out
> the failed pfn/page
> - Modified changelog per Michal's feedback
> - move put_page() out of the if/else branch
>
> ---
> >From
Hi Sunny,
On 13/12/2018 09:39, Sunny Luo wrote:
> The SPICC controller in Meson-AXG is capable of running at 80M clock.
> The ASIC IP is improved and the clock is actually running higher than
> previous old SoCs.
>
> Signed-off-by: Sunny Luo
> Signed-off-by: Yixun Lan
> ---
>
If all free_nat_bitmap are available, we can rebuild nat_bits from
free_nat_bitmap entirely during umount, let's make another chance
to reenable nat_bits for image.
Signed-off-by: Chao Yu
---
v2:
- fix bugs in f2fs_enable_nat_bits()
- add kmsg to record nat_bits {en,dis}abling operations
- fix
On Thu, Dec 13, 2018 at 04:40:17PM +0800, Louis Collard wrote:
> Some systems, for example embedded systems, do not generate
> enough entropy on boot through interrupts, and boot may be blocked for
> several minutes waiting for a call to getrandom to complete.
>
> Currently, random data is read
On Wed, Dec 12, 2018 at 11:54:32AM +0100, Thierry Reding wrote:
> On Mon, Oct 01, 2018 at 04:19:48PM +0200, Michal Vokáč wrote:
> > Implement the get_state() function and set the initial state to reflect
> > real state of the hardware. This allows to keep the PWM running if it was
> > enabled in
On Wed, Dec 12, 2018 at 7:36 PM Anders Roxell wrote:
>
> When option CONFIG_KASAN is enabled toghether with ftrace, function
> ftrace_graph_caller() gets in to a recursion, via functions
> kasan_check_read() and kasan_check_write().
>
> Breakpoint 2, ftrace_graph_caller () at
>
Hi Sunny,
On 13/12/2018 09:39, Sunny Luo wrote:
> The SPICC controller in Meson-AXG is capable of driving the CLK/MOSI/SS
> signal lines through the idle state (between two transmission operation),
> which avoid the signals floating in unexpected state.
This is welcome, because it's really
Hi Paul,
On Thu, 13 Dec 2018 at 03:58, Paul Burton wrote:
>
> Hi Firoz,
>
> On Wed, Dec 12, 2018 at 10:04:47AM +0530, Firoz Khan wrote:
> >
> > Sure, I think '64' to 'n64' conversion must be remove it from this patch
> > series.I can send v5 without '64' to 'n64' conversion.
> >
> > If we rename
On 12/12/2018 18:10, Ard Biesheuvel wrote:
> On Wed, 12 Dec 2018 at 18:59, Julien Thierry wrote:
>>
>>
>>
>> On 12/12/2018 17:27, Ard Biesheuvel wrote:
>>> On Wed, 12 Dec 2018 at 17:48, Julien Thierry wrote:
Instead disabling interrupts by setting the PSR.I bit, use a priority
Hi Sunny,
On 13/12/2018 09:39, Sunny Luo wrote:
> The SPICC controller in Meson-AXG SoC is capable of using
> a linear clock divider to reach a much fine tuned range of clocks,
> while the old controller only use a power of two clock divider,
> result at a more coarse clock range.
This patch
Hello,
On Wed, Dec 12, 2018 at 12:04:51PM +, Vokáč Michal wrote:
> Normally the PWM output is held LOW when PWM is disabled. This can cause
> problems when inverted PWM signal polarity is needed. With this behavior
> the connected circuit is fed by 100% duty cycle instead of being shut-off.
>
On (12/13/18 05:54), Dmitry Safonov wrote:
> > I thought about it for a second, but couldn't figure out if this race
> > was real.
> >
> > E.g. uart case - if there are two paths which concurrently free and
> > access debug object, then the same race condition should exist for
> > the xmit.buf
Quoting Lorenzo Pieralisi (2018-12-11 06:16:27)
> On Tue, Dec 04, 2018 at 10:42:19PM +0100, Rafael J. Wysocki wrote:
> > On Tuesday, December 4, 2018 10:45:58 AM CET Lorenzo Pieralisi wrote:
> > > On Mon, Dec 03, 2018 at 11:00:20PM +0100, Rafael J. Wysocki wrote:
> > > > On Monday, December 3,
On Thu, 2018-12-13 at 12:55 +0800, Jianxin Pan wrote:
> On 2018/12/12 0:59, Jerome Brunet wrote:
> > On Tue, 2018-12-11 at 00:04 +0800, Jianxin Pan wrote:
> > > From: Yixun Lan
> > >
> [...]
> > >
> > > +config COMMON_CLK_MMC_MESON
> > > + tristate "Meson MMC Sub Clock Controller Driver"
> > >
--
Hello Dear ,
I came across your contact during my private search
Mrs Aisha Al-Qaddafi is my name, the only daughter of late Libyan
president, I have funds the sum
of $27.5 million USD for investment, I am interested in you for
investment project assistance in your country,
i shall compensate
On Thu, Dec 13, 2018 at 04:43:57PM +0900, Tomasz Figa wrote:
> Hi Helen,
>
> On Sat, Nov 24, 2018 at 6:54 AM Helen Koike wrote:
> >
> > This flag tells core to jump ahead the queued update if the conditions
> > in drm_atomic_async_check() are met. That means we are only able to do an
> > async
NR_syscalls macro holds the number of system call exist
in powerpc architecture. We have to change the value of
NR_syscalls, if we add or delete a system call.
One of the patch in this patch series has a script which
will generate a uapi header based on syscall.tbl file.
The syscall.tbl file
On Thu, Dec 13, 2018 at 4:37 PM Pingfan Liu wrote:
>
> On Wed, Dec 12, 2018 at 7:53 PM Michal Hocko wrote:
> >
> > On Wed 12-12-18 16:31:35, Pingfan Liu wrote:
> > > On Mon, Dec 10, 2018 at 8:37 PM Michal Hocko wrote:
> > > >
> > > [...]
> > > >
> > > > In other words. Does the following work?
The purpose of this patch series is, we can easily
add/modify/delete system call table support by cha-
nging entry in syscall.tbl file instead of manually
changing many files. The other goal is to unify the
system call table generation support implementation
across all the architectures.
The
Move the macro definition for compat_sys_sigsuspend from
asm/systbl.h to the file which it is getting included.
One of the patch in this patch series is generating uapi
header and syscall table files. In order to come up with
a common implimentation across all architecture, we need
to do this
System call table generation script must be run to gener-
ate unistd_32/64.h and syscall_table_32/64/c32/spu.h files.
This patch will have changes which will invokes the script.
This patch will generate unistd_32/64.h and syscall_table-
_32/64/c32/spu.h files by the syscall table generation
The system call tables are in different format in all
architecture and it will be difficult to manually add or
modify the system calls in the respective files. To make
it easy by keeping a script and which will generate the
uapi header and syscall table file. This change will also
help to unify
PowerPC uses a syscall table with native and compat calls
interleaved, which is a slightly simpler way to define two
matching tables.
As we move to having the tables generated, that advantage
is no longer important, but the interleaved table gets in
the way of using the same scripts as on the
On Thu, 2018-12-13 at 16:39 +0800, Sunny Luo wrote:
> The SPICC controller in Meson-AXG is capable of driving the CLK/MOSI/SS
> signal lines through the idle state (between two transmission operation),
> which avoid the signals floating in unexpected state.
>
> Signed-off-by: Sunny Luo
>
On Thu, Dec 13, 2018 at 6:03 AM Kevin Easton wrote:
>
> On Tue, Dec 11, 2018 at 11:29:14AM +0100, John Paul Adrian Glaubitz wrote:
> ...
> > I can't say anything about the syscall interface. However, what I do know
> > is that the weird combination of a 32-bit userland with a 64-bit kernel
> >
Qcom's implementation of arm,mmu-500 works well with current
arm-smmu driver implementation. Adding a soc specific compatible
along with arm,mmu-500 makes the bindings future safe.
Signed-off-by: Vivek Gautam
Reviewed-by: Rob Herring
Cc: Will Deacon
---
Hi Joerg,
I am picking this out
Hi Keith,
I love your patch! Yet something to improve:
[auto build test ERROR on pm/linux-next]
[also build test ERROR on v4.20-rc6]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
The purpose of this patch series is, we can easily
add/modify/delete system call table support by cha-
nging entry in syscall.tbl file instead of manually
changing many files. The other goal is to unify the
system call table generation support implementation
across all the architectures.
The
When we get nanoMIPS support we'll be introducing the p32
ABI, and there's a reasonable chance that the equivalent
p64 ABI may come along in the future. Using 'n64' now would
avoid confusion in that case where we may have 2 different
64-bit ABIs.
Suggested-by: Paul Burton
Signed-off-by: Firoz
All other architectures are hold a value for __NR_syscalls will
be equal to the last system call number +1.
But in mips architecture, __NR_syscalls hold the value equal to
total number of system exits in the architecture. One of the
patch in this patch series will genarate uapi header files.
In
__NR_Linux_syscalls macro holds the number of system call
exist in mips architecture. We have to change the value of
__NR_Linux_syscalls, if we add or delete a system call.
One of the patch in this patch series has a script which
will generate a uapi header based on syscall.tbl file.
The
The config flag - CONFIG_MIPS_MT_FPAFF uses to check whether which
syscall entries need to be used in scall32-o32.S file.
One of the patch in this patch series will generate syscall table
file. But CONFIG_MIPS_MT_FPAFF flag will add more complexity in the
script to generate the syscall table
Remove NR_syscalls from asm/unistd.h as there is no
users to use NR_syscalls macro in mips kernel.
Remove __NR_Linux_syscalls from uapi/asm/unistd.h as
there is no users to use NR_syscalls macro in mips
kernel.
MAX_SYSCALL_NO can also remove as there is commit
2957c9e61ee9 ("[MIPS] IRIX: Goodbye
The system call tables are in different format in all
architecture and it will be difficult to manually add,
modify or delete the syscall table entries in the res-
pective files. To make it easy by keeping a script and
which will generate the uapi header and syscall table
file. This change will
System call table generation script must be run to gener-
ate unistd_(nr_)n64/n32/o32.h and syscall_table_32_o32/
64_n64/64_n32/64-o32.h files. This patch will have changes
which will invokes the script.
This patch will generate unistd_(nr_)n64/n32/o32.h and
On 10.12.18 18:12, Vivek Goyal wrote:
> Instead of assuming we had the fixed bar for the cache, use the
> value from the capabilities.
>
> Signed-off-by: Dr. David Alan Gilbert
> ---
> fs/fuse/virtio_fs.c | 32 +---
> 1 file changed, 17 insertions(+), 15 deletions(-)
On Thu, Dec 13, 2018 at 09:41:50AM +0100, Christian Zigotzky wrote:
> Today I tried the first patch (0001-get_required_mask.patch) with the last
> good commit (977706f9755d2d697aa6f45b4f9f0e07516efeda). Unfortunately this
> patch is already included in the last good commit
>
Hi,
On 06/12/2018 23:44, Jeremy Linton wrote:
> From: Mian Yousaf Kaukab
>
> Add is_meltdown_safe() which is a whitelist of known safe cores.
>
> Signed-off-by: Mian Yousaf Kaukab
> [Moved location of function]
> Signed-off-by: Jeremy Linton
> ---
> arch/arm64/kernel/cpufeature.c | 16
* David Hildenbrand (da...@redhat.com) wrote:
> On 10.12.18 18:12, Vivek Goyal wrote:
> > Instead of assuming we had the fixed bar for the cache, use the
> > value from the capabilities.
> >
> > Signed-off-by: Dr. David Alan Gilbert
> > ---
> > fs/fuse/virtio_fs.c | 32
On 13-12-18, 13:19, Taniya Das wrote:
> The CPUfreq HW present in some QCOM chipsets offloads the steps necessary
> for changing the frequency of CPUs. The driver implements the cpufreq
> driver interface for this hardware engine.
>
> Signed-off-by: Saravana Kannan
> Signed-off-by: Stephen Boyd
On Tue, 2018-12-11 at 21:20 +0100, Wolfram Sang wrote:
> On Mon, Dec 03, 2018 at 09:32:51PM +0800, qii.w...@mediatek.com wrote:
> > From: qii wang
> >
> > Completion_done is useless when we don't use its return value,
> > so we remove it. Different speeds have been defined by macros,
> > so we
Sasha Levin writes:
> From: Alexey Khoroshilov
>
> [ Upstream commit 05cc09de4c017663a217630682041066f2f9a5cd ]
>
> There is no unregister netlink notifier and family on error paths
> in init_mac80211_hwsim(). Also there is an error path where
> hwsim_class is not destroyed.
>
> Found by Linux
Hi Oza,
Thank you for the review.
Please find my comments in lined.
On Thu, Dec 13, 2018 at 11:33 AM wrote:
>
> On 2018-12-12 11:16, Srinath Mannam wrote:
> > IPROC host has the limitation that it can use
> > only those address ranges given by dma-ranges
> > property as inbound address.
> > So
When user space do memory recovery, it will check whether KVM and
guest support the error recovery, only when both of them support,
user space will do the error recovery. This patch exports this
capability of KVM to user space.
Cc: Peter Maydell
Signed-off-by: Dongjiu Geng
---
User space needs
On Thu, Dec 13, 2018 at 01:58:39PM +0900, Sergey Senozhatsky wrote:
> LKP has hit yet another circular locking dependency between uart
> console drivers and debugobjects [1]:
>
> CPU0CPU1
>
> rhltable_init()
>
On Wed, Dec 12, 2018 at 11:09:07PM +0100, Paul Cercueil wrote:
> The TCU channels 0 and 1 were previously reserved for system tasks, and
> thus unavailable for PWM.
>
> The driver will now only allow a PWM channel to be requested if memory
> resources corresponding to the register area of the
Some systems, for example embedded systems, do not generate
enough entropy on boot through interrupts, and boot may be blocked for
several minutes waiting for a call to getrandom to complete.
Currently, random data is read from a hwrng when it is registered,
and is loaded into primary_crng. This
> -Original Message-
> From: linux-kernel-ow...@vger.kernel.org ow...@vger.kernel.org> On Behalf Of Olof Johansson
> Sent: Thursday, December 13, 2018 8:48 AM
> To: Horia Geanta
> Cc: Marc Gonzalez ; arm-soc ;
> Linux ARM ; LKML ker...@vger.kernel.org>
> Subject: Re: [PATCH v3 7/9]
Hi Richard,
Am Donnerstag, den 13.12.2018, 08:02 + schrieb Richard Zhu:
> MSI_EN of iMX PCIe RC would be asserted when
> PCIEPORTBUS driver is selected.
> Thus, the MSI works fine on iMX PCIe before.
> Assert it unconditionally when MSI is supported.
> Otherwise, the MSI wouldn't be triggered
>> Under normal circumstances,When do_exit exits, mm->owner will
>> be updated on exit_mm(). but when the kernel process calls
>> unuse_mm() and then exits,mm->owner cannot be updated. And it
>> will point to a task that has been released.
>>
>> Below is my issue on vhost_net:
>> A,
This reverts commit 82db33dc5e49fb625262d81125625d07a0d6184e.
After the commit 29859aeb8a6e ("iommu/io-pgtable-arm-v7s: Abort
allocation when table address overflows the PTE"), v7s will return fail
if the page table allocation isn't expected. this PHYS_OFFSET check
is unnecessary now.
And this
On Thu, Dec 13, 2018 at 4:51 PM Herbert Xu wrote:
>
> On Thu, Dec 13, 2018 at 04:40:17PM +0800, Louis Collard wrote:
> > Some systems, for example embedded systems, do not generate
> > enough entropy on boot through interrupts, and boot may be blocked for
> > several minutes waiting for a call to
On Tue, Dec 11, 2018 at 6:19 PM Roger Quadros wrote:
>
> Pawel,
>
> On 10/12/18 14:39, Pawel Laszczak wrote:
> > This patch aim at documenting USB related dt-bindings for the
> > Cadence USBSS-DRD controller.
> >
> > Signed-off-by: Pawel Laszczak
> > ---
> >
Revert the following commits:
- 5bdcd510c2ac9efaf55c4cbd8d46421d8e2320cd
("x86/jump-labels: Macrofy inline assembly code to work around GCC inlining
bugs")
- d5a581d84ae6b8a4a740464b80d8d9cf1e7947b2
("x86/cpufeature: Macrofy inline assembly code to work around GCC inlining
bugs")
-
On Thu, Dec 13, 2018 at 11:59:40AM +0900, Sergey Senozhatsky wrote:
> On (12/12/18 17:28), Waiman Long wrote:
> >
> > warning from lockdep as reported in https://lkml.org/lkml/2018/12/11/143.
> >
>
> That link shows an empty page, lkml.org is quite unstable. Let's
> use this one instead:
>
>
From: Michal Hocko
Liu Bo has experienced a deadlock between memcg (legacy) reclaim and the
ext4 writeback
task1:
[] wait_on_page_bit+0x82/0xa0
[] shrink_page_list+0x907/0x960
[] shrink_inactive_list+0x2c7/0x680
[] shrink_node_memcg+0x404/0x830
[] shrink_node+0xd8/0x300
[]
On Tue, 11 Dec 2018, Enric Balletbo i Serra wrote:
> There are multiple ChromeOS EC sub-drivers spread in different
> subsystems, as all of them are related to the Chrome stuff add
> Benson and myself as a maintainers for all these sub-drivers.
>
> Signed-off-by: Enric Balletbo i Serra
> ---
>
Hi Jeremy,
On 06/12/2018 23:44, Jeremy Linton wrote:
> Add a simple state machine which will track whether
> all the online cores in a machine are vulnerable.
>
> Once that is done we have a fairly authoritative view
> of the machine vulnerability, which allows us to make a
> judgment about
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