Added suspend/resume pm ops. We need to store current regs vals on suspend and
restore them on resume.
Signed-off-by: Dmitry Osipenko
---
Tested on my tablet.
drivers/pinctrl/pinctrl-tegra.c | 94 +++--
1 file changed, 91 insertions(+), 3 deletions(-)
diff
Fixed err msg params order on irq request fail.
Signed-off-by: Dmitry Osipenko
---
drivers/dma/tegra20-apb-dma.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/dma/tegra20-apb-dma.c b/drivers/dma/tegra20-apb-dma.c
index 528c62d..4d816be 100644
--- a/drivers/dma
.
This happens because tegra_dma_abort_all() won't be called on channel freeing
if pending list is empty.
Signed-off-by: Dmitry Osipenko
---
drivers/dma/tegra20-apb-dma.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/dma/tegra20-apb-dma.c b/drivers/dma/tegra20-apb-dma.c
index 4d816be..
allocations.
Signed-off-by: Dmitry Osipenko
---
drivers/dma/tegra20-apb-dma.c | 60 ++-
1 file changed, 25 insertions(+), 35 deletions(-)
diff --git a/drivers/dma/tegra20-apb-dma.c b/drivers/dma/tegra20-apb-dma.c
index 4d816be..5a557af 100644
--- a/drivers
Also code looks not thread-safe, is it ok? For example we can protect prepare
functions with a spinlock and add tegra_dma_terminate_all_locked for calling on
channel freeing under spinlock to avoid reschedule. What do you think?
--
To unsubscribe from this list: send the line "unsubscribe linux-ke
This prevents playing sound with wrong speed.
Signed-off-by: Dmitry Osipenko
---
I'm using deep sleep on my tablet and faced with this bug when played sound via
hdmi after suspend. I know that there is no deep sleep support in upstream
kernel,
but will be nice to see that bug fixed.
soun
Use device_init_wakeup() instead of device_set_wakeup_capable() and move it
before rtc dev registering. This fixes issue with alarmtimer that checks wakeup
capability with device_may_wakeup() on device add.
Signed-off-by: Dmitry Osipenko
---
drivers/rtc/rtc-tps6586x.c | 3 ++-
1 file changed, 2
Use device_init_wakeup() instead of device_set_wakeup_capable() and move it
before rtc dev registering. This fixes alarmtimer not registered when tps6586x
rtc is the only wakeup compatible rtc in the system.
Signed-off-by: Dmitry Osipenko
---
V2: changed description
drivers/rtc/rtc-tps6586x.c
23.05.2013 02:22, Andrew Morton пишет:
> On Sun, 12 May 2013 18:25:06 +0400 Dmitry Osipenko wrote:
>
>> Use device_init_wakeup() instead of device_set_wakeup_capable() and move it
>> before rtc dev registering. This fixes issue with alarmtimer that checks
>> w
tps6586x MFD spews hundreds of "failed to read interrupt status" KMSG's on
resume from suspend with eventual disablement of the IRQ when tps6586x's
RTC wakes the system. This happens because IRQ gets handled before I2C been
resumed.
Signed-off-by: Dmitry Osipenko
---
drivers
Chromakey is a simple way of video overlay overlap implementation. This
patch adds 2 new IOCTL's: first - sets color key and is common across of
all Tegra SoC's, second - sets plane blending controls and allows to
utilize the color key, this one is exclusive to Tegra20/30.
Signed-off-
Overlay plane should be clipped, otherwise overlay output gets distorted
once plane crosses display boundary. As a "side effect" this patch also
adds a sanity check for the primary plane, insuring that it covers whole
display area.
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/
del
> ---
> drivers/iommu/tegra-gart.c | 26 ++
> 1 file changed, 26 insertions(+)
>
Reviewed-by: Dmitry Osipenko
Tested-by: Dmitry Osipenko
> diff --git a/drivers/iommu/tegra-gart.c b/drivers/iommu/tegra-gart.c
> index 29bafc6..b62f790 100644
> --- a/
On 17.08.2017 16:52, Thierry Reding wrote:
> On Thu, Aug 17, 2017 at 01:21:52AM +0300, Dmitry Osipenko wrote:
>> Hello Joerg,
>>
>> On 10.08.2017 01:29, Joerg Roedel wrote:
>>> From: Joerg Roedel
>>>
>>> Add a struct iommu_device to each tegra-ga
d on Tegra20.
Reviewed-by: Dmitry Osipenko
Tested-by: Dmitry Osipenko
--
Dmitry
On 18.10.2017 00:13, Rob Herring wrote:
> On Tue, Oct 17, 2017 at 3:24 PM, Thierry Reding
> wrote:
>> On Tue, Oct 17, 2017 at 03:13:54PM -0500, Rob Herring wrote:
>> [...]
diff --git
a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-vde.txt
b/Documentation/devicetree/bi
On 11.11.2017 00:15, Dmitry Osipenko wrote:
> On 07.11.2017 18:29, Dmitry Osipenko wrote:
>> On 07.11.2017 16:11, Mikko Perttunen wrote:
>>> On 05.11.2017 19:14, Dmitry Osipenko wrote:
>>>> On 05.11.2017 14:01, Mikko Perttunen wrote:
>>>>> Add an opti
On 11.11.2017 17:06, Vladimir Zapolskiy wrote:
> Hi Dmitry,
>
> I'll add just a couple of minor comments, in general the code looks
> very good.
>
Thank you very much for the review!
> On 10/20/2017 12:34 AM, Dmitry Osipenko wrote:
>> NVIDIA Tegra20/30/114/124
On 11.11.2017 17:21, Vladimir Zapolskiy wrote:
> Hi Dmitry,
>
> On 10/20/2017 12:34 AM, Dmitry Osipenko wrote:
>> Add binding documentation for the Video Decoder Engine which is found
>> on NVIDIA Tegra20/30/114/124/132 SoC's.
>>
>> Signed-off-by: Dmit
On 11.11.2017 17:18, Vladimir Zapolskiy wrote:
> Hi Dmitry,
>
> On 10/20/2017 12:34 AM, Dmitry Osipenko wrote:
>> From: Vladimir Zapolskiy
>>
>> All Tegra SoCs contain 256KiB IRAM, which is used to store CPU resume code
>> and by hardware engines like a v
On 07.11.2017 15:29, Mikko Perttunen wrote:
> On 05.11.2017 19:43, Dmitry Osipenko wrote:
>> On 05.11.2017 14:01, Mikko Perttunen wrote:
>>> In the traditional channel allocation model, a single hardware channel
>>> was allocated for each client. This is si
On 03.11.2017 16:07, Marcel Ziswiler wrote:
> Hi Rafael, dear community
>
> One of our customers reported seeing freezes when running the LTS Linux
> kernel 4.9.x on our Toradex Colibri T20 modules [1]. I was able to
> reproduce a complete SoC lock-up after a few minutes also running the
> latest
On 04.11.2017 23:49, Marcel Ziswiler wrote:
> On Fri, 2017-11-03 at 21:52 +0300, Dmitry Osipenko wrote:
>> I haven't seen any problems with the cpuidle on next and 4.14-rc7
>> works fine.
>>
>> # cat /sys/devices/system/cpu/cpu[0-1]/cpuidle/state[0-1]/usage
>&
On 05.11.2017 14:01, Mikko Perttunen wrote:
> Host1x has a feature called MLOCKs which allow a certain class
> (~HW unit) to be locked (in the mutex sense) and unlocked during
> command execution, preventing other channels from accessing the
> class while it is locked. This is necessary to prevent
On 05.11.2017 14:01, Mikko Perttunen wrote:
> Add an option to host1x_channel_request to interruptibly wait for a
> free channel. This allows IOCTLs that acquire a channel to block
> the userspace.
>
Wouldn't it be more optimal to request channel and block after job's pining,
when all patching an
On 05.11.2017 14:01, Mikko Perttunen wrote:
> In the traditional channel allocation model, a single hardware channel
> was allocated for each client. This is simple from an implementation
> perspective but prevents use of hardware scheduling.
>
> This patch implements a channel allocation model wh
Compile Tegra VDE driver as a module.
Signed-off-by: Dmitry Osipenko
---
arch/arm/configs/tegra_defconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index 6678f2929356..c931bd48f7fd 100644
--- a/arch
- Changed 'TODO'
- CC'd media maintainers for the review as per Greg's K-H request,
v1 can be viewed at https://lkml.org/lkml/2017/9/25/606
Dmitry Osipenko (4):
media: dt: bindings: Add binding for NVIDIA Tegra Video Decoder Engine
staging: Introduce
NVIDIA Tegra20/30/114/124/132 SoC's have video decoder engine that
supports standard set of video formats like H.264 / MPEG-4 / WMV / VC1.
Currently implemented decoding of CAVLC H.264 on Tegra20 only.
Signed-off-by: Dmitry Osipenko
---
drivers/staging/Kconfig|2 +
dr
Add binding documentation for the Video Decoder Engine which is found
on NVIDIA Tegra20/30/114/124/132 SoC's.
Signed-off-by: Dmitry Osipenko
---
.../devicetree/bindings/media/nvidia,tegra-vde.txt | 55 ++
1 file changed, 55 insertions(+)
create mode 100644 Document
Add Video Decoder Engine device node.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra20.dtsi | 27 +++
1 file changed, 27 insertions(+)
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index aaf32f96f1e8..6b2d7bf5c707 100644
--- a
From: Vladimir Zapolskiy
All Tegra SoCs contain 256KiB IRAM, which is used to store CPU resume code
and by hardware engines like a video decoder.
Signed-off-by: Vladimir Zapolskiy
---
arch/arm/boot/dts/tegra114.dtsi | 8
arch/arm/boot/dts/tegra124.dtsi | 8
arch/arm/boot/dts/
30.06.2015 17:15, Dmitry Osipenko пишет:
Commit 72daceb9a10a ("net: rfkill: gpio: Add default GPIO driver mappings
for ACPI") removed possibility to request GPIO by table index for non-ACPI
platforms without changing it users. As result "shutdown" GPIO request
will fail i
28.06.2015 22:27, Dmitry Osipenko пишет:
MLOCK's debug info, spewed on CDMA timeout, contains meaningless MLOCK
owner channel ID because HOST1X_SYNC_MLOCK_OWNER_CHID_F() returns shifted
value, while unshifted should be used. Fix it by changing '_F' to '_V'.
Signe
On Tuesday, 8 May 2018 19:58:41 MSK Dmitry Osipenko wrote:
> Currently Memory Controller informs about erroneous memory accesses done
> by memory clients and that's it. Let's make it to block whole HW unit
> that corresponds to the misbehaving memory client in order to tr
On Friday, 3 August 2018 20:24:56 MSK Linus Walleij wrote:
> On Thu, Aug 2, 2018 at 1:31 PM Stefan Agner wrote:
> > A while back at least using those init lists were not well received even
> > for GPIO/pinctrl drivers:
> >
> > https://lore.kernel.org/lkml/CACRpkdYk0zW12qNXgOstTLmdVDYacu0Un+8quTN+
On Sunday, 5 August 2018 03:11:57 MSK Mikko Perttunen wrote:
> One potential issue is with host1x clients where userspace processes can
> submit jobs with invalid memory accesses (addresses not mapped to
> IOMMU). If when such a failure happens, we disable the DMA for the whole
> host1x client, unr
TRL driver registration to the arch_init level and GPIO to the
subsys_init.
Signed-off-by: Dmitry Osipenko
Acked-by: Stefan Agner
---
Changelog:
v2: Corrected commit message with s/to suspend after/to suspend before/.
drivers/pinctrl/tegra/pinctrl-tegra114.c | 7 ++-
drivers/pinctrl/tegra/pinctrl-
TRL driver registration to the arch_init level and GPIO to the
subsys_init.
Signed-off-by: Dmitry Osipenko
Acked-by: Stefan Agner
---
Changelog:
v2: Corrected commit message with s/to suspend after/to suspend before/.
drivers/gpio/gpio-tegra.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
di
On Thursday, 2 August 2018 16:01:24 MSK Dmitry Osipenko wrote:
> On Thursday, 2 August 2018 14:11:43 MSK Dmitry Osipenko wrote:
> > There is a bug in regards to deferred probing within the drivers core
> > that causes GPIO-driver to suspend after its users. The bug appears if
>
On Monday, 6 August 2018 16:03:01 MSK Stefan Agner wrote:
> On 04.08.2018 16:01, Dmitry Osipenko wrote:
> > On Friday, 3 August 2018 20:24:56 MSK Linus Walleij wrote:
> >> On Thu, Aug 2, 2018 at 1:31 PM Stefan Agner wrote:
> >> > A while back at least using those ini
t, then
destroy sysfs data and finally release the cooling device.
Cc: # v4.17+
Fixes: 8ea229511e06 ("thermal: Add cooling device's statistics in sysfs")
Signed-off-by: Dmitry Osipenko
---
drivers/thermal/thermal_core.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
On Thursday, 26 July 2018 20:48:55 MSK Peter Geis wrote:
> On 07/26/2018 01:36 PM, Stefan Agner wrote:
> > On 26.07.2018 18:39, Peter Geis wrote:
> >> I finally got around to testing this on the Ouya (Tegra 3).
> >
> > Thanks for testing!
> >
> >> I found that the "Got command
On Friday, 27 July 2018 23:19:53 MSK Peter Geis wrote:
> Kingston KE4CN3K6A.
> Though I am pretty sure I've figured out the instability.
> Brought it in to work and hooked it to a scope.
> Couldn't find clock, but cmd and all eight bits are running at 1.2 volts.
> Repeated the results with the boot
EMC has a dedicated interrupt that is used to notify about completion of
HW operations. Document the interrupt property.
Signed-off-by: Dmitry Osipenko
Acked-by: Rob Herring
Acked-by: Peter De Schrijver
---
.../devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt| 2 ++
1 file changed
Add interrupt entry into the EMC DT node.
Signed-off-by: Dmitry Osipenko
Acked-by: Peter De Schrijver
---
arch/arm/boot/dts/tegra20.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 15b73bd377f0..9eb4163a4390 100644
Introduce driver for the External Memory Controller (EMC) found on Tegra20
chips, which controls the external DRAM on the board. The purpose of this
driver is to program memory timing for external memory on the EMC clock
rate change.
Signed-off-by: Dmitry Osipenko
Acked-by: Peter De Schrijver
Ensure that direct PLLM sourcing is turned off for EMC as we don't support
that configuration in the clk driver.
Signed-off-by: Dmitry Osipenko
Acked-by: Peter De Schrijver
---
drivers/clk/tegra/clk-tegra20.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/clk/tegr
- Minor code cleanups like consistent use of writel_relaxed instead
of non-relaxed version, reworded error messages, etc.
- Factored out use_pllm_ud bit checking into a standalone patch for
consistency.
Dmitry Osipenko (8):
dt: bindings: tegra20-emc: Document interr
Kernel should never gate the EMC clock as it causes immediate lockup, so
removing clk-gate functionality doesn't affect anything. Turning EMC clk
gate into divider allows to implement glitch-less EMC scaling, avoiding
reparenting to a backup clock.
Signed-off-by: Dmitry Osipenko
Acked-by:
Add clock entry into the EMC DT node.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra20.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 9eb4163a4390..979f38293fe5 100644
--- a/arch/arm/boot/dts/tegra20
Embedded memory controller has a corresponding clock, document the clock
property.
Signed-off-by: Dmitry Osipenko
Acked-by: Rob Herring
---
.../devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt| 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings
Move tegra20-emc binding to the memory-controllers directory for
consistency with the other Tegra memory bindings.
Signed-off-by: Dmitry Osipenko
Acked-by: Rob Herring
---
.../{arm/tegra => memory-controllers}/nvidia,tegra20-emc.txt | 0
1 file changed, 0 insertions(+), 0 deleti
This fixes irrelevant "tegra-mc 7000f000.memory-controller: no memory
timings for RAM code 0 registered" warning message during of kernels
boot-up on Tegra20.
Signed-off-by: Dmitry Osipenko
---
drivers/memory/tegra/mc.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletion
On Thursday, 19 July 2018 18:30:48 MSK Jon Hunter wrote:
> On 19/07/18 14:24, Dmitry Osipenko wrote:
> > This fixes irrelevant "tegra-mc 7000f000.memory-controller: no memory
> > timings for RAM code 0 registered" warning message during of kernels
> > boot-up
On Friday, 20 July 2018 11:02:04 MSK Jon Hunter wrote:
> On 19/07/18 16:38, Dmitry Osipenko wrote:
> > On Thursday, 19 July 2018 18:30:48 MSK Jon Hunter wrote:
> >> On 19/07/18 14:24, Dmitry Osipenko wrote:
> >>> This fixes irrelevant "tegra-mc 7000f000.memory-
On Saturday, 21 July 2018 12:56:15 MSK Mark Brown wrote:
> On Fri, Jul 20, 2018 at 12:31:07PM +, Marcel Ziswiler wrote:
> > On Fri, 2018-07-20 at 13:16 +0100, Mark Brown wrote:
> > > > ac97->sync_gpio = of_get_named_gpio(pdev->dev.of_node,
> > > >
> > > >
On Saturday, 21 July 2018 14:55:21 MSK Marcel Ziswiler wrote:
> On Sat, 2018-07-21 at 14:17 +0300, Dmitry Osipenko wrote:
>
> > On Saturday, 21 July 2018 12:56:15 MSK Mark Brown wrote:
> >
> > > On Fri, Jul 20, 2018 at 12:31:07PM +, Marcel Ziswiler wrote:
> >
On Saturday, 21 July 2018 15:03:57 MSK Dmitry Osipenko wrote:
> On Saturday, 21 July 2018 14:55:21 MSK Marcel Ziswiler wrote:
> > On Sat, 2018-07-21 at 14:17 +0300, Dmitry Osipenko wrote:
> > > On Saturday, 21 July 2018 12:56:15 MSK Mark Brown wrote:
> > > > On F
On Thursday, 19 July 2018 16:21:30 MSK Dmitry Osipenko wrote:
> Kernel should never gate the EMC clock as it causes immediate lockup, so
> removing clk-gate functionality doesn't affect anything. Turning EMC clk
> gate into divider allows to implement glitch-less EMC sca
On Friday, 20 July 2018 16:45:30 MSK Ben Dooks wrote:
> The 2D and 3D clocks have an IDLE field in bits 15:8 so add these
> clocks by making a 2D and 3D mux, and split the divider into the
> standard 2D/3D ones and 2D/3D idle clocks.
>
> Signed-off-by: Ben Dooks
> ---
> drivers/clk/tegra/clk-id.
On Thursday, 26 July 2018 18:40:25 MSK Stefan Agner wrote:
> The properties have been commented out to prevent a regression a
> while ago. The first regression should be resolved by
> commit 44af7927316e ("spi: Map SPI OF client IRQ at probe time").
>
> The second regression is probably addressed
On Thursday, 2 August 2018 01:51:42 MSK Stefan Agner wrote:
> On 01.08.2018 22:51, Dmitry Osipenko wrote:
> > On Thursday, 26 July 2018 18:40:25 MSK Stefan Agner wrote:
> >> The properties have been commented out to prevent a regression a
> >> while ago. The first regre
On Thursday, 2 August 2018 02:11:23 MSK Dmitry Osipenko wrote:
> On Thursday, 2 August 2018 01:51:42 MSK Stefan Agner wrote:
> > On 01.08.2018 22:51, Dmitry Osipenko wrote:
> > > On Thursday, 26 July 2018 18:40:25 MSK Stefan Agner wrote:
> > >> The properties have b
TRL driver registration to the arch_init level and GPIO to the
subsys_init.
Signed-off-by: Dmitry Osipenko
---
drivers/gpio/gpio-tegra.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c
index 2d940785bad0..a53c77db9744 100644
--- a/dr
TRL driver registration to the arch_init level and GPIO to the
subsys_init.
Signed-off-by: Dmitry Osipenko
---
drivers/pinctrl/tegra/pinctrl-tegra114.c | 7 ++-
drivers/pinctrl/tegra/pinctrl-tegra124.c | 7 ++-
drivers/pinctrl/tegra/pinctrl-tegra20.c | 7 ++-
drivers/pinctrl/tegra/pinctrl-tegr
On Thursday, 2 August 2018 14:11:43 MSK Dmitry Osipenko wrote:
> There is a bug in regards to deferred probing within the drivers core
> that causes GPIO-driver to suspend after its users. The bug appears if
I meant "before its users", of course. If the rest of the patches is fine
On Monday, 23 July 2018 11:28:25 MSK Ben Dooks wrote:
> On 2018-07-22 12:55, Dmitry Osipenko wrote:
> > On Friday, 20 July 2018 16:45:30 MSK Ben Dooks wrote:
> >> The 2D and 3D clocks have an IDLE field in bits 15:8 so add these
> >> clocks by making a 2D and 3D mux, and
On Friday, 20 July 2018 16:45:30 MSK Ben Dooks wrote:
> The 2D and 3D clocks have an IDLE field in bits 15:8 so add these
> clocks by making a 2D and 3D mux, and split the divider into the
> standard 2D/3D ones and 2D/3D idle clocks.
>
> Signed-off-by: Ben Dooks
> ---
> drivers/clk/tegra/clk-id.
On Monday, 23 July 2018 21:37:50 MSK Peter Geis wrote:
> On 07/23/2018 02:13 PM, Mark Brown wrote:
> > On Mon, Jul 23, 2018 at 01:58:26PM -0400, Peter Geis wrote:
> >> SW2 and SW4 use a shared table to provide voltage to the cpu core and
> >> devices on Tegra hardware.
> >> Added this table to the
On Monday, 23 July 2018 22:38:48 MSK Peter Geis wrote:
> Added support for the CPCAP power management regulator functions on
> Tegra devices.
> Added sw2_sw4 value tables, which provide power to the Tegra core and
> aux devices.
> Added the Tegra init tables and device tree compatibility match.
>
On Tuesday, 24 July 2018 04:57:24 MSK Peter Geis wrote:
> On 07/23/2018 08:27 PM, Dmitry Osipenko wrote:
> > On Monday, 23 July 2018 22:38:48 MSK Peter Geis wrote:
> >> Added support for the CPCAP power management regulator functions on
> >> Tegra devices.
> >&g
On Monday, 23 July 2018 16:05:21 MSK Dmitry Osipenko wrote:
> On Friday, 20 July 2018 16:45:30 MSK Ben Dooks wrote:
> > The 2D and 3D clocks have an IDLE field in bits 15:8 so add these
> > clocks by making a 2D and 3D mux, and split the divider into the
> > standard 2D/3
On Tuesday, 24 July 2018 15:24:34 MSK Marcel Ziswiler wrote:
> Sorry, I meant to write "minor revamp" in the subject line here as
> Apalis TK1 was already in quite good a shape but this are still some
> worthy improvements (;-p).
>
> On Tue, 2018-07-24 at 12:42 +0200, Marcel Ziswiler wrote:
>
Ma
On Sunday, 22 July 2018 19:49:09 MSK Marcel Ziswiler wrote:
> From: Marcel Ziswiler
>
> Avoid eMMC issues by specifying broken-hpi.
>
> Signed-off-by: Marcel Ziswiler
>
> ---
Is it a specific eMMC card model that has broken HPI or it is a host
controller bug?
On Tuesday, 24 July 2018 17:16:33 MSK Marcel Ziswiler wrote:
> On Tue, 2018-07-24 at 15:44 +0300, Dmitry Osipenko wrote:
>
> > On Tuesday, 24 July 2018 15:24:34 MSK Marcel Ziswiler wrote:
> >
> > > Sorry, I meant to write "minor revamp" in the subject line he
On Tuesday, 24 July 2018 17:45:01 MSK Marcel Ziswiler wrote:
> On Tue, 2018-07-24 at 17:31 +0300, Dmitry Osipenko wrote:
>
> > On Tuesday, 24 July 2018 17:16:33 MSK Marcel Ziswiler wrote:
> >
> > > On Tue, 2018-07-24 at 15:44 +0300, Dmitry Osipenko wrote:
> >
On Tuesday, 24 July 2018 17:26:58 MSK Marcel Ziswiler wrote:
> On Tue, 2018-07-24 at 17:03 +0300, Dmitry Osipenko wrote:
>
> > On Sunday, 22 July 2018 19:49:09 MSK Marcel Ziswiler wrote:
> >
> > > From: Marcel Ziswiler
> > >
> > > Avoid eMMC issues
This fixes irrelevant "tegra-mc 7000f000.memory-controller: no memory
timings for RAM code 0 registered" warning message during of kernels
boot-up on Tegra20.
Fixes: a8d502fd3348 ("memory: tegra: Squash tegra20-mc into common tegra-mc
driver")
Signed-off-by: Dmitry Osipenko
these clocks should be in the device tree.
- Some minor cleanups and fixes in the drivers code.
v2:
- Minor code cleanups like consistent use of writel_relaxed instead
of non-relaxed version, reworded error messages, etc.
- Factored out use_pllm_ud bit checki
Embedded memory controller has a corresponding clock, document the clock
property.
Signed-off-by: Dmitry Osipenko
Acked-by: Rob Herring
---
.../devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt| 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings
Move tegra20-emc binding to the memory-controllers directory for
consistency with the other Tegra memory bindings.
Signed-off-by: Dmitry Osipenko
Acked-by: Rob Herring
---
.../{arm/tegra => memory-controllers}/nvidia,tegra20-emc.txt | 0
1 file changed, 0 insertions(+), 0 deleti
EMC has a dedicated interrupt that is used to notify about completion of
HW operations. Document the interrupt property.
Signed-off-by: Dmitry Osipenko
Acked-by: Rob Herring
Acked-by: Peter De Schrijver
---
.../devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt| 2 ++
1 file changed
Add interrupt entry into the EMC DT node.
Signed-off-by: Dmitry Osipenko
Acked-by: Peter De Schrijver
---
arch/arm/boot/dts/tegra20.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 15b73bd377f0..9eb4163a4390 100644
Add clock entry into the EMC DT node.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra20.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 9eb4163a4390..979f38293fe5 100644
--- a/arch/arm/boot/dts/tegra20
Ensure that direct PLLM sourcing is turned off for EMC as we don't support
that configuration in the clk driver.
Signed-off-by: Dmitry Osipenko
Acked-by: Peter De Schrijver
---
drivers/clk/tegra/clk-tegra20.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/clk/tegr
Kernel should never gate the EMC clock as it causes immediate lockup, so
removing clk-gate functionality doesn't affect anything. Turning EMC clk
gate into divider allows to implement glitch-less EMC scaling, avoiding
reparenting to a backup clock.
Signed-off-by: Dmitry Osipenko
Acked-by:
Introduce driver for the External Memory Controller (EMC) found on Tegra20
chips, which controls the external DRAM on the board. The purpose of this
driver is to program memory timing for external memory on the EMC clock
rate change.
Signed-off-by: Dmitry Osipenko
Acked-by: Peter De Schrijver
On Tuesday, 24 July 2018 18:47:41 MSK Peter Geis wrote:
> On 07/24/2018 10:48 AM, Dmitry Osipenko wrote:
> > On Tuesday, 24 July 2018 17:45:01 MSK Marcel Ziswiler wrote:
> >> On Tue, 2018-07-24 at 17:31 +0300, Dmitry Osipenko wrote:
> >>> On Tuesday, 24 July 2018 17:1
On 10.01.2018 05:40, Ming Lei wrote:
> On Tue, Jan 09, 2018 at 08:02:53PM +0300, Dmitry Osipenko wrote:
>> On 09.01.2018 17:33, Ming Lei wrote:
>>> On Tue, Jan 09, 2018 at 04:18:39PM +0300, Dmitry Osipenko wrote:
>>>> On 09.01.2018 05:34, Ming Lei wrote:
>>&g
config TEGRA_VDE
> tristate "NVIDIA Tegra Video Decoder Engine driver"
> depends on ARCH_TEGRA || COMPILE_TEST
> + select DMA_SHARED_BUFFER
> select SRAM
> help
> Say Y here to enable support for the NVIDIA Tegra video decoder
>
Thanks!
Acked-by: Dmitry Osipenko
On 18.12.2017 15:22, Ming Lei wrote:
> When merging one bvec into segment, if the bvec is too big
> to merge, current policy is to move the whole bvec into another
> new segment.
>
> This patchset changes the policy into trying to maximize size of
> front segments, that means in above situation, p
On 09.01.2018 05:34, Ming Lei wrote:
> On Tue, Jan 09, 2018 at 12:09:27AM +0300, Dmitry Osipenko wrote:
>> On 18.12.2017 15:22, Ming Lei wrote:
>>> When merging one bvec into segment, if the bvec is too big
>>> to merge, current policy is to move the whole bvec i
On 09.01.2018 17:33, Ming Lei wrote:
> On Tue, Jan 09, 2018 at 04:18:39PM +0300, Dmitry Osipenko wrote:
>> On 09.01.2018 05:34, Ming Lei wrote:
>>> On Tue, Jan 09, 2018 at 12:09:27AM +0300, Dmitry Osipenko wrote:
>>>> On 18.12.2017 15:22, Ming Lei wrote:
>>&g
Currently VDE clock rate is determined by clock config left from
bootloader, let's not rely on it and explicitly specify the clock
rate in the CCF driver.
Signed-off-by: Dmitry Osipenko
Acked-by: Peter De Schrijver
---
Change log:
v2: No change.
v3: No change.
drivers/clk/tegr
Machine dies if HCLK, SCLK or EMC is disabled. Hence mark these clocks
as critical.
Signed-off-by: Dmitry Osipenko
Acked-by: Peter De Schrijver
---
Change log:
v2: Fixed accidentally missed marking EMC as critical on Tegra30 and
Tegra124. Switched to a use of common EMC gate
PLL_C_OUT_1 can't produce 216 MHz defined in the init_table. Let's
set it to 240 MHz and explicitly specify HCLK rate for consistency.
Signed-off-by: Dmitry Osipenko
Acked-by: Peter De Schrijver
---
Change log:
v2: No change.
v3: No change.
drivers/clk/tegra/clk-teg
On 10.01.2018 16:59, Dmitry Osipenko wrote:
> Machine dies if HCLK, SCLK or EMC is disabled. Hence mark these clocks
> as critical.
>
> Signed-off-by: Dmitry Osipenko
> Acked-by: Peter De Schrijver
> ---
>
> Change log:
> v2: Fixed accidentally missed marking EMC
Hello,
On 07.03.2018 19:37, Paul Kocialkowski wrote:
> Hi,
>
> First off, I'd like to take the occasion to say thank-you for your work.
> This is a major piece of plumbing that is required for me to add support
> for the Allwinner CedarX VPU hardware in upstream Linux. Other drivers,
> such as te
Hello,
On 07.03.2018 19:37, Paul Kocialkowski wrote:
> Hi,
>
> First off, I'd like to take the occasion to say thank-you for your work.
> This is a major piece of plumbing that is required for me to add support
> for the Allwinner CedarX VPU hardware in upstream Linux. Other drivers,
> such as te
1 - 100 of 4295 matches
Mail list logo
