This path is to add the support for dwc2 controller found ind
Rockchip processors rk3066, rk3188 and rk3288
This patch also add dr_mode for dwc2 driver.
Kever Yang (4):
Documentation: dt-bindings: add dt binding info for Rockchip dwc2
ARM: dts: add rk3288 dwc2 controller support
usb: dwc2
This add necessary dwc2 binding documentation for Rockchip socs:
rk3066, rk3188 and rk3288
add dr_mode as optional properties.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Documentation/devicetree/bindings/usb/dwc2.txt |5 +
1 file changed, 5 insertions(+)
diff --git
rk3288 has two kind of usb controller, this add the dwc2 controller
for otg and host1.
Controller can works with usb PHY default setting and Vbus on.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
arch/arm/boot/dts/rk3288.dtsi | 20
1 file changed, 20 insertions
Some devices with A female host port and without use of usb_id pin
will need this for the otg controller works as device role
during firmware period and works as host role in rich os.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
drivers/usb/dwc2/core.c | 13
This patch add compatible data for dwc2 controller found on
rk3066, rk3188 and rk3288 processors from rockchip.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
drivers/usb/dwc2/platform.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/drivers/usb
Hi Russell,
I'd value your feedback on this if you have a moment.
I think this will need by rk3288 soc.
Thanks
On 08/18/2014 05:58 PM, Kever Yang wrote:
From: Huang Tao huang...@rock-chips.com
On Cortex-A12 (r0p0..r0p1-00lac0-rc11), when a CPU executes a sequence of
two conditional store
We need use the hrtimer, which need the arch-timer to be 'always-on'
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
arch/arm/boot/dts/rk3288.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 5950b0a..698e6ea
Indicate that the generic dr_mode binding should be used for dwc2.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Changes in v2:
- Split out dr_mode and rk3288 bindings.
Documentation/devicetree/bindings/usb/dwc2.txt |2 ++
1 file changed, 2 insertions(+)
diff --git
These two patches enable the dr_mode for the dwc2 usb
controller. These are split from the patch series adding
rk3288 dwc2 support.
Changes in v2:
- Split out dr_mode and rk3288 bindings.
- put spaces around '+' operator
- expand the comment for dr_mode
- handle dr_mode is USB_DR_MODE_OTG
Kever
Some devices with A female host port and without use of usb_id pin
will need this for the otg controller works as device role
during firmware period and works as host role in rich os.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Changes in v2:
- put spaces around '+' operator
rk3288 has two kind of usb controller, this add the dwc2 controller
for otg and host1.
Controller can works with usb PHY default setting and Vbus on.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Changes in v2:
- change the node name from 'dwc2' to 'usb'
arch/arm/boot/dts/rk3288
USB otg port is the usb3.0 b-port on the board.
USB host1 port is the host A port nearby the otg port.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Changes in v2:
- evb patch added in version 2
arch/arm/boot/dts/rk3288-evb.dtsi |6 ++
1 file changed, 6 insertions(+)
diff
From: Kever Yang kever.y...@gmail.com
These patches to add support for dwc2 controller found in
Rockchip processors rk3066, rk3188 and rk3288,
and enable dts for rk3288 evb.
Changes in v2:
- Split out dr_mode and rk3288 bindings.
- add compatible snps,dwc2 bingding info
- set most parameters
This patch add compatible data for dwc2 controller found on
rk3066, rk3188 and rk3288 processors from rockchip.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Changes in v2:
- set most parameters as driver auto-detect
drivers/usb/dwc2/platform.c | 29 +
1
This add necessary dwc2 binding documentation for Rockchip socs:
rk3066, rk3188 and rk3288
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Changes in v2:
- Split out dr_mode and rk3288 bindings.
- add compatible snps,dwc2 bingding info
Documentation/devicetree/bindings/usb/dwc2.txt
USB otg port is the usb3.0 b-port on the board.
USB host1 port is the host A port nearby the otg port.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Changes in v3:
- Rebase
Changes in v2:
- evb patch added in version 2
arch/arm/boot/dts/rk3288-evb.dtsi |6 ++
1 file changed
From: Doug Anderson diand...@chromium.org
The EHCI and HSIC device tree nodes were added in the wrong place.
Fix them.
Signed-off-by: Doug Anderson diand...@chromium.org
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Changes in v3:
- EHCI and HSIC move new for version 3.
Changes in v2
rk3288 has two kind of usb controller, this add the dwc2 controller
for otg and host1.
Controller can works with usb PHY default setting and Vbus on.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Changes in v3:
- Moved out of pin control and sort by base address
Changes in v2
and rk3288 bindings.
- add compatible snps,dwc2 bingding info
- set most parameters as driver auto-detect
- change the node name from 'dwc2' to 'usb'
- evb patch added in version 2
Doug Anderson (1):
ARM: dts: Fix the sort ordering of EHCI and HSIC in rk3288.dtsi
Kever Yang (4):
Documentation: dt
This patch add compatible data for dwc2 controller found on
rk3066, rk3188 and rk3288 processors from rockchip.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
Acked-by: Paul Zimmerman pa...@synopsys.com
---
Changes in v3: None
Changes in v2:
- set most parameters as driver auto-detect
This add necessary dwc2 binding documentation for Rockchip socs:
rk3066, rk3188 and rk3288
Signed-off-by: Kever Yang kever.y...@rock-chips.com
Acked-by: Stephen Warren swar...@nvidia.com
---
Changes in v3: None
Changes in v2:
- Split out dr_mode and rk3288 bindings.
- add compatible snps,dwc2
This patch add compatible data for dwc2 controller found on
rk3066, rk3188 and rk3288 processors from rockchip.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
Acked-by: Paul Zimmerman pa...@synopsys.com
---
Changes in v3: None
Changes in v2:
- set most parameters as driver auto-detect
USB otg port is the usb3.0 b-port on the board.
USB host1 port is the host A port nearby the otg port.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Changes in v3:
- Rebase
Changes in v2:
- evb patch added in version 2
arch/arm/boot/dts/rk3288-evb.dtsi |6 ++
1 file changed
From: Doug Anderson diand...@chromium.org
The EHCI and HSIC device tree nodes were added in the wrong place.
Fix them.
Signed-off-by: Doug Anderson diand...@chromium.org
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Changes in v3:
- EHCI and HSIC move new for version 3.
Changes in v2
rk3288 has two kind of usb controller, this add the dwc2 controller
for otg and host1.
Controller can works with usb PHY default setting and Vbus on.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Changes in v3:
- Moved out of pin control and sort by base address
Changes in v2
in rk3288.dtsi
Kever Yang (4):
Documentation: dt-bindings: add dt binding info for Rockchip dwc2
usb: dwc2: add compatible data for rockchip soc
ARM: dts: add rk3288 dwc2 controller support
ARM: dts: Enable USB otg and host1(dwc) on rk3288-evb
Documentation/devicetree/bindings/usb/dwc2.txt |3
This add necessary dwc2 binding documentation for Rockchip socs:
rk3066, rk3188 and rk3288
Signed-off-by: Kever Yang kever.y...@rock-chips.com
Acked-by: Stephen Warren swar...@nvidia.com
---
Changes in v3: None
Changes in v2:
- Split out dr_mode and rk3288 bindings.
- add compatible snps,dwc2
bindings.
- put spaces around '+' operator
- expand the comment for dr_mode
- handle dr_mode is USB_DR_MODE_OTG
Kever Yang (2):
Documentation: dt-bindings: add dt binding info for dwc2 dr_mode
usb: dwc2: add 'mode' which based on Kconfig select or dts setting
Documentation/devicetree/bindings
Indicate that the generic dr_mode binding should be used for dwc2.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Changes in v3: None
Changes in v2:
- Split out dr_mode and rk3288 bindings.
Documentation/devicetree/bindings/usb/dwc2.txt | 2 ++
1 file changed, 2 insertions(+)
diff
According to the dr_mode, the otg controller can work as
device role during firmware period, and work as host role in
the kernel, without use of usb_id pin. As the commit usb: dwc3:
set 'mode' based on selected Kconfig choices.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Changes
Doug,
On 08/05/2014 12:34 AM, Doug Anderson wrote:
Kever,
On Mon, Aug 4, 2014 at 6:45 AM, Kever Yang kever.y...@rock-chips.com wrote:
According to the dr_mode, the otg controller can work as
device role during firmware period, and work as host role in
the kernel, without use of usb_id pin
struct
- From Jingoo's suggestion:
change the commit message
- add dr_mode init from Kconfig
Changes in v2:
- Split out dr_mode and rk3288 bindings.
- put spaces around '+' operator
- expand the comment for dr_mode
- handle dr_mode is USB_DR_MODE_OTG
Kever Yang (2):
Documentation: dt
According to the dr_mode, the otg controller can work as
device role and host role. Some boards always want to use host mode
and some other boards want to use gadget mode. We use the dts setting
to set dwc2's mode, rather than fixing it to whatever hardware says.
Signed-off-by: Kever Yang kever.y
Indicate that the generic dr_mode binding should be used for dwc2.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
Reviewed-by: Doug Anderson diand...@chromium.org
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- Split out dr_mode and rk3288 bindings.
Documentation/devicetree
bingding info
- set most parameters as driver auto-detect
- evb patch added in version 2
Kever Yang (4):
Documentation: dt-bindings: add dt binding info for Rockchip dwc2
usb: dwc2: add compatible data for rockchip soc
ARM: dts: add rk3288 dwc2 controller support
ARM: dts: Enable USB otg
This patch add compatible data for dwc2 controller found on
rk3066, rk3188 and rk3288 processors from rockchip.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
Acked-by: Paul Zimmerman pa...@synopsys.com
---
Changes in v4:
- max_transfer_size change to 65536, this should be enough
for most
rk3288 has two kind of usb controller, this add the dwc2 controller
for otg and host1.
Controller can works with usb PHY default setting and Vbus on.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Changes in v4: None
Changes in v3:
- EHCI and HSIC move new for version 3.
Changes
USB otg port is the usb3.0 b-port on the board.
USB host1 port is the host A port nearby the otg port.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Changes in v4: None
Changes in v3:
- Rebase
Changes in v2:
- evb patch added in version 2
arch/arm/boot/dts/rk3288-evb.dtsi | 6
This add necessary dwc2 binding documentation for Rockchip socs:
rk3066, rk3188 and rk3288
Signed-off-by: Kever Yang kever.y...@rock-chips.com
Acked-by: Stephen Warren swar...@nvidia.com
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- Split out dr_mode and rk3288 bindings.
- add
Paul,
On 08/08/2014 02:26 AM, Paul Zimmerman wrote:
From: Kever Yang [mailto:kever.y...@gmail.com] On Behalf Of Kever Yang
Sent: Thursday, August 07, 2014 2:35 AM
This patch add compatible data for dwc2 controller found on
rk3066, rk3188 and rk3288 processors from rockchip.
Signed-off
this value if they use the dwc2
controller.
The way we get the register value here can not make sure this is the
power-on
value which we actually need.
Let me do more test for that, and maybe we need another patch.
Anyway, this patch works and reasonable.
Reviewed-by: Kever Yang kever.y...@rock
This patch add compatible data for dwc2 controller found on
rk3066, rk3188 and rk3288 processors from rockchip.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
Acked-by: Paul Zimmerman pa...@synopsys.com
---
Changes in v5:
- max_transfer_size change to 65535 to met the requirement
USB host1 port is the host A port nearby the otg port.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Changes in v5:
- don't enable otg port for evb
Changes in v4: None
Changes in v3:
- Rebase
Changes in v2:
- evb patch added in version 2
arch/arm/boot/dts/rk3288-evb.dtsi | 4
rk3288 has two kind of usb controller, this add the dwc2 controller
for otg and host1.
Controller can works with usb PHY default setting and Vbus on.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
Reviewed-by: Doug Anderson diand...@chromium.org
Tested-by: Doug Anderson diand
This add necessary dwc2 binding documentation for Rockchip socs:
rk3066, rk3188 and rk3288
Signed-off-by: Kever Yang kever.y...@rock-chips.com
Acked-by: Stephen Warren swar...@nvidia.com
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- Split out dr_mode and rk3288
had post it seprately.
Changes in v3:
- EHCI and HSIC move new for version 3.
- Rebase
Changes in v2:
- Split out dr_mode and rk3288 bindings.
- add compatible snps,dwc2 bingding info
- set most parameters as driver auto-detect
- evb patch added in version 2
Kever Yang (4):
Documentation: dt
is an UNPREDICTABLE STR or STM
instruction. This workaround setting bit[12] of the Feature Register
prevents the erratum. This bit disables an optimisation applied to a
sequence of 2 instructions that use opposing condition codes.
Signed-off-by: Huang Tao huang...@rock-chips.com
Signed-off-by: Kever Yang kever.y
Heiko,
On 10/14/2014 02:23 PM, Heiko Stübner wrote:
Am Dienstag, 14. Oktober 2014, 13:24:03 schrieb Doug Anderson:
Kever,
On Mon, Oct 13, 2014 at 1:12 PM, Kever Yang kever.y...@rock-chips.com
wrote:
+ /*
+* We need to soft reset the cpu when we turn off the cpu power
domain
Russell,
On 10/14/2014 04:37 PM, Russell King - ARM Linux wrote:
On Tue, Oct 14, 2014 at 02:50:07PM -0700, Kever Yang wrote:
Heiko,
On 10/14/2014 02:23 PM, Heiko Stübner wrote:
Am Dienstag, 14. Oktober 2014, 13:24:03 schrieb Doug Anderson:
Kever,
On Mon, Oct 13, 2014 at 1:12 PM, Kever Yang
This patch add intmem node des which is needed by platsmp.c
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Changes in v5: None
Changes in v4:
- remove rockchip,rk3288-pmu-sram because we don't use it here
Changes in v3:
- remove 'enable-method' from this patch
- add compitable name
This patch add pmu reference and enable-method for smp
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Changes in v5: None
Changes in v4: None
Changes in v3:
- add this patch
Changes in v2: None
arch/arm/boot/dts/rk3288.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch
This patch add reset for CPU nodes to use the reset controller.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/rk3288.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm
processors might be stalled when the individual processor is powered down,
we can avoid this prolbem by softreset the processor before power it down.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Changes in v5:
- use read_cpuid_part() but not read_cpuid_part_number()
Changes in v4:
- merge
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Changes in v5: None
Changes in v4:
- add rockchip,pmu property into cpus.txt
Changes in v3:
- add this patch
Changes in v2: None
Documentation/devicetree/bindings/arm/cpus.txt | 9 +
arch/arm/mach-rockchip/platsmp.c | 13
ofsmp_boot_secondary
- discards the power domain operation
- handle the per cpu starup when actived by 'sev'
- adjust the alignment
Kever Yang (6):
ARM: rockchip: convert to regmap and use pmu syscon if available
ARM: rockchip: add option to access the pmu via a phandle in
smp_operations
ARM: dts
the necessary regmap on
top of it.
Signed-off-by: Heiko Stuebner he...@sntech.de
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Changes in v5: None
Changes in v4: None
Changes in v3:
- add this patch in version 3
Changes in v2: None
arch/arm/mach-rockchip/platsmp.c | 104
This patch make a common source for uart0 pll src and sclk_gpu,
so that gpu can get its cloc from npll.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
drivers/clk/rockchip/clk-rk3288.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/rockchip/clk
We need use the hrtimer, which need the arch-timer to be 'always-on'
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
arch/arm/boot/dts/rk3288.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 5950b0a..698e6ea
Mark,
Thanks for your reply and advice.
On 08/28/2014 11:11 PM, Mark Rutland wrote:
On Thu, Aug 28, 2014 at 10:17:58AM +0100, Mark Rutland wrote:
Hi Kever,
On Thu, Aug 28, 2014 at 02:40:17AM +0100, Kever Yang wrote:
We need use the hrtimer, which need the arch-timer to be 'always-on'
I
This patch add 400MHz and 500MHz to clock rate table for rk3288.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
drivers/clk/rockchip/clk-rk3288.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/rockchip/clk-rk3288.c
b/drivers/clk/rockchip/clk-rk3288.c
index d053529
This patch add init rate for PLLs and some bus clock from dts for rk3288,
add two clock rate of 400M and 500M into rate table for we will use it.
Kever Yang (2):
clk: rockchip: add 400MHz and 500MHz for rk3288 clock rate
ARM: dts: enable init rate for clock
arch/arm/boot/dts/rk3288.dtsi
We need to initialize PLL rate and some of bus clock rate while
kernel init, for there is no other module will do that.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
arch/arm/boot/dts/rk3288.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288
be on during boot or no module driver in kernel will initialize it.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
drivers/clk/rockchip/clk-rk3188.c | 32 -
drivers/clk/rockchip/clk-rk3288.c | 146 +++---
drivers/clk/rockchip/clk.c| 9
me
how to test the usb suspend/resume API easily?
Changes in v2:
- remove the clock from hcd
- adjust the delay time when resume
- move all the clock operation into platform
Kever Yang (2):
usb: dwc2: add bus suspend/resume for dwc2
usb: dwc2: move the clock management from gadget to platform
This patch adds suspend/resume for dwc2 hcd controller.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Changes in v2:
- remove the clock from hcd
- adjust the delay time when resume
drivers/usb/dwc2/hcd.c | 75 ++
1 file changed, 64
This patch move clock management out of gadget into platform,
make both hcd and gadget can use the clock.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Changes in v2:
- move all the clock operation into platform
drivers/usb/dwc2/gadget.c | 24 ++--
drivers/usb
Hi
On 10/30/2014 05:53 AM, Heiko Stübner wrote:
Am Mittwoch, 29. Oktober 2014, 13:50:20 schrieb Doug Anderson:
Kever,
On Wed, Oct 29, 2014 at 3:06 AM, Kever Yang kever.y...@rock-chips.com
wrote:
The rockchip clock driver use CLK_IGNORE_UNUSED flag to make sure
all the clocks are available
be on during boot or no module driver in kernel will initialize it.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Changes in v2:
- get some clock ID back
- add CLK_IGNORE_UNUSED tag for aclk_strc and aclk_core in clk-rk3188.c
- add CLK_IGNORE_UNUSED tag for rk3288 dwc2
drivers/clk
Hi Dinh,
On 10/29/2014 07:25 AM, dingu...@opensource.altera.com wrote:
From: Dinh Nguyen dingu...@opensource.altera.com
Since the dwc2 hcd driver is currently not looking for a clock node during
init, we should not completely fail if there isn't a clock provided.
For dual-role mode, we will
Hi Dinh
On 10/29/2014 07:25 AM, dingu...@opensource.altera.com wrote:
From: Dinh Nguyen dingu...@opensource.altera.com
Adds the gadget data structure and appropriate data structure pointers
to the common dwc2_hsotg data structure. To keep the driver data
dereference code looking clean, the
be on during boot or no module driver in kernel will initialize it.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Changes in v3:
- get CLK_DIVIDER_READ_ONLY tag back fro armcores
- add CLK_IGNORE_UNUSED tag for cs_dbg, pclk_dgb_pre and pclk_rkpwm
Changes in v2:
- get some clock ID back
|- hclk_sdio1
|- hclk_emmc
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
drivers/clk/rockchip/clk-rk3288.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3288.c
b/drivers/clk/rockchip/clk-rk3288.c
index 7a0741d..e1106ad 100644
This patch adds suspend/resume for dwc2 hcd controller.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
drivers/usb/dwc2/hcd.c | 74 ++
1 file changed, 63 insertions(+), 11 deletions(-)
diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb
works on my rk3288 evb, so,
Tested-by: Kever Yang kever.y...@rock-chips.com
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Please read the FAQ at http
On 09/23/2014 10:55 AM, jinkun.hong wrote:
From: jinkun.hong jinkun.h...@rock-chips.com
Any summary for rk3288 power controller?
Maybe you can say something about how rk3288 TRM described this module.
Signed-off-by: Jack Dai jack@rock-chips.com
Signed-off-by: Wang Caesar
Hi Jay,
On 11/19/2014 04:09 PM, Jianqun Xu wrote:
Patch is from Sonny Rao sonny...@chromium.org
Here should be,
From: Sonny Rao sonny...@chromium.org
- Kever
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This patch add intmem node des which is needed by platsmp.c
and enable the smp.
Signed-off-by: Heiko Stuebner he...@sntech.de
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
arch/arm/boot/dts/rk3288.dtsi | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm
basic rk3288 smp support
Signed-off-by: Heiko Stuebner he...@sntech.de
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
arch/arm/mach-rockchip/core.h| 1 +
arch/arm/mach-rockchip/platsmp.c | 60 +---
2 files changed, 57 insertions(+), 4 deletions
rk3288 is dual-core CPU Soc, we need to enable the smp.
This patchset works with either arch-timer use the phisical counter
in kernel or the firmware initialize the arch-timer virtual counter
offset and use virtual counter in kernel.
Kever Yang (2):
ARM: rockchip: add basic smp support
This add documentation for rk3288 smp dt binding
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Changes in v2:
- add documentation
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt
b
instead ofsmp_boot_secondary
- discards the power domain operation
- handle the per cpu starup when actived by 'sev'
- adjust the alignment
Kever Yang (3):
Documentation: dt-bindings: add dt binding info for rk3288-smp
ARM: rockchip: add basic smp support for rk3288
ARM: dts: add intmem node
This patch add basic rk3288 smp support, cpu 1~3 are in wfe state
when get into kernel.
Signed-off-by: Heiko Stuebner he...@sntech.de
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Changes in v2:
- use rk3288_boot_secondary instead ofsmp_boot_secondary
- discards the power domain
This patch add intmem node des which is needed by platsmp.c
and enable the smp.
Signed-off-by: Heiko Stuebner he...@sntech.de
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Changes in v2:
- adjust the alignment
arch/arm/boot/dts/rk3288.dtsi | 18 ++
1 file changed, 18
Sonny,
On 09/17/2014 04:17 AM, Sonny Rao wrote:
On Tue, Sep 16, 2014 at 3:44 AM, Kever Yang kever.y...@rock-chips.com wrote:
This patch add basic rk3288 smp support, cpu 1~3 are in wfe state
when get into kernel.
Signed-off-by: Heiko Stuebner he...@sntech.de
Signed-off-by: Kever Yang kever.y
Hi Mark,
Thanks for your comment.
On 09/17/2014 02:54 AM, Mark Rutland wrote:
On Tue, Sep 16, 2014 at 11:44:28AM +0100, Kever Yang wrote:
This add documentation for rk3288 smp dt binding
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Changes in v2:
- add documentation
Hi Jianqun,
pls add linux-rockc...@lists.infradead.org next time.
On 09/30/2014 11:12 AM, Jianqun wrote:
The relation of i2s nodes as follows:
i2s_src 0 059400 0
i2s_frac 0 011289600 0
Hi Julius,
On 11/07/2014 06:11 AM, Julius Werner wrote:
On Wed, Nov 5, 2014 at 5:30 PM, Kever Yang kever.y...@rock-chips.com wrote:
Hcd controller needs bus_suspend/resume, dwc2 controller make
root hub generate suspend/resume signal with hprt0 register
when work in host mode.
After the root
.
This patch has tested on rk3288 with suspend/resume.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
Acked-by: Paul Zimmerman pa...@synopsys.com
---
Changes in v3:
- remove CONFIG_PM macro for bus_suspend/resume
- add PCGCTL operation for no device connect case
Changes in v2:
- update commit
Doug,
On 11/13/2014 07:22 AM, Doug Anderson wrote:
Kever,
On Mon, Nov 10, 2014 at 5:09 AM, Kever Yang kever.y...@rock-chips.com wrote:
Hcd controller needs bus_suspend/resume, dwc2 controller make
root hub generate suspend/resume signal with hprt0 register
when work in host mode.
After
with
CLK_IGNORE_UNUSED
tag so far.
Reviewed-by: Kever Yang kever.y...@rock-chips.com
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Please read the FAQ
According to rk3288 trm, the clk_usbphy480m_gate is locate at
bit 14 of CRU_CLKGATE5_CON register.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
drivers/clk/rockchip/clk-rk3288.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-rk3288.c
b
for it so that we can use in dts.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
include/dt-bindings/clock/rk3288-cru.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/clock/rk3288-cru.h
b/include/dt-bindings/clock/rk3288-cru.h
index 100a08c..3dcc906 100644
Use the clock ID for usbphy480m_src so that we can find
this clock node in dts.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
drivers/clk/rockchip/clk-rk3288.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-rk3288.c
b/drivers/clk/rockchip
- clk_otgphy0 - USB PHY OTG
- clk_otgphy1 - USB PHY host0
- clk_otgphy2 - USB PHY host1
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
drivers/clk/rockchip/clk-rk3288.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3288.c
b/drivers/clk
Hi Heiko,
On 11/07/2014 05:06 AM, Heiko Stübner wrote:
Hi Kever,
Am Dienstag, 4. November 2014, 15:52:34 schrieb Kever Yang:
we are going to make a clock usage solution for rk3288:
1. CPLL and GPLL always not change after assign init;
2. NPLL default as 500MHz, may used for most scene;
3
When we assgined a clock rate in dts, we may need to update
the clock setting like PLLs who can get the same output rate with
different parameter even if we don't need to change the rate.
Kever Yang (2):
clk: add property for force to update clock setting
dt-bindings: clk: add document
if the rate is not changed by now.
This patch adds a option property 'assigned-clock-force-rates'
to make sure we update all the setting even if we don't need to
update the clock rate.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
drivers/clk/clk-conf.c | 33
This patch adds document for how to use the opetion property
assigned-clock-force-rates.
We may use this property to force update a clock setting.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Documentation/devicetree/bindings/clock/clock-bindings.txt | 7 +--
1 file changed, 5
Hi
On 11/14/2014 09:46 AM, Mike Turquette wrote:
Looking through the clock-tree there are a lot more components possibly
using
(or wanting to use) the npll: of course the VOPs, the edp, hdmi, isp,
hevc,
gpu, tsp uart0 and gmac. So I'm slightly uncomfortable with somehow
reserving
the npll
Heiko,
On 09/24/2014 01:52 AM, Heiko Stübner wrote:
Am Montag, 22. September 2014, 19:55:16 schrieb jinkun.hong:
From: jinkun.hong jinkun.h...@rock-chips.com
Signed-off-by: Jack Dai jack@rock-chips.com
Signed-off-by: Wang Caesar caesar.w...@rock-chips.com
Signed-off-by: jinkun.hong
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