We move register_netdev() to the end of dwceqos_probe() to close any
races where the netdev callbacks are called before the initialization
has finished.
Reported-by: Pavel Andrianov
Signed-off-by: Lars Persson
---
drivers/net/ethernet/synopsys/dwc_eth_qos.c | 38
On 10/25/2017 12:18 PM, Kees Cook wrote:
In preparation for unconditionally passing the struct timer_list pointer to
all timer callbacks, switch to using the new timer_setup() and from_timer()
to pass the timer pointer explicitly.
Cc: Herbert Xu
Cc: Jesper Nilsson
Cc: Lars Persson
Cc
s/dwc_eth_qos.ko]
> undefined!
> ERROR: "dma_map_single" [drivers/net/ethernet/synopsys/dwc_eth_qos.ko]
> undefined!
>
> Signed-off-by: Geert Uytterhoeven
Acked-by: Lars Persson
> ---
> drivers/net/ethernet/synopsys/Kconfig | 2 +-
> 1 file changed, 1 i
This adds an smc wrapper according to the ARM standard for secure
monitor calling conventions (ARM DEN 0028A).
Signed-off-by: Lars Persson
---
arch/arm/include/asm/smc-call.h | 12
arch/arm/kernel/Makefile| 2 ++
arch/arm/kernel/smc-call.S | 22
On Mon, Sep 24, 2018 at 8:32 AM Richard Weinberger wrote:
>
> Lars,
>
> Am Sonntag, 23. September 2018, 15:49:42 CEST schrieb Lars Persson:
> > Hi Richard
> >
> > Sorry, I assumed this omission from -stable was a mistake.
> >
> > The timing for our boot
MA FS in a couple of our customers.
> Without it the non-DMA root FS crashes are catastrophic in aliasing
> systems but it is still a problem for I-cache too but much rare.
>
> Unfortunately, it is also a performance hit, however is less than run a
> page cache flush at eac
if page_mapped() will return true at that
point. If it does, then your proposed patch for flush_icache_page is a
better fix.
- Lars
On fre, 2014-12-05 at 22:41 +0100, Leonid Yegoshin wrote:
> Lars,
>
> On 12/05/2014 01:32 AM, Lars Persson wrote:
> > Hi
> >
> > Our setup
Due to a change in flush_dcache_page, highmem pages may have the
dcache dirty flag set. Until there is proper support for highmen in
cache.c we must filter out highmem pages to avoid NULL pointer
dereferences.
Signed-off-by: Lars Persson
---
arch/mips/mm/cache.c |4
1 file changed, 4
:53 skrev Paul Burton :
>
>> On Thu, Feb 26, 2015 at 02:16:01PM +0100, Lars Persson wrote:
>> This patch set proposes an improved fix for the race condition that
>> originally was fixed in commit 2a4a8b1e5d9d ("MIPS: Remove race window
>> in page fault
nce inside move_to_new_page
to make it common for both cases.
Cc: sta...@vger.kernel.org
Fixes: 97ee0524614 ("flush cache before installing new page at migraton")
Reviewed-by: Paul Burton
Acked-by: Mel Gorman
Signed-off-by: Lars Persson
---
v2: Added a Fixes footer and CC for stable.
On 2/25/19 4:07 PM, Vlastimil Babka wrote:
On 2/19/19 1:32 PM, Lars Persson wrote:
Our MIPS 1004Kc SoCs were seeing random userspace crashes with SIGILL
and SIGSEGV that could not be traced back to a userspace code
bug. They had all the magic signs of an I/D cache coherency issue.
Now
On Tue, Feb 26, 2019 at 10:23 AM Anshuman Khandual
wrote:
> On 02/19/2019 06:02 PM, Lars Persson wrote:
> > Our MIPS 1004Kc SoCs were seeing random userspace crashes with SIGILL
> > and SIGSEGV that could not be traced back to a userspace code
> > bug. They had all the magic
On 2/26/19 11:07 AM, Vlastimil Babka wrote:
On 2/26/19 9:40 AM, Lars Persson wrote:
What about CC stable and a Fixes tag, would it be applicable here?
Yes this is candidate for stable so let's add:
Cc:
I do not find a good candidate for a Fixes tag.
How bout a version range wher
The tsgl scatterlist must be re-initialized after each
operation. Otherwise the sticky bits in the page_link will corrupt the
list with pre-mature termination or false chaining.
Signed-off-by: Lars Persson
---
crypto/algif_aead.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/crypto
Add device tree binding documentation for the Synopsys DWC Ethernet
QoS driver supporting revision 4.10a of the hardware IP.
Signed-off-by: Lars Persson
---
.../bindings/net/snps,dwc-qos-ethernet.txt | 75 ++
1 file changed, 75 insertions(+)
create mode 100644
Signed-off-by: Lars Persson
---
drivers/net/ethernet/Kconfig | 1 +
drivers/net/ethernet/Makefile | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig
index f3bb178..05aa759 100644
--- a/drivers/net/ethernet/Kconfig
+++ b/drivers/net
total available feature set. Currently
it supports:
* TSO
* Checksum offload for RX and TX.
* Energy efficient ethernet.
* GMII phy interface.
* The statistics module.
* Single RX and TX queue.
Lars Persson (4):
dwc_eth_qos: Add Synopsys DWC Ethernet QoS bindings
dwc_eth_qos: Add support for
This patch adds a platform driver for the new generation of the
gigabit ethernet IP from Synopsys. It is developed for version 4.10a
of the IP core.
Signed-off-by: Lars Persson
---
drivers/net/ethernet/synopsys/Kconfig | 27 +
drivers/net/ethernet/synopsys/Makefile |5
Add maintainer information for the Synopsys DWC Ethernet QOS driver.
Signed-off-by: Lars Persson
---
MAINTAINERS | 7 +++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index a226416..0c78766 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8903,6 +8903,13 @@ F
On 02/17/2016 12:59 AM, Michael Turquette wrote:
Quoting Lars Persson (2016-02-14 00:03:06)
On 02/12/2016 05:39 PM, Rob Herring wrote:
On Thu, Feb 11, 2016 at 05:01:03PM +0100, Lars Persson wrote:
Add device tree documentation for the main PLL in the Artpec-6 SoC.
Roughly how many clocks
On 02/17/2016 01:02 AM, Michael Turquette wrote:
Hi Lars,
Quoting Lars Persson (2016-02-11 08:01:04)
The PLL1 clock is a fixed-factor clock with factors derived from boot
mode pins. This driver is a simple wrapper to register the fixed
factor clock according to the pin settings.
Signed-off
Basic support for the Axis Artpec-6 ARM SoC. Timers, interrupts, UARTs and
ethernet are wired up.
Lars Persson (8):
clk: add device tree binding for artpec-6 pll1 clock
clk: add artpec-6 pll1 clock driver
arm: add device-tree SoC bindings for Axis Artpec-6
arm: dts: add Artpec-6 soc dtsi
Signed-off-by: Lars Persson
---
arch/arm/boot/dts/artpec6.dtsi | 238 +
1 file changed, 238 insertions(+)
create mode 100644 arch/arm/boot/dts/artpec6.dtsi
diff --git a/arch/arm/boot/dts/artpec6.dtsi b/arch/arm/boot/dts/artpec6.dtsi
new file mode 100644
Signed-off-by: Lars Persson
---
arch/arm/configs/multi_v7_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/configs/multi_v7_defconfig
b/arch/arm/configs/multi_v7_defconfig
index 8e8b2ac..bf3840e 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs
The PLL1 clock is a fixed-factor clock with factors derived from boot
mode pins. This driver is a simple wrapper to register the fixed
factor clock according to the pin settings.
Signed-off-by: Lars Persson
---
drivers/clk/Makefile | 1 +
drivers/clk/clk-artpec6.c | 70
Basic machine port for the Artpec-6 SoC from Axis
Communications.
Signed-off-by: Lars Persson
---
arch/arm/Kconfig | 2 ++
arch/arm/Makefile| 1 +
arch/arm/mach-artpec/Kconfig | 22
arch/arm/mach-artpec/Makefile| 1 +
arch
Signed-off-by: Lars Persson
---
arch/arm/boot/dts/Makefile | 2 ++
arch/arm/boot/dts/artpec6-devboard.dts | 57 ++
2 files changed, 59 insertions(+)
create mode 100644 arch/arm/boot/dts/artpec6-devboard.dts
diff --git a/arch/arm/boot/dts/Makefile b
Signed-off-by: Lars Persson
---
Documentation/devicetree/bindings/arm/axis.txt | 8
1 file changed, 8 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/axis.txt
diff --git a/Documentation/devicetree/bindings/arm/axis.txt
b/Documentation/devicetree/bindings/arm
Signed-off-by: Lars Persson
Signed-off-by: Jesper Nilsson
---
MAINTAINERS | 10 ++
1 file changed, 10 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 7f1fa4f..d32c1aa 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -932,6 +932,16 @@ M: Tsahee Zidenberg
S: Maintained
F
Signed-off-by: Lars Persson
---
Documentation/devicetree/bindings/clock/artpec6.txt | 14 ++
1 file changed, 14 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/artpec6.txt
diff --git a/Documentation/devicetree/bindings/clock/artpec6.txt
b/Documentation
.
The memory allocation was improved to support use of the CMA as DMA allocator
backend.
Lars Persson (2):
dwc_eth_qos: release descriptors outside netif_tx_lock
dwc_eth_qos: do phy_start before resetting hardware
Rabin Vincent (3):
dwc_eth_qos: fix race condition in dwceqos_start_xmit
Signed-off-by: Lars Persson
---
drivers/net/ethernet/synopsys/dwc_eth_qos.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/synopsys/dwc_eth_qos.c
b/drivers/net/ethernet/synopsys/dwc_eth_qos.c
index 3ca2d5c..6897c1d 100644
--- a/drivers/net/ethernet/synopsys
From: Rabin Vincent
The xmit handler and the tx_reclaim tasklet had a race on the tx_free
variable which could lead to a tx timeout if tx_free was updated after
the tx complete interrupt.
Signed-off-by: Rabin Vincent
Signed-off-by: Lars Persson
---
drivers/net/ethernet/synopsys/dwc_eth_qos.c
o plug the race with the phy state machine we defer link speed
setting until the hardware init has finished.
Signed-off-by: Lars Persson
---
drivers/net/ethernet/synopsys/dwc_eth_qos.c | 23 ---
1 file changed, 20 insertions(+), 3 deletions(-)
diff --git a/drivers/net/etherne
.
Signed-off-by: Lars Persson
---
drivers/net/ethernet/synopsys/dwc_eth_qos.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ethernet/synopsys/dwc_eth_qos.c
b/drivers/net/ethernet/synopsys/dwc_eth_qos.c
index 926db2d..53d48c0 100644
--- a/drivers/net
From: Rabin Vincent
Since we are in non-atomic context here we can pass GFP_KERNEL to
dma_alloc_coherent(). This enables use of the CMA.
Signed-off-by: Rabin Vincent
Signed-off-by: Lars Persson
---
drivers/net/ethernet/synopsys/dwc_eth_qos.c | 4 ++--
1 file changed, 2 insertions(+), 2
On 02/12/2016 05:39 PM, Rob Herring wrote:
On Thu, Feb 11, 2016 at 05:01:03PM +0100, Lars Persson wrote:
Add device tree documentation for the main PLL in the Artpec-6 SoC.
Roughly how many clocks does this SoC have?
It will have 17 clocks declared in the device tree and three
SoC-specific
e, before the page is
provided to userland.
Reviewed-by: Lars Persson
Signed-off-by: Paul Burton
---
arch/mips/mm/cache.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
index 3f159ca..734cb2f 100644
--- a/arc
Add device tree documentation for the main clock controller in the
Artpec-6 SoC.
Acked-by: Rob Herring
Signed-off-by: Lars Persson
---
.../devicetree/bindings/clock/artpec6.txt | 41 ++
include/dt-bindings/clock/axis,artpec6-clkctrl.h | 38
2
s from the main clock controller block
through one DT node.
- Added a header file for the clock indexes.
- Refer to clock-bindings.txt in the bindings document.
A platform driver was not possible because the clocks are needed earlier in the
kernel startup.
Lars Persson (2):
clk: add device tr
Add a driver for the main clock controller of the Artpec-6 Soc.
Signed-off-by: Lars Persson
---
drivers/clk/Makefile | 1 +
drivers/clk/axis/Makefile | 1 +
drivers/clk/axis/clk-artpec6.c | 177 +
3 files changed, 179 insertions
Relaxed the license on the dtsi to permit use in other projects.
Signed-off-by: Lars Persson
---
arch/arm/boot/dts/artpec6.dtsi | 40 +---
1 file changed, 37 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/artpec6.dtsi b/arch/arm/boot/dts
The clock bindings for the main clock controller was changed to an
indexed controller style binding on request of the clk
maintainers. This updates the dtsi to use the new bindings.
Signed-off-by: Lars Persson
---
Note: This patch depends on a header file delivered through the clk tree in
&quo
Add a driver for the main clock controller of the Artpec-6 Soc.
Signed-off-by: Lars Persson
---
drivers/clk/Makefile | 1 +
drivers/clk/axis/Makefile | 1 +
drivers/clk/axis/clk-artpec6.c | 189 +
3 files changed, 191 insertions
Add device tree documentation for the main clock controller in the
Artpec-6 SoC.
Acked-by: Rob Herring
Signed-off-by: Lars Persson
---
.../devicetree/bindings/clock/artpec6.txt | 41 ++
include/dt-bindings/clock/axis,artpec6-clkctrl.h | 38
2
le for the clock indexes.
- Refer to clock-bindings.txt in the bindings document.
A platform driver was not possible because the clocks are needed earlier in the
kernel startup.
Lars Persson (2):
clk: add device tree binding for Artpec-6 clock controller
clk: add artpec-6 clock controller
.../
Hi Leonid
First let me describe the mechanism of this race condition, which was a
fault in the kernel's MIPS architecture code. Specifically in its
implementation of lazy dcache flushing. AFAIK, it would only hit on
systems where the pagein code path writes to the page from the CPU.
The order of
It is the flush_dcache_page() that was called from the file-system
reading the page contents into memory.
- Lars
On Wed, 2014-12-03 at 14:42 +0100, Ralf Baechle wrote:
> Lars,
>
> normally set_pte_at() is invoked in a
>
> cache_flush_*()
> set_pte_at()
> tlb_flush_*()
>
> sequence. So
Ralf
I remember now that we have applied to our tree the proposed patch
titled "MIPS HIGHMEM fixes for cache aliasing and non-DMA I/O".
This patch changes the semantics of flush_dcache_page() by using
page_mapped() instead of mapping_mapped() to decide if the flush should
be lazy. Is it this chan
race window. It also reduces the amount of flushes on non-executable
mappings because we never enter __flush_dcache_page() for non-aliasing
CPUs.
Regressions can occur in drivers that mistakenly relies on the
flush_dcache_page() in get_user_pages() for DMA operations.
Signed-off-by: Lars Persson
tion about the executability
of the mapping in set_pte_at() and thus we would have to flush all
pages to be safe.
http://lists.infradead.org/pipermail/linux-arm-kernel/2010-November/030915.html
Lars Persson (2):
Revert "MIPS: Remove race window in page fault handling"
MIPS: Fix ra
Revert commit 2a4a8b1e5d9d ("MIPS: Remove race window in page fault
handling") because it increased the number of flushed dcache pages and
became a performance problem for some workloads.
Signed-off-by: Lars Persson
---
arch/mips/include/asm/pgtable.h | 10 ++
arch/mips/
edule call conditional to avoid scheduling an
empty queue.
Fixes: 55a93b3ea780 ("qdisc: validate skb without holding lock")
Signed-off-by: Lars Persson
---
net/sched/sch_generic.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/net/sched/sch_generi
On 04/11/2016 03:23 PM, Eric Dumazet wrote:
On Mon, 2016-04-11 at 08:24 +0200, Lars Persson wrote:
A failure in validate_xmit_skb_list() triggered an unconditional call
to dev_requeue_skb with skb=NULL. This slowly grows the queue
discipline's qlen count until all traffic through the
A failure in validate_xmit_skb_list() triggered an unconditional call
to dev_requeue_skb with skb=NULL. This slowly grows the queue
discipline's qlen count until all traffic through the queue stops.
Fixes: 55a93b3ea780 ("qdisc: validate skb without holding lock")
Signed-off-b
> 24 apr. 2016 kl. 01:31 skrev Arnd Bergmann :
>
>> On Monday 14 March 2016, Lars Persson wrote:
>> The clock binding for the main clock controller was changed to an
>> indexed controller style binding on request of the clk
>> maintainers. This updates th
Add device tree documentation for the main clock controller in the
Artpec-6 SoC.
Acked-by: Rob Herring
Signed-off-by: Lars Persson
---
.../devicetree/bindings/clock/artpec6.txt | 41 ++
include/dt-bindings/clock/axis,artpec6-clkctrl.h | 38
2
Add a driver for the main clock controller of the Artpec-6 Soc.
Signed-off-by: Lars Persson
---
MAINTAINERS| 2 +-
drivers/clk/Makefile | 1 +
drivers/clk/axis/Makefile | 1 +
drivers/clk/axis/clk-artpec6.c | 230
bindings.
Changes since v1:
- The driver now provides all clocks from the main clock controller block
through one DT node.
- Added a header file for the clock indexes.
- Refer to clock-bindings.txt in the bindings document.
Lars Persson (2):
clk: add device tree binding for Artpec-6 clock
On 04/02/2016 03:39 AM, Stephen Boyd wrote:
On 03/31, Lars Persson wrote:
diff --git a/drivers/clk/axis/Makefile b/drivers/clk/axis/Makefile
new file mode 100644
index 000..628c9d3
--- /dev/null
+++ b/drivers/clk/axis/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_MACH_ARTPEC6) += clk-artpec6.o
the clock indexes.
- Refer to clock-bindings.txt in the bindings document.
Lars Persson (2):
clk: add device tree binding for Artpec-6 clock controller
clk: add artpec-6 clock controller
Lars Persson (2):
clk: add device tree binding for Artpec-6 clock controller
clk: add artpec-6 clock
Add a driver for the main clock controller of the Artpec-6 Soc.
Signed-off-by: Lars Persson
---
MAINTAINERS| 2 +-
drivers/clk/Makefile | 1 +
drivers/clk/axis/Makefile | 1 +
drivers/clk/axis/clk-artpec6.c | 242
Add device tree documentation for the main clock controller in the
Artpec-6 SoC.
Acked-by: Rob Herring
Signed-off-by: Lars Persson
---
.../devicetree/bindings/clock/artpec6.txt | 41 ++
include/dt-bindings/clock/axis,artpec6-clkctrl.h | 38
2
On 04/11/2016 04:22 PM, Eric Dumazet wrote:
On Mon, 2016-04-11 at 15:38 +0200, Lars Persson wrote:
I though it would be prudent because the queue can be non-empty even for
the case of skb=NULL. So should it be there in this patch, another patch
or not at all ?
Then maybe change return code
known if later packets also will fail in the
validate path.
Fixes: 55a93b3ea780 ("qdisc: validate skb without holding lock")
Signed-off-by: Lars Persson
---
v3: After a discussion with Eric and Cong I went back to v1 and added the
likely() for the common path.
---
net/sched/sch_generic
This is intended for new machines that call secure monitors compliant with ARM
DEN 0028A.
Changes since RFC:
* Build only for V6 and V7 CPUs.
Lars Persson (1):
arm: Add generic smc wrapper
arch/arm/include/asm/smc-call.h | 12
arch/arm/kernel/Makefile| 3 +++
arch/arm
This adds an smc wrapper according to the ARM standard for secure
monitor calling conventions (ARM DEN 0028A).
Signed-off-by: Lars Persson
---
arch/arm/include/asm/smc-call.h | 12
arch/arm/kernel/Makefile| 3 +++
arch/arm/kernel/smc-call.S | 22
nce inside move_to_new_page
to make it common for both cases.
Signed-off-by: Lars Persson
---
mm/migrate.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/mm/migrate.c b/mm/migrate.c
index d4fd680be3b0..80fc19e610b5 100644
--- a/mm/migrate.c
+++ b/mm/migrate.c
@@ -248
On 1/22/19 4:14 PM, Greg Kroah-Hartman wrote:
When calling debugfs functions, there is no need to ever check the
return value. The function can work or not, but the code logic should
never do something different based on this.
Cc: Jesper Nilsson
Cc: Lars Persson
Cc: Herbert Xu
Cc: "
On Fri, Nov 30, 2018 at 1:07 PM Jan Stancek wrote:
>
> LTP proc01 testcase has been observed to rarely trigger crashes
> on arm64:
> page_mapped+0x78/0xb4
> stable_page_flags+0x27c/0x338
> kpageflags_read+0xfc/0x164
> proc_reg_read+0x7c/0xb8
> __vfs_read+0x58/0x178
> vfs_re
On Wed, May 15, 2019 at 1:19 PM Greg Kroah-Hartman
wrote:
>
> [ Upstream commit 05fd5c2c61732152a6bddc318aae62d7e436629b ]
>
> Commit 088aaf17aa79300cab14dbee2569c58cfafd7d6e introduced a leak where
> if SMB2_read() returned an error we would return without freeing the
> request buffer.
>
> Cc: St
On Fri, Jun 21, 2019 at 12:50 PM Wolfram Sang wrote:
>
> Hi,
>
> On Fri, Jun 21, 2019 at 03:16:11PM +0900, Masahiro Yamada wrote:
> > (Added Lars Persson, Guennadi Liakhovetski)
> >
> > On Fri, Jun 21, 2019 at 3:06 PM Masahiro Yamada
> > wrote:
> >
>
On Mon, Jul 22, 2019 at 12:18 PM Ilias Apalodimas
wrote:
>
> On Thu, Jul 18, 2019 at 07:48:04AM +, Jose Abreu wrote:
> > From: Jon Hunter
> > Date: Jul/17/2019, 19:58:53 (UTC+00:00)
> >
> > > Let me know if you have any thoughts.
> >
> > Can you try attached patch ?
> >
>
> The log says some
: I38b6fd0addc1d93ae172332b67e6eb71c0871508
Signed-off-by: Lars Persson
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 677ef41cb012..a91d04e5c084 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1432,6 +1432,7 @@ F:arch/arm/mach-artpec
F: arch/arm/boot/dts/artpec6*
F
On Tue, Feb 5, 2019 at 8:14 AM Jan Stancek wrote:
> Hi,
>
> are you using THP (CONFIG_TRANSPARENT_HUGEPAGE)?
>
> The changed line should affect only THP and normal compound pages,
> so a test with THP disabled might be interesting.
>
> >
> > The breakage consists of random processes dying with SIG
On 2/26/19 12:57 PM, Lars Persson wrote:
On 2/26/19 11:07 AM, Vlastimil Babka wrote:
On 2/26/19 9:40 AM, Lars Persson wrote:
What about CC stable and a Fixes tag, would it be applicable here?
Yes this is candidate for stable so let's add:
Cc:
I do not find a good candidate
ly
handle interrupted erasures in EBA
This will in turn require also this follow-up patch:
25677478474a91fa1b46f19a4a591a9848bca6fb ubi: Initialize Fastmap
checkmapping correctly
BR,
Lars Persson
On Sun, Sep 23, 2018 at 2:58 PM Richard Weinberger wrote:
>
> Lars,
>
> Am Sonntag, 23. September 2018, 14:49:23 CEST schrieb Lars Persson:
> > On Sun, Jul 1, 2018 at 6:27 PM Greg Kroah-Hartman
> > wrote:
> > >
> > > 4.9-stable review patch. I
> 23 nov. 2016 kl. 12:11 skrev Joao Pinto :
>
> Hi Peppe and Lars,
>
>> On 23-11-2016 10:59, Giuseppe CAVALLARO wrote:
>> Hello Joao, Lars.
>>
>>> On 11/22/2016 3:16 PM, Joao Pinto wrote:
> Ok, it makes sense.
> Just for curiosity the target setup is the following:
> https://www.you
> 21 nov. 2016 kl. 13:53 skrev Giuseppe CAVALLARO :
>
> Hello Joao
>
>> On 11/21/2016 1:32 PM, Joao Pinto wrote:
>> Hello,
>>
>>> On 21-11-2016 05:29, Rayagond Kokatanur wrote:
On Sat, Nov 19, 2016 at 7:26 PM, Rabin Vincent wrote:
> On Fri, Nov 18, 2016 at 02:20:27PM +, Joao Pint
> 21 nov. 2016 kl. 16:06 skrev Joao Pinto :
>
>> On 21-11-2016 14:25, Giuseppe CAVALLARO wrote:
>>> On 11/21/2016 2:28 PM, Lars Persson wrote:
>>>
>>>
>>>> 21 nov. 2016 kl. 13:53 skrev Giuseppe CAVALLARO :
>>>>
>>>>
On 03/13/2016 01:14 AM, Olof Johansson wrote:
On Thu, Feb 25, 2016 at 10:34:14AM +0100, Lars Persson wrote:
The clock bindings for the main clock controller was changed to an
indexed controller style binding on request of the clk
maintainers. This updates the dtsi to use the new bindings
The clock binding for the main clock controller was changed to an
indexed controller style binding on request of the clk
maintainers. This updates the dtsi to use the new bindings.
Signed-off-by: Lars Persson
---
v2: Use numerical clock indexes to enable merge before the clock driver bindings
> 1 mars 2016 kl. 03:38 Paul Burton :
>
> The flush_kernel_dcache_page function was previously essentially a nop.
> This is incorrect for MIPS, where if a page has been modified & either
> it aliases or it's executable & the icache doesn't fill from dcache then
> the content needs to be written
d code, typically resulting in a reserved
> instruction exception, a trap or a segfault.
>
> Fix this race condition fully by performing any cache maintenance
> required to keep the icache & dcache in sync in set_pte_at, before the
> page is made valid. This has the added bonus
gh a platform driver. Is this the style we should
implement ?
Best Regards,
Lars Persson
On 02/25/2016 03:58 PM, Lars Persson wrote:
Add clock support for the Artpec-6 SoC port. The ARM parts are in the series
"arm: Add Artpec-6 SoC" and it goes through the arm-soc tree.
Changes s
Add device tree documentation for the main clock controller in the
Artpec-6 SoC.
Signed-off-by: Lars Persson
---
.../devicetree/bindings/clock/artpec6.txt | 41 ++
1 file changed, 41 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/artpec6
the clock indexes.
- Refer to clock-bindings.txt in the bindings document.
A platform driver was not possible because the clocks are needed earlier in the
kernel startup.
Lars Persson (2):
clk: add device tree binding for Artpec-6 clock controller
clk: add artpec-6 clock controller
.../devicetre
Add a driver for the main clock controller of the Artpec-6 Soc.
Signed-off-by: Lars Persson
---
drivers/clk/Makefile | 1 +
drivers/clk/axis/Makefile| 1 +
drivers/clk/axis/clk-artpec6.c | 177
Signed-off-by: Lars Persson
---
arch/arm/boot/dts/Makefile | 2 ++
arch/arm/boot/dts/artpec6-devboard.dts | 64 ++
2 files changed, 66 insertions(+)
create mode 100644 arch/arm/boot/dts/artpec6-devboard.dts
diff --git a/arch/arm/boot/dts/Makefile b
This adds device tree bindings for the Artpec-6 SoC.
Signed-off-by: Lars Persson
---
Documentation/devicetree/bindings/arm/axis.txt | 29 ++
1 file changed, 29 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/axis.txt
diff --git a/Documentation
Basic machine port for the Artpec-6 SoC from Axis
Communications.
Signed-off-by: Lars Persson
---
arch/arm/Kconfig | 2 +
arch/arm/Makefile| 1 +
arch/arm/mach-artpec/Kconfig | 20 ++
arch/arm/mach-artpec/Makefile| 1 +
arch/arm
The PLL1 clock is a fixed-factor clock with factors derived from boot
mode pins. This driver is a simple wrapper to register the fixed
factor clock according to the pin settings.
Signed-off-by: Lars Persson
---
drivers/clk/Makefile | 1 +
drivers/clk/clk-artpec6.c | 70
Add device tree documentation for the main PLL in the Artpec-6 SoC.
Signed-off-by: Lars Persson
---
Documentation/devicetree/bindings/clock/artpec6.txt | 16
1 file changed, 16 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/artpec6.txt
diff --git a
Initial device tree for the Artpec-6 SoC.
Signed-off-by: Lars Persson
---
arch/arm/boot/dts/artpec6.dtsi | 236 +
1 file changed, 236 insertions(+)
create mode 100644 arch/arm/boot/dts/artpec6.dtsi
diff --git a/arch/arm/boot/dts/artpec6.dtsi b/arch/arm
Signed-off-by: Lars Persson
---
arch/arm/configs/multi_v7_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/configs/multi_v7_defconfig
b/arch/arm/configs/multi_v7_defconfig
index 8e8b2ac..1149642 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs
Signed-off-by: Lars Persson
Signed-off-by: Jesper Nilsson
---
MAINTAINERS | 10 ++
1 file changed, 10 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 7f1fa4f..d32c1aa 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -932,6 +932,16 @@ M: Tsahee Zidenberg
S: Maintained
F
CONFIG_SYNOPSYS_DWC_ETH_QOS to multi_v7_defconfig.
- Added binding documentation for axis,artpec6-dev-board.
Lars Persson (8):
clk: add device tree binding for artpec-6 pll1 clock
clk: add artpec-6 pll1 clock driver
arm: add device-tree SoC bindings for Axis Artpec-6
arm: dts: add Artpec-6 SoC
Add clock support for the Artpec-6 SoC port. The ARM parts are in the series
"arm: Add Artpec-6 SoC" and it goes through the arm-soc tree.
Lars Persson (2):
clk: add device tree binding for artpec-6 pll1 clock
clk: add artpec-6 pll1 clock driver
.../devicetree/bindings/clock/a
The PLL1 clock is a fixed-factor clock with factors derived from boot
mode pins. This driver is a simple wrapper to register the fixed
factor clock according to the pin settings.
Signed-off-by: Lars Persson
---
drivers/clk/Makefile | 1 +
drivers/clk/clk-artpec6.c | 70
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