of readl/writel to do the endianness reordering,
and removes an extra variable in the function.
Fixes: f68a7dcb91b7 ("spi: a3700: Add full-duplex support")
Signed-off-by: Maxime Chevallier
---
drivers/spi/spi-armada-3700.c | 13 ++---
1 file changed, 6 insertions(+), 7 deletion
this into two patches, since the first applies on an already
mainlined commit, and the other on a recent patch that I sent.
Mark, if you wish I can resend this in another form (just one patch,
or as a rework of my previous patchset
"spi: a3700: Add improvements and full-duplex transfers")
-converson functions, since the
converted values are going through readl/writel anyway, which take care
of the conversion.
Fixes: 6fd6fd68c9e2 ("spi: armada-3700: Fix padding when sending not 4-byte
aligned data")
Signed-off-by: Maxime Chevallier
---
drivers/spi/spi-armada-3700.c | 5 ++-
either 1 or 4 bytes at a time. Because this is more
CPU intensive, and a bit slower than FIFO mode, we only use the
full-duplex way of transferring data when necessary.
Maxime Chevallier (4):
spi: a3700: Clear DATA_OUT when performing a read
spi: a3700: Set frequency limits at startup
spi: a3700
Armada 3700 SPI controller has an internal clock divider which can
divide the parent clock frequency by up to 30.
This patch sets the limits in the spi_controller fields so that we can
detect when a non-supported frequency is requested by a device for a
transfer.
Signed-off-by: Maxime Chevallier
The armada 3700 SPI controller allows to make transfers without using
the 32 bytes RFIFO and WFIFO.
This commit enable switching between FIFO and non-FIFO mode, which is
necessary to implement full-duplex transfers.
Signed-off-by: Maxime Chevallier
---
drivers/spi/spi-armada-3700.c | 9
beginning each transfer.
This was tested on EspressoBin with a logical analyser, and a simple
setup where MISO is connected on MOSI. Transfers were made from
userspace using spidev and spi-pipe from the spi-tools project
Signed-off-by: Maxime Chevallier
---
drivers/spi/spi-armada-3700.c | 85
EspressoBin.
Signed-off-by: Maxime Chevallier
---
drivers/spi/spi-armada-3700.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/spi/spi-armada-3700.c b/drivers/spi/spi-armada-3700.c
index d653453..c11ea6c 100644
--- a/drivers/spi/spi-armada-3700.c
+++ b/drivers/spi/spi-armada-3700
ever unicast or multicast range for one port is full, the filtering
is disabled and port goes into promiscuous mode for the given type of
addresses.
Signed-off-by: Maxime Chevallier
---
drivers/net/ethernet/marvell/mvpp2.c | 296 +++
1 file changed, 161 insertions(+)
addresses to the per-port filter.
This commit changes the function so that it takes struct mvpp2_port as
a parameter instead.
Signed-off-by: Maxime Chevallier
---
drivers/net/ethernet/marvell/mvpp2.c | 30 +++---
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a
icast promiscuous mode.
The first patch reworks the function that adds and removes addresses to the
filter. This is preparatory work to ease UC filter implementation.
The second patch adds the UC filtering feature.
Maxime Chevallier (2):
net: mvpp2: Simplify MAC filtering function parameters
net:
r prs_entry, by passing it the
index as a parameter. The function now zeroes the entry, and sets the
index field before doing all other init from HW.
The function is renamed 'mvpp2_prs_init_from_hw' to make that clear.
Signed-off-by: Maxime Chevallier
---
drivers/net/ethe
into mvpp2_prs_init_from_hw,
make it zero-out the struct and take the index as a parameter. That's what's
done in the first patch of the series.
The second patch is the V3 of
("net: mvpp2: Don't use dynamic allocs for local variables"), making use of
mvpp2_prs_init_from_hw and taking previous
TCAM entry, we simply return the TCAM id that matches
the requested entry.
Signed-off-by: Maxime Chevallier
---
V2: Remove unnecessary brackets, following Antoine Tenart's review.
V3: Make sure prs_entry objects are zeroed before using them, following
David Miller and Yan Markman's re
-by: Maxime Chevallier
---
David, this patch should not conflict with other the pending PPv2 series I sent
earlier ("[PATCH net-next 0/2] net: mvpp2: Remove unnecessary dynamic allocs")
drivers/net/ethernet/marvell/mvpp2.c | 43 +---
1 file changed, 30
TCAM entry, we simply return the TCAM id that matches
the requested entry.
Signed-off-by: Maxime Chevallier
---
drivers/net/ethernet/marvell/mvpp2.c | 282 +++
1 file changed, 124 insertions(+), 158 deletions(-)
diff --git a/drivers/net/ethernet/marvell/mvpp2
TCAM entry, we simply return the TCAM id that matches
the requested entry.
Signed-off-by: Maxime Chevallier
---
V2: Remove unnecessary brackets, following Antoine Tenart's review.
drivers/net/ethernet/marvell/mvpp2.c | 289 +++
1 file changed, 127 insertio
Hello Yan,
On Wed, 21 Mar 2018 19:57:47 +,
Yan Markman wrote :
> Hi Maxime
Please avoid top-posting on this list.
> Please check the TWO points:
>
> 1). The mvpp2_prs_flow_find() returns TID if found
> The TID=0 is valid FOUND value
> For Not-found use -ENOENT (just like your mvpp
Hello David,
On Thu, 22 Mar 2018 14:47:09 -0400 (EDT),
David Miller wrote :
> From: Maxime Chevallier
> Date: Wed, 21 Mar 2018 16:14:00 +0100
>
> > diff --git a/drivers/net/ethernet/marvell/mvpp2.c
> > b/drivers/net/ethernet/marvell/mvpp2.c index
> > 9bd35f
On Thu, 22 Mar 2018 15:43:08 -0400 (EDT),
David Miller wrote :
> From: Maxime Chevallier
> Date: Thu, 22 Mar 2018 20:14:53 +0100
>
> > Hello David,
> >
> > On Thu, 22 Mar 2018 14:47:09 -0400 (EDT),
> > David Miller wrote :
> >
> >> From: M
t fine.
Thanks,
Tested-by: Maxime Chevallier
>Signed-off-by: Grygorii Strashko
>---
> drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 19 +-
> drivers/phy/marvell/phy-mvebu-cp110-comphy.c| 83 ++---
> 2 files changed, 48 insertions(+), 54 deletions(-)
&g
at is in charge of detecting when there
is a single VLAN tag.
This commits adds the missing update of the result_info in this case.
Signed-off-by: Maxime Chevallier
---
drivers/net/ethernet/marvell/mvpp2.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/net/ethernet/marvell/mvpp2.c
e and full
duplex with a wide range of transfer sizes and bit_per_words values.
I however couldn't test the slave mode with these patches, so some review is
very welcomed, especially on the last patch.
Thanks,
Maxime
Maxime Chevallier (5):
spi: imx: Remove duplicate variable assignments
Some fields in struct spi_imx_data are assigned a different value twice
in a row, in spi_imx_setupxfer.
Signed-off-by: Maxime Chevallier
---
drivers/spi/spi-imx.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c
index d3b21faf6b1f..d75153c995af
the can_dma
function, since the SPI core validates that we always have a transfer
length that is a multiple of the number of bytes per word.
Signed-off-by: Maxime Chevallier
---
drivers/spi/spi-imx.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/spi/spi
o and imx6 quad.
Signed-off-by: Maxime Chevallier
---
drivers/spi/spi-imx.c | 122 +++---
1 file changed, 85 insertions(+), 37 deletions(-)
diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c
index ef6d3648396a..08dd3a31a3e5 100644
--- a/drivers/spi
ticks for transfers with
bit_per_word values not aligned on 8 bits.
With that , we are sure that only the correct number of bits is
shifted out at each transfer, so we don't need to mask out the remaining
parts of the words.
Signed-off-by: Maxime Chevallier
---
drivers/spi
xtra check for the wml being different than 0.
Signed-off-by: Maxime Chevallier
---
drivers/spi/spi-imx.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c
index 3ae706dac660..ef6d3648396a 100644
--- a/drivers/spi/spi-imx.c
+++ b/drivers/spi
ticks for transfers with
bit_per_word values not aligned on 8 bits.
With that , we are sure that only the correct number of bits is
shifted out at each transfer, so we don't need to mask out the remaining
parts of the words.
Signed-off-by: Maxime Chevallier
---
drivers/spi
xtra check for the wml being different than 0.
Signed-off-by: Maxime Chevallier
---
drivers/spi/spi-imx.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c
index 3ae706dac660..ef6d3648396a 100644
--- a/drivers/spi/spi-imx.c
+++ b/drivers/spi
s was tested on imx6s and imx6q, with and without DMA, in single and full
duplex with a wide range of transfer sizes and bit_per_words values.
I however couldn't test the slave mode with these patches, so some review is
very welcomed, especially on the last patch.
Thanks,
Maxime
Maxime Che
Some fields in struct spi_imx_data are assigned a different value twice
in a row, in spi_imx_setupxfer.
Signed-off-by: Maxime Chevallier
---
drivers/spi/spi-imx.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c
index d3b21faf6b1f..d75153c995af
o and imx6 quad.
Signed-off-by: Maxime Chevallier
---
drivers/spi/spi-imx.c | 122 +++---
1 file changed, 85 insertions(+), 37 deletions(-)
diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c
index ef6d3648396a..08dd3a31a3e5 100644
--- a/drivers/spi
the can_dma
function, since the SPI core validates that we always have a transfer
length that is a multiple of the number of bytes per word.
Signed-off-by: Maxime Chevallier
---
drivers/spi/spi-imx.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/spi/spi
Hi Alexis,
On Mon, 09 Sep 2024 22:02:07 +0200
Alexis Lothoré (eBPF Foundation) wrote:
> test_xdp_features.sh is a shell script allowing to test that xdp features
> advertised by an interface are indeed delivered. The test works by starting
> two instance of the same program, both attaching speci
arking
>this commit with Fixes line? E.g.:
>
>Fixes: 2636ac3cc2b4 ("net: mvneta: Add network support for Armada 3700
> SoC")
Yes you're correct, I'll add that to the V2 !
Thanks for the review,
Maxime
--
Maxime Chevallier, Bootlin
Embedded Linux and kernel engineering
https://bootlin.com
Hi Andrew,
On Sat, 13 Feb 2021 20:45:25 +0100
Andrew Lunn wrote:
>On Fri, Feb 12, 2021 at 04:12:20PM +0100, Maxime Chevallier wrote:
>> +static void mvneta_setup_rx_prio_map(struct mvneta_port *pp)
>> +{
>> +int i;
>> +u32 val = 0;
>
>Hi Maxime
>
left to be dealt with.
The second patch implements the MQPrio offloading for the receive path.
Changes in V2 :
- Add a Fixes tag for the first patch
- Fix some warnings and the xmas tree in the second patch
Thanks,
Maxime
Maxime Chevallier (2):
net: mvneta: Remove per-cpu queue mapping for A
the CPUs in
the system, both in the init path and in the cpu_hotplug path.
Fixes: 2636ac3cc2b4 ("net: mvneta: Add network support for Armada 3700 SoC")
Signed-off-by: Maxime Chevallier
---
V2: Added Fixes tag, as per Pali's review
drivers/net/ethernet/marvell/mvneta.c | 9 -
Implement a basic MQPrio support, inserting rules in RX that translate
the TC to prio mapping into vlan prio to queues.
The TX logic stays the same as when we don't offload the qdisc.
Signed-off-by: Maxime Chevallier
---
V2 : Fixed the reverse xmas tree, as per Andrew's review.
patch implements the ndo_set_features to allow for disabling of VLAN
filtering using ethtool.
The default config has VLAN filtering disabled.
Signed-off-by: Maxime Chevallier
---
V2: Use correct order for local variable declarations
drivers/net/ethernet/marvell/mvpp2.c
Boundary check in mvpp2_prs_init_from_hw must be done according to the
passed "tid" parameter, not the mvpp2_prs_entry index, which is not yet
initialized at the time of the check.
Fixes: 47e0e14eb1a6 ("net: mvpp2: Make mvpp2_prs_hw_read a parser entry init
function")
S
ment for finding the root cause of this bug.
Maxime Chevallier (3):
net: mvpp2: Fix clk error path in mvpp2_probe
net: mvpp2: Fix clock resource by adding missing mg_core_clk
ARM64: dts: marvell: armada-cp110: Add clocks for the xmdio node
.../devicetree/bindings/net/marvell-pp2.txt
f4 ("clk: mvebu: cp110: Fix clock tree representation")
Signed-off-by: Maxime Chevallier
---
.../devicetree/bindings/net/marvell-pp2.txt | 9 +
arch/arm64/boot/dts/marvell/armada-cp110.dtsi| 5 +++--
drivers/net/ethernet/marvell/mvpp2.c | 20
ation")
Signed-off-by: Maxime Chevallier
---
arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
index 6c137ac656e9..ed2f1237ea1e 100644
--- a/arch/arm6
When clk_prepare_enable fails for the axi_clk, the mg_clk isn't properly
cleaned up. Add another jump label to handle that case, and make sure we
jump to it in the later error cases.
Fixes: 4792ea04bcd0 ("net: mvpp2: Fix clock resource by adding an optional bus
clock")
Signed
Hi Gregory,
On Wed, 25 Apr 2018 13:43:14 +0200
Gregory CLEMENT wrote:
>Hi Maxime,
>
> On mer., avril 25 2018, Maxime Chevallier
> wrote:
>
>> Marvell's PPv2.2 IP needs an additional clock named "MG Core clock".
>> This is required on Armada 7K and 8K.
ccordingly.
Fixes: c7e92def1ef4 ("clk: mvebu: cp110: Fix clock tree representation")
Signed-off-by: Maxime Chevallier
---
Documentation/devicetree/bindings/net/marvell-pp2.txt | 9 +
arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 5 +++--
2 files changed, 8 insertions(+),
Marvell's PPv2.2 IP needs an additional clock named "MG Core clock".
This is required on Armada 7K and 8K.
This commit adds the required clock in mvpp2, making sure it's only
used on PPv2.2.
Fixes: c7e92def1ef4 ("clk: mvebu: cp110: Fix clock tree representation")
Si
V2 : Remove all DT patches from this series, they will be merged through
the mvebu tree.
Maxime Chevallier (2):
net: mvpp2: Fix clk error path in mvpp2_probe
net: mvpp2: Fix clock resource by adding missing mg_core_clk
drivers/net/ethernet/marvell/mvpp2.c | 30 +++---
When clk_prepare_enable fails for the axi_clk, the mg_clk isn't properly
cleaned up. Add another jump label to handle that case, and make sure we
jump to it in the later error cases.
Fixes: 4792ea04bcd0 ("net: mvpp2: Fix clock resource by adding an optional bus
clock")
Signed
ports but the 9 and 10, and because modes supported by 6390
ports 9 and 10 are a subset of those supported on 6390X.
This was tested on 6390X using RXAUI mode.
Fixes: 364e9d7776a3 ("net: dsa: mv88e6xxx: Power on/off SERDES on cmode change")
Signed-off-by: Maxime Chevallier
---
drive
Hello Russell,
On Mon, 21 Jan 2019 13:00:30 +
Russell King - ARM Linux admin wrote:
>On Mon, Jan 21, 2019 at 01:29:45PM +0100, Maxime Chevallier wrote:
>> Hello Russell,
>>
>> On Mon, 21 Jan 2019 10:52:06 +
>> Russell King - ARM Linux admin wrote:
>>
Contrary to the 3310, the 2110 PHY correctly reports it's 2.5G/5G
abilities. We can therefore use the genphy_c45_pma_read_abilities helper
to build the list of features.
Signed-off-by: Maxime Chevallier
---
drivers/net/phy/marvell10g.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
The genphy_c45_pma_read_abilities helper now sets the Autoneg ability
in phydev->supported according to what the AN MMD reports.
We therefore don't need to manually do that in mv3310_get_features().
Signed-off-by: Maxime Chevallier
Suggested-by: Heiner Kallweit
---
drivers
, since it doesn't have the
issue with the wrong abilities being reported.
Maxime Chevallier (2):
net: phy: marvell10g: Let genphy_c45_pma_read_abilities set Aneg bit
net: phy: marvell10g: Use the generic C45 helper to read the 2110
features
drivers/net/phy/marvell10g.c | 12 +-
Implement a basic MQPrio support, inserting rules in RX that translate
the TC to prio mapping into vlan prio to queues.
The TX logic stays the same as when we don't offload the qdisc.
Signed-off-by: Maxime Chevallier
---
drivers/net/ethernet/marvell/mvneta.c | 65 +
ements the MQPrio offloading for the receive path.
Thanks !
Maxime
Maxime Chevallier (2):
net: mvneta: Remove per-cpu queue mapping for Armada 3700
net: mvneta: Implement mqprio support
drivers/net/ethernet/marvell/mvneta.c | 74 ++-
1 file changed, 73 insertions(+),
the CPUs in
the system, both in the init path and in the cpu_hotplug path.
Signed-off-by: Maxime Chevallier
---
drivers/net/ethernet/marvell/mvneta.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/marvell/mvneta.c
b/drivers/net/ethernet/marvell
Add prefix for Techwell, Inc.
Acked-by: Rob Herring
Signed-off-by: Maxime Chevallier
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml
b/Documentation/devicetree/bindings
ong with a
binding example validation error.
Any feedback is appreciated,
Thanks,
Maxime
Maxime Chevallier (3):
dt-bindings: vendor-prefixes: Add techwell vendor prefix
media: dt-bindings: media: i2c: Add bindings for TW9900
media: i2c: Introduce a driver for the Techwell TW99
aml
@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/i2c/tw9900.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Techwell TW9900 NTSC/PAL/SECAM video decoder
+
+maintainers:
+ - Maxime
The Techwell video decoder supports PAL, NTSC and SECAM input formats,
and outputs a BT.656 signal.
This commit adds support for this device, with basic support for NTSC
and PAL, along with brightness and contrast controls.
Signed-off-by: Maxime Chevallier
---
v1 -> v2: Set the media ent
tainer)
>
>A quick review below...
>
>On 03/04/2020 16:21, Maxime Chevallier wrote:
>> Introduce a driver for the camera interface on some Rockchip platforms.
>>
>> This controller supports CSI2, Parallel and BT656 interfaces, but for
>> now only the parallel interf
fixes the
example binding.
Any feedback is appreciated,
Thanks,
Maxime
Maxime Chevallier (3):
dt-bindings: vendor-prefixes: Add techwell vendor prefix
media: dt-bindings: media: i2c: Add bindings for TW9900
media: i2c: Introduce a driver for the Techwell TW9900 decoder
.../devicetree/bind
Add prefix for Techwell, Inc.
Acked-by: Rob Herring
Signed-off-by: Maxime Chevallier
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml
b/Documentation/devicetree/bindings
The Techwell video decoder supports PAL, NTSC and SECAM input formats,
and outputs a BT.656 signal.
This commit adds support for this device, with basic support for NTSC
and PAL, along with brightness and contrast controls.
Signed-off-by: Maxime Chevallier
---
v1 -> v2: Set the media ent
OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/i2c/tw9900.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Techwell TW9900 NTSC/PAL/SECAM video decoder
+
+maintainers:
+ - Maxime Chevallier
+
+description:
+ The tw9900 is a multi-standard video
Add a documentation for the Rockchip Camera Interface controller
binding.
This controller can be found on platforms such as the PX30 or the
RK3288, the PX30 being the only platform supported so far.
Signed-off-by: Maxime Chevallier
---
v3: Renmed the controller to "vip"
v4: fixed t
ased on a BSP driver, and I'm not fully familiar with the media
and V4L2 frameworks, so I guess some review is still needed.
On top of the previous series, this series addresses most of the reviews
by Ezequiel (Thanks again), and was tested on a PX30 chip.
Maxime
Maxime Chevallier (3):
media
The PX30 has a camera interface, supporting CSI2 and BT656
modes. Add a DT description for this interface.
Signed-off-by: Maxime Chevallier
---
V3 : Renamed the controlled
V4: Fixed the clock names
arch/arm64/boot/dts/rockchip/px30.dtsi | 12
1 file changed, 12 insertions
ng" mode of the controller, which is a
double-buffering mechanism.
Signed-off-by: Maxime Chevallier
---
V3:
- renamed the driver
- Took Hans, Robin and Ezequiel's reviews into account
- Implemented the ouble-buffering mode
v4:
- Took Ezequiel's reviews into account
- Reworked
test VIDIOC_EXPBUF: OK
test Requests: OK (Not Supported)
Total for rk_vip device /dev/video0: 45, Succeeded: 45, Failed: 0, Warnings: 0
Once again, any review is welcome :)
Thanks a lot,
Maxime
Maxime Chevallier (3):
media: dt-bindings: media: Document Rockchip VIP bindings
Add a documentation for the Rockchip Camera Interface controller
binding.
This controller can be found on platforms such as the PX30 or the
RK3288, the PX30 being the only platform supported so far.
Signed-off-by: Maxime Chevallier
---
v3: Renamed the controller to "vip"
v4: fixed t
ng" mode of the controller, which is a
double-buffering mechanism.
Signed-off-by: Maxime Chevallier
---
V3:
- renamed the driver
- Took Hans, Robin and Ezequiel's reviews into account
- Implemented the ouble-buffering mode
v4:
- Took Ezequiel's reviews into account
- Reworked
The PX30 has a camera interface, supporting CSI2 and BT656
modes. Add a DT description for this interface.
Signed-off-by: Maxime Chevallier
---
V3 : Renamed the controlled
V4: Fixed the clock names
v5: No change
arch/arm64/boot/dts/rockchip/px30.dtsi | 12
1 file changed, 12
Add prefix for Techwell, Inc.
Acked-by: Rob Herring
Signed-off-by: Maxime Chevallier
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml
b/Documentation/devicetree/bindings
he notable
addition of the querystd ops for standard detection.
Any feedback is appreciated,
Thanks,
Maxime
Maxime Chevallier (3):
dt-bindings: vendor-prefixes: Add techwell vendor prefix
media: dt-bindings: media: i2c: Add bindings for TW9900
media: i2c: Introduce a driver for the Techw
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Techwell TW9900 NTSC/PAL/SECAM video decoder
+
+maintainers:
+ - Maxime Chevallier
+
+description:
+ The tw9900 is a multi-standard video decoder, supporting NTSC, PAL and SECAM
+ standards with auto-detection features.
implemented with support for PAL and NTSC autodetection.
Signed-off-by: Maxime Chevallier
---
v1 -> v2: Set the media entity type to decoder, and implement the
s_std/g_std ops
V2 ->V3 : Fix coding-style issues, and remove the use of the bulk API
for regulators. Make the driver select the
Hi Hans, and thanks for the review.
On Thu, 4 Mar 2021 16:37:53 +0100
Hans Verkuil wrote:
>Hi Maxime,
>
>Some more code review comments:
>
>> +static int tw9900_set_fmt(struct v4l2_subdev *sd,
>> + struct v4l2_subdev_pad_config *cfg,
>> + struct v4l2_su
gt;> + struct vb2_v4l2_buffer *vb_done)
>> +{
>> + vb2_set_plane_payload(&vb_done->vb2_buf, 0,
>> + stream->pixm.plane_fmt[0].sizeimage);
>> + vb_done->vb2_buf.timestamp = ktime_get_ns();
>
>
Hello Heiner,
>Hi Maxime,
>
>Andrew and me are working on Aquantia PHY support and he handed over
>to me a patch series which includes parts of the first version of your
>series. Having said that I'm especially interested in your patches
>5 and 6. Because your series is somewhat bigger and there a
/20190118152352.26417-1-maxime.chevall...@bootlin.com/
[2] :
https://lore.kernel.org/netdev/20190207094939.27369-1-maxime.chevall...@bootlin.com/
[3] :
https://lore.kernel.org/netdev/81c340ea-54b0-1abf-94af-b8dc4ee83...@gmail.com/
Maxime Chevallier (4):
net: phy: Mask-out non-compatible modes when setting the
-off-by: Maxime Chevallier
---
drivers/net/phy/phy-c45.c | 37 +
include/uapi/linux/mdio.h | 16
2 files changed, 53 insertions(+)
diff --git a/drivers/net/phy/phy-c45.c b/drivers/net/phy/phy-c45.c
index 6f028de4dae1..7af5fa81daf6 100644
--- a
g and uses it to introduce the genphy_c45_pma_read_abilities
function.
Only PMA modes are read, it's still up to the caller to set the Pause
parameters.
Signed-off-by: Maxime Chevallier
---
drivers/net/phy/marvell10g.c | 78
drivers/net/phy/phy-c45
When setting a PHY's max speed using either the max-speed DT property
or ethtool, we should mask-out all non-compatible modes according to the
settings table, instead of just the 10/100BASET modes.
Signed-off-by: Maxime Chevallier
Suggested-by: Russell King
Reviewed-by: Andrew
Since of_set_phy_supported was moved to phy-core.c, we can also move
of_set_phy_eee_broken to the same location, so that we have all OF
functions in the same place.
This patch doesn't intend to introduce any change in behaviour.
Signed-off-by: Maxime Chevallier
Reviewed-by: Andrew
The PHY core expects PHY drivers not to set Pause and Asym_Pause bits,
unless the driver only wants to specify one of them due to HW
limitation. In the case of the Marvell10g driver, we don't need to set
them.
Signed-off-by: Maxime Chevallier
Suggested-by: Andrew Lunn
---
drivers/ne
Hello Russell,
On Thu, 7 Feb 2019 23:48:24 +
Russell King - ARM Linux admin wrote:
>On Thu, Feb 07, 2019 at 10:49:36AM +0100, Maxime Chevallier wrote:
>> The Marvell Alaska family of PHYs supports 2.5GBaseT and 5GBaseT modes,
>> as defined in the 802.3bz specification.
>&
adding autoneg ability based on what's reported by the AN
MMD.
.config_init is still used to validate the interface_mode.
Signed-off-by: Maxime Chevallier
---
drivers/net/phy/marvell10g.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/net/phy/marvell10
ue as the 88x3310 regarding 2.5/5G
abilities, and correctly follows the 802.3bz standard to list the
supported abilities.
Signed-off-by: Maxime Chevallier
Suggested-by: Antoine Tenart
---
drivers/net/phy/marvell10g.c | 13 +
include/linux/marvell_phy.h | 1 +
2 files changed, 14 inser
Cosmetic patch making use of helpers dedicated to linkmodes handling.
Signed-off-by: Maxime Chevallier
---
drivers/net/phy/marvell10g.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index 65ef469adf58
The PHY ID corresponding to the 88X3310 is also used for other PHYs in
the same family, such as the 88E2010. Use a #define for the PHY id, that
ignores the last nibble.
Signed-off-by: Maxime Chevallier
---
drivers/net/phy/marvell10g.c | 4 ++--
include/linux/marvell_phy.h | 1 +
2 files
g the correct helper to set a linkmode bit and adding macros for the
PHY ids.
We also add support for the 88E2110 PHY, which doesn't require the
quirk, and support for 2500BaseT in the PPv2 driver, in order to have a
fully working setup on the MacchiatoBin board.
Maxime Chevallier (7):
The PPv2 controller is able to support 2.5G speeds, allowing to use
2.5GBASET in conjunction with PHYs that use 2500BASEX as their MII
interface when using this mode.
Signed-off-by: Maxime Chevallier
Reviewed-by: Andrew Lunn
---
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 1 +
1 file
1.11.14 bit set, as it should.
Signed-off-by: Maxime Chevallier
---
drivers/net/phy/marvell10g.c | 35 +++
1 file changed, 35 insertions(+)
diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index 9323bcf15dbd..c48669d50653 100644
--- a/driv
x27;t supported by any MAC for now.
This was tested with :
- The 88X3310, which is on the MacchiatoBin
- The 88E2010, an Alaska PHY that has no fiber interfaces, and is
limited to 5G maximum speed.
Signed-off-by: Maxime Chevallier
---
drivers/net/phy/marvell10g.c | 26 +++
Hello Russell,
On Thu, 21 Feb 2019 10:22:15 +
Russell King - ARM Linux admin wrote:
>> +return 0;
>> +}
>> +
>> +static int mv3310_get_features(struct phy_device *phydev)
>> +{
>> +int ret, val;
>
>Please try to keep the formatting/style consistent in the file you are
>editing. A
When setting a PHY's max speed using either the max-speed DT property
or ethtool, we should mask-out all non-compatible modes according to the
settings table, instead of just the 10/100BASET modes.
Signed-off-by: Maxime Chevallier
Suggested-by: Russell King
---
drivers/net/phy/phy-c
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